Tobias Gysi [Tue, 20 Apr 2021 11:26:44 +0000 (11:26 +0000)]
[mlir][linalg] lower index operations during linalg to vector lowering.
The patch extends the vectorization pass to lower linalg index operations to vector code. It allocates constant 1d vectors that enumerate the indexes along the iteration dimensions and broadcasts/transposes these 1d vectors to the iteration space.
Differential Revision: https://reviews.llvm.org/D100373
Simon Pilgrim [Tue, 20 Apr 2021 10:59:23 +0000 (11:59 +0100)]
[DAG] SelectionDAG.cpp - breakup if-else chains where each block returns. NFCI.
Match style guide that requests that if+return blocks are separate.
Simon Pilgrim [Tue, 20 Apr 2021 10:41:04 +0000 (11:41 +0100)]
Fix Wdocumentation warning by consistently using '///' comment blocks. NFCI.
Tobias Gysi [Tue, 20 Apr 2021 09:49:06 +0000 (09:49 +0000)]
[mlir] test gather/scatter index vector of type index.
Test the vector to llvm lowering of index vectors with index element type.
Differential Revision: https://reviews.llvm.org/D100827
Thomas Preud'homme [Thu, 1 Apr 2021 14:02:36 +0000 (15:02 +0100)]
[lit, test] Fix test cancellation feature detection
A lit feature guards tests for the lit timeout functionality because on
most system it depends on the availability of the psutil Python module.
However, that feature is defined based on the ability of the testing lit
to cancel test, which does not necessarily apply to the ability of the
tested lit.
In particular, RUN commands have a cleared PYTHONPATH and user site
packages are disabled. In the case where psutil is found by the testing
lit from one of those two source of python path, the tested lit would
not be able to find it, causing timeout tests to fail.
This commit fixes the issue by testing the ability to cancel tests in
the RUN command environment.
Reviewed By: yln
Differential Revision: https://reviews.llvm.org/D99728
Martin Probst [Mon, 19 Apr 2021 11:31:06 +0000 (13:31 +0200)]
clang-format: [JS] do not merge imports and exports.
Previously, clang-format would erroneously merge import and export
statements. These need to be kept separate, as the semantics differ.
Differential Revision: https://reviews.llvm.org/D100752
Thomas Preud'homme [Sat, 3 Apr 2021 10:49:50 +0000 (11:49 +0100)]
[C++, test] Fix typo in NSS* vars
The NSS FileCheck variables at the end of the
CodeGenCXX/split-stacks.cpp clang testcase are off by 1, resulting in
the use of an undefined variable (NSS3). One of the CHECK-NOT is also
redundant because _Z8tnosplitIiEiv uses the same attribute as _Z3foov
without split stack. This commit fixes that.
Reviewed By: ChuanqiXu
Differential Revision: https://reviews.llvm.org/D99839
hsmahesha [Tue, 20 Apr 2021 10:47:05 +0000 (16:17 +0530)]
[AMDGPU] Re-arrange ds_read/ds_write ISel pattern for better readability.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D100773
Dávid Bolvanský [Tue, 20 Apr 2021 10:38:55 +0000 (12:38 +0200)]
[MemoryBuiltins] Added support for memalign
memalign is older aligned_alloc.
Simon Pilgrim [Tue, 20 Apr 2021 10:21:26 +0000 (11:21 +0100)]
[Support] APInt.h - remove <algorithm> include. NFCI.
Replace std::min use which should allow us to avoid including the <algorithm> header in every include of APInt.h.
Simon Pilgrim [Tue, 20 Apr 2021 09:43:45 +0000 (10:43 +0100)]
[CodeGen] CodeGenPassBuilder.h - remove unnecessary <string> include. NFCI.
We only use StringRef so include that.
Ben Shi [Tue, 20 Apr 2021 10:04:25 +0000 (18:04 +0800)]
[RISCV] Refactor an optimization of addition with immediate
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D100769
Joe Ellis [Thu, 15 Apr 2021 08:12:11 +0000 (08:12 +0000)]
[AArch64] Constant fold sve_convert_from_svbool(zero) to zero
Co-authored-by: Paul Walker <paul.walker@arm.com>
Differential Revision: https://reviews.llvm.org/D100463
Joe Ellis [Fri, 16 Apr 2021 10:05:05 +0000 (10:05 +0000)]
[AArch64][SVE][InstCombine] Replace last{a,b} intrinsics with extracts...
when the predicate used by last{a,b} specifies a known vector length.
For example:
aarch64_sve_lasta(VL1, D) -> extractelement(D, #1)
aarch64_sve_lastb(VL1, D) -> extractelement(D, #0)
Co-authored-by: Paul Walker <paul.walker@arm.com>
Differential Revision: https://reviews.llvm.org/D100476
Kristina Bessonova [Tue, 20 Apr 2021 09:58:41 +0000 (11:58 +0200)]
[libcxx][test] Split off debug mode tests
This continues the work started by @ldionne in
2908eb20ba7.
The debug mode tests from
- libcxx/containers/sequences/vector/
- libcxx/strings/basic.string/string.access/
- libcxx/strings/basic.string/string.iterators/
similarly contain two tests in every file making the second test never
run. The patch splits the tests into separate files.
Reviewed By: Quuxplusone, ldionne
Differential Revision: https://reviews.llvm.org/D100592
David Green [Tue, 20 Apr 2021 09:54:41 +0000 (10:54 +0100)]
[ARM] Regenerate a couple of tests. NFC
Matthias Springer [Tue, 20 Apr 2021 08:17:56 +0000 (17:17 +0900)]
[mlir] Progressively lower vector to SCF
Add a new ProgressiveVectorToSCF pass that lowers vector transfer ops to SCF by gradually unpacking one dimension at time. Unpacking stops at 1D, but can be configured to stop earlier, should the HW support (N>1)-d vectors.
The current implementation cannot handle permutation maps, masks, tensor types and unrolling yet. These will be added in subsequent commits. Once features are on par with VectorToSCF, this implementation will replace VectorToSCF.
Differential Revision: https://reviews.llvm.org/D100622
Tres Popp [Tue, 13 Apr 2021 08:18:34 +0000 (10:18 +0200)]
[mlir] Add patterns to lower Math operations to LLVM based libm calls.
Some Math operations do not have an equivalent in LLVM. In these cases,
allow a low priority fallback of calling the libm functions. This is to
give functionality and is not a performant option.
Differential Revision: https://reviews.llvm.org/D100367
Simon Pilgrim [Mon, 19 Apr 2021 16:56:42 +0000 (17:56 +0100)]
[Support] BinaryStreamReader.h - remove unnecessary <string> include. NFCI.
We only use StringRef so include that.
Serguei Katkov [Tue, 20 Apr 2021 05:59:44 +0000 (12:59 +0700)]
Re-land [GreedyRA ORE] Add Cost of spill locations into remark
Re-land the patch with a fix of clang test.
Cost of spill location is computed basing on relative branch frequency
where corresponding spill/reload/copy are located.
While the number itself is highly depends on incoming IR,
the total cost can be used when do some changes in RA.
Revert "Revert "[GreedyRA ORE] Add Cost of spill locations into remark""
This reverts commit
680f3d6de79f7dd75ee0cda256a541d18e504a22.
Fraser Cormack [Thu, 15 Apr 2021 16:02:20 +0000 (17:02 +0100)]
[RISCV] Fix missing emergency slots for scalable stack offsets
This patch adds an additional emergency spill slot to RVV code. This is
required as RVV stack offsets may require an additional register to compute.
This patch includes an optimization by @HsiangKai <kai.wang@sifive.com>
to reduce the number of registers required for the computation of stack
offsets from 3 to 2. Otherwise we'd need two additional emergency spill
slots.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D100574
Sander de Smalen [Mon, 19 Apr 2021 09:59:30 +0000 (10:59 +0100)]
[LV] Let selectVectorizationFactor reason directly on VectorizationFactor.
Rather than maintaining two separate values, a `float` for the per-lane
cost and a Width for the VF, maintain a single VectorizationFactor which
comprises the two and also removes the need for converting an integer value
to float.
This simplifies the query when asking if one VF is more profitable than
another when we want to extend this for scalable vectors (which may
require additional options to determine if e.g. a scalable VF of the
some cost, is more profitable than a fixed VF of the same cost).
The patch isn't entirely NFC because it also fixes an issue in
selectEpilogueVectorizationFactor, where the cost passed to ProfitableVFs
no longer truncates the floating-point cost from `float` to `unsigned` to
then perform the calculation on the truncated cost. It now does
a cost comparison with the correct precision.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D100121
Qiu Chaofan [Tue, 20 Apr 2021 08:32:24 +0000 (16:32 +0800)]
[PowerPC] Use mtvsrdd to put callee-saved GPR into VSR
This patch exploits mtvsrdd instruction (available in ISA3.0+) to save
two callee-saved GPR registers into a single VSR, making it more
efficient.
Reviewed By: jsji, nemanjai
Differential Revision: https://reviews.llvm.org/D62565
Jun Ma [Tue, 20 Apr 2021 03:37:06 +0000 (11:37 +0800)]
[DAGCombiner] Support fold zero scalar vector.
This patch changes ISD::isBuildVectorAllZeros to
ISD::isConstantSplatVectorAllZeros which handles zero sclar vector.
TestPlan: check-llvm
Differential Revision: https://reviews.llvm.org/D100813
Jay Foad [Mon, 19 Apr 2021 13:48:20 +0000 (14:48 +0100)]
[AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used
Don't shrink VOP3 instructions if there are any uses of a carry-out
operand, because the shrunken form of the instruction would write the
carry-out to vcc instead of to a virtual register.
Differential Revision: https://reviews.llvm.org/D100760
Luo, Yuanke [Tue, 20 Apr 2021 07:52:29 +0000 (15:52 +0800)]
[X86][AMX] Verify illegal types or instructions for x86_amx.
This patch is related to https://reviews.llvm.org/D100032 which define
some illegal types or operations for x86_amx. There are no arguments,
arrays, pointers, vectors or constants of x86_amx.
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D100472
Arthur Eubanks [Sun, 18 Apr 2021 08:35:52 +0000 (01:35 -0700)]
Explicitly pass type to cast load constant folding result
Previously we would use the type of the pointee to determine what to
cast the result of constant folding a load. To aid with opaque pointer
types, we should explicitly pass the type of the load rather than
looking at pointee types.
ConstantFoldLoadThroughBitcast() converts the const prop'd value to the
proper load type (e.g. [1 x i32] -> i32). Instead of calling this in
every intermediate step like bitcasts, we only call this when we
actually see the global initializer value.
In some existing uses of this API, we don't know the exact type we're
loading from immediately (e.g. first we visit a bitcast, then we visit
the load using the bitcast). In those cases we have to manually call
ConstantFoldLoadThroughBitcast() when simplifying the load to make sure
that we cast to the proper type.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D100718
Qiu Chaofan [Tue, 20 Apr 2021 07:47:54 +0000 (15:47 +0800)]
[PowerPC] Support f128 under VSX
This patch is the last one in backend to support fp128 type in
pre-POWER9 subtargets with VSX, removing temporary option and updating
remaining tests.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D92374
Fraser Cormack [Wed, 14 Apr 2021 08:03:27 +0000 (09:03 +0100)]
[SelectionDAG] Relax constraints on STEP_VECTOR step operand
This patch relaxes the requirement that the STEP_VECTOR step constant
must be of a type at least as large as the vector element type. This
does not permit its use on targets which have legal vector element types
larger than the largest legal scalar type, such as i64 vectors on RV32.
As such, the requirement has been loosened so that the step operand must
be any scalar type so long as the constant immediate is non-negative and
the value fits inside the vector element type.
This limits combining optimizations in certain circumstances but in
practice it's unlikely to be a hindrance.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D100660
Zi Xuan Wu [Tue, 20 Apr 2021 06:42:26 +0000 (14:42 +0800)]
[CSKY 6/n] Add support branch and symbol series instruction
This patch adds basic CSKY branch instructions and symbol address series instructions.
Those two kinds of instruction have relationship between each other, and it involves much work about Fixups.
For now, basic instructions are enabled except for disassembler support.
We would support to generate basic codegen asm firstly and delay disassembler work later.
Differential Revision: https://reviews.llvm.org/D95029
Zi Xuan Wu [Tue, 20 Apr 2021 06:40:46 +0000 (14:40 +0800)]
[CSKY 5/n] Add support for all CSKY basic integer instructions except for branch series
This patch adds basic CSKY integer instructions except for branch series such as bsr, br.
It mainly includes basic ALU, load & store, compare and data move instructions.
Branch series instructions need handle complex symbol operand as following patch later.
Differential Revision: https://reviews.llvm.org/D94007
Zi Xuan Wu [Tue, 20 Apr 2021 06:06:36 +0000 (14:06 +0800)]
[CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter
This basic parser will handle basic instructions with register or immediate operands.
With the addition of CSKYInstPrinter, we can now make use of lit tests.
Differential Revision: https://reviews.llvm.org/D93798
Max Kazantsev [Tue, 20 Apr 2021 06:59:03 +0000 (13:59 +0700)]
[NFC] Restructure code to make it possible to insert other GCs
KareemErgawy-TomTom [Tue, 20 Apr 2021 07:01:43 +0000 (09:01 +0200)]
[MLIR][LinAlg] Detensoring CF cost-model: look forward.
This patch extends the control-flow cost-model for detensoring by
implementing a forward-looking pass on block arguments that should be
detensored. This makes sure that if a (to-be-detensored) block argument
"escapes" its block through the terminator, then the successor arguments
are also detensored.
Reviewed By: silvas
Differential Revision: https://reviews.llvm.org/D100457
Luo, Yuanke [Wed, 7 Apr 2021 12:57:21 +0000 (20:57 +0800)]
[X86][AMX] Add description of x86_amx to LangRef.
Differential Revision: https://reviews.llvm.org/D100032
Max Kazantsev [Tue, 20 Apr 2021 06:07:33 +0000 (13:07 +0700)]
[Test] Add -lcssa run to force LI in GVN
Martin Storsjö [Fri, 16 Apr 2021 10:30:47 +0000 (13:30 +0300)]
[llvm-rc] Fix handling of the /X option to match its documentation and rc.exe
This matches how it's documented in the option listing.
Differential Revision: https://reviews.llvm.org/D100754
Martin Storsjö [Wed, 14 Apr 2021 13:23:50 +0000 (16:23 +0300)]
[llvm-rc] Simplify Opts.td to avoid repetition. NFC.
Differential Revision: https://reviews.llvm.org/D100753
Tobias Gysi [Tue, 20 Apr 2021 05:28:26 +0000 (05:28 +0000)]
[mlir][linalg] update fusion on tensors to support linalg index operations.
The patch replaces the index operations in the body of fused producers and linearizes the indices after expansion.
Differential Revision: https://reviews.llvm.org/D100479
Zakk Chen [Fri, 9 Apr 2021 13:48:29 +0000 (06:48 -0700)]
[RISCV] Handle PseudoVRELOAD and PseudoVSPILL in getInstSizeInBytes.
It's necessary to calculate correct instruction size because
PseudoVRELOAD and PseudoSPILL will be expanded into multiple
instructions.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D100702
Tobias Gysi [Tue, 20 Apr 2021 04:50:43 +0000 (04:50 +0000)]
[mlir][linalg] update drop unit dims to support linalg index operations.
Update the dimensions of the index operations to account for dropped dimensions and replace the index operations of dropped dimensions by zero.
Differential Revision: https://reviews.llvm.org/D100395
Max Kazantsev [Tue, 20 Apr 2021 04:30:17 +0000 (11:30 +0700)]
[Test] Add loop load PRE test with GC pointers
Ben Shi [Tue, 20 Apr 2021 04:11:56 +0000 (12:11 +0800)]
[RISCV][test] Add a new test of addition
Reviewed by: craig.topper
Differential Revision: https://reviews.llvm.org/D100767
Serguei Katkov [Tue, 20 Apr 2021 04:08:24 +0000 (11:08 +0700)]
Revert "[GreedyRA ORE] Add Cost of spill locations into remark"
This reverts commit
328377307ad2da961b3be0f2bbf1814a6f1f4ed3.
This commit causes buildbot failures due to some clang tests are not updated.
Temporary revert to fix clang tests.
xgupta [Tue, 20 Apr 2021 03:57:57 +0000 (09:27 +0530)]
[Docs] Mention LLVM_EXPERIMENTAL_TARGETS_TO_BUILD variable in CMake.rst
Beginners might not aware of this variable and wanted to try a new experimental target.
Although this variable mention in Writing a Backend Documentation. But it becomes easy to search when listed in cmake.rst doc where most variables are listed.
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D100729
Serguei Katkov [Fri, 9 Apr 2021 10:22:36 +0000 (17:22 +0700)]
[GreedyRA ORE] Add Cost of spill locations into remark
Cost of spill location is computed basing on relative branch frequency
where corresponding spill/reload/copy are located.
While the number itself is highly depends on incoming IR,
the total cost can be used when do some changes in RA.
Reviewers: reames, MatzeB, anemet, thegameg
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100020
Jun Ma [Thu, 8 Apr 2021 13:21:42 +0000 (21:21 +0800)]
[AArch64][SVE] Combine add and index_vector
This patch tries to combine pattern add(index_vector(zero, step), dup(X)) into index_vector(X, step)
TestPlan: check-llvm
Differential Revision: https://reviews.llvm.org/D100107
Fangrui Song [Tue, 20 Apr 2021 02:39:10 +0000 (19:39 -0700)]
[lldb] Fix one leak in reproducer
Use a variable of static storage duration to reference an intentionally
leaked variable. A static data area is in the GC-set of various leak
checkers.
This fixes 3 `check-lldb-shell` tests in a `-DLLVM_USE_SANITIZER={Leaks,Address}` build,
e.g. `test/Shell/Reproducer/TestHomeDir.test`
Differential Revision: https://reviews.llvm.org/D100806
clementval [Tue, 20 Apr 2021 01:45:01 +0000 (21:45 -0400)]
[mlir][llvm] Add UnnamedAddr attribute to GlobalOp
This patch add the UnnamedAddr attribute for the GlobalOp in the LLVM
dialect. The attribute is also handled to and from LLVM IR.
This is meant to be used in a follow up patch to lower OpenACC/OpenMP ops to
call to kmp and tgt runtime calls (D100678).
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D100677
Hongtao Yu [Tue, 13 Apr 2021 06:51:44 +0000 (23:51 -0700)]
[CSSPGO] Exclude pseudo probes from slot index
Pseudo probe are currently given a slot index like other regular instructions. This affects register pressure and lifetime weight computation because of enlarged lifetime length with pseudo probe instructions. As a consequence, program could get different code generated w/ and w/o pseudo probes. I'm closing the gap by excluding pseudo probes from stack index and downstream register allocation related passes.
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D100334
Hongtao Yu [Mon, 19 Apr 2021 15:51:57 +0000 (08:51 -0700)]
[CSSPGO] Flip SkipPseudoOp to true for MIR APIs.
Flipping the default value of SkipPseudoOp to true for those MIR APIs to favor maximum performance. Note that certain spots like branch folding and MIR if-conversion is are disabled for better counts quality. For these two optimizations, this is a no-diff change.
The counts quality with SPEC2017 before/after this change is unchanged.
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D100332
Evgenii Stepanov [Wed, 14 Apr 2021 20:11:38 +0000 (13:11 -0700)]
Fix android-x86 library name in asan_device_setup.
https://reviews.llvm.org/D26764 removed i686 variants of compiler-rt
libraries and canonicalized the i386 name.
https://reviews.llvm.org/D37278 partially reverted the previous change
to keep i686 name on Android, but did not update asan_device_setup
script.
This changes fixes asan_device_setup.
Differential Revision: https://reviews.llvm.org/D100505
Dávid Bolvanský [Tue, 20 Apr 2021 00:03:38 +0000 (02:03 +0200)]
[InstCombine] Enhance deduction of alignment for aligned_alloc
This patch improves https://reviews.llvm.org/D76971 (Deduce attributes for aligned_alloc in InstCombine) and implements "TODO" item mentioned in the review of that patch.
> The function aligned_alloc() is the same as memalign(), except for the added restriction that size should be a multiple of alignment.
Currently, we simply bail out if we see a non-constant size - change that.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D100785
Fangrui Song [Mon, 19 Apr 2021 23:36:54 +0000 (16:36 -0700)]
[lldb] Fix demangler leaks in the DWARF AST parser
This fixes 6 check-lldb-shell failures in a `-DLLVM_USE_SANITIZER=Leaks` build.
Differential Revision: https://reviews.llvm.org/D100800
Kamlesh Kumar [Mon, 19 Apr 2021 23:18:34 +0000 (04:48 +0530)]
[libc++] [C++20] [P0586] Implement safe integral comparisons
* https://wg21.link/P0586
Reviewed By: #libc, curdeius, Quuxplusone
Differential Revision: https://reviews.llvm.org/D94511
Nick Lewycky [Mon, 19 Apr 2021 03:51:43 +0000 (20:51 -0700)]
Add a cache of checked AttributeLists.
Differential Revision: https://reviews.llvm.org/D100738
Min-Yih Hsu [Mon, 19 Apr 2021 22:53:52 +0000 (15:53 -0700)]
[M68k] Put M68kDesc as the direct library dependency for disassembler
M68kDisassembler should put M68kDesc as its direct library dependency
since it uses logics releated to code beads Otherwise the build will
fail when building LLVM libraries as shared objects (building LLVM
libraries statically won't have this problem though)
Roman Tereshin [Tue, 11 Aug 2020 06:29:39 +0000 (23:29 -0700)]
Reset NextFnNum in MachineModuleInfo::initialize
In an env that reuses compiler instances for multiple compilations, this
omission results in non-deterministic assembly output (names of the
auto-generated labels) if the order or full set of Modules compiled
varies.
Differential Revision: https://reviews.llvm.org/D100797
zoecarver [Mon, 19 Apr 2021 21:59:32 +0000 (14:59 -0700)]
[libc++][gardening] Replace instances of `\x{AD}`.
This is a NFC.
Differential Revision: https://reviews.llvm.org/D100799
Alexandre Ganea [Mon, 19 Apr 2021 21:43:24 +0000 (17:43 -0400)]
Revert "[clang-scan-deps] Add support for clang-cl"
This reverts commit
bb26fa8c286bf524ed9235c3e293ad22ecf3e984.
Sanjay Patel [Mon, 19 Apr 2021 20:41:27 +0000 (16:41 -0400)]
[PhaseOrdering] add test to show unintended code sinking; NFC
See D87479 for discussion.
Ricky Taylor [Thu, 11 Mar 2021 22:12:47 +0000 (22:12 +0000)]
[M68k] Implement Disassembler
This is an implementation of a disassembler for M68k.
Differential Revision: https://reviews.llvm.org/D98540
Ricky Taylor [Sat, 17 Apr 2021 10:03:34 +0000 (11:03 +0100)]
[M68k] Change printing of absolute memory references
This also includes PC-relative addresses since they are still
referenced as absolute addresses in assembly and converted to
relative addresses by the assembler.
This changes, for example:
- `bra #-2` -> `bra $100`
- `jsr #16` -> `jsr $10`
Differential Revision: https://reviews.llvm.org/D100697
Alexey Bataev [Mon, 19 Apr 2021 21:09:40 +0000 (14:09 -0700)]
Revert "[SLP]Add detection of shuffled/perfect matching of tree entries."
This reverts commit
d6fde913790db898e72e27b51defbc7442f3418a to fix
compiler crashes.
Zequan Wu [Wed, 14 Apr 2021 17:42:50 +0000 (10:42 -0700)]
[ThinLTO] Copy UnnamedAddr when spliting module.
The unnamedaddr property of a function is lost when using
`-fwhole-program-vtables` and thinlto which causes size increase under linker's
safe icf mode.
The size increase of chrome on Linux when switching from all icf to safe icf
drops from 5 MB to 3 MB after this change, and from 6 MB to 4 MB on Windows.
There is a repro:
```
# a.h
struct A {
virtual int f();
virtual int g();
};
# a.cpp
#include "a.h"
int A::f() { return 10; }
int A::g() { return 10; }
# main.cpp
#include "a.h"
int g(A* a) {
return a->f();
}
int main(int argv, char** args) {
A a;
return g(&a);
}
$ clang++ -O2 -ffunction-sections -flto=thin -fwhole-program-vtables -fsplit-lto-unit -c main.cpp -o main.o && clang++ -Wl,--icf=safe -fuse-ld=lld -flto=thin main.o -o a.out && llvm-readobj -t a.out | grep -A 1 -e _ZN1A1fEv -e _ZN1A1gEv
Name: _ZN1A1fEv (480)
Value: 0x201830
--
Name: _ZN1A1gEv (490)
Value: 0x201840
```
Differential Revision: https://reviews.llvm.org/D100498
Emily Shi [Sat, 10 Apr 2021 00:47:54 +0000 (17:47 -0700)]
[compiler-rt] assert max virtual address is <= mmap range size
If these sizes do not match, asan will not work as expected.
If possible, assert at compile time that the vm size is less than or equal to mmap range.
If a compile time assert is not possible, check at run time (for iOS)
rdar://
76477969
Reviewed By: delcypher, yln
Differential Revision: https://reviews.llvm.org/D100239
Alexey Bataev [Wed, 14 Apr 2021 16:44:01 +0000 (09:44 -0700)]
[SLP]Add detection of shuffled/perfect matching of tree entries.
SLP supports perfect diamond matching for the vectorized tree entries
but do not support it for gathered entries and does not support
non-perfect (shuffled) matching with 1 or 2 tree entries. Patch adds
support for this matching to improve cost of the vectorized tree.
Differential Revision: https://reviews.llvm.org/D100495
David Penry [Mon, 19 Apr 2021 20:27:45 +0000 (21:27 +0100)]
[CodeGen] Use ProcResGroup information in SchedBoundary
When the ProcResGroup has BufferSize=0,
1. if there is a subunit in the list of write resources for the
scheduling class, do not attempt to schedule the ProcResGroup.
2. if there is not a subunit in the list of write resources for the
scheduling class, choose a subunit to use instead of the ProcResGroup.
3. having both the ProcResGroup and any of its subunits in the resources
implied by a InstRW is not supported.
Used to model parallel uses from a pool of resources.
Differential Revision: https://reviews.llvm.org/D98976
David Penry [Mon, 19 Apr 2021 20:23:05 +0000 (21:23 +0100)]
[ARM] Use ProcResGroup in Cortex-M7 scheduling model
Used to model structural hazards on FP issue, where some
instructions take up 2 issue slots and others one as well
as similar structural hazards on load issue, where some
instructions take up two load lanes and others one.
Differential Revision: https://reviews.llvm.org/D98977
Philip Reames [Mon, 19 Apr 2021 20:19:39 +0000 (13:19 -0700)]
[funcattrs] Consistently check call site attributes
This is mostly stylistic cleanup after D100226, but not entirely. When skimming the code, I found one case where we weren't accounting for attributes on the callsite at all. I'm also suspicious we had some latent bugs related to operand bundles (which are supposed to be able to *override* attributes on declarations), but I don't have concrete test cases for those, just suspicions.
Aside: The only case left in the file which directly checks attributes on the declaration is the norecurse logic. I left that because I didn't understand it; it looks obviously wrong, so I suspect I'm misinterpreting the intended semantics of the attribute.
Differential Revision: https://reviews.llvm.org/D100689
Stephen Kelly [Sun, 18 Apr 2021 12:15:01 +0000 (13:15 +0100)]
[AST] Fix comparison to of SourceRanges in container
Differential Revision: https://reviews.llvm.org/D100723
Philip Reames [Mon, 19 Apr 2021 20:03:24 +0000 (13:03 -0700)]
[rs4gc] Fix a latent bug around attribute stripping for intrinsics
This change fixes a latent bug which was exposed by a change currently in review (https://reviews.llvm.org/D99802#2685032).
The story on this is a bit involved. Without this change, what ended up happening with the pending review was that we'd strip attributes off intrinsics, and then selectiondag would fail to lower the intrinsic. Why? Because the lowering of the intrinsic relies on the presence of the readonly attribute. We don't have a matcher to select the case where there's a glue node needed.
Now, on the surface, this still seems like a codegen bug. However, here it gets fun. I was unable to reproduce this with a standalone test at all, and was pretty much struck until skatkov provided the critical detail. This reproduces only when RS4GC and codegen are run in the same process and context. Why? Because it turns out we can't roundtrip the stripped attribute through serialized IR!
We'll happily print out the missing attribute, but when we parse it back, the auto-upgrade logic has a side effect of blindly overwriting attributes on intrinsics with those specified in Intrinsics.td. This makes it impossible to exercise SelectionDAG from a standalone test case.
At this point, I decided to treat this an RS4GC bug as a) we don't need to strip in this case, and b) I could write a test which shows the correct behavior to ensure this doesn't break again in the future.
As an aside, I'd originally set out to handle libfuncs too - since in theory they might have the same issues - but backed away quickly when I realized how the semantics of builtin, nobuiltin, and no-builtin-x all interacted. I'm utterly convinced that no part of the optimizer handles that correctly, and decided not to open that can of worms here.
Nikita Popov [Mon, 19 Apr 2021 20:09:15 +0000 (22:09 +0200)]
[InstCombine] Fold multiuse shr eq zero
The single-use case is handled implicity by converting the icmp
into a mask check first. When comparing with zero in particular,
we don't need the one-use restriction, as we only produce a single
icmp.
https://alive2.llvm.org/ce/z/MSixcm
https://alive2.llvm.org/ce/z/GwpG0M
Nikita Popov [Mon, 19 Apr 2021 19:01:13 +0000 (21:01 +0200)]
[InstCombine] Add tests for multiuse shr eq zero (NFC)
The exact case is folded, the inexact one is not.
Stephen Kelly [Sun, 18 Apr 2021 10:02:41 +0000 (11:02 +0100)]
[AST] Update introspection API to use const-ref for copyable types
Differential Revision: https://reviews.llvm.org/D100720
Martin Storsjö [Fri, 26 Feb 2021 10:56:41 +0000 (12:56 +0200)]
[libcxx] [test] Ifdef out tests that rely on perms::none on directories for triggering errors
On Windows, one can't use perms::none on a directory to trigger
failures to read the directory entries.
These remaining tests can't use GetWindowsInaccessibleDir() sensibly,
e.g. for tests that rely on toggling accessibility back and forth during
the test, or where the semantics of the dir provided by
GetWindowsInaccessibleDir() doesn't allow for running the ifdeffed tests
meaningfully.
Differential Revision: https://reviews.llvm.org/D97538
Thomas Lively [Mon, 19 Apr 2021 19:43:58 +0000 (12:43 -0700)]
[WebAssembly] Use v128.const instead of splats for constants
We previously used splats instead of v128.const to materialize vector constants
because V8 did not support v128.const. Now that V8 supports v128.const, we can
use v128.const instead. Although this increases code size, it should also
increase performance (or at least require fewer engine-side optimizations), so
it is an appropriate change to make.
Differential Revision: https://reviews.llvm.org/D100716
Martin Storsjö [Thu, 15 Apr 2021 08:16:28 +0000 (11:16 +0300)]
[libcxx] Base MSVC autolinking on _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS
Previously the decision of which library to try to autolink was
based on _DLL, however the _DLL define (which is set by the compiler)
is tied to whether using a dynamically linked CRT or not, and the choice
of dynamic or static CRT is entirely orthogonal to whether libc++ is
linked dynamically or statically.
If _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS isn't defined, then all
declarations are decorated with dllimport, and there's no doubt that
the DLL version of the library is what must be linked.
_LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS is defined if building with
LIBCXX_ENABLE_SHARED disabled, and thus the static library is what
should be linked.
If defining _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS manually but wanting
to link against the DLL version of the library, that's not a canonical
configuration, and then it's probably reasonable to manually define
_LIBCPP_NO_AUTO_LINK too, and manually link against the desired
library.
This fixes, among other issues, running tests for the library if
built with LIBCXX_ENABLE_STATIC disabled.
Differential Revision: https://reviews.llvm.org/D100539
Nicolas Vasilache [Mon, 19 Apr 2021 19:30:29 +0000 (19:30 +0000)]
[mlir][python] ExecutionEngine can dump to object file
Differential Revision: https://reviews.llvm.org/D100786
Jonas Devlieghere [Mon, 19 Apr 2021 19:24:58 +0000 (12:24 -0700)]
[lldb] Stop unsetting LLDB_DEBUGSERVER_PATH from TestLaunchProcessPosixSpawn
We no longer need this after Pavel's change to automatically find debug
servers to test. (3ca7b2d)
Jinsong Ji [Mon, 19 Apr 2021 18:57:18 +0000 (18:57 +0000)]
[PowerPC] Disable relative lookup table converter pass for AIX
XCOFF hasn't implemented lowerRelativeReference.
So we need to disable new pass introduced by https://reviews.llvm.org/D94355 for
AIX for now.
Reviewed By: gulfem
Differential Revision: https://reviews.llvm.org/D100584
Jonas Devlieghere [Mon, 19 Apr 2021 19:22:31 +0000 (12:22 -0700)]
[lldb] Update breakpoint_function_callback.test for different error message
Adjust for the Lua error message printed by Lua 5.4.3.
Jonas Devlieghere [Fri, 16 Apr 2021 21:10:26 +0000 (14:10 -0700)]
[lldb] Print the fixed address if symbolication fails in DumpDataExtractor
When formatting memory with as eFormatAddressIn and symbolication fails,
fix the code address and print the symbol it points to, if any.
Emily Shi [Fri, 9 Apr 2021 00:49:22 +0000 (17:49 -0700)]
[compiler-rt][asan] use full vm range on apple silicon macs
We previously shrunk the mmap range size on ios, but those settings got inherited by apple silicon macs.
Don't shrink the vm range on apple silicon Mac since we have access to the full range.
Also don't shrink vm range for iOS simulators because they have the same range as the host OS, not the simulated OS.
rdar://
75302812
Reviewed By: delcypher, kubamracek, yln
Differential Revision: https://reviews.llvm.org/D100234
madhur13490 [Fri, 16 Apr 2021 08:42:38 +0000 (14:12 +0530)]
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
This patch removes -fixed-abi check for indirect calls
and also adds queue-ptr which is required for indirect calls to work.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D100633
Pavel Iliin [Tue, 9 Mar 2021 00:18:27 +0000 (00:18 +0000)]
[AArch64] Peephole rule to remove redundant cmp after cset.
Comparisons to zero or one after cset instructions can be safely
removed in examples like:
cset w9, eq cset w9, eq
cmp w9, #1 ---> <removed>
b.ne .L1 b.ne .L1
cset w9, eq cset w9, eq
cmp w9, #0 ---> <removed>
b.ne .L1 b.eq .L1
Peephole optimization to detect suitable cases and get rid of that
comparisons added.
Differential Revision: https://reviews.llvm.org/D98564
Yaxun (Sam) Liu [Mon, 8 Mar 2021 17:29:03 +0000 (12:29 -0500)]
[CUDA][HIP] Allow non-ODR use of host var in device
Reviewed by: Artem Belevich, Richard Smith
Differential Revision: https://reviews.llvm.org/D98193
peter klausler [Thu, 15 Apr 2021 21:11:47 +0000 (14:11 -0700)]
[flang] Define missing & needed IEEE_ARITHMETIC symbols
Define IEEE_IS_NAN, IEEE_IS_FINITE, & IEEE_REM.
Differential Revision: https://reviews.llvm.org/D100599
LLVM GN Syncbot [Mon, 19 Apr 2021 18:35:15 +0000 (18:35 +0000)]
[gn build] Port
e0adf7e06a9e
Nikita Popov [Sat, 17 Apr 2021 13:25:29 +0000 (15:25 +0200)]
[LICM] Make capture check more precise
During store promotion, we check whether the pointer was captured
to exclude potential reads from other threads. However, we're only
interested in captures before or inside the loop. Check this using
PointerMayBeCapturedBefore against the loop header.
Differential Revision: https://reviews.llvm.org/D100706
zoecarver [Mon, 19 Apr 2021 18:28:27 +0000 (14:28 -0400)]
[libc++][NFC] Move incrementable_traits and indirectly_readable_traits into separate headers.
Differential Revision: https://reviews.llvm.org/D100682
Craig Topper [Mon, 19 Apr 2021 18:06:58 +0000 (11:06 -0700)]
[RISCV] Fix mistake in comment. NFC
Philip Reames [Mon, 19 Apr 2021 18:14:39 +0000 (11:14 -0700)]
Update a test for auto-update format change
Craig Topper [Mon, 19 Apr 2021 17:52:22 +0000 (10:52 -0700)]
[RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte.
As noted in the FIXME there's a sort of agreement that the any
extra bits stored will be 0.
The generated code is pretty terrible. I was really hoping we
could use a tail undisturbed trick, but tail undisturbed no
longer applies to masked destinations in the current draft
spec.
Fingers crossed that it isn't common to do this. I doubt IR
from clang or the vectorizer would ever create this kind of store.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D100618
Arthur Eubanks [Mon, 19 Apr 2021 18:03:19 +0000 (11:03 -0700)]
[test] Make global in split-gep-and-gvn.ll not constant
An upcoming change will cause loads from a constant zeroinitializer
global to be constant folded, breaking this test.
Fangrui Song [Mon, 19 Apr 2021 17:56:48 +0000 (10:56 -0700)]
[lld] Delete unused includes. NFC
Jessica Paquette [Tue, 13 Apr 2021 17:11:25 +0000 (10:11 -0700)]
[AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP
This is a partial port of AArch64TargetLowering::LowerCTPOP.
This custom lowering tries to uses NEON instructions to give a more efficient
CTPOP lowering when possible.
In the non-NEON/noimplicitfloat case, this should use the generic lowering
(see: https://godbolt.org/z/GcaPvWe4x). I think that's worth implementing after
implementing the widening code for s16/s8 though.
Differential Revision: https://reviews.llvm.org/D100399
Nick Desaulniers [Mon, 19 Apr 2021 17:36:33 +0000 (10:36 -0700)]
[TargetLowering] move "o" and "X" constraint handling to base class
These constraints are machine agnostic; there's no reason to handle
these per-arch. If arches don't support these constraints, then they
will fail elsewhere during instruction selection. We don't need virtual
calls to look these up; TargetLowering::getInlineAsmMemConstraint should
only be overridden by architectures with additional unique memory
constraints.
Reviewed By: echristo, MaskRay
Differential Revision: https://reviews.llvm.org/D100416
Jessica Paquette [Tue, 13 Apr 2021 17:03:17 +0000 (10:03 -0700)]
[AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv
It turns out we actually import a bunch of selection code for intrinsics. The
imported code checks that the register banks on the G_INTRINSIC instruction
are correct. If so, it goes ahead and selects it.
This adds code to AArch64RegisterBankInfo to allow us to correctly determine
register banks on intrinsics which have known register bank constraints.
For now, this only handles @llvm.aarch64.neon.uaddlv. This is necessary for
porting AArch64TargetLowering::LowerCTPOP.
Also add a utility for getting the intrinsic ID from a G_INTRINSIC instruction.
This seems a little nicer than having to know about how intrinsic instructions
are structured.
Differential Revision: https://reviews.llvm.org/D100398
Jonas Devlieghere [Mon, 19 Apr 2021 17:20:13 +0000 (10:20 -0700)]
[lldb] Support "absolute memory address" images in crashlog.py
The binary image list contains the following entry when a frame is not
found in any know binary image:
{
"size" : 0,
"source" : "A",
"base" : 0,
"uuid" : "
00000000-0000-0000-0000-
000000000000"
}
Note that this object is missing the name and path keys. This patch
makes the JSON parser resilient against their absence.