Marek Olšák [Tue, 26 Sep 2023 00:09:17 +0000 (20:09 -0400)]
radeonsi: fix compute-only contexts
We can't skip redundant register updates on compute queues, at least
not all of them.
Fixes:
315231b5a519bdc14 - radeonsi: eliminate redundant compute SH register changes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25390>
Faith Ekstrand [Thu, 28 Sep 2023 15:13:31 +0000 (10:13 -0500)]
nvk: Init pipelineCacheUUID
Fixes:
968cefbff113 ("nvk: Cache NIR shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25458>
Martin Roukala (né Peres) [Sun, 17 Sep 2023 10:55:34 +0000 (13:55 +0300)]
radv/ci: add a manual job for vkd3d-proton on navi31
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25266>
Martin Roukala (né Peres) [Sun, 17 Sep 2023 10:50:52 +0000 (13:50 +0300)]
radv/ci: add a manual job to run vkcts on navi31
We currently only have a single navi31, but we'll get more in the
next month or so.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25266>
Martin Roukala (né Peres) [Wed, 27 Sep 2023 07:01:02 +0000 (10:01 +0300)]
radv/ci: update the vkcts gfx1100 flake/fail lists
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25266>
Timothy Arceri [Mon, 25 Sep 2023 08:18:44 +0000 (18:18 +1000)]
glsl: remove now unused varying linker code
All of this varying linking code has now been ported to the NIR linker.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Timothy Arceri [Mon, 25 Sep 2023 00:57:15 +0000 (10:57 +1000)]
glsl: switch to nir linkers cross_validate_outputs_to_inputs()
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Timothy Arceri [Mon, 25 Sep 2023 00:45:24 +0000 (10:45 +1000)]
glsl: implement cross_validate_outputs_to_inputs() in nir linker
This is mostly a direct port of the GLSL IR code there are only
2 real functional changes.
1. The direct use of mesa symbol_table instead of glsl_symbol_table.
However since none of the extra functionality offered by
glsl_symbol_table was ever used here this can be seen as an
improvement.
2. Because interface blocks are lowered before this new nir linker
sees them we must explicitly skip them (they are validated
elsewhere) to avoid errors.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Timothy Arceri [Mon, 25 Sep 2023 00:37:05 +0000 (10:37 +1000)]
nir: add used field to nir variables
Will be use in a following path by the glsl nir based linker.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Timothy Arceri [Mon, 25 Sep 2023 00:16:15 +0000 (10:16 +1000)]
glsl: move is_gl_identifier() to linker_util
This had started to multiply around the NIR linker. Here we move it to a
common helper shared by GLSL IR and NIR.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Timothy Arceri [Mon, 25 Sep 2023 00:04:24 +0000 (10:04 +1000)]
glsl: move interpolation_string() to linker_util
Moving it here allows us to use in in the NIR linker too.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Timothy Arceri [Fri, 22 Sep 2023 06:07:25 +0000 (16:07 +1000)]
nir: copy explicit_invariant flag to nir vars
This will be used in the following patch.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
Samuel Pitoiset [Tue, 26 Sep 2023 14:37:28 +0000 (16:37 +0200)]
radv: stop skip emitting CB states when there is no color attachment
This is actually wrong. For example, if there is a DCC decompress
draw followed by a draw without any color attachments,
CB_COLOR_CONTROL.MODE is still CB_DCC_DECOMPRESS but it should be
CB_DISABLED. For some reasons, this hangs on RDNA3 (VM faults are also
reported through dmesg).
This fixes GPU hangs with Resident Evil 6, Star Wars The Old Republic
and probably more games on RDNA3.
Strictly speaking, I don't think this dynamic state optimization is
worth a try, even for other states, and I think it would be safer to
remove it completely.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9335
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8327
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9878
Fixes:
c08082e8615 ("radv: ignore all CB dynamic states when there is no color attachments")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25402>
Mike Blumenkrantz [Wed, 27 Sep 2023 18:43:09 +0000 (14:43 -0400)]
glx: XFree visual info
cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25441>
Cong Liu [Wed, 27 Sep 2023 07:30:14 +0000 (15:30 +0800)]
r300: Fix out-of-bounds access in ntr_emit_store_output()
This patch resolves the problem by modifying the for loop condition
to ensure that it stays within the bounds of the array (i.e., i < 4)
Signed-off-by: Cong Liu <liucong2@kylinos.cn>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25419>
Eric Engestrom [Wed, 27 Sep 2023 13:14:14 +0000 (14:14 +0100)]
ci/zink+radv: document flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25427>
Christian Gmeiner [Thu, 31 Aug 2023 13:38:04 +0000 (15:38 +0200)]
isaspec: python does not need ';'
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25437>
Ian Romanick [Wed, 26 Jul 2023 21:42:59 +0000 (14:42 -0700)]
spirv: Track when a shader has a cooperative matrix
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Caio Oliveira [Sat, 17 Jun 2023 00:02:39 +0000 (17:02 -0700)]
spirv: Implement SPV_KHR_cooperative_matrix
Includes a modified version of using extract/insert for OpLoad/OpStore
from Ian.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (earlier version)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (earlier version)
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Caio Oliveira [Sat, 23 Sep 2023 08:19:26 +0000 (01:19 -0700)]
spirv: Let vtn_ssa_value hold references to variables
In certain cases, we have complex opaque objects that are loaded
into (SPIR-V) SSA values. To represent these, we now can store a
reference to a variable in vtn_ssa_value.
Also implements a few operations we know will have to be supported,
like Select and Copy.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Caio Oliveira [Sat, 17 Jun 2023 00:22:04 +0000 (17:22 -0700)]
spirv: Expose some memory related functions in vtn_private.h
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Caio Oliveira [Tue, 8 Aug 2023 18:02:33 +0000 (11:02 -0700)]
nir: Handle cooperative matrix in various passes
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Caio Oliveira [Tue, 8 Aug 2023 18:02:14 +0000 (11:02 -0700)]
nir: Add new intrinsics for Cooperative Matrix
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Caio Oliveira [Wed, 31 May 2023 06:26:14 +0000 (23:26 -0700)]
compiler/types: Add support for Cooperative Matrix types
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
Paulo Zanoni [Mon, 14 Aug 2023 16:41:11 +0000 (09:41 -0700)]
anv: enable sparse resources by default
This of course only applies to xe.ko. There is no reason to keep it
disabled by default.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
Paulo Zanoni [Thu, 20 Jul 2023 21:30:16 +0000 (14:30 -0700)]
anv/sparse: add INTEL_DEBUG=sparse
This pollutes stderr a lot, but I've used it countless times while
developing this code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
Paulo Zanoni [Mon, 7 Aug 2023 22:07:37 +0000 (15:07 -0700)]
anv/sparse: get ready to issue a single vm_bind ioctl per non-opaque bind
Game testing shows it's common for this operation to result in
multiple bind regions, so try to use a single ioctl when we can.
Actual testing reveals 136 shader-related tests fail when we actually
do this, so for now keep doing a single bind per ioctl while leaving a
very easy way to the desired behavior when we figure this out.
It should also be possible to go even higher-level and do this at the
anv_queue_submit_sparse_bind_locked() layer, but that should happen in
future commits.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
Paulo Zanoni [Wed, 19 Apr 2023 00:26:05 +0000 (17:26 -0700)]
anv/sparse: add the initial code for Sparse Resources
This giant patch implements a huge chunk of the Vulkan Sparse
Resources API. I previously had this as a nice series of many smaller
patches that evolved as the xe.ko added more features, but once I was
asked to squash some of the major reworks I realized I wouldn't be
able easily rewrite history, so I just squased basically the whole
series into a giant patch. I may end up splitting this again later if
I find a way to properly do it.
If we want to support the DX12 API through vkd3d we need to support
part of the the Sparse Resources API. If we don't, a bunch of Steam
games won't work.
For now we only support the xe.ko backend, but the vast majority of
the code is KMD-independent and so an i915.ko implementation would use
most of what's here, just extending the part that binds and unbinds
memory.
v2+: There's no way to sanely track the version history of this patch
in this commit message. Please refer to Gitlab.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
Paulo Zanoni [Mon, 25 Sep 2023 20:45:06 +0000 (13:45 -0700)]
intel/isl: simplify the check for maximum surface size
The only thing that changes between these 3 checks is the size.
This entire patch was suggested by Kenneth Graunke, I just converted
his gitlab comment to a git commit.
Credits-to: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
Paulo Zanoni [Fri, 21 Apr 2023 23:33:00 +0000 (16:33 -0700)]
intel/isl: add ISL_SURF_USAGE_SPARSE_BIT
Vulkan Sparse resources have their own set of rules, so here we try to
make ISL aware of them through ISL_SURF_USAGE_SPARSE_BIT.
The big deal here is when some image ends up not using Tile64 nor
TileYs. Previously Ys was not supported on TGL at all, and Tile64 did
not have support for 3D. Now we still have some formats that end up
not being used with either Tile64 and Ys, but need to support Sparse
on them (e.g., YUV on Tile64). In the future we may have new tiling
formats or hardware restrictions that would force this case to happen
again.
So here we do some adjustments so we can make sparse work with other
tiling formats, although with limited functionality (e.g., those
formats may be restricted to opaque binds, and certainly don't support
the standard block shapes).
v2: before we had Ys support, we had defined TGL's block size as 4k.
v3: move the size_B chunk to before nte notify_failure() checks (Ken).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
Faith Ekstrand [Wed, 27 Sep 2023 20:10:22 +0000 (15:10 -0500)]
nvk: Cache NIR shaders
We can't cache shader binaries just yet but this at least lets us cache
the output of spirv_to_nir and the initial optimize.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
Faith Ekstrand [Wed, 27 Sep 2023 20:09:53 +0000 (15:09 -0500)]
nvk: Add a default pipeline cache
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
Faith Ekstrand [Wed, 27 Sep 2023 19:48:29 +0000 (14:48 -0500)]
nvk: Re-structure early shader compilation a bit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
Faith Ekstrand [Wed, 27 Sep 2023 19:28:05 +0000 (14:28 -0500)]
nvk: Hook up the disk cache
This won't actually do much yet because we don't have pipeline caches
yet but it turns on the infrastructure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
Faith Ekstrand [Wed, 27 Sep 2023 17:45:39 +0000 (12:45 -0500)]
nvk: Store a 20-bit driver_build_sha in nvk_instance
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
Timothy Arceri [Tue, 26 Sep 2023 04:47:50 +0000 (14:47 +1000)]
nir: fix typo in comment
The variable is unused or dead, not used.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25414>
antonino [Thu, 17 Aug 2023 13:09:15 +0000 (15:09 +0200)]
vulkan: Handle vkSetDebugUtilsObjectNameEXT on WSI objects
Some WSI objects don't extend `vk_object_base` therefore they need
special handling.
Fixes:
3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
antonino [Thu, 17 Aug 2023 13:07:04 +0000 (15:07 +0200)]
vulkan: Extend vkGet/SetPrivateDataEXT handling to VkSurface
VkSurface is handled by WSI and it doesn't extend `vk_object_base` so it
needs special handling.
Fixes:
3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
antonino [Thu, 17 Aug 2023 13:06:18 +0000 (15:06 +0200)]
vulkan: Extend vkGet/SetPrivateDataEXT handling to all platforms
Non-android platforms use mesa WSI, however some WSI object still don't
extend `vk_object_base` so they still need special handling.
Fixes:
3c87618d357 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
Dave Airlie [Wed, 27 Sep 2023 05:30:05 +0000 (15:30 +1000)]
llvmpipe/cs: migrate cs image handle to common jit code.
This moves some of the code over, and uses the generic paths.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
Dave Airlie [Wed, 27 Sep 2023 05:26:47 +0000 (15:26 +1000)]
llvmpipe/cs: migrate to generic jit texture from pipe code.
This moves some cs specific bits to the generic code and uses it.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
Marcin Ślusarz [Mon, 20 Mar 2023 10:32:07 +0000 (11:32 +0100)]
intel/compiler: mask GS URB handles at thread payload construction
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Wed, 1 Feb 2023 13:56:56 +0000 (14:56 +0100)]
intel/compiler/mesh: implement IO for xe2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Wed, 1 Feb 2023 13:40:59 +0000 (14:40 +0100)]
intel/compiler/mesh: fix position of output URB handle for xe2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Thu, 29 Sep 2022 00:07:32 +0000 (17:07 -0700)]
intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB reads.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Wed, 28 Sep 2022 23:50:41 +0000 (16:50 -0700)]
intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB writes.
Rework:
* Marcin: update emit_urb_indirect_vec4_write
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Wed, 28 Sep 2022 23:38:35 +0000 (16:38 -0700)]
intel/fs: Specify number of data components of logical URB writes via control immediate.
This is what most logical SEND messages do when they take a variable
number of components. 'inst->mlen' is expected to be zero for logical
SEND opcodes, which are expected to behave like plain arithmetic
operations, so certain automated transformations (like SIMD lowering)
can manipulate them without opcode-specific special-casing.
Guessing the number of components from 'inst->mlen' has other
disadvantages, because it requires duplicating the logic that infers
the message payload size in every use of the instruction -- Instead we
can just do the computation once during logical send lowering. In
addition on LNL platform this causes the 'inst->mlen' field of URB
writes to have units inconsistent with every other SEND instruction,
which is likely to lead to confusion and bugs down the road.
Rework:
* Marcin: update emit_urb_indirect_vec4_write
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Francisco Jerez [Thu, 29 Sep 2022 00:10:25 +0000 (17:10 -0700)]
intel/fs/xe2+: Fix URB writes with 0 data components.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Caio Oliveira [Thu, 8 Sep 2022 03:37:26 +0000 (20:37 -0700)]
intel/compiler/xe2: Update TCS ICP handle code to support SIMD16
Rework:
* Use ffs(grf_size_bytes) (s-b Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Caio Oliveira [Wed, 7 Sep 2022 07:21:20 +0000 (00:21 -0700)]
intel/compiler/xe2: Fix URB writes in TCS
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Caio Oliveira [Sat, 27 Aug 2022 02:02:16 +0000 (19:02 -0700)]
intel/compiler/xe2: URB fence uses LSC now
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Ian Romanick [Fri, 29 Jul 2022 00:44:06 +0000 (17:44 -0700)]
intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8
v2: Account for 512b physical registers which causes the URB handle to be in FIXED_GFR 2 instead of 1.
XXX - Use fs_builder::vgrf() instead of open-coded dispatch_width calculations.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Kenneth Graunke [Thu, 8 Sep 2022 00:48:07 +0000 (17:48 -0700)]
intel/fs: Fix Xe2 URB read/lowering with per-slot offsets
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Fri, 5 Aug 2022 21:58:09 +0000 (14:58 -0700)]
intel/compiler: Use enum xe2_lsc_cache_load on xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Fri, 5 Aug 2022 21:31:10 +0000 (14:31 -0700)]
intel/compiler: Add enum xe2_lsc_cache_load
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Thu, 8 Sep 2022 00:39:31 +0000 (17:39 -0700)]
intel/compiler: Use enum xe2_lsc_cache_store on xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Jordan Justen [Fri, 5 Aug 2022 21:18:43 +0000 (14:18 -0700)]
intel/compiler: Add enum xe2_lsc_cache_store
Rework:
* Rohan: Fix enum value for L1WB_L3WB
* Fix write-through comments (Ken)
Ref: bspec 71167
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Fri, 12 Aug 2022 14:02:50 +0000 (16:02 +0200)]
intel/compiler: add initial support for URB_LOGICAL_SRC_CHANNEL_MASK to lower_urb_write_logical_send_xe2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Marcin Ślusarz [Fri, 12 Aug 2022 14:00:38 +0000 (16:00 +0200)]
intel/compiler: add lsc_msg_desc_wcmask
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Ian Romanick [Wed, 20 Jul 2022 17:21:21 +0000 (10:21 -0700)]
intel/compiler/xe2: Handle new URB write messages
Rework:
* idr v1: Fix compilation error.
* idr v2: Add support for per-channel offsets.
* idr v3: get_lowered_simd_width is 16 on Xe2+.
* idr v4: Add disassembly support. Add validation support.
* Sqaushed in changes Marcin Ślusarz's patches:
* "intel/compiler: skip adding 0 to payload address"
* "intel/compiler/xe2: drop masking off top 8 bits of URB handle"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Ian Romanick [Mon, 25 Jul 2022 17:03:39 +0000 (10:03 -0700)]
intel/compiler/xe2: Handle new URB read messages
Rework:
* Sqaushed in changes Marcin Ślusarz's patches:
* "intel/compiler: skip adding 0 to payload address"
* "intel/compiler/xe2: drop masking off top 8 bits of URB handle"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
Konstantin Seurer [Fri, 18 Aug 2023 10:44:57 +0000 (12:44 +0200)]
vulkan: Remove vk_get_physical_device_core_1_*_feature_ext
It's unused.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>
Konstantin Seurer [Wed, 13 Sep 2023 15:07:32 +0000 (17:07 +0200)]
hasvk: Use the common GetPhysicalDeviceFeatures2 implementation
Reviewed-by: Julia Tatz <tatz.j@northeastern.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>
Rhys Perry [Tue, 26 Sep 2023 18:36:21 +0000 (19:36 +0100)]
nir/algebraic: optimize u2u32(a >> 32)
fossil-db (navi21):
Totals from 352 (0.44% of 79330) affected shaders:
Instrs: 271816 -> 271240 (-0.21%); split: -0.28%, +0.07%
CodeSize: 1546520 -> 1544448 (-0.13%); split: -0.23%, +0.09%
SpillVGPRs: 832 -> 827 (-0.60%); split: -1.08%, +0.48%
Latency: 4037120 -> 4021748 (-0.38%); split: -0.41%, +0.03%
InvThroughput: 1369540 -> 1362066 (-0.55%); split: -0.59%, +0.04%
VClause: 6476 -> 6471 (-0.08%); split: -0.12%, +0.05%
SClause: 6798 -> 6794 (-0.06%)
Copies: 44828 -> 44630 (-0.44%); split: -0.89%, +0.45%
Branches: 8845 -> 8844 (-0.01%); split: -0.05%, +0.03%
PreSGPRs: 14684 -> 14659 (-0.17%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>
Rhys Perry [Tue, 26 Sep 2023 18:29:37 +0000 (19:29 +0100)]
nir/lower_int64: fix find_lsb(0)
If the high 32 bits were zero, this would be umin(find_lsb(lo), 31). This
evaluates to 31 if lo is also zero, instead of -1.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes:
9293d8e64bc7 ("nir: Add find_lsb lowering to nir_lower_int64.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>
wangra [Wed, 27 Sep 2023 17:11:00 +0000 (13:11 -0400)]
tu/kgsl: Fix bitfield of DITHER_MODE_MRT6
The enum `adreno_rb_dither_mode` needs 2 bits, change the `high` to 13 to make sure 2 bits are used for `DITHER_MODE_MRT6`
Fixes:
e03259974e2f2c8e8c0295f8dab56d88e7bd896c ("freedreno: Generate headers from xml files")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25439>
Jordan Justen [Thu, 8 Sep 2022 08:37:04 +0000 (01:37 -0700)]
anv: Print warning that Xe2 is not supported rather than failing
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Wed, 29 Jun 2022 08:51:36 +0000 (01:51 -0700)]
anv: Build for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Wed, 6 Jul 2022 01:57:28 +0000 (18:57 -0700)]
anv: Disable Ray Tracing on xe2 until our compiler supports Xe2 RT
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Thu, 30 Jun 2022 00:34:44 +0000 (17:34 -0700)]
anv/blorp: Use anv_genX to set device->blorp.exec
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Jordan Justen [Wed, 29 Jun 2022 08:35:06 +0000 (01:35 -0700)]
iris: Build for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
Lionel Landwerlin [Wed, 27 Sep 2023 12:42:32 +0000 (15:42 +0300)]
iris: add missing workaround for 3DSTATE_LINE_STIPPLE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>
Lionel Landwerlin [Wed, 27 Sep 2023 12:42:21 +0000 (15:42 +0300)]
anv: add missing workaround for 3DSTATE_LINE_STIPPLE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>
Lionel Landwerlin [Wed, 27 Sep 2023 12:53:25 +0000 (15:53 +0300)]
anv/iris: widen Wa_14015946265 to Gfx11+
We missed out that ICL+ added a programming requiring a CS_STALL.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25426>
Connor Abbott [Fri, 1 Sep 2023 17:10:56 +0000 (19:10 +0200)]
tu: Expose VK_KHR_maintenance5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Wed, 27 Sep 2023 09:03:39 +0000 (11:03 +0200)]
freedreno/ci: Skip dEQP-VK.info.device_extensions
Copied from anv and radv.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 17:10:39 +0000 (19:10 +0200)]
tu: Add maintenance5 properties
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 17:09:31 +0000 (19:09 +0200)]
tu: Check for DEVICE_LOST in vkGetEventStatus()
Required by maintenance5.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 14:07:30 +0000 (16:07 +0200)]
tu: Support VkPipelineCreateFlags2CreateInfoKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:46:37 +0000 (15:46 +0200)]
tu: Use new buffer usage flags
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:32:40 +0000 (15:32 +0200)]
tu: Implement vkGetRenderingAreaGranularityKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:31:57 +0000 (15:31 +0200)]
tu: Implement vkGetImageSubresourceLayout2KHR and vkGetDeviceImageSubresourceLayoutKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:31:08 +0000 (15:31 +0200)]
tu: Implement vkCmdBindIndexBuffer2KHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:30:11 +0000 (15:30 +0200)]
tu: Allow VK_WHOLE_SIZE in tu_CmdBindVertexBuffers2EXT pSizes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:28:27 +0000 (15:28 +0200)]
tu/clear_blit: Allow VK_REMAINING_ARRAY_LAYERS as layerCount
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 13:23:13 +0000 (15:23 +0200)]
tu/clear_blit: Fix staging image view layer count
This seems to be a mistake that didn't affect anything.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 12:22:18 +0000 (14:22 +0200)]
freedreno/fdl: Support PIPE_FORMAT_R5G5B5A1_UNORM on a6xx
This is just a different swap of the same format.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 17:08:57 +0000 (19:08 +0200)]
tu: Support clearing A8_UNORM
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Fri, 1 Sep 2023 12:20:19 +0000 (14:20 +0200)]
freedreno/fdl: Use A8_UNORM HW format for sampling
We've already been using this for 3d blits on turnip and it works fine.
There's no need to emulate it, and it won't work on turnip where we
can't swizzle the border colors.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Connor Abbott [Wed, 27 Sep 2023 12:17:19 +0000 (14:17 +0200)]
zink: Rework color clamping and conversion
Before this commit, zink_format_clamp_channel_color() ignored the format
swizzle, so it was assuming that for emulated formats like alpha,
alpha-luminance etc. that the color had already been swizzled to match
the internal format rather than the emulated one. It's somewhat confusing
that passing in e.g. A8_UNORM actually means R8_UNORM, and led to a bug
when using VK_FORMAT_A8_UNORM for texture border colors because we
didn't swizzle it back. It also wouldn't have worked for media formats
like R10X6G10X6 due to the void channel in the middle.
In order to fix this, we need to untangle the mess in its users.
For convert_color() used when clearing, this means we now need to clamp
and then swizzle instead of swizzle and then clamp, and we can drop the
hack for A8_UNORM.
For texture border colors, the state tracker duplicates colors for the
emulated formats to help drivers, which zink was previously relying on,
but fixing zink_format_clamp_channel_color() breaks this because it
assumes that those duplicated colors are useless and clamps them.
However, because we know the format we can just swizzle the border color
ourself, which convert_color() was already doing. So, we pull that out
into a common zink_convert_color() function that handles both clamping
and format emulation, and have both clearing and border color handling
use it.
This fixes A8_UNORM in turnip+zink once we enable it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
Erico Nunes [Wed, 20 Sep 2023 20:06:39 +0000 (22:06 +0200)]
v3dv: allow headless device without display device
When trying to create a headless Vulkan instance without a display
device available, device enumeration would fail.
Part of the physical device creation code already accounts for a missing
display device, allow device enumeration to continue in that case too so
headless instances can be created.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25313>
Matt Coster [Wed, 20 Sep 2023 15:00:19 +0000 (16:00 +0100)]
pvr: Force compile error on GNU void pointer arithmetic
This GNU extension caused a bug where a void pointer was modified then
interpreted as uint32_t* (instead of the other way round). Force a
compile error to (hopefully) prevent this from happening again.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25327>
Matt Coster [Wed, 20 Sep 2023 15:34:43 +0000 (16:34 +0100)]
pvr: Don't rely on GNU void pointer arithmetic
Besides being not standard C, one instance (in pvr_cmd_buffer.c) was a
bug caused by adding-then-casting, which would likely have been caught
if void pointer arithmetic were not allowed.
All instances detected by -Wpointer-arith have been fixed here.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25327>
Georg Lehmann [Tue, 26 Sep 2023 16:29:31 +0000 (18:29 +0200)]
aco: implement 64bit div find_lsb
This can be selected for divergent subgroupBallotFindLSB.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25407>
Georg Lehmann [Tue, 26 Sep 2023 15:13:12 +0000 (17:13 +0200)]
aco: fix p_extract with v1 dst and s1 operand
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
f14023666ca ("aco: Allow p_extract to have different definition and operand sizes.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25403>
Rhys Perry [Mon, 25 Sep 2023 11:29:26 +0000 (12:29 +0100)]
aco/waitcnt: add print helpers
These may be useful in the future.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25373>
Rhys Perry [Mon, 25 Sep 2023 11:22:05 +0000 (12:22 +0100)]
aco/waitcnt: replace wait_cnt::*_cnt with booleans
Previously, a loop could be revisited until a counter reaches it's
maximum:
loop {
store()
}
Each visit of that loop would increase vs_cnt until it reaches max.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25373>
Karol Herbst [Tue, 19 Sep 2023 12:44:26 +0000 (14:44 +0200)]
zink: lower vec8/16
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25330>
Karol Herbst [Thu, 21 Sep 2023 12:03:55 +0000 (14:03 +0200)]
nir: add nir_lower_alu_vec8_16_srcs pass
This pass is useful for vector based backends as we might end up with alu
instructions referencing vec8/vec16 values even though being vec4 or
smaller themselves.
This new pass intents to clean up any use of vec8/vec16 sources other
passes won't.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25330>
Jose Maria Casanova Crespo [Mon, 25 Sep 2023 19:16:59 +0000 (21:16 +0200)]
vc4: Fix mask RGBA validation at YUV blit
Solves regression on video players using GPU for
video decoding that just displays the video in green.
Fixes:
d13da7782cd80 ("vc4: call blit paths in chain")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25412>