Andrea Di Biagio [Mon, 27 Aug 2018 14:52:52 +0000 (14:52 +0000)]
[llvm-mca] Improved report generated by the SchedulerStatistics view.
Before this patch, the SchedulerStatistics only printed the maximum number of
buffer entries consumed in each scheduler's queue at a given point of the
simulation.
This patch restructures the reported table, and adds an extra field named
"Average number of used buffer entries" to it.
This patch also uses different colors to help identifying bottlenecks caused by
high scheduler's buffer pressure.
llvm-svn: 340746
Gheorghe-Teodor Bercea [Mon, 27 Aug 2018 14:52:20 +0000 (14:52 +0000)]
[OpenMP][Fix] Ensure comparison between unsigned values.
Summary: Ensure the values being compared are both unsigned.
Reviewers: ABataev, Hahnfeld, caomhin, grokos, AndreyChurbanov
Reviewed By: AndreyChurbanov
Subscribers: AndreyChurbanov, guansong, openmp-commits
Differential Revision: https://reviews.llvm.org/D51301
llvm-svn: 340745
Nico Weber [Mon, 27 Aug 2018 14:25:22 +0000 (14:25 +0000)]
fix comment typo
llvm-svn: 340744
Nico Weber [Mon, 27 Aug 2018 14:23:50 +0000 (14:23 +0000)]
fix comment typo
llvm-svn: 340743
Nico Weber [Mon, 27 Aug 2018 14:22:25 +0000 (14:22 +0000)]
fix comment typo
llvm-svn: 340742
Sanjay Patel [Mon, 27 Aug 2018 14:20:15 +0000 (14:20 +0000)]
[SelectionDAG] add helper query for binops; NFC
We will also use this in a planned enhancement for vector insertelement.
llvm-svn: 340741
Nemanja Ivanovic [Mon, 27 Aug 2018 13:20:42 +0000 (13:20 +0000)]
[PowerPC] Revert commit r339779
This commit has caused failures in some internal benchmarks. Temporarily
reverting this patch until the issue can be diagnosed and fixed.
llvm-svn: 340740
Sid Manning [Mon, 27 Aug 2018 12:55:28 +0000 (12:55 +0000)]
[ELF][HEXAGON] Add R_HEX_11/10/9_X support
Differential Revision: https://reviews.llvm.org/D51225
llvm-svn: 340739
Matt Arsenault [Mon, 27 Aug 2018 12:40:00 +0000 (12:40 +0000)]
Handle identifying AMDGPU bitcode files
llvm-svn: 340738
Aleksandr Urakov [Mon, 27 Aug 2018 11:56:32 +0000 (11:56 +0000)]
[X86] Adding the test pointing to the fail case of D45653
Summary:
This commit adds the case of tail calling a sret function from a non-sret
function when both functions have the C calling convention.
llvm-svn: 340737
Daniel Cederman [Mon, 27 Aug 2018 11:43:59 +0000 (11:43 +0000)]
[Sparc] Avoid writing outside array in applyFixup
Summary: If an object file ends with a relocation that is smaller
than 4 bytes we will write outside the Data array and trigger an
"Invalid index" assertion.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D50971
llvm-svn: 340736
Aleksandr Urakov [Mon, 27 Aug 2018 11:25:38 +0000 (11:25 +0000)]
[NFC][X86] Fix `sibcall.ll` formatting
Summary:
Remove unnecessary lines from `sibcall.ll` and rename labels according
to @RKSimon's recommendations in the D45653 conversation.
llvm-svn: 340735
Nemanja Ivanovic [Mon, 27 Aug 2018 11:20:27 +0000 (11:20 +0000)]
[PowerPC] Recommit r340016 after fixing the reported issue
The internal benchmark failure reported by Google was due to a missing
check for the result type for the sign-extend and shift DAG. This commit
adds the check and re-commits the patch.
llvm-svn: 340734
Daniel Cederman [Mon, 27 Aug 2018 11:11:47 +0000 (11:11 +0000)]
[Sparc] Add support for the cycle counter available in GR740
Summary: The GR740 provides an up cycle counter in the registers ASR22
and ASR23. As these registers can not be read together atomically we only
use the value of ASR23 for llvm.readcyclecounter(). The ASR23 register
holds the 32 LSBs of the up-counter.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: jfb, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48638
llvm-svn: 340733
Max Kazantsev [Mon, 27 Aug 2018 10:09:28 +0000 (10:09 +0000)]
[NFC] Try to make buildbot happy about virtual destructors
llvm-svn: 340732
Kirill Bobyrev [Mon, 27 Aug 2018 09:47:50 +0000 (09:47 +0000)]
[clangd] Use TRUE iterator instead of complete posting list
Stop using `$$$` (empty) trigram and generating a posting list with all
items. Since TRUE iterator is already implemented and correctly inserted
when there are no real trigram posting lists, this is a valid
transformation.
Benchmarks show that this simple change allows ~30% speedup on dataset
of real completion queries.
Before
```
-------------------------------------------------------
Benchmark Time CPU Iterations
-------------------------------------------------------
DexAdHocQueries 5640321 ns 5640265 ns 120
DexRealQ
939835603 ns
939830296 ns 1
```
After
```
-------------------------------------------------------
Benchmark Time CPU Iterations
-------------------------------------------------------
DexAdHocQueries 3452014 ns 3451987 ns 203
DexRealQ
667455912 ns
667455750 ns 1
```
Reviewed by: ilya-biryukov
Differential Revision: https://reviews.llvm.org/D51287
llvm-svn: 340729
Max Kazantsev [Mon, 27 Aug 2018 09:43:16 +0000 (09:43 +0000)]
[NFC] Split logic of ImplicitControlFlowTracking to allow generalization
We have a class `ImplicitControlFlowTracking` which allows us to keep track of
instructions that can abnormally exit and answer queries like "whether or not
there is side-exiting instruction above this instruction in its block".
We may want to have the similar tracking for other types of "special" instructions,
for example instructions that write memory.
This patch separates ImplicitControlFlowTracking into two classes, isolating all
general logic not related to implicit control flow into its parent class. We can
later make another child of this class to keep track of instructions that write
memory.
The motivation for that is that we want to make these checks efficiently in the
patch https://reviews.llvm.org/D50891.
NOTE: The naming of the parent class is not super cool, but the other options we
have are hardly better. Please feel free to rename it as NFC if you think you've
found a more informative name for it.
Differential Revision: https://reviews.llvm.org/D50954
Reviewed By: fedor.sergeev
llvm-svn: 340728
Chandler Carruth [Mon, 27 Aug 2018 08:49:20 +0000 (08:49 +0000)]
Try to fix this clang driver test case after r340709.
If any of the bots complain about this, I'll just revert. This test case
is essentially trying to test the exact change made, but I think this
matches the intent of the patch in question.
llvm-svn: 340727
Martin Storsjo [Mon, 27 Aug 2018 08:43:31 +0000 (08:43 +0000)]
[COFF] Support MinGW automatic dllimport of data
Normally, in order to reference exported data symbols from a different
DLL, the declarations need to have the dllimport attribute, in order to
use the __imp_<var> symbol (which contains an address to the actual
variable) instead of the variable itself directly. This isn't an issue
in the same way for functions, since any reference to the function without
the dllimport attribute will end up as a reference to a thunk which loads
the actual target function from the import address table (IAT).
GNU ld, in MinGW environments, supports automatically importing data
symbols from DLLs, even if the references didn't have the appropriate
dllimport attribute. Since the PE/COFF format doesn't support the kind
of relocations that this would require, the MinGW's CRT startup code
has an custom framework of their own for manually fixing the missing
relocations once module is loaded and the target addresses in the IAT
are known.
For this to work, the linker (originall in GNU ld) creates a list of
remaining references needing fixup, which the runtime processes on
startup before handing over control to user code.
While this feature is rather controversial, it's one of the main features
allowing unix style libraries to be used on windows without any extra
porting effort.
Some sort of automatic fixing of data imports is also necessary for the
itanium C++ ABI on windows (as clang implements it right now) for importing
vtable pointers in certain cases, see D43184 for some discussion on that.
The runtime pseudo relocation handler supports 8/16/32/64 bit addresses,
either PC relative references (like IMAGE_REL_*_REL32*) or absolute
references (IMAGE_REL_AMD64_ADDR32, IMAGE_REL_AMD64_ADDR32,
IMAGE_REL_I386_DIR32). On linking, the relocation is handled as a
relocation against the corresponding IAT slot. For the absolute references,
a normal base relocation is created, to update the embedded address
in case the image is loaded at a different address.
The list of runtime pseudo relocations contains the RVA of the
imported symbol (the IAT slot), the RVA of the location the relocation
should be applied to, and a size of the memory location. When the
relocations are fixed at runtime, the difference between the actual
IAT slot value and the IAT slot address is added to the reference,
doing the right thing for both absolute and relative references.
With this patch alone, things work fine for i386 binaries, and mostly
for x86_64 binaries, with feature parity with GNU ld. Despite this,
there are a few gotchas:
- References to data from within code works fine on both x86 architectures,
since their relocations consist of plain 32 or 64 bit absolute/relative
references. On ARM and AArch64, references to data doesn't consist of
a plain 32 or 64 bit embedded address or offset in the code. On ARMNT,
it's usually a MOVW+MOVT instruction pair represented by a
IMAGE_REL_ARM_MOV32T relocation, each instruction containing 16 bit of
the target address), on AArch64, it's usually an ADRP+ADD/LDR/STR
instruction pair with an even more complex encoding, storing a PC
relative address (with a range of +/- 4 GB). This could theoretically
be remedied by extending the runtime pseudo relocation handler with new
relocation types, to support these instruction encodings. This isn't an
issue for GCC/GNU ld since they don't support windows on ARMNT/AArch64.
- For x86_64, if references in code are encoded as 32 bit PC relative
offsets, the runtime relocation will fail if the target turns out to be
out of range for a 32 bit offset.
- Fixing up the relocations at runtime requires making sections writable
if necessary, with the VirtualProtect function. In Windows Store/UWP apps,
this function is forbidden.
These limitations are addressed by a few later patches in lld and
llvm.
Differential Revision: https://reviews.llvm.org/D50917
llvm-svn: 340726
Martin Storsjo [Mon, 27 Aug 2018 08:42:39 +0000 (08:42 +0000)]
[COFF] Expose an easier helper function for getting names for relocation types
The existing method is protected, and requires using DataRefImpl
and SmallVector.
Differential Revision: https://reviews.llvm.org/D50995
llvm-svn: 340725
Daniel Cederman [Mon, 27 Aug 2018 07:14:53 +0000 (07:14 +0000)]
[Sparc] Custom bitcast between f64 and v2i32
Summary:
Currently bitcasting constants from f64 to v2i32 is done by storing the
value to the stack and then loading it again. This is not necessary, but
seems to happen because v2i32 is a valid type for Sparc V8. If it had not
been legal, we would have gotten help from the type legalizer.
This patch tries to do the same work as the legalizer would have done by
bitcasting the floating point constant and splitting the value up into a
vector of two i32 values.
Reviewers: venkatra, jyknight
Reviewed By: jyknight
Subscribers: glaubitz, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D49219
llvm-svn: 340723
Roger Ferrer Ibanez [Mon, 27 Aug 2018 07:08:18 +0000 (07:08 +0000)]
[RISCV] atomic_store_nn have a different layout to regular store
We cannot directy reuse the patterns of StPat because for some reason the store
DAG node and the atomic_store_nn DAG nodes put the ptr and the value in
different positions. Currently we attempt to store the address to an address
formed by the value.
Differential Revision: https://reviews.llvm.org/D51217
llvm-svn: 340722
Chandler Carruth [Mon, 27 Aug 2018 06:52:14 +0000 (06:52 +0000)]
Fix this file to have the necessary standard library includes and use
the `std::` namespace. Should fix a number of build bots as well.
llvm-svn: 340721
Craig Topper [Mon, 27 Aug 2018 06:35:02 +0000 (06:35 +0000)]
[X86] Cleanup the LowerMULH code by hoisting some commonalities between the vXi32 and vXi8 handling. NFCI
vXi32 support was recently moved from LowerMUL_LOHI to LowerMULH.
This commit shares the getOperand calls, switches both to use common IsSigned flag, and hoists the NumElems/NumElts variable.
llvm-svn: 340720
Craig Topper [Mon, 27 Aug 2018 06:20:22 +0000 (06:20 +0000)]
[X86] Add intrinsics for kand/kandn/knot/kor/kxnor/kxor with 8, 32, and 64-bit mask registers.
This also adds a second intrinsic name for the 16-bit mask versions.
These intrinsics match gcc and icc. They just aren't published in the Intel Intrinsics Guide so I only recently found they existed.
llvm-svn: 340719
Craig Topper [Mon, 27 Aug 2018 06:20:20 +0000 (06:20 +0000)]
[X86] Remove min_vector_width 512 from some intrinsics that operate only on k-registers.
llvm-svn: 340718
Craig Topper [Mon, 27 Aug 2018 06:20:19 +0000 (06:20 +0000)]
[X86] Rename __DEFAULT_FN_ATTRS to a__DEFAULT_FN_ATTRS512 in avx512dqintrin.h and avx512bwintrin.h.
This is preparation for adding removing min_vector_width 512 from some intrinsics.
llvm-svn: 340717
Rui Ueyama [Mon, 27 Aug 2018 06:18:10 +0000 (06:18 +0000)]
Rename a function to follow the LLVM coding style.
llvm-svn: 340716
Martin Storsjo [Mon, 27 Aug 2018 06:04:36 +0000 (06:04 +0000)]
[COFF] Check the instructions in ARM MOV32T relocations
For this relocation, which applies to two consecutive instructions,
it's plausible that the second instruction might not actually be
the right one.
Differential Revision: https://reviews.llvm.org/D50998
llvm-svn: 340715
Craig Topper [Mon, 27 Aug 2018 05:44:45 +0000 (05:44 +0000)]
[X86] Undef __DEFAULT_FN_ATTRS in avx512fintrin.h.
Fixes test failure after r340713
llvm-svn: 340714
Craig Topper [Mon, 27 Aug 2018 05:27:15 +0000 (05:27 +0000)]
[X86] Don't set min_vector_width to 512 on intrinsics that only operate on k registers.
llvm-svn: 340713
David Carlier [Mon, 27 Aug 2018 05:16:09 +0000 (05:16 +0000)]
[Xray] Darwin - Enable in the driver side
Reviewers: dberris
Reviered By: dberris
Differential Revision: https://reviews.llvm.org/D51269
llvm-svn: 340712
Zachary Turner [Mon, 27 Aug 2018 04:04:41 +0000 (04:04 +0000)]
[MS Demangler] Add virtual destructor.
Silence -Wnon-virtual-dtor.
llvm-svn: 340711
Zachary Turner [Mon, 27 Aug 2018 03:48:03 +0000 (03:48 +0000)]
[MS Demangler] Re-write the Microsoft demangler.
This is a pretty large refactor / re-write of the Microsoft
demangler. The previous one was a little hackish because it
evolved as I was learning about all the various edge cases,
exceptions, etc. It didn't have a proper AST and so there was
lots of custom handling of things that should have been much
more clean.
Taking what was learned from that experience, it's now
re-written with a completely redesigned and much more sensible
AST. It's probably still not perfect, but at least it's
comprehensible now to someone else who wants to come along
and make some modifications or read the code.
Incidentally, this fixed a couple of bugs, so I've enabled
the tests which now pass.
llvm-svn: 340710
Fangrui Song [Sun, 26 Aug 2018 19:47:23 +0000 (19:47 +0000)]
[Driver] Change MipsLinux default linker from "lld" to "ld.lld"
Reviewers: kzhuravl, atanasyan
Reviewed By: atanasyan
Subscribers: sdardis, arichardson, jrtc27, atanasyan, cfe-commits
Differential Revision: https://reviews.llvm.org/D51234
llvm-svn: 340709
Craig Topper [Sun, 26 Aug 2018 18:47:44 +0000 (18:47 +0000)]
[X86] Correct the cost of (v4i32 (fptoui (v4f64))) under AVX512F.
Summary: This was inheriting the cost from the AVX table, but should be legal under AVX512.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51267
llvm-svn: 340708
Craig Topper [Sun, 26 Aug 2018 18:29:33 +0000 (18:29 +0000)]
[X86] Add FeatureCMOV explicitly to all CPUs that support it. Remove FeatureCMOV implication from Feature64Bit and FeatureSSE1
Summary:
Previously most CPUs inherited cmov support through Feature64Bit(or FeatureCMPXCHG16HB implying Feature64Bit) or FeatureSSE1.
This has the surprising side effect that -mattr=-cmov causes an assert to fire in 64-bit mode because it clears the Feature64Bit. Or in 32-bit mode, -mattr=-cmov disables any sse/avx features which seems surprising.
This patch removes the implication and instead updates hasCMOV in X86Subtarget to check SSE1 or is64Bit in addition to the regular cmov flag. This should keep most things working the way they did before. I don't believe there is a way to specific "-cmov" directly from clang so this should only effect our lower level tools.
This does stop -mattr=cx16(cmpxchg16b) from implying cmov is enabled via the 64bit flag as you can see from one of the changed tests. But that was a 32-bit test so I don't know why it enabled cx16 anyway.
For the other test I had to add -sse to override the new sse check in hasCMOV.
Reviewers: RKSimon, DavidKreitzer, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits, jfb
Differential Revision: https://reviews.llvm.org/D51228
llvm-svn: 340707
Craig Topper [Sun, 26 Aug 2018 18:29:27 +0000 (18:29 +0000)]
[X86] Add FeatureCMOV to athlon and athlon-tbird cpus.
Summary: This matches gcc and one cpuid dump I found online. Given that these are considered 7th generation x86 CPU it seems likely they support cmov since cmov was added by Intel in their 6th generation.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51264
llvm-svn: 340706
Sanjay Patel [Sun, 26 Aug 2018 18:20:41 +0000 (18:20 +0000)]
[SelectionDAG][x86] turn insertelement into undef with variable index into splat
I noticed this along with the patterns in D51125, but when the index is variable,
we don't convert insertelement into a build_vector.
For x86, that means these get expanded at legalization time into the loading/spilling
code that we see in the tests. I think it's always better to avoid going to memory on
these, and we get the optimal 'broadcast' if it's available.
I suspect other targets may want to look at enabling the hook. AArch64 and AMDGPU have
regression tests that would be affected (although I did not check what would happen in
those cases). In the most basic cases shown here, AArch64 would probably do much
better with a splat.
Differential Revision: https://reviews.llvm.org/D51186
llvm-svn: 340705
Lang Hames [Sun, 26 Aug 2018 16:46:02 +0000 (16:46 +0000)]
[ORC] Remove a workaround for systems lacking 8-byte atomics.
SymbolStringPool ref counts are now size_t, rather than uint64_t, so I do not
think this is necessary any more.
llvm-svn: 340704
Lang Hames [Sun, 26 Aug 2018 16:46:02 +0000 (16:46 +0000)]
[ORC] Do not include non-global symbols in getObjectSymbolFlags.
Private symbols are not visible outside the object file, and so not defined by
the object file from ORC's perspective.
No test case yet. Ideally this would be a unit test parsing a checked-in binary,
but I am not aware of any way to reference the LLVM source root from a unit
test.
llvm-svn: 340703
Chandler Carruth [Sun, 26 Aug 2018 10:03:08 +0000 (10:03 +0000)]
Replace fancy use of initializer lists with simple functions that return
vectors, and move this test code into an anonymous namespace.
Hoping that this will avoid hitting an MSVC bug that causes it to crash
and burn pretty spectacularly. Also, this degree of clever use of
initializer lists seems somewhat questionable in general. ;]
llvm-svn: 340702
Chandler Carruth [Sun, 26 Aug 2018 09:51:22 +0000 (09:51 +0000)]
[IR] Replace `isa<TerminatorInst>` with `isTerminator()`.
This is a bit awkward in a handful of places where we didn't even have
an instruction and now we have to see if we can build one. But on the
whole, this seems like a win and at worst a reasonable cost for removing
`TerminatorInst`.
All of this is part of the removal of `TerminatorInst` from the
`Instruction` type hierarchy.
llvm-svn: 340701
Chandler Carruth [Sun, 26 Aug 2018 09:17:49 +0000 (09:17 +0000)]
Avoid specializing a variadic member template in a way that seems to not
agree with MSVC.
There isn't actually a need for specialization here as we can write the
code generically and just have a test that will fold away as a constant.
llvm-svn: 340700
Chandler Carruth [Sun, 26 Aug 2018 08:56:42 +0000 (08:56 +0000)]
[IR] Sink `isExceptional` predicate to `Instruction`, rename it to
`isExceptionalTermiantor` and implement it for opcodes as well following
the common pattern in `Instruction`.
Part of removing `TerminatorInst` from the `Instruction` type hierarchy
to make it easier to share logic and interfaces between instructions
that are both terminators and not terminators.
llvm-svn: 340699
Chandler Carruth [Sun, 26 Aug 2018 08:41:15 +0000 (08:41 +0000)]
[IR] Begin removal of TerminatorInst by removing successor manipulation.
The core get and set routines move to the `Instruction` class. These
routines are only valid to call on instructions which are terminators.
The iterator and *generic* range based access move to `CFG.h` where all
the other generic successor and predecessor access lives. While moving
the iterator here, simplify it using the iterator utilities LLVM
provides and updates coding style as much as reasonable. The APIs remain
pointer-heavy when they could better use references, and retain the odd
behavior of `operator*` and `operator->` that is common in LLVM
iterators. Adjusting this API, if desired, should be a follow-up step.
Non-generic range iteration is added for the two instructions where
there is an especially easy mechanism and where there was code
attempting to use the range accessor from a specific subclass:
`indirectbr` and `br`. In both cases, the successors are contiguous
operands and can be easily iterated via the operand list.
This is the first major patch in removing the `TerminatorInst` type from
the IR's instruction type hierarchy. This change was discussed in an RFC
here and was pretty clearly positive:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123407.html
There will be a series of much more mechanical changes following this
one to complete this move.
Differential Revision: https://reviews.llvm.org/D47467
llvm-svn: 340698
Petar Jovanovic [Sun, 26 Aug 2018 07:25:33 +0000 (07:25 +0000)]
[MIPS GlobalISel] Legalize i8 and i16 add
Legalize G_ADD for types smaller than i32.
LegalizationArtifactCombiner replaces extend instructions with appropriate
bitwise instructions.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D51213
llvm-svn: 340697
Argyrios Kyrtzidis [Sun, 26 Aug 2018 06:27:23 +0000 (06:27 +0000)]
[index] Introduce 'ProtocolInterface' as part of SymbolPropertySet
This is useful to directly infer that a method or property is from a protocol interface
at the point of the symbol occurrences.
llvm-svn: 340696
Craig Topper [Sun, 26 Aug 2018 03:43:23 +0000 (03:43 +0000)]
[X86] Fix typo in comment, expect->except. NFC
llvm-svn: 340695
Craig Topper [Sun, 26 Aug 2018 00:22:07 +0000 (00:22 +0000)]
[X86] Add test cases for D50952, paddus patterns involving constants. NFC
llvm-svn: 340694
Sid Manning [Sat, 25 Aug 2018 23:16:37 +0000 (23:16 +0000)]
[ELF][HEXAGON] Add R_HEX_B13_PCREL relocation support
Differential Revision: https://reviews.llvm.org/D51166
llvm-svn: 340693
Sid Manning [Sat, 25 Aug 2018 21:25:35 +0000 (21:25 +0000)]
[ELF][HEXAGON] Add R_HEX_B9_PCREL and R_HEX_B9_PCREL_X relocation support
Differential Revision: https://reviews.llvm.org/D51045
llvm-svn: 340692
Robert Widmann [Sat, 25 Aug 2018 19:54:39 +0000 (19:54 +0000)]
[C-API][DIBuilder] Use NameLen in LLVMDIBuilderCreateParameterVariable
Summary: NameLen wasn't being used and caused the parameters in gdb to very long, in my case, crashes in others. Please also perform the correct magical incarnations to have this be applied to the LLVM 7 branch.
Reviewers: whitequark, CodaFi
Reviewed By: CodaFi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51141
llvm-svn: 340691
Craig Topper [Sat, 25 Aug 2018 18:01:24 +0000 (18:01 +0000)]
[X86] Replace support for vXi32 SMUL_LOHI/UMUL_LOHI with MULHS/MULHU support instead.
Summary:
The only time vector SMUL_LOHI/UMUL_LOHI nodes are created is during division/remainder lowering. If its created before op legalization, generic DAGCombine immediately turns that SMUL_LOHI/UMUL_LOHI into a MULHS/MULHU since only the upper half is used. That node will stick around through vector op legalization and will be turned back into UMUL_LOHI/SMUL_LOHI during op legalization. It will then be custom lowered by the X86 backend. Due to this two step lowering the vector shuffles created by the custom lowering get legalized after their inputs rather than before. This prevents the shuffles from being combined with any build_vector of constants.
This patch uses changes vXi32 to use MULHS/MULHU instead. This is what the later DAG combine did anyway. But by skipping the change back to UMUL_LOHI/SMUL_LOHI we lower it before any constant BUILD_VECTORS. This allows the vector_shuffle creation to constant fold with the build_vectors. This accounts for the test changes here.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51254
llvm-svn: 340690
Craig Topper [Sat, 25 Aug 2018 17:48:17 +0000 (17:48 +0000)]
[SelectionDAG][X86] Reorder the operands the MaskedStoreSDNode to put the value first.
Summary:
Previously the value being stored is the last operand in SDNode. This causes the type legalizer to visit the mask operand before the value operand. The type legalizer was more complicated because of this since we want the type of the value to drive the decisions.
This patch moves the value to be the first operand so we visit it first during type legalization. It also simplifies the type legalization code accordingly.
X86 is currently the only in tree target that uses this SDNode. Not sure if there are any users out of tree.
Reviewers: RKSimon, delena, hfinkel, eli.friedman
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50402
llvm-svn: 340689
Craig Topper [Sat, 25 Aug 2018 17:23:43 +0000 (17:23 +0000)]
[X86] Make sure type is a vector before calling VT.getVectorNumElements() in combineLoopMAddPattern
Fixes PR38700.
llvm-svn: 340688
Simon Pilgrim [Sat, 25 Aug 2018 17:11:11 +0000 (17:11 +0000)]
Fix -Wunused-function warning. NFCI.
llvm-svn: 340687
Simon Pilgrim [Sat, 25 Aug 2018 16:49:35 +0000 (16:49 +0000)]
Remove superfluous semicolon. NFCI.
llvm-svn: 340686
Sanjay Patel [Sat, 25 Aug 2018 14:56:05 +0000 (14:56 +0000)]
[x86] try harder to use broadcast to load a scalar into vector reg
This is a preliminary step for a preliminary step for D50992.
I noticed that x86 often misses chances to load a scalar directly
into a vector register.
So this patch is just allowing more of those cases to match a
broadcast op in lowerBuildVectorAsBroadcast(). The old code comment
said it doesn't make sense to use a broadcast when we're loading a
single element and everything else is undef, but I think that's the
best case in the improved tests in insert-loaded-scalar.ll. We avoid
scalar-to-vector-register move and/or less efficient shuffling.
Note that there are some existing types that were already producing
a broadcast, but that happens semi-accidentally. Ie, it's not
happening as part of lowerBuildVectorAsBroadcast(). The build vector
gets expanded into load + shuffle, and then shuffle lowering produces
the broadcast.
Description of the other test diffs:
1. avx-basic.ll - replacing load+shufle is a win.
2. sse3-avx-addsub-2.ll - vmovddup vs. vbroadcastss is neutral
3. sse41.ll - don't care - we convert that intrinsic to generic IR now, so this test is deprecated
4. vector-shuffle-128-v8.ll / vector-shuffle-256-v16.ll - pshufb alternatives with an extra instruction are not obviously bad
Differential Revision: https://reviews.llvm.org/D51125
llvm-svn: 340685
Tim Renouf [Sat, 25 Aug 2018 14:53:17 +0000 (14:53 +0000)]
[AMDGPU] Add support for multi-dword s.buffer.load intrinsic
Summary:
Patch by Marek Olsak and David Stuttard, both of AMD.
This adds a new amdgcn intrinsic supporting s.buffer.load, in particular
multiple dword variants. These are convenient to use from some front-end
implementations.
Also modified the existing llvm.SI.load.const intrinsic to common up the
underlying implementation.
This modification also requires that we can lower to non-uniform loads correctly
by splitting larger dword variants into sizes supported by the non-uniform
versions of the load.
V2: Addressed minor review comments.
V3: i1 glc is now i32 cachepolicy for consistency with buffer and
tbuffer intrinsics, plus fixed formatting issue.
V4: Added glc test.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D51098
Change-Id: I83a6e00681158bb243591a94a51c7baa445f169b
llvm-svn: 340684
Sanjay Patel [Sat, 25 Aug 2018 14:37:08 +0000 (14:37 +0000)]
[InstCombine] add tests for shuffle+binop transform; NFC
llvm-svn: 340683
Simon Pilgrim [Sat, 25 Aug 2018 14:16:03 +0000 (14:16 +0000)]
[X86] Make requested test changes from D50636
The tests were relying on X / X -> 1 and X % X -> 0 combines not happening in the DAG.
llvm-svn: 340682
Jonas Hahnfeld [Sat, 25 Aug 2018 13:42:40 +0000 (13:42 +0000)]
[CUDA/OpenMP] Define only some host macros during device compilation
When compiling CUDA or OpenMP device code Clang parses header files
that expect certain predefined macros from the host architecture. To
make this work the compiler passes the host triple via the -aux-triple
argument and (until now) pulls in all macros for that "auxiliary triple"
unconditionally.
However this results in defines like __SSE_MATH__ that will trigger
inline assembly making use of the "advertised" target features. See
the discussion of D47849 and PR38464 for a detailed explanation of
the encountered problems.
Instead of blacklisting "known bad" examples this patch starts adding
defines that are needed for certain headers like bits/wordsize.h and
bits/mathinline.h.
The disadvantage of this approach is that it decouples the definitions
from their target toolchain. However in my opinion it's more important
to keep definitions for one header close together. For one this will
include a clear documentation why these particular defines are needed.
Furthermore it simplifies maintenance because adding defines for a new
header or support for a new aux-triple only needs to touch one piece
of code.
Differential Revision: https://reviews.llvm.org/D50845
llvm-svn: 340681
Bjorn Pettersson [Sat, 25 Aug 2018 11:26:17 +0000 (11:26 +0000)]
[CodeGen] Set FrameSetup/FrameDestroy on BUNDLE instructions
Summary:
If any of the bundled instructions are marked as FrameSetup
or FrameDestroy, then that property is set on the BUNDLE
instruction as well.
As long as the scheduler/packetizer aren't mixing
prologue/epilogue instructions (i.e. all the bundled
instructions have the same property) then this simply gives
the bundle the correct property (so when using a bundle
iterator in late passes a bundle will be correctly identified
as FrameSetup/FrameDestroy).
When for example bundling a mix of FrameSetup instructions
with non-FrameSetup instructions it could be discussed if
the bundle should have the property or not. The choice here
has been to set these properties on the BUNDLE instruction if
any of the bundled instructions have the property set.
Reviewers: #debug-info, kparzysz
Reviewed By: kparzysz
Subscribers: vsk, thegameg, llvm-commits
Differential Revision: https://reviews.llvm.org/D50637
llvm-svn: 340680
Bjorn Pettersson [Sat, 25 Aug 2018 10:02:03 +0000 (10:02 +0000)]
[LiveDebugVariables] Avoid faulty addDefsFromCopies in computeIntervals
Summary:
When computeIntervals is looking through COPY instruction to
extend the location mapping for a debug variable it did not
handle subregisters correctly.
For example
DBG_VALUE debug-use %0.sub_8bit_hi, ...
%1:gr16 = COPY %0
was transformed into
DBG_VALUE debug-use %0.sub_8bit_hi, ...
%1:gr16 = COPY %0
DBG_VALUE debug-use %1, ...
So the subregister index was missing in the added DBG_VALUE.
As long as the subreg refered to the least significant bits
of the superreg, then I guess we could get the correct
result in a debugger even when referring to the superreg.
But as in the example above when the subreg refers to other
parts of the superreg, then debuginfo would be incorrect.
I'm not sure exactly how to fix this properly, so this patch
just avoids looking through the COPY when there is a subreg
involved (for more info, see the FIXME added in the code).
Reviewers: rnk, aprantl
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D50788
llvm-svn: 340679
Ana Pazos [Sat, 25 Aug 2018 01:34:32 +0000 (01:34 +0000)]
[MC, RISCV] Fixed StringRef Assertion `Index < Length && "Invalid index!"'
Summary:
Handle the case IDVal is an empty string.
This bug was uncovered by a LLVM MC Assembler Protocol Buffer
Fuzzer for the RISC-V assembly language.
Reviewers: rnk
Reviewed By: rnk
Subscribers: rnk, niravd, pcc, peter.smith, asb, grosbach, llvm-commits, bcain, kito-cheng, shiva0217, rogfer01, PkmX
Differential Revision: https://reviews.llvm.org/D50808
llvm-svn: 340678
Kuba Mracek [Sat, 25 Aug 2018 01:27:48 +0000 (01:27 +0000)]
[llvm] Document "%T" as deprecated in CommandGuide/lit.rst
Differential Revision: https://reviews.llvm.org/D48842
llvm-svn: 340677
Frederic Riss [Sat, 25 Aug 2018 01:25:24 +0000 (01:25 +0000)]
Disable exceptions for TestDataFormatterLibcxxOptional.py
On macOS, some of the <optional> APIs used by the test are available only
starting on macOS 10.14 when using exceptions. Build the test with
-fno-exceptions so that the test builds on older systems too.
rdar://problem/
43700544
llvm-svn: 340676
Eric Christopher [Sat, 25 Aug 2018 01:08:18 +0000 (01:08 +0000)]
This patch adds support to LLVM for writing HermitCore (https://hermitcore.org) ELF binaries.
HermitCore is a POSIX-compatible kernel for running a single application in an isolated environment to get maximum performance and predictable runtime behavior. It can either be used bare-metal on hardware or a VM (Unikernel) or side by side to an existing Linux system (Multikernel).
Due to the latter feature, HermitCore binaries are marked with ELFOSABI_STANDALONE to let the Linux ELF loader distinguish them from regular Unix/Linux binaries and load them using the HermitCore "proxy" tool.
Patch by Colin Finck!
llvm-svn: 340675
Ana Pazos [Fri, 24 Aug 2018 23:47:49 +0000 (23:47 +0000)]
[RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.
Summary:
Missing check for isImm() in some Immediate classes.
This bug was uncovered by a LLVM MC Assembler Protocol Buffer Fuzzer
for the RISC-V assembly language.
Reviewers: hiraditya, asb
Reviewed By: hiraditya, asb
Subscribers: llvm-commits, hiraditya, kito-cheng, shiva0217, rkruppe, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei
Differential Revision: https://reviews.llvm.org/D50797
llvm-svn: 340674
Adrian Prantl [Fri, 24 Aug 2018 23:30:57 +0000 (23:30 +0000)]
Prevent DILocation::getMergedLocation() from creating invalid metadata.
The function's new implementation from r340583 had a bug in it that
could cause an invalid scope to be generated when merging two
DILocations with no common ancestor scope.
This patch detects this situation and picks the scope of the first
location. This is not perfect, because the scope is misleading, but on
the other hand, this will be a line 0 location.
rdar://problem/
43687474
Differential Revision: https://reviews.llvm.org/D51238
llvm-svn: 340672
Richard Smith [Fri, 24 Aug 2018 23:30:26 +0000 (23:30 +0000)]
Port my recent changes from LLVM copy of the demangler:
r340663 - Allow Allocator::make to make a node of a different type than that
requested.
r340664 - Add documentation comment to ForwardTemplateReference.
r340665 - Fix ExpandedSpecialSubstitution demangling for Sa and Sb.
r340670 - Allow demangler's node allocator to fail, and bail out of the entire
demangling process when it does.
llvm-svn: 340671
Richard Smith [Fri, 24 Aug 2018 23:26:05 +0000 (23:26 +0000)]
Allow demangler's node allocator to fail, and bail out of the entire
demangling process when it does.
Use this to support a "lookup" query for the mangling canonicalizer that
does not create new nodes. This could also be used to implement
demangling with a fixed-size temporary storage buffer.
Reviewers: erik.pilkington
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51003
llvm-svn: 340670
Ana Pazos [Fri, 24 Aug 2018 23:13:59 +0000 (23:13 +0000)]
[RISCV] Fix std::advance slowness
Summary:
It seems std::advance template is treating "-MFI.getCalleeSavedInfo().size()"
as a large unsigned value", causing slowness.
Thanks to Henrik Gustafsson for reporting the issue.
Reviewers: asb
Reviewed By: asb
Subscribers: llvm-commits, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb
Differential Revision: https://reviews.llvm.org/D51148
llvm-svn: 340669
Matt Davis [Fri, 24 Aug 2018 22:59:13 +0000 (22:59 +0000)]
[llvm-mca] Move ResourceManager from Scheduler into its own file. NFC.
This time I should be preserving history of the ResourceManager changes.
llvm-svn: 340668
Hans Wennborg [Fri, 24 Aug 2018 22:46:33 +0000 (22:46 +0000)]
Revert r323281 "Adjust MaxAtomicInlineWidth for i386/i486 targets."
As reported on http://lists.llvm.org/pipermail/cfe-dev/2018-August/058760.html,
this broke i386-freebsd11 due to its lack of atomic 64 bit primitives.
While that's not really this commit's fault, let's revert back to the old
behaviour until this can be fixed. This means generating cmpxchg8b etc for i386
and i486 which don't technically support those, but that's been the behaviour
for a long time, so a little longer probably doesn't hurt that much.
> Adjust MaxAtomicInlineWidth for i386/i486 targets.
>
> This is to fix the bug reported in https://bugs.llvm.org/show_bug.cgi?id=34347#c6.
> Currently, all MaxAtomicInlineWidth of x86-32 targets are set to 64. However,
> i386 doesn't support any cmpxchg related instructions. i486 only supports cmpxchg.
> So in this patch MaxAtomicInlineWidth is reset as follows:
> For i386, the MaxAtomicInlineWidth should be 0 because no cmpxchg is supported.
> For i486, the MaxAtomicInlineWidth should be 32 because it supports cmpxchg.
> For others 32 bits x86 cpu, the MaxAtomicInlineWidth should be 64 because of cmpxchg8b.
>
> Differential Revision: https://reviews.llvm.org/D42154
llvm-svn: 340666
Richard Smith [Fri, 24 Aug 2018 22:34:20 +0000 (22:34 +0000)]
Fix ExpandedSpecialSubstitution demangling for Sa and Sb.
No functionality change: we never actually create these forms currently.
llvm-svn: 340665
Richard Smith [Fri, 24 Aug 2018 22:33:53 +0000 (22:33 +0000)]
Add documentation comment to ForwardTemplateReference.
This node doesn't directly correspond to a mangled name fragment, so
it's useful to explicitly describe when it's created and what it's for.
llvm-svn: 340664
Richard Smith [Fri, 24 Aug 2018 22:31:51 +0000 (22:31 +0000)]
Add data structure to form equivalence classes of mangled names.
Summary:
Given a set of equivalent name fragments, this mechanism determines whether two
mangled names are equivalent. The intent is to use this for fuzzy matching of
profile data against the program after certain refactorings are performed.
Reviewers: erik.pilkington, dlj
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D50935
llvm-svn: 340663
Matt Davis [Fri, 24 Aug 2018 22:05:14 +0000 (22:05 +0000)]
[llvm-mca] Revert r340659. NFC.
Choosing to revert the change and do it again, hopefully preserving the history
of the changes by using svn copy instead of simply creating a new file from the
contents within Scheduler.
llvm-svn: 340661
Philip Reames [Fri, 24 Aug 2018 21:56:43 +0000 (21:56 +0000)]
[CVP] Extend tests to illustrate an old patch isn't needed
Back in https://reviews.llvm.org/D19559, I tried to teach CVP about range facts implied by value/value icmps (i.e. no constants.) In the meantime, we've implemented the optimization, but I couldn't find tests checked in, so adding them.
llvm-svn: 340660
Matt Davis [Fri, 24 Aug 2018 21:53:12 +0000 (21:53 +0000)]
[llvm-mca] Move the ResourceManger from the Scheduler into its own file. NFC.
llvm-svn: 340659
Stella Stamenova [Fri, 24 Aug 2018 21:42:53 +0000 (21:42 +0000)]
[vscode] Skip some of the vscode tests on Linux and fix one
Summary: These are already skipped on Darwin because they cause build bot failures. Both on the build bots as well as in our testing we have seen a number of these tests fail and hang. This change skips the failing/hanging tests on Linux and also fixes one of the test - the test needs the thread library to build.
Reviewers: asmith, clayborg, aprantl
Subscribers: teemperor, lldb-commits
Differential Revision: https://reviews.llvm.org/D51227
llvm-svn: 340658
Xinliang David Li [Fri, 24 Aug 2018 21:38:24 +0000 (21:38 +0000)]
[PGO] add target md5sum in warning message for icall
Differential revision: http://reviews.llvm.org/D51193
llvm-svn: 340657
Jonathan Peyton [Fri, 24 Aug 2018 21:34:10 +0000 (21:34 +0000)]
[OpenMP] Remove deprecated/obsolete MIC attributes from headers
llvm-svn: 340656
Matt Arsenault [Fri, 24 Aug 2018 21:24:18 +0000 (21:24 +0000)]
DAG: Allow matching fminnum/fmaxnum from vselect
llvm-svn: 340655
Vitaly Buka [Fri, 24 Aug 2018 21:03:35 +0000 (21:03 +0000)]
Use unique_ptr to hold MCInstrInfo
llvm-svn: 340654
Adrian Prantl [Fri, 24 Aug 2018 21:01:58 +0000 (21:01 +0000)]
Verifier: verify that a DILocation's scope is a DILocalScope.
This fixes an assertion failure(!) in the Verifier.
rdar://problem/
43687474
llvm-svn: 340653
Raphael Isemann [Fri, 24 Aug 2018 20:55:23 +0000 (20:55 +0000)]
Fixed windows bots that were failing because of PATH_MAX
As we only use PATH_MAX for an assert in a unit test that is supposed
to catch the random failures on the Swift CI bots, we might as well
just ifdef this assert out on Windows.
llvm-svn: 340652
Eli Friedman [Fri, 24 Aug 2018 20:42:32 +0000 (20:42 +0000)]
[SafeStack] Set debug location for calls to __safestack_pointer_address.
Otherwise, the debug info is incorrect. On its own, this is mostly
harmless, but the safe-stack also later inlines the call to
__safestack_pointer_address, which leads to debug info with the wrong
scope, which eventually causes an assertion failure (and incorrect debug
info in release mode).
Differential Revision: https://reviews.llvm.org/D51075
llvm-svn: 340651
Adrian Prantl [Fri, 24 Aug 2018 20:41:08 +0000 (20:41 +0000)]
Reduce the memory footprint of dsymutil. (NFC)
This (partially) fixes a regression introduced by
https://reviews.llvm.org/D43945 / r327399, which parallelized
DwarfLinker. This patch avoids parsing and allocating the memory for
all input DIEs up front and instead only allocates them in the
concurrent loop in the AnalyzeLambda. At the end of the loop the
memory from the LinkContext is cleared again.
This reduces the peak memory needed to link the debug info of a
non-modular build of the Swift compiler by >3GB.
rdar://problem/
43444464
Differential Revision: https://reviews.llvm.org/D51078
llvm-svn: 340650
Peter Collingbourne [Fri, 24 Aug 2018 20:38:15 +0000 (20:38 +0000)]
Reland r340552, "Driver: Enable address-significance tables by default when targeting COFF." which was reverted in r340579.
The underlying problem that caused the revert was fixed in r340648.
Differential Revision: https://reviews.llvm.org/D51049
llvm-svn: 340649
Peter Collingbourne [Fri, 24 Aug 2018 20:37:09 +0000 (20:37 +0000)]
CodeGen: Add two more conditions for adding symbols to the address-significance table.
Firstly, require the symbol to be used within the module. If a
symbol is unused within a module, then by definition it cannot be
address-significant within that module. This condition is useful on all
platforms because it could make symbol tables smaller -- without this
change, emitting an address-significance table could cause otherwise
unused undefined symbols to be added to the object file.
But this change is necessary with COFF specifically in order to
preserve the property that an unreferenced undefined symbol in an IR
module does not result in a link failure. This is already the case for
ELF because ELF linkers only reject links with unresolved symbols if
there is a relocation to that symbol, but COFF linkers require all
undefined symbols to be resolved regardless of relocations. So if
a module contains an unreferenced undefined symbol, we need to make
sure not to add it to the address-significance table (and thus the
symbol table) in case it doesn't end up resolved at link time.
Secondly, do not add dllimport symbols to the table. These symbols
won't be able to be resolved because their definitions live in another
module and are accessed via the IAT, and the address-significance
table has no effect on other modules anyway. It wouldn't make sense
to add the IAT entry symbol to the address-significance table either
because the IAT entry isn't address-significant -- the generated code
never takes its address.
Differential Revision: https://reviews.llvm.org/D51199
llvm-svn: 340648
Jonathan Peyton [Fri, 24 Aug 2018 20:35:42 +0000 (20:35 +0000)]
[OpenMP] Fixed affinity verbose double printing for balanced type.
llvm-svn: 340647
David Blaikie [Fri, 24 Aug 2018 20:31:05 +0000 (20:31 +0000)]
DebugInfo: Fix skipping CUs in DWARFv5 debug_names table
My previoust test case had skipped CUs from one TU out of a two-TU LTO
scenario, which meant the CU index wasn't needed (as it was unambiguous
which CU a table entry applied to) - expanding the test to use 3 TUs,
skipping one (so long as it's not the last one) shows the indexes are
miscomputed. Fix that with a little indirection for the index.
llvm-svn: 340646
Matt Davis [Fri, 24 Aug 2018 20:24:53 +0000 (20:24 +0000)]
[llvm-mca] Move views and stats into a Views subdir. NFC.
llvm-svn: 340645
Eli Friedman [Fri, 24 Aug 2018 20:18:34 +0000 (20:18 +0000)]
Add REQUIRES: x86-registered-target to test.
(This isn't really x86-specific, but we have to pick some non-Apple
triple to exercise the right codepath.)
llvm-svn: 340644
Stefan Pintilie [Fri, 24 Aug 2018 20:00:24 +0000 (20:00 +0000)]
[PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9
This patch will address using the xscpsgndp instruction to copy floating point
scalar registers instead of the xxlor (specifically XXLORf) instruction that is
currently used. Additionally, this patch of utilizing xscpsgndp will apply to
P9, while pre-P9 will still use xxlor.
Patch by amyk
Differential Revision: https://reviews.llvm.org/D50004
llvm-svn: 340643
Joel Galenson [Fri, 24 Aug 2018 19:40:35 +0000 (19:40 +0000)]
Use unique_ptr.
llvm-svn: 340642
Stefan Pintilie [Fri, 24 Aug 2018 19:38:29 +0000 (19:38 +0000)]
[Exception Handling] Unwind tables are required for all functions that have an EH personality.
This patch is for defect:
https://bugs.llvm.org/show_bug.cgi?id=32611
Functions may require unwind tables even if they are marked with the attribute
nounwind. Any function with an EH personality may require an unwind table.
Differential Revision: https://reviews.llvm.org/D50987
llvm-svn: 340641