clk: rockchip: pll: Add pll_rk3588 type for rk3588

Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

clk: rockchip: Add rk3588 clk support

Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

dt-bindings: clk: Add dt-binding header for RK3588

Add the dt-bindings header for the Rockchip RK3588, that gets
shared between the clock controller and the clock references
in the dts.

commit <f204a60e545c> ("dt-bindings: clock: add rk3588 clock
definitions")

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm: rockchip: Add grf header for rk3588

Add GRF header for Rockchip RK3588.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm: rockchip: Add cru header for rk3588

Add clock and reset unit header include for rk3588.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: mkimage: Add rk3588 support

Add support for rk3588 package header in mkimage tool.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

evb-rk3568: Update MAINTAINERS and documentation

Update the MAINTAINERS file to include the devicetree for the
rk3568-evb1-v10 board.

Also update Rockchip board docs to include information on building
RK3568 based devices.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

arm64: dts: rockchip: add gpio-ranges property to gpio nodes

Add gpio-ranges property to GPIO nodes so that the bank ID can
be correctly derived for each GPIO bank.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: rk3568: enable automatic power savings

It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: rk3568: add boot device detection

Enable spl to detect which device it was booted from.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm64: dts: rockchip: Sync rk356x from Linux main

Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
this writing).

Note that this will rename the rk3568-evb to rk3568-evb1-v10.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

dts: rockchip: px30: add gpio-ranges property to gpio nodes

Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".

Fixes: 537b1a277479 ("rockchip: add px30 devicetrees")

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

gpio: gpio-rockchip: parse gpio-ranges for bank id

Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rk3566: radxa-cm3: Enable USB2.0, USB3.0 support

=> usb start
starting USB...
Bus usb@fd000000: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd800000: USB EHCI 1.00
scanning bus usb@fd000000 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning bus usb@fd800000 for devices... 4 USB Device(s) found
       scanning usb for storage devices... 2 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Mass Storage (5 Gb/s, 224mA)
       SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5

  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 100mA)
    |   USB 2.0 Hub
    |
    +-3  Mass Storage (480 Mb/s, 500mA)
    |    JetFlash Mass Storage Device 19M7I4ZQFTSC08SU
    |
    +-4  Human Interface (12 Mb/s, 98mA)
         Logitech USB Receiver

Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: rk3568: Select DM_REGULATOR_FIXED

Select the DM_REGULATOR_FIXED on RK3568 platform.

Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: rk3568: add rk3568 pinctrl driver

Add driver supporting pin multiplexing on rk3568 platform.

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates

combphy1 is failing to probe due to unhandled assigned-clocks and
assigned-clocks-rates.

=> usb start
starting USB...
Bus usb@fd000000: Failed to get PHY1 for usb@fd000000
Port not available.
Bus usb@fd800000: USB EHCI 1.00

There is no real requirement for them in U-Boot to handle, hence
mark them as deleted-properties for the  probe to success

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

drivers: phy: add naneng combphy for rk3568

RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

phy: rockchip-inno-usb2: Add USB2 PHY for rk3568

RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.

However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.

This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.

Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Co-developed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

phy: rockchip: inno-usb2: Add support #address_cells = 2

New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only
use 32 bit addresses.

Adjust the driver to check if the returned address is "0", and adjust
the index in that case.

Derived and adjusted the similar change from linux-next with below
 commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support
 #address_cells = 2")

Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

board: rockchip: Add Radxa Compute Module 3 IO Board

Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO

Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.

Specification:
- 1x HDMI,
- 2x MIPI DSI
- 2x MIPI CSI2
- 1x eDP
- 1x PCIe card
- 2x SATA
- 2x USB 2.0 Host
- 1x USB 3.0
- 1x USB 2.0 OTG
- Phone jack
- microSD slot
- 40-pin GPIO expansion header
- 12V DC

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

linux-next commit for the same,

commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")

Add support for Radxa CM3 IO Board.

Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3

Radxa Compute Module 3(CM3) is one of the modules from a series
System On Module based on the Radxa ROCK 3 series and is compatible
with Raspberry Pi CM4 pinout and form factor.

Specification:
- Rockchip RK3566
- up to 8GB LPDDR4
- up to 128GB high performance eMMC
- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
  BT 5.0, BLE with onboard and external antenna.
- Gigabit Ethernet PHY

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.

linux-next commit for the same,

commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")

Add support for Radxa CM3.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

dt-bindings: rockchip: Sync rockchip, vop2.h from Linux

Sync rockchip,vop2.h from linux-next, and the last commit is

commit <604be85547ce> ("drm/rockchip: Add VOP2 driver")

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

rockchip: rk3568: Move DM_RESET in arch kconfig

Like other rockchip SoCs, DM_RESET is useful across rk3568
platform.

Select it from arch kconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

board: edgeble: Fix neural-compute-module-2 board name

The board should be RV1126-NEU2 instead RV1126-ECM0.

Fix the wrong name.

Fixes: b8f1ca954013 ("board: rockchip: Add Edgeble Neu2 IO Board")
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

include: rk3328: Add default env for compressed kernel images

Add default memory addresses for kernel_comp_addr_r and kernel_comp_size
to enable booting from a compressed kernel image. This area is temporarily
used to decompress the kernel image on-the-fly.

Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support

Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.

ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply

Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")

Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support

Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7

Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A

Refer Linux commit <22a442e6586c>
("arm64: dts: rockchip: add basic dts for the radxa rock3 model a")

Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

binman: Mark mkimage entry missing when its subnodes is missing

Using the mkimage entry with the multiple-data-files prop and having a
missing external blob result in an unexpected ValueError exception using
the --allow-missing flag.

  ValueError: Filename 'missing.bin' not found in input path (...)

Fix this by using _pathname that is resolved by ObtainContents for blob
entries, ObtainContents also handles allow missing for external blobs.

Mark mkimage entry as missing and return without running mkimage when
missing entries is reported by CheckMissing.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: mkimage: Update init size limit for RK3568

The current init size limit of 76KiB is too big to fit in the 64KiB SRAM
on RK3568, sync init size limit from vendor u-boot to fix this.

Set init size limit to 60KiB (-16KiB) for RK3568.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: mkimage: Update init size limit for RK3328

Latest vendor TPL for RK3328 has grown past the current init size limit
of 28KiB, sync the init size limit from vendor u-boot to fix this.

Set init size limit to 30KiB (+2KiB) for RK3328.

This makes it possible to use latest vendor TPL on RK3328 without
getting a size limit error running the mkimage command.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Revert "board: rockchip: Fix binman_init failure on EVB-RK3568"

An external TPL binary is now expected to be provided using ROCKCHIP_TPL
when building RK3568 targets.

This reverts commit 31500e7bcfaca08ab7c2879f502a6cf852410244.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: Use an external TPL binary on RK3568

Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
jumps to U-Boot SPL to continue the normal boot flow.

However, there is no support to initialize DRAM on RK35xx SoCs using
U-Boot TPL and instead an external TPL binary must be used to generate a
bootable u-boot-rockchip.bin image.

Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
bootable u-boot-rockchip.bin image for RK3568.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>

binman: Add support for a rockchip-tpl entry

The rockchip-tpl entry can be used when an external TPL binary should be
used instead of the normal U-Boot TPL.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>

rockchip: dts: rk3328: fix sdram params

The rk3328 sdram driver read sdram parameters from the devicetree into a
struct rk3328_sdram_params using dev_read_u32_array.

After commit 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30")
changed the size of struct ddr_pctl_regs, a member of struct
rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328.

Add ten u32 to the sdram parameter array in devicetree to align with
this size change. This fixes DRAM initialization on RK3328.

Fixes: 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc

rockchip: sdram: add dram bank with usable memory beyond 4GB

Add a second dram bank of usable memory beyond the blob of space for
peripheral near 4GB. Any memory that exists beyond the 4GB mark is added
to the second bank.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: sdram: add basic support for sdram reg info version 3

Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.

Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.

This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.

Details on the new format was deciphered from vendor u-boot commit [1].

[1] https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: ringneck: fix SDRAM init fail

CONFIG_RAM_PX30_DDR4 got renamed to CONFIG_RAM_ROCKCHIP_DDR4 in commit
26f92be07e2a ("ram: rockchip: Add common ddr type configs"). Since both
patchsets were merged unbeknownst to the other, the conflict wasn't
detected while testing each patchset individually and could only be
observed after a merge to master branch.

Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handling

The RK3288 TRM states that, for 8-bit DDR modes:

The CLKDIV register should always be programmed with a value
higher than zero (0); that is, a clock divider should always be
used for 8-bit DDR mode.

In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.

Add the necessary code to double the clock frequency when 8-bit DDR is
selected.  The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfo

Provide human-readable manufacturer and product names for the
FriendlyELEC NanoPi R4S.

Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default.

Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Prepare v2023.04-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>

configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra

Merge branch '2023-02-23-assorted-fixes'

- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally,
  relax one of the trace test time requirements (so CI doesn't fail due
  to test being slightly slow, but still correct), and correct env on
  MMC and checking for where GPT can be

ARM: tegra20: implement BCT patching

This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypt BCT.

Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra30: implement BCT patching

This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypted BCT.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: crypto: extend crypto functional

Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: expose crypto module for all Tegra SoCs

Move crypto module from T20 only into common Tegra dir.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

board: tegra30: switch to updated pre-dm i2c write

Configure PMIC voltages for early stages using updated
early i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>

board: tegra124: switch to updated pre-dm i2c write

Configure PMIC for early stages using updated i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: create common pre-dm i2c write

This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.

Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: add late init support

Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: provide default USB gadget setup

All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.

Inspired by commit e02687bda96c ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.

Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

spi: tegra20_slink: accept any word length

Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: Fix Tegra PWM parent clock

Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra30: add PLLD to pll setup

On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: clock: add clock_decode_pair helper

Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: tegra: clock: add clk_id_to_pll_id helper

This function allows to convert a device tree clock ID to PLL ID.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

ARM: t20/t30: swap host1x and disp1 clock parents

According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

tegra30: clock: add EXTPERIPH

This mappings were missing for some reason.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>

env: mmc: Apply GPT only on eMMC user HW partition

Apply the GPT U-Boot environment GUID type look up only on eMMC user
HW partition, do not apply the look up on eMMC boot HW partitions as
mmc_offset_try_partition() assumes either SD partitions or eMMC user
HW partition.

This fixes environment operation on systems where CONFIG_SYS_MMC_ENV_PART
is non-zero and CONFIG_SYS_REDUNDAND_ENVIRONMENT is set.

Fixes: 80105d8fd52 ("env: mmc: select GPT env partition by type guid")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

trace: Relax test requirements

We expect the profile and bootstage to agree on timing, but when
running on slow machines there can be a larger descrepency. Increase the
tolerance to fix this.

Fixes: 9cea4797aeb ("trace: Add a test")
Signed-off-by: Simon Glass <sjg@chromium.org>

x86: Pass -z execstack for EFI payload flags

To match how we link EFI executables elsewhere, and to silence a linker
warning, pass -z execstack here as well.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile: Link with -z noexectack

When moving to gcc-12.2 we started trying to quiet some of the new
linker warnings, that are not relevant to us. However, a
misunderstanding of the mechanics at play meant that I intentionally
omitted passing -z noexecstack to the linker, when we do need to. Add
this flag and in turn remove warnings from the linker.

Fixes: 1e1c51f8ace8 ("Makefile: link with --no-warn-rwx-segments")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

fs: btrfs: limit the mapped length to the original length

[BUG]
There is a bug report that btrfs driver caused hang during file read:

  This breaks btrfs on the HiFive Unmatched.

  => pci enum
  PCIE-0: Link up (Gen1-x8, Bus0)
  => nvme scan
  => load nvme 0:2 0x8c000000 /boot/dtb/sifive/hifive-unmatched-a00.dtb
  [hangs]

[CAUSE]
The reporter provided some debug output:

  read_extent_data: cur=615817216, orig_len=16384, cur_len=16384
  read_extent_data: btrfs_map_block: cur_len=479944704; ret=0
  read_extent_data: ret=0
  read_extent_data: cur=615833600, orig_len=4096, cur_len=4096
  read_extent_data: btrfs_map_block: cur_len=479928320; ret=0

Note the second and the last line, the @cur_len is 450+MiB, which is
almost a chunk size.

And inside __btrfs_map_block(), we limits the returned value to stripe
length, but that's depending on the chunk type:

if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 |
 BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 |
 BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 |
 BTRFS_BLOCK_GROUP_RAID10 |
 BTRFS_BLOCK_GROUP_DUP)) {
/* we limit the length of each bio to what fits in a stripe */
*length = min_t(u64, ce->size - offset,
      map->stripe_len - stripe_offset);
} else {
*length = ce->size - offset;
}

This means, if the chunk is SINGLE profile, then we don't limit the
returned length at all, and even for other profiles, we can still return
a length much larger than the requested one.

[FIX]
Properly clamp the returned length, preventing it from returning a much
larger range than expected.

Reported-by: Andreas Schwab <schwab@linux-m68k.org>
Signed-off-by: Qu Wenruo <wqu@suse.com>

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb

- DWC3 bugfix

Merge https://source.denx.de/u-boot/custodians/u-boot-socfpga

- chameleonv3 updates

chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig

This file was missed during the conversion process. Add the symbol to
defconfig.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

arm: dts: chameleonv3: Add 270-2 variant

Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi

This file is included by the different chameleonv3 variants. Change the
name to .dtsi.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

arm: dts: chameleonv3: Override chameleonv3 bitstream names

Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

socfpga: chameleonv3: Move environment to a text file

Move the environment to an easily editable text file in the boot
partition

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

socfpga: chameleonv3: Enable ext4 in SPL

Allow SPL to boot from an ext4 filesystem.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpio

As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>

Merge tag 'efi-2023-04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-04-rc3

Documentation

* Add a document for the RISC-V architecture
* Move gateworks and bcm7xxx documentation to HTML

UEFI

* measure the loaded device-tree
* make CapsuleMax configurable and provide sensible default

doc: remove superfluous warning

We have been using Sphinx >=3 since 2020. We don't expect issues.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

efi_loader: set CapsuleMax from CONFIG_EFI_CAPSULE_MAX

Adds CONFIG_EFI_CAPSULE_MAX to configure the max index value used in
EFI capsule reports. Prior to this change is the hard coded value was
65535 which would exceed available storage for variables. Now the
default value is 15 which should work fine with most systems.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

efi_loader: Measure the loaded DTB

Measures the DTB passed to the EFI application upon new boolean config
switch CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB. For platforms where the
content of the DTB passed to the OS can change across reboots, there is
not point measuring it hence the config switch to allow platform to not
embed this feature.

Co-developed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

efi_loader: fix wrong attribute check for QueryVariableInfo

QueryVariableInfo with EFI_VARIABLE_HARDWARE_ERROR_RECORD is
accepted, remove wrong attribute check.

Fixes: 454a9442fbce ("efi_loader: update attribute check for QueryVariableInfo()")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

efi_loader: avoid buffer overrun in efi_var_mem_compare

We should not scan beyond the end of string name.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

doc: arch: Add document for RISC-V architecture

This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

board: gateworks: venice: move README to RST

Move board/gateworks/venice/README to RST documentation.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

doc: board: bcm7xxx: Convert to reStructuredText format

Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

doc: devicetree: dt_qemu.rst: Fix the typo and space

Fix typo and whitespace in the document.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

Merge branch '2023-02-17-assorted-fixes'

- avb_verify bugfix, and cpsw_mdio bugfix

common: avb_verify: prevent opening incorrect session

The arg->session is not valid if arg->ret != NULL, so can't be
assigned, correct this.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@globallogic.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

cpsw_mdio.c: Use correct reg in cpsw_mdio_get_alive

cpsw_mdio_get_alive reads the wrong register.
See page 2316 in SPRUH73Q AM335x TRM

Signed-off-by: Ulf Samuelsson <ulf@emagii.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>

configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>

Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

- binman: Add help message if opensbi is absent when building u-boot SPL
- AndesTech: rename cpu and board name to 'andesv5' and 'ae350'
- Clean up cache operation for Andes ae350 platform

riscv: binman: Add help message for missing blobs

Add the 'missing-msg' for more detailed output
on missing system firmware.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

riscv: ae350: Adjust the memory layout of ae350

Adjust the initial stack pointer address to 0x10000000(256M)

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

riscv: Rename Andes cpu and board names

The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

driver: cache-v5l2: Fix type casting warning on RV32

This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

configs: ae350: Display CPU and board info for AE350 platforms

Display information about CPU and board during start up.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

configs: ae350: Increase maximum retry count for AE350 platforms

Loading an image via TFTP is often interrupted when retrying more than
10 times, increase the number of retries so that it does not simply stop
the transfer.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

configs: ae350: Enable v5l2 cache for AE350 platforms in SPL

To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac2c643db3a3f2eb37afc60fae15177e

Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

riscv: ae350: dts: Update L2 cache compatible string

Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>