Stephen Neuendorffer [Mon, 9 Dec 2019 22:27:11 +0000 (14:27 -0800)]
[MLIR] Allow non-binary operations to be commutative
NFC for binary operations.
Differential Revision: https://reviews.llvm.org/D73670
Rachel Craik [Mon, 10 Feb 2020 18:14:59 +0000 (13:14 -0500)]
[LoopCacheAnalysis]: Add support for negative stride
LoopCacheAnalysis currently assumes the loop will be iterated over in
a forward direction. This patch addresses the issue by using the
absolute value of the stride when iterating backwards.
Note: this patch will treat negative and positive array access the
same, resulting in the same cost being calculated for single and
bi-directional access patterns. This should be improved in a
subsequent patch.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D73064
Dimitry Andric [Thu, 6 Feb 2020 22:18:19 +0000 (23:18 +0100)]
[Sanitizers] Get link map on FreeBSD via documented API
Summary:
Instead of hand-crafting an offset into the structure returned by
dlopen(3) to get at the link map, use the documented API. This is
described in dlinfo(3): by calling it with `RTLD_DI_LINKMAP`, the
dynamic linker ensures the right address is returned.
Reviewers: devnexen, emaste, MaskRay, krytarowski
Reviewed By: krytarowski
Subscribers: krytarowski, vitalybuka, #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D73990
Vedant Kumar [Mon, 10 Feb 2020 18:10:10 +0000 (10:10 -0800)]
debugserver: Rely on mig architectures being specified externally
Look up the -arch flags to pass to the mig invocation from an
optionally-defined MIG_ARCHS variable. We can't use CMAKE_OSX_ARCHS
because the {i,tv,watch}OS builds don't use this mechanism to achieve
fat builds (they build each slice separately & then lipo them together).
This supercedes the mig -arch/-isysroot fix from
510758dae2a8fa4b0b26dea89d4d1efd576b8ad6.
Jonas Paulsson [Wed, 5 Feb 2020 13:43:35 +0000 (14:43 +0100)]
[SystemZ] Add a subtarget cache like some other targets already have.
Each function is with this compiled with the SystemZSubtarget initialized
from the functions attributes.
Review: Ulrich Weigand.
Differential Revision: https://reviews.llvm.org/D74086
Eric Christopher [Mon, 10 Feb 2020 18:07:37 +0000 (10:07 -0800)]
Remove llgo per discussion on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139058.html
Approved by dblaikie, pcc.
Vedant Kumar [Mon, 10 Feb 2020 18:06:14 +0000 (10:06 -0800)]
[Host.mm] Check for the right macro instead of inlining it
Differential Revision: https://reviews.llvm.org/D73938
Matt Arsenault [Sun, 9 Feb 2020 21:38:56 +0000 (16:38 -0500)]
AMDGPU: Move R600 test compatability hack
Instead of handling the r600 intrinsics on amdgcn, handle the amdgcn
intrinsics on r600.
Simon Pilgrim [Mon, 10 Feb 2020 17:47:46 +0000 (17:47 +0000)]
[X86] combineConcatVectorOps - combine X86ISD::PACKSS ops
Simon Pilgrim [Mon, 10 Feb 2020 17:32:58 +0000 (17:32 +0000)]
[X86] combineConcatVectorOps - combine X86ISD::VPERMI ops
Michael Kruse [Mon, 10 Feb 2020 17:13:00 +0000 (11:13 -0600)]
Silence compiler warning. NFC.
The idiom
for (auto i = n - n; i < n; i += 1)
was intended to automatically derive the type of i from n
(signed/unsigned int) and avoid the 'mixed signed/unsigned comparison'
warning. However, almost-always-auto was never used in the LLVM coding
style (although we used it in Polly for some time) and I did never
intended to use this idiom upstream.
PVS Studio may warns about this idiom as 'warning: both sides of
operator are equivalent [misc-redundant-expression]'.
Remove the use of auto and directly use unsigned.
Also see http://llvm.org/PR44768
aartbik [Fri, 7 Feb 2020 22:32:08 +0000 (14:32 -0800)]
[mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect
Summary:
This allows for lowering of VectorOps (and others) into a LLVM IR
that maps directly to efficient implementations on the target machines.
http://llvm.org/docs/LangRef.html#experimental-vector-reduction-intrinsics
Reviewers: ftynse, andydavis1, nicolasvasilache, rriddle
Reviewed By: ftynse, rriddle
Subscribers: jfb, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74171
Nicolas Vasilache [Mon, 10 Feb 2020 16:55:02 +0000 (11:55 -0500)]
[mlir][EDSC] Almost NFC - Refactor and untangle EDSC dependencies
This CL refactors EDSCs to layer them better and break unnecessary
dependencies. After this refactoring, the top-level EDSC target only
depends on IR but not on Dialects anymore and each dialect has its
own EDSC directory.
This simplifies the layering and breaks cyclic dependencies.
In particular, the declarative builder + folder are made explicit and
are now confined to Linalg.
As the refactoring occurred, certain classes and abstractions that were not
paying for themselves have been removed.
Differential Revision: https://reviews.llvm.org/D74302
Simon Pilgrim [Mon, 10 Feb 2020 16:48:39 +0000 (16:48 +0000)]
[X86] combineConcatVectorOps - combine VSHLI/VSRAI/VSRLI ops
Non-AVX512BW targets failed to concatenate 256-bit shifts back to 512-bits (split during 512-bit shuffle lowering as they don't have v32i16/v64i8 types).
David Stenberg [Mon, 10 Feb 2020 16:14:15 +0000 (17:14 +0100)]
Revert "[InstCombine][DebugInfo] Fold constants wrapped in metadata"
This reverts commit
b54a8ec1bcd3689771c847cb37515b627034e518.
The commit triggered debug invariance (different output with/without
-g). The patch seems to have exposed a pre-existing invariance problem
in GlobalOpt, which I'll write a bug report for.
Kadir Cetinkaya [Mon, 10 Feb 2020 16:54:00 +0000 (17:54 +0100)]
[mlir] Delete unused header
Saleem Abdulrasool [Mon, 10 Feb 2020 16:52:31 +0000 (08:52 -0800)]
unwind: rename `__personality_routine` to `_Unwind_Personality_Fn`
This patch renames `__personality_routine` to `_Unwind_Personality_Fn`
in `unwind.h`. Both `unwind.h` from clang and GCC headers use this name
instead of `__personality_routine`. With this patch one is also able to
build libc++abi with libunwind support on Windows.
Patch by Markus Böck!
Tobias Gysi [Mon, 10 Feb 2020 16:29:50 +0000 (17:29 +0100)]
[mlir] subview op lowering for target memrefs with const offset
The current standard to llvm conversion pass lowers subview ops only if
dynamic offsets are provided. This commit extends the lowering with a
code path that uses the constant offset of the target memref for the
subview op lowering (see Example 3 of the subview op definition for an
example) if no dynamic offsets are provided.
Differential Revision: https://reviews.llvm.org/D74280
Stanislav Mekhanoshin [Fri, 7 Feb 2020 20:08:32 +0000 (12:08 -0800)]
[AMDGPU] Split R600 and GCN subregs
These are generated and do not need to have the same values.
We are defining separate subregs for R600 and GCN but then
using AMDGPU subregs on R600.
Differential Revision: https://reviews.llvm.org/D74248
James Henderson [Mon, 10 Feb 2020 16:21:46 +0000 (16:21 +0000)]
[DebugInfo][test] Fix host endian test issue
The test previously assumed that the host was little endian, which broke
the big endian build bots.
Simon Pilgrim [Mon, 10 Feb 2020 16:16:16 +0000 (16:16 +0000)]
[X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
REAPPLIED rGe82e17d4d4ca after reversion at rG39eade73a567 - fixed offset matching in matchShuffleAsBitRotate.
LLVM GN Syncbot [Mon, 10 Feb 2020 15:56:57 +0000 (15:56 +0000)]
[gn build] Port
0151ddc2e83
Michael Wyman [Fri, 7 Feb 2020 23:08:17 +0000 (16:08 -0700)]
Create a clang-tidy check to warn when -dealloc is implemented inside an ObjC class category.
Summary: Such implementations may override the class's own implementation, and even be a danger in case someone later comes and adds one to the class itself. Most times this has been encountered have been a mistake.
Reviewers: stephanemoore, benhamilton, dmaclach
Reviewed By: stephanemoore, benhamilton, dmaclach
Subscribers: dmaclach, mgorny, cfe-commits
Tags: #clang-tools-extra, #clang
Differential Revision: https://reviews.llvm.org/D72876
Gabor Marton [Mon, 10 Feb 2020 15:16:44 +0000 (16:16 +0100)]
[analyzer] StdLibraryFunctionsChecker refactor: remove macros
Reviewers: NoQ
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73897
Kadir Cetinkaya [Mon, 10 Feb 2020 13:44:51 +0000 (14:44 +0100)]
Revert "[OpenMP] Fix unused variable"
This breaks under asan, see http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/38597/steps/check-clang%20asan/logs/stdio
This reverts commit
bb5045429545f47a76980864322a637c31594c7f.
Revert "[FIX] Ordering problem accidentally introduced with D72304"
This reverts commit
08c0a06d8f375e48d4acebac886bfdf19a2276ed.
Revert "[OpenMP][OMPIRBuilder] Add Directives (master and critical) to OMPBuilder."
This reverts commit
e8a436c5ea26f69378e4c1cf3ddb5b647b201e0f.
Florian Hahn [Mon, 10 Feb 2020 15:18:46 +0000 (15:18 +0000)]
[DSE,MSSA] Adjust mda-with-dbg-values.ll to MSSA backed DSE.
-memdep-block-scan-limit is not relevant with MSSA.
James Henderson [Mon, 10 Feb 2020 15:09:16 +0000 (15:09 +0000)]
[DebugInfo][test] Fix(?) build bots due to incorrect type usage
Bill Wendling [Mon, 10 Feb 2020 15:06:45 +0000 (07:06 -0800)]
Revert "Remove redundant "std::move"s in return statements"
The build failed with
error: call to deleted constructor of 'llvm::Error'
errors.
This reverts commit
1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
Max Moroz [Thu, 6 Feb 2020 16:44:42 +0000 (08:44 -0800)]
[compiler-rt] Some clean up / refactoring in sanitizer_symbolizer_libcdep.cpp.
Summary:
Nothing critical, just a few potential improvements I've noticed while reading
the code:
- return `false` when symbolizer buffer is too small to read all data
- invert some conditions to reduce indentation
- prefer `nullptr` over `0` for pointers; init some pointers on stack;
- remove minor code duplication
Reviewers: eugenis, vitalybuka
Subscribers: dberris, #sanitizers, llvm-commits, kcc
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D74137
James Henderson [Mon, 10 Feb 2020 14:17:46 +0000 (14:17 +0000)]
[DebugInfo] Reject line tables of version > 5
If a debug line section with version of greater than 5 is encountered,
prior to this change the parser would accept it and treat it as version
5. This might work to some extent, but then it might not at all, as it
really depends on the format of the unspecified future version, which
will be different (otherwise there would be no point in changing the
version number). Any information we could provide has a good chance of
being invalid, so we should just refuse to parse such tables.
Reviewed by: dblaikie, MaskRay
Differential Revision: https://reviews.llvm.org/D74204
James Henderson [Mon, 10 Feb 2020 14:40:47 +0000 (14:40 +0000)]
[NFC] Fix line endings
Bill Wendling [Mon, 10 Feb 2020 13:18:09 +0000 (05:18 -0800)]
Remove redundant "std::move"s in return statements
Luke Geeson [Mon, 10 Feb 2020 14:29:59 +0000 (14:29 +0000)]
[AArch64] Make Read Write System Registers Read Only
This patch makes the following System Registers Read Only:
- CurrentEL
- ICH_MISR_EL2
- PMBIDR_EL1
- PMSIDR_EL1
as found in:
https://developer.arm.com/docs/ddi0595/e/aarch64-system-registers
Relative line numbers were also added to the tests so we get more
informative error messages on failure.
Change-Id: I963b4f01ca5737b58f9e8e7abe9ca1d99e328758
Richard Smith [Mon, 10 Feb 2020 14:05:59 +0000 (06:05 -0800)]
CWG2445: For function template partial ordering, take reversal of
function arguments into account when forming P/A pairs.
Sebastian Neubauer [Fri, 31 Jan 2020 13:18:18 +0000 (14:18 +0100)]
[SelectionDAG] Optimize build_vector of truncates and shifts
Add a simplification to fuse a manual vector extract with shifts and
truncate into a bitcast.
Unpacking and packing values into vectors is only optimized with
extractelement instructions, not when manually unpacked using shifts
and truncates.
This patch simplifies shifts and truncates into a bitcast if possible.
Simplify (build_vec (trunc $1)
(trunc (srl $1 width))
(trunc (srl $1 (2 * width))) ...)
to (bitcast $1)
Differential Revision: https://reviews.llvm.org/D73892
Alex Zinenko [Mon, 10 Feb 2020 13:12:47 +0000 (14:12 +0100)]
[mlir] use unpacked memref descriptors at function boundaries
The existing (default) calling convention for memrefs in standard-to-LLVM
conversion was motivated by interfacing with LLVM IR produced from C sources.
In particular, it passes a pointer to the memref descriptor structure when
calling the function. Therefore, the descriptor is allocated on stack before
the call. This convention leads to several problems. PR44644 indicates a
problem with stack exhaustion when calling functions with memref-typed
arguments in a loop. Allocating outside of the loop may lead to concurrent
access problems in case the loop is parallel. When targeting GPUs, the contents
of the stack-allocated memory for the descriptor (passed by pointer) needs to
be explicitly copied to the device. Using an aggregate type makes it impossible
to attach pointer-specific argument attributes pertaining to alignment and
aliasing in the LLVM dialect.
Change the default calling convention for memrefs in standard-to-LLVM
conversion to transform a memref into a list of arguments, each of primitive
type, that are comprised in the memref descriptor. This avoids stack allocation
for ranked memrefs (and thus stack exhaustion and potential concurrent access
problems) and simplifies the device function invocation on GPUs.
Provide an option in the standard-to-LLVM conversion to generate auxiliary
wrapper function with the same interface as the previous calling convention,
compatible with LLVM IR porduced from C sources. These auxiliary functions
pack the individual values into a descriptor structure or unpack it. They also
handle descriptor stack allocation if necessary, serving as an allocation
scope: the memory reserved by `alloca` will be freed on exiting the auxiliary
function.
The effect of this change on MLIR-generated only LLVM IR is minimal. When
interfacing MLIR-generated LLVM IR with C-generated LLVM IR, the integration
only needs to require auxiliary functions and change the function name to call
the wrapper function instead of the original function.
This also opens the door to forwarding aliasing and alignment information from
memrefs to LLVM IR pointers in the standrd-to-LLVM conversion.
James Henderson [Fri, 7 Feb 2020 09:18:43 +0000 (09:18 +0000)]
[DebugInfo][test] Replace pre-canned binary test
The DebugInfo/dwarfdump-invalid-line-table test used a pre-canned binary
generated by a fuzzer to demonstrate a bug fix. Unfortunately, the
binary is rigid and requires hand-editing if we change behaviour, such
as rejecting certain properties within it (as I plan on doing in another
change).
Rather than hand-edit the binary, I have replaced it with two tests. The
first tests the high-level code path from the debug line parser that
produces the same error as this test previously did, and the second is a
set of unit test cases that comprehensively cover the
FormValue::skipValue method, which in turn covers the area that the
original bug fix touched.
Reviewed by: MaskRay, dblaikie
Differential Revision: https://reviews.llvm.org/D74202
Kai Nacke [Wed, 8 Jan 2020 19:26:12 +0000 (14:26 -0500)]
[SystemZ] Add implementation for the intrinsic llvm.read_register
This change implements the llvm intrinsic llvm.read_register for
the SystemZ platform which returns the value of the specified
register
(http://llvm.org/docs/LangRef.html#llvm-read-register-and-llvm-write-register-intrinsics).
This implementation returns the value of the stack register, and
can be extended to return the value of other registers. The
implementation for this intrinsic exists on various other platforms
including Power, x86, ARM, etc. but missing on SystemZ.
Reviewers: uweigand
Differential Revision: https://reviews.llvm.org/D73378
Hans Wennborg [Mon, 10 Feb 2020 13:07:41 +0000 (14:07 +0100)]
Fix an unused variable warning
Georgii Rymar [Wed, 5 Feb 2020 13:53:27 +0000 (16:53 +0300)]
[llvm-readobj] - Change the error to warning when a section name is unknown.
We reported the error in this case.
But it was asked (https://reviews.llvm.org/D73193#inline-665595) to convert it
to a warning. This patch does it.
Differential revision: https://reviews.llvm.org/D74047
Mikael Holmen [Mon, 10 Feb 2020 12:32:44 +0000 (13:32 +0100)]
Fix compiler warning when compiling without asserts [NFC]
Louis Dionne [Mon, 10 Feb 2020 12:47:27 +0000 (13:47 +0100)]
[libc++][span] Add failing tests for span::first and span::last
Both methods have compile time constraints that we should test against.
Patch by Michael Schellenberger Costa
Differential Revision: https://reviews.llvm.org/D71999
Kadir Cetinkaya [Mon, 10 Feb 2020 12:38:58 +0000 (13:38 +0100)]
[OpenMP] Fix unused variable
Nico Weber [Mon, 10 Feb 2020 12:42:27 +0000 (07:42 -0500)]
[gn build] make 'clang' target depend on libcxx/include on mac
On macOS, libc++ headers are distributed with the compiler, not
the sysroot. Without this, compiling a file that includes something
like <string> won't compile with gn-built clang without manual tweaks.
I used to do the manual tweaks, but now that other people are starting
to use this on mac, let's make it Just Work.
(This is marginally nicer than the cmake build now in that you can
just build 'clang' and it'll do the right thing.)
Differential Revision: https://reviews.llvm.org/D74247
Louis Dionne [Mon, 10 Feb 2020 12:38:04 +0000 (13:38 +0100)]
[libc++] Protect <span> against min/max macro
Patch by Corentin Jabot
Differential Revision: https://reviews.llvm.org/D73855
Florian Hahn [Mon, 10 Feb 2020 12:37:22 +0000 (12:37 +0000)]
[DSE,MSSA] Move more passing test cases from todo to simple.ll.
Kerry McLaughlin [Mon, 10 Feb 2020 11:33:06 +0000 (11:33 +0000)]
[AArch64][SVE] SVE2 intrinsics for complex integer arithmetic
Summary:
Adds the following SVE2 intrinsics:
- cadd & sqcadd
- cmla & sqrdcmlah
- saddlbt, ssublbt & ssubltb
Reviewers: sdesmalen, dancgr, efriedma, cameron.mcinally, c-rhodes, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73636
Simon Pilgrim [Mon, 10 Feb 2020 11:58:05 +0000 (11:58 +0000)]
Revert rGe82e17d4d4cac8b2df00094e80d5e1cb22795664 - [X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
---
Internal shuffle tests indicate theres a bug somewhere that I haven't been able to track down yet.
Raphael Isemann [Mon, 10 Feb 2020 11:45:19 +0000 (12:45 +0100)]
[lldb][NFC] Don't hide a bool in LibCxxOptional's OptionalFrontend::m_size
m_size can only be 1 or 0 and indicates if the optional has a value. Calling
it 'm_size', giving it a size_t data type and then also comparing indices against
'size' is very confusing. Let's just make this a bool.
Florian Hahn [Mon, 10 Feb 2020 10:44:37 +0000 (10:44 +0000)]
[DSE] Add first version of MemorySSA-backed DSE (Bottom up walk).
This patch adds a first version of a MemorySSA based DSE. It is missing
a lot of features, which will get added as follow-ups, to help to keep
the review manageable.
The patch uses the following general approach: given a MemoryDef, walk
upwards to find clobbering MemoryDefs that may be killed by the
starting def. Then check that there are no uses that may read the
location of the original MemoryDef in between both MemoryDefs. A bit
more concretely:
For all MemoryDefs StartDef:
1. Get the next dominating clobbering MemoryDef (DomAccess) by walking upwards.
2. Check that there no reads between DomAccess and the StartDef by checking
all uses starting at DomAccess and walking until we see StartDef.
3. For each found DomDef, check that:
1. There are no barrier instructions between DomDef and StartDef (like
throws or stores with ordering constraints).
2. StartDef is executed whenever DomDef is executed.
3. StartDef completely overwrites DomDef.
4. Erase DomDef from the function and MemorySSA.
The patch uses a very simple approach to guarantee that no throwing
instructions are between 2 stores: We only allow accesses to stack
objects, access that are in the same basic block if the block does not
contain any throwing instructions or accesses in functions that do
not contain any throwing instructions. This will get lifted later.
Besides adding support for the missing cases, there is plenty of additional
potential for improvements as follow-up work, e.g. the way we visit stores
(could be just a traversal of the MemorySSA, rather than collecting them
up-front), using the alias information discovered during walking to optimize
the MemorySSA.
This is loosely based on D40480 by Dave Green.
Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea, Tyker
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D72700
Raphael Isemann [Mon, 10 Feb 2020 11:39:42 +0000 (12:39 +0100)]
[lldb][NFC] Don't call call formatv for no reason in LibCxxOptional
Raphael Isemann [Mon, 10 Feb 2020 11:37:44 +0000 (12:37 +0100)]
[lldb][NFC] Fix code style of LibcxxVariantIndexValidity
Enum cases aren't all uppercase.
Raphael Isemann [Mon, 10 Feb 2020 11:23:01 +0000 (12:23 +0100)]
[lldb][NFC] Don't construct a ConstString twice in LibCxxVariant
Kerry McLaughlin [Mon, 10 Feb 2020 11:08:00 +0000 (11:08 +0000)]
[AArch64][SVE] SVE2 intrinsics for character match & histogram generation
Summary:
Implements the following intrinsics:
- @llvm.aarch64.sve.histcnt
- @llvm.aarch64.sve.histseg
- @llvm.aarch64.sve.match
- @llvm.aarch64.sve.nmatch
Reviewers: c-rhodes, sdesmalen, dancgr, efriedma, rengolin
Reviewed By: c-rhodes
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74117
Kirill Bobyrev [Mon, 10 Feb 2020 10:53:17 +0000 (11:53 +0100)]
[clangd] Support renaming designated initializers
Summary:
Clangd does not find references of designated iniitializers yet and, as a
result, is unable to rename such references. This patch addresses this issue.
Resolves: https://github.com/clangd/clangd/issues/247
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: merge_guards_bot, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72867
Kerry McLaughlin [Mon, 10 Feb 2020 10:30:12 +0000 (10:30 +0000)]
[AArch64][SVE] Add SVE2 intrinsics for widening DSP operations
Summary:
Implements the following intrinsics:
- @llvm.aarch64.sve.[s|u]abalb
- @llvm.aarch64.sve.[s|u]abalt
- @llvm.aarch64.sve.[s|u]addlb
- @llvm.aarch64.sve.[s|u]addlt
- @llvm.aarch64.sve.[s|u]sublb
- @llvm.aarch64.sve.[s|u]sublt
- @llvm.aarch64.sve.[s|u]abdlb
- @llvm.aarch64.sve.[s|u]abdlt
- @llvm.aarch64.sve.sqdmullb
- @llvm.aarch64.sve.sqdmullt
- @llvm.aarch64.sve.[s|u]mullb
- @llvm.aarch64.sve.[s|u]mullt
Reviewers: sdesmalen, dancgr, efriedma, cameron.mcinally, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73719
Florian Hahn [Fri, 6 Dec 2019 14:55:07 +0000 (14:55 +0000)]
[DSE] Add tests for MemorySSA based DSE.
This copies the DSE tests into a MSSA subdirectory to test the MemorySSA
backed DSE implementation, without disturbing the original tests.
Differential Revision: https://reviews.llvm.org/D72145
Frank Laub [Mon, 10 Feb 2020 09:17:28 +0000 (01:17 -0800)]
[MLIR][Affine] NFC: Move AffineValueMap and MutableAffineMap
Summary:
The `AffineValueMap` is moved into `Dialect/AffineOps` to prevent a cyclic
dependency between `Analysis` and `Dialect/AffineOps`.
Reviewers: bondhugula, herhut, nicolasvasilache, rriddle, mehdi_amini
Reviewed By: rriddle, mehdi_amini
Subscribers: mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74277
Richard Smith [Mon, 10 Feb 2020 10:17:43 +0000 (02:17 -0800)]
Fix handling of destructor names that name typedefs.
1) Fix a regression in llvmorg-11-init-2485-g0e3a4877840 that would
reject some cases where a class name is shadowed by a typedef-name
causing a destructor declaration to be rejected. Prefer a tag type over
a typedef in destructor name lookup.
2) Convert the "type in destructor declaration is a typedef" error to an
error-by-default ExtWarn to allow codebases to turn it off. GCC and MSVC
do not enforce this rule.
Djordje Todorovic [Mon, 10 Feb 2020 09:43:41 +0000 (10:43 +0100)]
[CSInfo] Fix the assertions regarding updating the CSInfo
The call site info was not updated correctly when deleting
corresponding call instructions.
Differential Revision: https://reviews.llvm.org/D73700
Simon Moll [Mon, 10 Feb 2020 09:34:58 +0000 (10:34 +0100)]
[Doc] Proposal for vector predication
Summary:
Proposal and roadmap towards vector predication in LLVM.
This patch documents that
a) It is recognized that current LLVM is ill-equipped for vector predication.
b) The community is working on a solution.
c) A concrete prototype exists in the VP extension (D57504).
Reviewers: rkruppe, rengolin, cameron.mcinally, SjoerdMeijer, andrew.w.kaylor, craig.topper, sdesmalen, k-ishizaka, lattner, fhahn
Reviewed By: andrew.w.kaylor
Subscribers: rogfer01, merge_guards_bot, simoncook, s.egerton, llvm-commits, efocht
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73889
Jan Kratochvil [Mon, 10 Feb 2020 09:29:26 +0000 (10:29 +0100)]
[lldb] Fix+re-enable Assert StackFrame Recognizer on Linux
D73303 was failing on Fedora Linux and so it was disabled by Skip the
AssertFrameRecognizer test for Linux.
I find no easy way how to find out if it gets recognized as
`__assert_fail` or `__GI___assert_fail` as during `Process` ctor
libc.so.6 is not yet loaded by the debuggee.
DWARF symbol `__GI___assert_fail` overrides the ELF symbol `__assert_fail`.
While external debug info (=DWARF) gets disabled for testsuite (D55859)
that sure does not apply for real world usage.
Differential Revision: https://reviews.llvm.org/D74252
Martin Storsjö [Mon, 10 Feb 2020 09:17:48 +0000 (11:17 +0200)]
[LLDB] Fix GCC warnings about extra semicolons. NFC.
Kai Nacke [Wed, 5 Feb 2020 20:08:19 +0000 (15:08 -0500)]
[SytemZ] Disable vector ABI when using option -march=arch[8|9|10]
When specifying -march=arch[8|9|10], those CPU types do NOT support
the vector extension. In this case the vector ABI must be disabled.
The generated data layout should NOT contain 64-v128.
Reviewers: uweigand
Differential Revision: https://reviews.llvm.org/D74146
Djordje Todorovic [Mon, 10 Feb 2020 08:49:14 +0000 (09:49 +0100)]
[CSInfo] Use isCandidateForCallSiteEntry() when updating the CSInfo
Use the isCandidateForCallSiteEntry().
This should mostly be an NFC, but there are some parts ensuring
the moveCallSiteInfo() and copyCallSiteInfo() operate with call site
entry candidates (both Src and Dest should be the call site entry
candidates).
Differential Revision: https://reviews.llvm.org/D74122
Jan Kratochvil [Mon, 10 Feb 2020 08:50:37 +0000 (09:50 +0100)]
[lldb] [doc] Change sample commands prefix from > to $
Remove all beginning > from the sample commands as my accidental
copy-paste (multiple times...) will discard ./bin/llvm-lit which is
difficult to rebuild (I have to rm -rf and cmake it all again).
Differential Revision: https://reviews.llvm.org/D74296
Raphael Isemann [Thu, 6 Feb 2020 14:11:06 +0000 (15:11 +0100)]
[lldb] Refactored TestCallOverriddenMethod.py to general virtual function test
This actually tests all the different situations in which we can call virtual
functions. This removes also all skipIfs as the first skipIf for Linux is
apparently fixed and the second skipIf was just failing due to the constructor
call (which should be its own test and not be tested here).
Sebastian Neubauer [Wed, 29 Jan 2020 09:04:36 +0000 (10:04 +0100)]
[AMDGPU] Add a16 feature to gfx10
Based on D72931
This adds a new feature called A16 which is enabled for gfx10.
gfx9 keeps the R128A16 feature so it can share all the instruction encodings
with gfx7/8.
Differential Revision: https://reviews.llvm.org/D73956
Johannes Doerfert [Mon, 10 Feb 2020 07:31:20 +0000 (01:31 -0600)]
[Attributor][FIX] Make check lines explicit
There is a bug in `update_test_checks.py` that combines check lines it
should not. For now we unbreak the bots by making all possibilities
explicit.
Johannes Doerfert [Sun, 26 Jan 2020 02:21:41 +0000 (20:21 -0600)]
[Attributor] Simple casts preserve no-alias property
This is a minimal but important advancement over the existing code. A
cast with an operand that is only used in the cast retains the no-alias
property of the operand.
Johannes Doerfert [Mon, 10 Feb 2020 01:08:19 +0000 (19:08 -0600)]
[Attributor][Tests] Run the CGSCC versions on the range.ll test
Djordje Todorovic [Fri, 7 Feb 2020 17:15:04 +0000 (18:15 +0100)]
[llvm-dwarfdump][Stats] Fix the License header
Fix the added License.
Differential Revision: https://reviews.llvm.org/D74207
Amara Emerson [Sun, 9 Feb 2020 18:09:51 +0000 (10:09 -0800)]
[GlobalISel][CallLowering] Tighten constantexpr check for callee.
I'm not sure there's a test case for this, but it's better to be safe.
Johannes Doerfert [Mon, 10 Feb 2020 02:14:35 +0000 (20:14 -0600)]
[Attributor] Allow PHI nodes in AAValueConstantRangeFloating
Traversing PHI nodes is natural with the genericValueTraversal but also
a bit tricky. The problem is similar to the ones we have seen in AAAlign
and AADereferenceable, namely that we continue to increase the range in
each iteration. We use a pessimistic approach here to stop the
iterations. Nevertheless, optimistic information can now be propagated
through a PHI node.
Johannes Doerfert [Mon, 10 Feb 2020 02:21:56 +0000 (20:21 -0600)]
[Attributor][FIX] Remove FIXME that seems outdated
The change is performed as stated by the FIXME and the tests are
adjusted. All changes look fine to me and values can be inferred as
undef without it being an error.
Johannes Doerfert [Mon, 10 Feb 2020 01:08:04 +0000 (19:08 -0600)]
[Attributor] Allow SelectInst in AAValueConstantRangeFloating
The genericValueTraversal will already handle SelectInst properly and we
just needed to allow them in the initialize method.
Johannes Doerfert [Mon, 10 Feb 2020 01:07:30 +0000 (19:07 -0600)]
[Attributor] Look through (some) casts in AAValueConstantRangeFloating
Casts can be handled natively by the ConstantRange class. We do limit it
to extends for now as we assume an integer type in different locations.
A TODO and a test case with a FIXME was added to remove that restriction
in the future.
Johannes Doerfert [Mon, 10 Feb 2020 01:05:15 +0000 (19:05 -0600)]
[Attributor][FIX] Call right base method in AAValueConstantRangeFloating
We now call the base class method as we should.
Craig Topper [Mon, 10 Feb 2020 06:31:30 +0000 (22:31 -0800)]
[X86] Autogenerate complete checks. NFC
Johannes Doerfert [Mon, 10 Feb 2020 01:06:09 +0000 (19:06 -0600)]
[Attributor][Tests][NFC] Add more range tests
Inspired by https://llvm.discourse.group/t/impossible-condition-optimization/461
Johannes Doerfert [Sun, 26 Jan 2020 02:16:31 +0000 (20:16 -0600)]
[Attributor][NFC] Use existing constant instead of magic one
Craig Topper [Mon, 10 Feb 2020 05:48:00 +0000 (21:48 -0800)]
[X86] Make (insert_vector_elt (v8i16 zerovec), i16 %x, 0) generate the same code as (v8i16 (build_vector %x, 0, 0, 0, 0, 0, 0, 0)).
Instead of using a insrw to element 0, use movzx and movd.
Same for v16i8.
Michael Liao [Mon, 10 Feb 2020 05:41:46 +0000 (00:41 -0500)]
Fix `-Wparentheses` warning. NFC.
Michael Liao [Sun, 9 Feb 2020 18:09:19 +0000 (13:09 -0500)]
[clang][codegen] Fix another lifetime emission on alloca on non-default address space.
- Lifetime intrinsics expect the pointer directly from alloca. Need
extra handling for targets with alloca on non-default (or non-zero)
address space.
Craig Topper [Mon, 10 Feb 2020 04:31:56 +0000 (20:31 -0800)]
[X86] Autogenerate complete checks. NFC
Craig Topper [Mon, 10 Feb 2020 02:35:57 +0000 (18:35 -0800)]
[X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns.
Using sign extend forces the adjacent element to either all zeros
or all ones. But all ones is a NAN. So that doesn't seem like a
great idea.
Trying to work on supporting this with strict FP where NAN would
definitely be bad.
Shiva Chen [Mon, 3 Feb 2020 05:52:13 +0000 (13:52 +0800)]
[RISCV] Fix incorrect FP base CFI offset for variable argument functions
When the FP exists, the FP base CFI directive offset should take the size of variable arguments into account.
Differential Revision: https://reviews.llvm.org/D73862
Fangrui Song [Mon, 10 Feb 2020 01:28:20 +0000 (17:28 -0800)]
[DebugInfo] Add a DWARFDataExtractor constructor that takes ArrayRef<uint8_t>
Similar to D67797 (DataExtractor).
Matt Arsenault [Fri, 7 Feb 2020 17:24:15 +0000 (12:24 -0500)]
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF
Narrow these for 64-bit VALU for AMDGPU.
Matt Arsenault [Sun, 26 Jan 2020 02:10:17 +0000 (21:10 -0500)]
AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect
Matt Arsenault [Fri, 7 Feb 2020 16:55:39 +0000 (11:55 -0500)]
GlobalISel: Fix narrowing of G_CTLZ/G_CTTZ
The result type is separate from the source type.
Matt Arsenault [Thu, 6 Feb 2020 22:18:17 +0000 (17:18 -0500)]
AMDGPU/GlobalISel: Don't mis-select vector index on a constant
Vector indexing with a constant index should be folded out in the
legalizer, but this was accidentally falling through. This would
produce the indexing operation with $noreg. Handle this case as a
dynamic index just in case a bug like this happens again in the
future.
Matt Arsenault [Thu, 6 Feb 2020 21:52:04 +0000 (16:52 -0500)]
AMDGPU/GlobalISel: Look through casts when legalizing vector indexing
We were failing to find constants that were casted. I feel like the
artifact combiner should have folded the constant in the trunc before
the custom lowering, but that doesn't happen.
Matt Arsenault [Mon, 6 Jan 2020 20:57:51 +0000 (15:57 -0500)]
AMDGPU: Remove dead kill handling
At one point a custom node was used for kill handling, but now the
intrinsic is directly selected. Remove leftover pattern machinery.
Matt Arsenault [Fri, 27 Dec 2019 18:11:06 +0000 (13:11 -0500)]
AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses
Reverts part of
6524a7a2b9ca072bd7f7b4355d1230e70c679d2f. Since that
commit, the expansion was ignoring the actual save exec register
produced by the instruction, and looking at other instructions. I do
not understand why it was looking at other instructions, but relying
on this scan was wrong.
Fixes verifier errors after SI_IF is tail duplicated, which should be
correct to do. The results were fed into a phi, which was lowered to
the S_MOV_B64_term instructions.
Simon Pilgrim [Sun, 9 Feb 2020 21:49:37 +0000 (21:49 +0000)]
[X86] combineConcatVectorOps - combine VROTLI/VROTRI ops
Fix issue mentioned on rGe82e17d4d4ca - non-AVX512BW targets failed to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
Craig Topper [Sun, 9 Feb 2020 21:08:25 +0000 (13:08 -0800)]
[X86] Use custom isel for (X86sbb_flag 0, 0) so we can use 32-bit SBB for i8/i16.
We were using MOV32r0 and an extract_subreg as an input. By using
custom isel we can move the extract_subreg to after the SBB instead
of on the input.
Craig Topper [Sun, 9 Feb 2020 20:31:21 +0000 (12:31 -0800)]
[X86] Add flag result VT to a MOV32r0 created in X86DAGToDAGISel::Select
The flag isn't used, but I believe this matches the MOV32r0 that
would be created by the table emitter. This should allow this node
to be CSEed with any others created by the table.
Simon Pilgrim [Sun, 9 Feb 2020 21:15:03 +0000 (21:15 +0000)]
[X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
Craig Topper [Sun, 9 Feb 2020 19:57:22 +0000 (11:57 -0800)]
[X86] Use MVT::i32 for the type of a MOV32r0 created in X86DAGToDAGISel::Select.
Not sure if this really matters. The VT isn't really used after
this point. At best it might affect CSE.