sparc: Print out bit names for LEON and LEON3 with -mdebug

gcc/ChangeLog:

* config/sparc/sparc.c (dump_target_flag_bits): Print bit names for
LEON and LEON3.

testsuite: Support single-precision in g++.dg/eh/arm-vfp-unwind.C

g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on
double-precision FPU support. This patch extends it support
single-precision, useful for targets without double-precision.

2021-09-16  Richard Earnshaw  <rearnsha@arm.com>

gcc/testsuite/
* g++.dg/eh/arm-vfp-unwind.C: Support single-precision.

mips: Fix macro typo

gcc/ChangeLog:

* config/mips/netbsd.h: Fix typo in name of a macro.

Check mask type when doing cond_op related gimple simplification.

gcc/ChangeLog:

PR middle-end/102080
* match.pd: Check mask type when doing cond_op related gimple
simplification.
* tree.c (is_truth_type_for): New function.
* tree.h (is_truth_type_for): New declaration.

gcc/testsuite/ChangeLog:

PR middle-end/102080
* gcc.target/i386/pr102080.c: New test.

AVX512FP16: Add testcase for vcvtw2ph/vcvtuw2ph/vcvtdq2ph/vcvtudq2ph/vcvtqq2ph/vcvtuqq2ph.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c: New test.
* gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtw2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtw2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c: Ditto.

AVX512FP16: Add vcvtuw2ph/vcvtw2ph/vcvtdq2ph/vcvtudq2ph/vcvtqq2ph/vcvtuqq2ph

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h (_mm512_cvtepi32_ph): New
intrinsic.
(_mm512_mask_cvtepi32_ph): Likewise.
(_mm512_maskz_cvtepi32_ph): Likewise.
(_mm512_cvt_roundepi32_ph): Likewise.
(_mm512_mask_cvt_roundepi32_ph): Likewise.
(_mm512_maskz_cvt_roundepi32_ph): Likewise.
(_mm512_cvtepu32_ph): Likewise.
(_mm512_mask_cvtepu32_ph): Likewise.
(_mm512_maskz_cvtepu32_ph): Likewise.
(_mm512_cvt_roundepu32_ph): Likewise.
(_mm512_mask_cvt_roundepu32_ph): Likewise.
(_mm512_maskz_cvt_roundepu32_ph): Likewise.
(_mm512_cvtepi64_ph): Likewise.
(_mm512_mask_cvtepi64_ph): Likewise.
(_mm512_maskz_cvtepi64_ph): Likewise.
(_mm512_cvt_roundepi64_ph): Likewise.
(_mm512_mask_cvt_roundepi64_ph): Likewise.
(_mm512_maskz_cvt_roundepi64_ph): Likewise.
(_mm512_cvtepu64_ph): Likewise.
(_mm512_mask_cvtepu64_ph): Likewise.
(_mm512_maskz_cvtepu64_ph): Likewise.
(_mm512_cvt_roundepu64_ph): Likewise.
(_mm512_mask_cvt_roundepu64_ph): Likewise.
(_mm512_maskz_cvt_roundepu64_ph): Likewise.
(_mm512_cvtepi16_ph): Likewise.
(_mm512_mask_cvtepi16_ph): Likewise.
(_mm512_maskz_cvtepi16_ph): Likewise.
(_mm512_cvt_roundepi16_ph): Likewise.
(_mm512_mask_cvt_roundepi16_ph): Likewise.
(_mm512_maskz_cvt_roundepi16_ph): Likewise.
(_mm512_cvtepu16_ph): Likewise.
(_mm512_mask_cvtepu16_ph): Likewise.
(_mm512_maskz_cvtepu16_ph): Likewise.
(_mm512_cvt_roundepu16_ph): Likewise.
(_mm512_mask_cvt_roundepu16_ph): Likewise.
(_mm512_maskz_cvt_roundepu16_ph): Likewise.
* config/i386/avx512fp16vlintrin.h (_mm_cvtepi32_ph): New
intrinsic.
(_mm_mask_cvtepi32_ph): Likewise.
(_mm_maskz_cvtepi32_ph): Likewise.
(_mm256_cvtepi32_ph): Likewise.
(_mm256_mask_cvtepi32_ph): Likewise.
(_mm256_maskz_cvtepi32_ph): Likewise.
(_mm_cvtepu32_ph): Likewise.
(_mm_mask_cvtepu32_ph): Likewise.
(_mm_maskz_cvtepu32_ph): Likewise.
(_mm256_cvtepu32_ph): Likewise.
(_mm256_mask_cvtepu32_ph): Likewise.
(_mm256_maskz_cvtepu32_ph): Likewise.
(_mm_cvtepi64_ph): Likewise.
(_mm_mask_cvtepi64_ph): Likewise.
(_mm_maskz_cvtepi64_ph): Likewise.
(_mm256_cvtepi64_ph): Likewise.
(_mm256_mask_cvtepi64_ph): Likewise.
(_mm256_maskz_cvtepi64_ph): Likewise.
(_mm_cvtepu64_ph): Likewise.
(_mm_mask_cvtepu64_ph): Likewise.
(_mm_maskz_cvtepu64_ph): Likewise.
(_mm256_cvtepu64_ph): Likewise.
(_mm256_mask_cvtepu64_ph): Likewise.
(_mm256_maskz_cvtepu64_ph): Likewise.
(_mm_cvtepi16_ph): Likewise.
(_mm_mask_cvtepi16_ph): Likewise.
(_mm_maskz_cvtepi16_ph): Likewise.
(_mm256_cvtepi16_ph): Likewise.
(_mm256_mask_cvtepi16_ph): Likewise.
(_mm256_maskz_cvtepi16_ph): Likewise.
(_mm_cvtepu16_ph): Likewise.
(_mm_mask_cvtepu16_ph): Likewise.
(_mm_maskz_cvtepu16_ph): Likewise.
(_mm256_cvtepu16_ph): Likewise.
(_mm256_mask_cvtepu16_ph): Likewise.
(_mm256_maskz_cvtepu16_ph): Likewise.
* config/i386/i386-builtin-types.def: Add corresponding builtin types.
* config/i386/i386-builtin.def: Add corresponding new builtins.
* config/i386/i386-expand.c
(ix86_expand_args_builtin): Handle new builtin types.
(ix86_expand_round_builtin): Ditto.
* config/i386/i386-modes.def: Declare V2HF and V6HF.
* config/i386/sse.md (VI2H_AVX512VL): New.
(qq2phsuff): Ditto.
(sseintvecmode): Add HF vector modes.
(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>):
New.
(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>): Ditto.
(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>): Ditto.
(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Ditto.
(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Ditto.
(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask_1): Ditto.
(avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Ditto.
(*avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Ditto.
(avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask): Ditto.
(*avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask): Ditto.
(*avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask_1): Ditto.
* config/i386/subst.md (round_qq2phsuff): New subst_attr.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add test for new builtins.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add test for new intrinsics.
* gcc.target/i386/sse-22.c: Ditto.

AVX512FP16: Add testcase for vcvtph2w/vcvtph2uw/vcvtph2dq/vcvtph2udq/vcvtph2qq/vcvtph2uqq.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-helper.h (V512): Add QI
components.
* gcc.target/i386/avx512fp16-vcvtph2dq-1a.c: New test.
* gcc.target/i386/avx512fp16-vcvtph2dq-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2qq-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2qq-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2udq-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2udq-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2uw-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2uw-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2w-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtph2w-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c: Ditto.

AVX512FP16: Add vcvtph2dq/vcvtph2qq/vcvtph2w/vcvtph2uw/vcvtph2uqq/vcvtph2udq

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h (_mm512_cvtph_epi32):
New intrinsic/
(_mm512_mask_cvtph_epi32): Likewise.
(_mm512_maskz_cvtph_epi32): Likewise.
(_mm512_cvt_roundph_epi32): Likewise.
(_mm512_mask_cvt_roundph_epi32): Likewise.
(_mm512_maskz_cvt_roundph_epi32): Likewise.
(_mm512_cvtph_epu32): Likewise.
(_mm512_mask_cvtph_epu32): Likewise.
(_mm512_maskz_cvtph_epu32): Likewise.
(_mm512_cvt_roundph_epu32): Likewise.
(_mm512_mask_cvt_roundph_epu32): Likewise.
(_mm512_maskz_cvt_roundph_epu32): Likewise.
(_mm512_cvtph_epi64): Likewise.
(_mm512_mask_cvtph_epi64): Likewise.
(_mm512_maskz_cvtph_epi64): Likewise.
(_mm512_cvt_roundph_epi64): Likewise.
(_mm512_mask_cvt_roundph_epi64): Likewise.
(_mm512_maskz_cvt_roundph_epi64): Likewise.
(_mm512_cvtph_epu64): Likewise.
(_mm512_mask_cvtph_epu64): Likewise.
(_mm512_maskz_cvtph_epu64): Likewise.
(_mm512_cvt_roundph_epu64): Likewise.
(_mm512_mask_cvt_roundph_epu64): Likewise.
(_mm512_maskz_cvt_roundph_epu64): Likewise.
(_mm512_cvtph_epi16): Likewise.
(_mm512_mask_cvtph_epi16): Likewise.
(_mm512_maskz_cvtph_epi16): Likewise.
(_mm512_cvt_roundph_epi16): Likewise.
(_mm512_mask_cvt_roundph_epi16): Likewise.
(_mm512_maskz_cvt_roundph_epi16): Likewise.
(_mm512_cvtph_epu16): Likewise.
(_mm512_mask_cvtph_epu16): Likewise.
(_mm512_maskz_cvtph_epu16): Likewise.
(_mm512_cvt_roundph_epu16): Likewise.
(_mm512_mask_cvt_roundph_epu16): Likewise.
(_mm512_maskz_cvt_roundph_epu16): Likewise.
* config/i386/avx512fp16vlintrin.h (_mm_cvtph_epi32):
New intrinsic.
(_mm_mask_cvtph_epi32): Likewise.
(_mm_maskz_cvtph_epi32): Likewise.
(_mm256_cvtph_epi32): Likewise.
(_mm256_mask_cvtph_epi32): Likewise.
(_mm256_maskz_cvtph_epi32): Likewise.
(_mm_cvtph_epu32): Likewise.
(_mm_mask_cvtph_epu32): Likewise.
(_mm_maskz_cvtph_epu32): Likewise.
(_mm256_cvtph_epu32): Likewise.
(_mm256_mask_cvtph_epu32): Likewise.
(_mm256_maskz_cvtph_epu32): Likewise.
(_mm_cvtph_epi64): Likewise.
(_mm_mask_cvtph_epi64): Likewise.
(_mm_maskz_cvtph_epi64): Likewise.
(_mm256_cvtph_epi64): Likewise.
(_mm256_mask_cvtph_epi64): Likewise.
(_mm256_maskz_cvtph_epi64): Likewise.
(_mm_cvtph_epu64): Likewise.
(_mm_mask_cvtph_epu64): Likewise.
(_mm_maskz_cvtph_epu64): Likewise.
(_mm256_cvtph_epu64): Likewise.
(_mm256_mask_cvtph_epu64): Likewise.
(_mm256_maskz_cvtph_epu64): Likewise.
(_mm_cvtph_epi16): Likewise.
(_mm_mask_cvtph_epi16): Likewise.
(_mm_maskz_cvtph_epi16): Likewise.
(_mm256_cvtph_epi16): Likewise.
(_mm256_mask_cvtph_epi16): Likewise.
(_mm256_maskz_cvtph_epi16): Likewise.
(_mm_cvtph_epu16): Likewise.
(_mm_mask_cvtph_epu16): Likewise.
(_mm_maskz_cvtph_epu16): Likewise.
(_mm256_cvtph_epu16): Likewise.
(_mm256_mask_cvtph_epu16): Likewise.
(_mm256_maskz_cvtph_epu16): Likewise.
* config/i386/i386-builtin-types.def: Add new builtin types.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-expand.c
(ix86_expand_args_builtin): Handle new builtin types.
(ix86_expand_round_builtin): Ditto.
* config/i386/sse.md (sseintconvert): New.
(ssePHmode): Ditto.
(UNSPEC_US_FIX_NOTRUNC): Ditto.
(sseintconvertsignprefix): Ditto.
(avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode><mask_name><round_name>):
Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add test for new builtins.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add test for new intrinsics.
* gcc.target/i386/sse-22.c: Ditto.

AVX512FP16: Add testcase for vmovsh/vmovw.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-vmovsh-1a.c: New test.
* gcc.target/i386/avx512fp16-vmovsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-2a.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-2b.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-3a.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-3b.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-4a.c: Ditto.
* gcc.target/i386/avx512fp16-vmovw-4b.c: Ditto.

AVX512FP16: Add vmovw/vmovsh.

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h: (_mm_cvtsi16_si128):
New intrinsic.
(_mm_cvtsi128_si16): Likewise.
(_mm_mask_load_sh): Likewise.
(_mm_maskz_load_sh): Likewise.
(_mm_mask_store_sh): Likewise.
(_mm_move_sh): Likewise.
(_mm_mask_move_sh): Likewise.
(_mm_maskz_move_sh): Likewise.
* config/i386/i386-builtin-types.def: Add corresponding builtin types.
* config/i386/i386-builtin.def: Add corresponding new builtins.
* config/i386/i386-expand.c
(ix86_expand_special_args_builtin): Handle new builtin types.
(ix86_expand_vector_init_one_nonzero): Adjust for FP16 target.
* config/i386/sse.md (VI2F): New mode iterator.
(vec_set<mode>_0): Use new mode iterator.
(avx512f_mov<ssescalarmodelower>_mask): Adjust for HF vector mode.
(avx512f_store<mode>_mask): Ditto.

c++: Small location tweak

As Marek suggested.

gcc/cp/ChangeLog:

* constexpr.c (cxx_eval_outermost_constant_expr): Use
protected_set_expr_location.

rs6000: Remove useless toc-fusion option

toc-fusion was intended for Power9 toc fusion previously,
but Power9 doesn't support fusion at all eventually, this
patch is to remove this useless option.

gcc/ChangeLog:

* config/rs6000/rs6000.opt (-mtoc-fusion): Remove.

Daily bump.

c++: shortcut bad convs during overload resolution, part 2 [PR101904]

The r12-3346 change makes us avoid computing excess argument conversions
during overload resolution, but only when it turns out there's a
strictly viable candidate in the overload set.  If there's no such
candidate then we still need to compute more conversions than strictly
necessary because subsequent conversions after the first bad conversion
can turn a non-strictly viable candidate into an unviable one, and that
affects the outcome of overload resolution and the behavior of its
callers (because of -fpermissive).

But at least in a SFINAE context, the distinction between a non-strictly
viable and an unviable candidate shouldn't matter all that much since
performing a bad conversion is always an error (even with -fpermissive),
and so forming a call to a non-strictly viable candidate will end up
being a SFINAE error anyway, just like in the unviable case.  Hence a
non-strictly viable candidate is effectively unviable (in a SFINAE
context), and we don't really need to distinguish between the two kinds.
We can take advantage of this observation to avoid computing excess
argument conversions even when there's no strictly viable candidate in
the overload set.

This patch implements this idea.  We usually detect a SFINAE context by
looking for the absence of the tf_error flag, but that's not specific
enough: we can also get here from build_user_type_conversion with
tf_error cleared, and there the distinction between a non-strictly
viable candidate and an unviable candidate still matters (it determines
whether a user-defined conversion is bad or just doesn't exist).  So this
patch sets and checks for the tf_conv flag to detect this situation too,
which avoids regressing conv2.C below.

Unlike the previous change, this one does affect the outcome of overload
resolution, but it should do so only in a way that preserves backwards
compatibility with -fpermissive.

PR c++/101904

gcc/cp/ChangeLog:

* call.c (build_user_type_conversion_1): Add tf_conv to complain.
(add_candidates): When in a SFINAE context, instead of adding a
candidate to bad_fns just mark it unviable.

gcc/testsuite/ChangeLog:

* g++.dg/ext/conv2.C: New test.
* g++.dg/template/conv17.C: Extend test.

rs6000: fix xcoff section encoding

The encoding needs to be applied if the decl is not an alias: both a NULL
summary *OR* the decl alias flag is false.  This patch updates the
earlier fix to continue with the encoding selection if the summary is
NULL.

gcc/ChangeLog:
* config/rs6000/rs6000.c (rs6000_xcoff_encode_section_info):
Proceed if no symbol summary or the symbol alias flag is false.

c++: add parsing_function_declarator predicate

While looking at PR96184 I noticed that we were recognizing the situation of
parsing a function declarator based on current_binding_level, and that we
ought to make that a predicate function.  This patch is just refactoring,
but I just suggested using it in a review of another patch.

gcc/cp/ChangeLog:

* cp-tree.h (parsing_function_declarator): Declare.
* name-lookup.c (set_decl_context_in_fn): Use it.
* parser.c (cp_parser_direct_declarator): Use it.
(parsing_function_declarator): New.

c++: Fix handling of decls with flexible array members initialized with side-effects [PR88578]

> > Note, if the flexible array member is initialized only with non-constant
> > initializers, we have a worse bug that this patch doesn't solve, the
> > splitting of initializers into constant and dynamic initialization removes
> > the initializer and we don't have just wrong DECL_*SIZE, but nothing is
> > emitted when emitting those vars into assembly either and so the dynamic
> > initialization clobbers other vars that may overlap the variable.
> > I think we need keep an empty CONSTRUCTOR elt in DECL_INITIAL for the
> > flexible array member in that case.
>
> Makes sense.

So, the following patch fixes that.

The typeck2.c change makes sure we keep those CONSTRUCTORs around (although
they should be empty because all their elts had side-effects/was
non-constant if it was removed earlier), and the varasm.c change is to avoid
ICEs on those as well as ICEs on other flex array members that had some
initializers without side-effects, but not on the last array element.

The code was already asserting that the (index of the last elt in the
CONSTRUCTOR + 1) times elt size is equal to TYPE_SIZE_UNIT of the local->val
type, which is true for C flex arrays or for C++ if they don't have any
side-effects or the last elt doesn't have side-effects, this patch changes
that to assertion that the TYPE_SIZE_UNIT is greater than equal to the
offset of the end of last element in the CONSTRUCTOR and uses TYPE_SIZE_UNIT
(int_size_in_bytes) in the code later on.

2021-09-15  Jakub Jelinek  <jakub@redhat.com>

PR c++/88578
PR c++/102295
gcc/
* varasm.c (output_constructor_regular_field): Instead of assertion
that array_size_for_constructor result is equal to size of
TREE_TYPE (local->val) in bytes, assert that the type size is greater
or equal to array_size_for_constructor result and use type size as
fieldsize.
gcc/cp/
* typeck2.c (split_nonconstant_init_1): Don't throw away empty
initializers of flexible array members if they have non-zero type
size.
gcc/testsuite/
* g++.dg/ext/flexary39.C: New test.
* g++.dg/ext/flexary40.C: New test.

c++: default ctor that's also a list ctor [PR102050]

In grok_special_member_properties we need to set TYPE_HAS_COPY_CTOR,
TYPE_HAS_DEFAULT_CONSTRUCTOR and TYPE_HAS_LIST_CTOR independently
from each other because a constructor can be both a default and list
constructor (as in the first testcase), or both a default and copy
constructor (as in the second testcase).

PR c++/102050

gcc/cp/ChangeLog:

* decl.c (grok_special_member_properties): Set
TYPE_HAS_COPY_CTOR, TYPE_HAS_DEFAULT_CONSTRUCTOR
and TYPE_HAS_LIST_CTOR independently from each other.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/initlist125.C: New test.
* g++.dg/cpp0x/initlist126.C: New test.

zero-call-used-regs attr for ada

Make the zero_call_used_regs attribute usable as a Machine_Attribute
pragma.

for  gcc/ada/ChangeLog

* gcc-interface/utils.c: Include opts.h.
(handle_zero_call_used_regs_attribute): New.
(gnat_internal_attribute_table): Add zero_call_used_regs.

for  gcc/testsuite/ChangeLog

* gnat.dg/zcur_attr.adb, gnat.dg/zcur_attr.ads: New.

i386: port vxworks to TARGET_CPU_P macro

PR target/102351

gcc/ChangeLog:

* config/i386/vxworks.h: Use new macro TARGET_CPU_P.

c++: don't warn about internal interference sizes

Most any compilation on ARM/AArch64 was warning because the default L1 cache
line size of 32B was smaller than the default
std::hardware_constructive_interference_size of 64B.  This is mostly due to
inaccurate --param l1-cache-line-size, but it's not helpful to complain to a
user that didn't set the values.

gcc/cp/ChangeLog:

* decl.c (cxx_init_decl_processing): Only warn about odd
interference sizes if they were specified with --param.

rs6000: fix symtab_node::get == NULL issue

PR target/102349

gcc/ChangeLog:

* config/rs6000/rs6000.c (rs6000_xcoff_encode_section_info):
Check that we have a symbol summary for a symbol.

gcc-changelog: Add FIXME note.

contrib/ChangeLog:

* gcc-changelog/git_commit.py: Add FIXME note.

gcc-changelog: check git commit email address

contrib/ChangeLog:

* gcc-changelog/git_commit.py: Check commit email.
* gcc-changelog/test_email.py: Add new test.
* gcc-changelog/test_patches.txt: Likewise.

target/102348 - fix powerpc-lynxos build

This fixes a similar issue for powerpc-lynxos as fixed for i686-lynxos
already.

2021-09-15  Richard Biener  <rguenther@suse.de>

PR target/102348
* config/rs6000/lynx.h: Remove undef of PREFERRED_DEBUGGING_TYPE
to inherit from elfos.h

Optimize for V{8,16,32}HFmode vec_set/extract/init.

gcc/ChangeLog:

PR target/102327
* config/i386/i386-expand.c
(ix86_expand_vector_init_interleave): Use puncklwd to pack 2
HFmodes.
(ix86_expand_vector_set): Use blendw instead of pinsrw.
* config/i386/i386.c (ix86_can_change_mode_class): Adjust for
AVX512FP16 which supports 16bit vector load.
* config/i386/sse.md (avx512bw_interleave_highv32hi<mask_name>):
Rename to ..
(avx512bw_interleave_high<mode><mask_name>): .. this, and
extend to V32HFmode.
(avx2_interleave_highv16hi<mask_name>): Rename to ..
(avx2_interleave_high<mode><mask_name>): .. this, and extend
to V16HFmode.
(vec_interleave_highv8hi<mask_name>): Rename to ..
(vec_interleave_high<mode><mask_name>): .. this, and extend to V8HFmode.
(<mask_codefor>avx512bw_interleave_lowv32hi<mask_name>):
Rename to ..
(<mask_codefor>avx512bw_interleave_low<mode><mask_name>):
this, and extend to V32HFmode.
(avx2_interleave_lowv16hi<mask_name>): Rename to ..
(avx2_interleave_low<mode><mask_name>): .. this, and extend to V16HFmode.
(vec_interleave_lowv8hi<mask_name>): Rename to ..
(vec_interleave_low<mode><mask_name>): .. this, and extend to V8HFmode.
(sse4_1_pblendw): Rename to ..
(sse4_1_pblend<blendsuf>): .. this, and extend to V8HFmode.
(avx2_pblendph): New define_expand.
(<sse2p4_1>_pinsr<ssemodesuffix>): Refactor, use
sseintmodesuffix instead of ssemodesuffix.
(blendsuf): New mode attr.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr102327-1.c: New test.
* gcc.target/i386/pr102327-2.c: New test.
* gcc.target/i386/avx512fp16-1c.c: Adjust testcase.

Maintain (mis-)alignment info in the first element of a group

This changes us to maintain and compute (mis-)alignment info for
the first element of a group only rather than for each DR when
doing interleaving and for the earliest, first, or first in the SLP
node (or any pair or all three of those) when SLP vectorizing.

For this to work out the easiest way I have changed the accessors
DR_MISALIGNMENT and DR_TARGET_ALIGNMENT to do the indirection to
the first element rather than adjusting all callers.

2021-09-13  Richard Biener  <rguenther@suse.de>

* tree-vectorizer.h (dr_misalignment): Move out of line.
(dr_target_alignment): New.
(DR_TARGET_ALIGNMENT): Wrap dr_target_alignment.
(set_dr_target_alignment): New.
(SET_DR_TARGET_ALIGNMENT): Wrap set_dr_target_alignment.
* tree-vect-data-refs.c (dr_misalignment): Compute and
return the group members misalignment.
(vect_compute_data_ref_alignment): Use SET_DR_TARGET_ALIGNMENT.
(vect_analyze_data_refs_alignment): Compute alignment only
for the first element of a DR group.
(vect_slp_analyze_node_alignment): Likewise.

AVX512FP16: Adjust builtin name for FP16 builtins to match AVX512F style

For AVX512FP16 builtins, they all contain format like vaddph_v8hf,
while AVX512F builtins use addps128 which succeeded SSE/AVX style.
Adjust AVX512FP16 builtins to match such format.

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h: Adjust all builtin calls.
* config/i386/avx512fp16vlintrin.h: Likewise.
* config/i386/i386-builtin.def: Adjust builtin name and
enumeration to match AVX512F style.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Adjust builtin macros.
* gcc.target/i386/sse-13.c: Likewise.
* gcc.target/i386/sse-23.c: Likewise.

tree-optimization/102318 - reduction epilogue re-use

This refines the fix for PR102226 to do the mode conversion
from V2DI to VNx2DI separately from the sign-conversion, retaining
the signedness of the saved accumulator as before the original fix.

2021-09-15  Richard Biener <rguenther@suse.de>

PR tree-optimization/102318
* tree-vect-loop.c (vect_transform_cycle_phi): Revert
previous change and do the mode conversion separately from
the sign conversion.

* gcc.dg/vect/pr102318.c: New testcase.

libstdc++: Check for TLS support on mingw cross-compilers

Native mingw builds enable TLS, but crosses don't because we don't use
GCC_CHECK_TLS in the cross-compiler config.

libstdc++-v3/ChangeLog:

* crossconfig.m4: Check for TLS support on mingw.
* configure: Regenerate.

Output vextract{i,f}{32x4,64x2} for (vec_select:(reg:Vmode) idx) when byte_offset of idx % 16 == 0.

2020-09-13  Hongtao Liu  <hongtao.liu@intel.com>
    Peter Cordes  <peter@cordes.ca>
gcc/ChangeLog:

PR target/91103
* config/i386/sse.md (extract_suf): Add V8SF/V8SI/V4DF/V4DI.
(*vec_extract<mode><ssescalarmodelower>_valign): Output
vextract{i,f}{32x4,64x2} instruction when byte_offset % 16 ==
0.

gcc/testsuite/ChangeLog:

PR target/91103
* gcc.target/i386/pr91103-1.c: Add extract tests.
* gcc.target/i386/pr91103-2.c: Ditto.

Add OpenACC 'host_data' testing to 'gfortran.dg/goacc/unexpected-end.f90'

Use underscore instead of space in 'host_data'.

Follow-up to recent commit 33fdbbe4ce6055eb858096d01720ccf94aa854ec
"Fortran: Add missing ST_OMP_END_SCOPE handling [PR102313]".

gcc/testsuite/
* gfortran.dg/goacc/unexpected-end.f90: Add OpenACC 'host_data'
testing.

Remove support for vax-openbsd

This removes the support for vax-openbsd which has been discontinued
after the OpenBSD 5.9 release and which has no supported gas or GNU ld
configuration [anymore].  In particular this target does only support
STABS debuginfo generation.

2021-09-13  Richard Biener  <rguenther@suse.de>

* config.gcc: Remove vax-*-openbsd* configuration.

contrib/
* config-list.mk: Remove vax-openbsd.

Remove m68k-openbsd support

This removes m68k-openbsd as a valid configuration, according
to openbsd.org m68k-openbsd [on the mac] was discontinued after
the 5.1 release.  The configuration is also not (or no longer)
supported by gas and GNU ld so I could not figure whether it is still
a.out (I suspect it is).  But first and foremost the target only supports
STABS as a debugging format.

2021-09-13  Richard Biener  <rguenther@suse.de>

* config.gcc: Remove m68k-openbsd.

contrib/
* config-list.mk: Remove m68k-openbsd.

c++: don't predeclare std::type_info [PR48396]

We've always predeclared std::type_info, which has been wrong for a while,
but now with modules it becomes more of a practical problem, if we want to
declare it in the purview of a module.  So don't predeclare it.  For
building up the type_info information to write out with the vtable, we can
use void* instead of type_info*, since they already aren't the real types.

PR c++/48396

gcc/cp/ChangeLog:

* cp-tree.h (enum cp_tree_index): Remove CPTI_TYPE_INFO_PTR_TYPE.
(type_info_ptr_type): Remove.
* rtti.c (init_rtti_processing): Don't predeclare std::type_info.
(typeid_ok_p): Check for null const_type_info_type_node.
(type_info_ptr_type, get_void_tinfo_ptr): New fns.
(get_tinfo_decl_dynamic, get_tinfo_ptr): Use them.
(ptr_initializer, ptm_initializer, get_pseudo_ti_init): Use them.
(get_tinfo_desc): Use const_ptr_type_node.

gcc/testsuite/ChangeLog:

* g++.dg/rtti/undeclared1.C: New test.

c++: correct object scope handling

The way cp_parser_lookup_name handles object scope (i.e. the scope on the
RHS of a . or -> expression) is a bit subtle: before the lookup it's in
parser->context->object type, and after the lookup it's in
parser->object_scope.  But a couple of places that elide lookups were
failing to do the same transform.

I'm not aware of this breaking anything currently.

gcc/cp/ChangeLog:

* parser.c (cp_parser_template_name): Move object type.
(cp_parser_pre_parsed_nested_name_specifier): Likewise.

c++: tweak C++20 destructor template-id rule

While working on a larger change to destructor lookup I noticed that this
rule talks about declarators, but we weren't limiting the error to the case
where we're parsing a declarator.  I don't know if this actually broke
anything, since a CPP_TEMPLATE_ID would have to have been parsed once
before, but it's more correct this way.

gcc/cp/ChangeLog:

* parser.c (cp_parser_unqualified_id): Only complain about ~A<T> in
a declarator.

gcc: xtensa: fix PR target/102336

2021-09-14  Max Filippov  <jcmvbkbc@gmail.com>
gcc/
PR target/102336
* config/xtensa/t-xtensa (TM_H): Add include/xtensa-config.h.

Daily bump.

Fortran - fix ICE during error recovery checking entry characteristics

gcc/fortran/ChangeLog:

PR fortran/102311
* resolve.c (resolve_entries): Attempt to recover cleanly after
rejecting mismatched function entries.

gcc/testsuite/ChangeLog:

PR fortran/102311
* gfortran.dg/entry_25.f90: New test.

c++tools : Add a simple handler for ModuleCompiledRequest.

This just replies with "OK".

c++tools/ChangeLog:

* resolver.cc (module_resolver::ModuleCompiledRequest):
Add a simple handler.
* resolver.h: Declare handler for ModuleCompiledRequest.

rs6000: Disable optimizing multiple xxsetaccz instructions into one xxsetaccz

Fwprop will happily optimize two xxsetaccz instructions into one xxsetaccz
by propagating the results of the first to the uses of the second.
We really don't want that to happen given the late priming/depriming of
accumulators.  I fixed this by making the xxsetaccz source operand an
unspec volatile.  I also removed the mma_xxsetaccz define_expand and
define_insn_and_split and replaced it with a simple define_insn.
The expand and splitter patterns were leftovers from the pre opaque mode
code when the xxsetaccz code was part of the movpxi pattern, and we don't
need them now.

Rather than a new test case, I was able to just modify the current test case
to add another __builtin_mma_xxsetaccz call which shows the bad code gen
with unpatched compilers.

2021-09-14  Peter Bergner  <bergner@linux.ibm.com>

gcc/
* config/rs6000/mma.md (unspec): Delete UNSPEC_MMA_XXSETACCZ.
(unspecv): Add UNSPECV_MMA_XXSETACCZ.
(*mma_xxsetaccz): Delete.
(mma_xxsetaccz): Change to define_insn.  Remove operand 1.
Use UNSPECV_MMA_XXSETACCZ.  Update comment.
* config/rs6000/rs6000.c (rs6000_rtx_costs): Use UNSPECV_MMA_XXSETACCZ.

gcc/testsuite/
* gcc.target/powerpc/mma-builtin-6.c: Add second call to xxsetacc
built-in.  Update instruction counts.

configure: Avoid unnecessary constraints on executables for $build.

The executables for GCC's c-family compilers must be built with no-PIE
because they use PCH and the current model for this requires that the
exe is always lauched at the same address.  Since the other language
compilers share code with the c-family this constraint is also applied
to them.

However, the executables that run on $build (generators, and parsers
for md and def files) need not have any such constraint they do not
consume PCH files.

This change simplifies the configuration and Makefile content by
removing the code enforcing no-PIE on these exes.  This also fixes a
bootstrap issue with some Darwin versions and clang as the bootstrap
compiler,  where -no-PIE causes the correct relocation model to be
switched off leading to invalid user-space code.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
gcc/ChangeLog:

* Makefile.in: Remove variables related to applying no-PIE
to the exes on $build.
* configure: Regenerate.
* configure.ac: Remove configuration related to applying
no-PIE to the exes on $build.

coroutines: Make proxy vars for the function arg copies.

This adds top level proxy variables for the coroutine frame
copies of the original function args.  These are then available
in the debugger to refer to the frame copies.  We rewrite the
function body to use the copies, since the original parms will
no longer be in scope when the coroutine is running.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
gcc/cp/ChangeLog:

* coroutines.cc (struct param_info): Add copy_var.
(build_actor_fn): Use simplified param references.
(register_param_uses): Likewise.
(rewrite_param_uses): Likewise.
(analyze_fn_parms): New function.
(coro_rewrite_function_body): Add proxies for the fn
parameters to the outer bind scope of the rewritten code.
(morph_fn_to_coro): Use simplified version of param ref.

coroutines: Expose implementation state to the debugger.

In the process of transforming a coroutine into the separate representation
as the ramp function and a state machine, we generate some variables that
are of interest to a user during debugging.  Any variable that is persistent
for the execution of the coroutine is placed into the coroutine frame.

In particular:
  The promise object.
  The function pointers for the resumer and destroyer.
  The current resume index (suspend point).
  The handle that represents this coroutine 'self handle'.
  Any handle provided for a continuation coroutine.
  Whether the coroutine frame is allocated and needs to be freed.

Visibility of some of these has already been requested by end users.

This patch ensures that such variables have names that are usable in a
debugger, but are in the reserved namespace for the implementation (they
all begin with _Coro_).  The identifiers are generated lazily when the
first coroutine is encountered.

We place the variables into the outermost bind expression and then add a
DECL_VALUE_EXPR to each that points to the frame entry.

These changes simplify the handling of the variables in the body of the
function (in particular, the use of the DECL_VALUE_EXPR means that we now
no longer need to rewrite proxies for the promise and coroutine handles into
the frame->offset form).

Partial improvement to debugging (PR c++/99215).

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
gcc/cp/ChangeLog:

* coroutines.cc (coro_resume_fn_id, coro_destroy_fn_id,
coro_promise_id, coro_frame_needs_free_id, coro_resume_index_id,
coro_self_handle_id, coro_actor_continue_id,
coro_frame_i_a_r_c_id): New.
(coro_init_identifiers): Initialize new name identifiers.
(coro_promise_type_found_p): Use pre-built identifiers.
(struct await_xform_data): Remove unused fields.
(transform_await_expr): Delete code that is now unused.
(build_actor_fn): Simplify interface, use pre-built identifiers and
remove transforms that are no longer needed.
(build_destroy_fn): Use revised field names.
(register_local_var_uses): Use pre-built identifiers.
(coro_rewrite_function_body): Simplify interface, use pre-built
identifiers.  Generate proxy vars in the outer bind expr scope for the
implementation state that we wish to expose.
(morph_fn_to_coro): Adjust comments for new variable names, use pre-
built identifiers.  Remove unused code to generate frame entries for
the implementation state.  Adjust call for build_actor_fn.

c++: empty union member activation during constexpr [PR102163]

Here, the union's constructor is defined to activate its empty data
member _M_rest, but during constexpr evaluation of this constructor the
subobject constructor call O::O(&_M_rest, 42) doesn't produce a side
effect that actually activates the member, so the union still appears
uninitialized after its constructor has run.  This patch fixes this by
using a dummy MODIFY_EXPR in this situation, whose evaluation ensures
the member gets activated.

PR c++/102163

gcc/cp/ChangeLog:

* constexpr.c (cxx_eval_call_expression): After evaluating a
subobject constructor call for an empty union member, produce a
side effect that makes sure the member gets activated.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/constexpr-empty17.C: New test.

c++: Update DECL_*SIZE for objects with flexible array members with initializers [PR102295]

The C FE updates DECL_*SIZE for vars which have initializers for flexible
array members for many years, but C++ FE kept DECL_*SIZE the same as the
type size (i.e. as if there were zero elements in the flexible array
member).  This results e.g. in ELF symbol sizes being too small.

Note, if the flexible array member is initialized only with non-constant
initializers, we have a worse bug that this patch doesn't solve, the
splitting of initializers into constant and dynamic initialization removes
the initializer and we don't have just wrong DECL_*SIZE, but nothing is
emitted when emitting those vars into assembly either and so the dynamic
initialization clobbers other vars that may overlap the variable.
I think we need keep an empty CONSTRUCTOR elt in DECL_INITIAL for the
flexible array member in that case.

2021-09-14  Jakub Jelinek  <jakub@redhat.com>

PR c++/102295
* decl.c (layout_var_decl): For aggregates ending with a flexible
array member, add the size of the initializer for that member to
DECL_SIZE and DECL_SIZE_UNIT.

* g++.target/i386/pr102295.C: New test.

c++: Fix __is_*constructible/assignable for templates [PR102305]

is_xible_helper returns error_mark_node (i.e. false from the traits)
for abstract classes by testing ABSTRACT_CLASS_TYPE_P (to) early.
Unfortunately, as the testcase shows, that doesn't work on class templates
that haven't been instantiated yet, ABSTRACT_CLASS_TYPE_P for them is false
until it is instantiated, which is done when the routine later constructs
a dummy object with that type.

The following patch fixes this by calling complete_type first, so that
ABSTRACT_CLASS_TYPE_P test will work properly, while keeping the handling
of arrays with unknown bounds, or incomplete types where it is done
currently.

2021-09-14  Jakub Jelinek  <jakub@redhat.com>

PR c++/102305
* method.c (is_xible_helper): Call complete_type on to.

* g++.dg/cpp0x/pr102305.C: New test.

Fortran: Add missing ST_OMP_END_SCOPE handling [PR102313]

PR fortran/102313

gcc/fortran/ChangeLog:

* parse.c (gfc_ascii_statement): Add missing ST_OMP_END_SCOPE.

gcc/testsuite/ChangeLog:

* gfortran.dg/goacc/unexpected-end.f90: New test.
* gfortran.dg/gomp/unexpected-end.f90: New test.

testsuite: fix failing pytest tests

gcc/testsuite/ChangeLog:

* g++.dg/gcov/gcov.py: Fix failing pytests as gcov.json.gz
  filename was changed in b777f228b481ae881a7fbb09de367a053740932c.

Fix PR ada/101970

This is a regression present on the mainline and 11 branch in the form of an
ICE for an enumeration type with a full signed representation for its size.

gcc/ada/
PR ada/101970
* exp_attr.adb (Expand_N_Attribute_Reference) <Attribute_Enum_Rep>:
Use an unchecked conversion instead of a regular conversion in the
enumeration case and remove Conversion_OK flag in the integer case.
<Attribute_Pos>: Remove superfluous test.

gcc/testsuite/
* gnat.dg/enum_rep2.adb: New test.

arc: Update ZOL pattern.

The ZOL pattern is missing modes which may lead to errors during
var_tracking. Add them.

gcc/
* config/arc/arc.md (doloop_end): Add missing mode.
(loop_end): Likewise.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>

Do not issue size error for too large array type

The error is to be issued when objects of the type are declared instead.

gcc/ada/
* gcc-interface/decl.c (validate_size): Do not issue an error if the
old size has overflowed.

Fix inaccurate bounds in debug info for vector array types

They should not be 0-based, unless the array type itself is.

gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_entity): For vector types, make
the representative array the debug type.

Fix internal error on broken import of vector intrinsics

The change also makes small adjustments to warning messages for intrinsics.

gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_subprog_type): Turn variable
into constant.  Capitalize GCC in warning message.
(intrin_arglists_compatible_p): Change parameter to pointer-to-const
Adjust warning messages.  Turn warning into error for vector types.
(intrin_return_compatible_p): Likewise.
(intrin_profiles_compatible_p): Change parameter to pointer-to-const

Strengthen compatibility warning for GCC builtins

This is necessary for vector builtins, which are picky about the
signedness of the element type.

gcc/ada/
* libgnat/s-atopri.ads (bool): Delete.
(Atomic_Test_And_Set): Replace bool with Boolean.
(Atomic_Always_Lock_Free): Likewise.
* libgnat/s-aoinar.adb (Is_Lock_Free): Adjust.
* libgnat/s-aomoar.adb (Is_Lock_Free): Likewise.
* libgnat/s-aotase.adb (Atomic_Test_And_Set): Likewise.
* libgnat/s-atopex.adb (Atomic_Compare_And_Exchange): Likewise.
* gcc-interface/decl.c: Include gimple-expr.h.
(intrin_types_incompatible_p): Delete.
(intrin_arglists_compatible_p): Call types_compatible_p.
(intrin_return_compatible_p): Likewise.

Fix internal error on pointer-to-pointer binding in LTO mode

gcc/ada/
* gcc-interface/utils.c (update_pointer_to): Set TYPE_CANONICAL on
pointer and reference types.

testsuite: Use sync_long_long instead of sync_int_long for atomic-29.c test

As discussed, the test tests atomics on doubles which are 64-bit and so we
should use sync_long_long effective target instead of sync_int_long that
covers 64-bit atomics only on 64-bit arches.  I've added -march=pentium
to follow what is documented for sync_long_long, I guess -march=zarch should
be added for s390* too, but haven't tested that.

And using sync_long_long found a syntax error in that effective target
implementation, so I've fixed that too.

2021-09-14  Jakub Jelinek  <jakub@redhat.com>

* c-c++-common/gomp/atomic-29.c: Add -march=pentium
dg-additional-options for ia32.  Use sync_long_long effective target
instead of sync_int_long.
* lib/target-supports.exp (check_effective_target_sync_long_long): Fix
a syntax error.

openmp: Add testing checks (whether lhs appears in operands at all) to more trees

This patch adds testing checks (goa_stabilize_expr with NULL pre_p) for more
tree codes, so that we don't gimplify their operands individually unless lhs
appears in them.  Also, so that we don't have exponential compile time complexity
with the added checks, I've added a depth computation, we don't expect lhs
to be found in depth 8 or above as all the atomic forms must have x expression
in specific places in the expressions.

2021-09-14  Jakub Jelinek  <jakub@redhat.com>

* gimplify.c (goa_stabilize_expr): Add depth argument, propagate
it to recursive calls, for depth above 7 just gimplify or return.
Perform a test even for MODIFY_EXPR, ADDR_EXPR, COMPOUND_EXPR with
__builtin_clear_padding and TARGET_EXPR.
(gimplify_omp_atomic): Adjust goa_stabilize_expr callers.

Implement PR ada/101385

For consistency's sake with -Wall & -w, this makes -Werror imply -gnatwe.

gcc/ada/
PR ada/101385
* doc/gnat_ugn/building_executable_programs_with_gnat.rst
(-Wall): Minor fixes.
(-w): Likewise.
(-Werror): Document that it also sets -gnatwe by default.
* gcc-interface/lang-specs.h (ada): Expand -gnatwe if -Werror is
passed and move expansion of -gnatw switches to before -gnatez.

Remove superfluous call to UI_Is_In_Int_Range

gcc/ada/
* gcc-interface/utils.c (can_materialize_object_renaming_p): Do not
call UI_Is_In_Int_Range on the result of Normalized_First_Bit.

Give more informative error message for by-reference types

Recent compilers enforce more strictly the RM C.6(18) clause, which says
that volatile record types are by-reference types.  This changes the typical
error message now given in these cases.

gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_entity) <is_type>: Declare new
constant.  Adjust error message issued by validate_size in the case
of by-reference types.
(validate_size): Always use the error strings passed by the caller.

AVX512FP16: Add testcase for fpclass/getmant/getexp instructions.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-helper.h (V512):
Add xmm component.
* gcc.target/i386/avx512fp16-vfpclassph-1a.c: New test.
* gcc.target/i386/avx512fp16-vfpclassph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vfpclasssh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vfpclasssh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vgetexpph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vgetexpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vgetexpsh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vgetexpsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vgetmantph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vgetmantph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vgetmantsh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vgetmantsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfpclassph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfpclassph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vgetexpph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vgetexpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vgetmantph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vgetmantph-1b.c: Ditto.

AVX512FP16: Add fpclass/getexp/getmant instructions.

Add vfpclassph/vfpclasssh/vgetexpph/vgetexpsh/vgetmantph/vgetmantsh.

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h (_mm_fpclass_sh_mask):
New intrinsic.
(_mm_mask_fpclass_sh_mask): Likewise.
(_mm512_mask_fpclass_ph_mask): Likewise.
(_mm512_fpclass_ph_mask): Likewise.
(_mm_getexp_sh): Likewise.
(_mm_mask_getexp_sh): Likewise.
(_mm_maskz_getexp_sh): Likewise.
(_mm512_getexp_ph): Likewise.
(_mm512_mask_getexp_ph): Likewise.
(_mm512_maskz_getexp_ph): Likewise.
(_mm_getexp_round_sh): Likewise.
(_mm_mask_getexp_round_sh): Likewise.
(_mm_maskz_getexp_round_sh): Likewise.
(_mm512_getexp_round_ph): Likewise.
(_mm512_mask_getexp_round_ph): Likewise.
(_mm512_maskz_getexp_round_ph): Likewise.
(_mm_getmant_sh): Likewise.
(_mm_mask_getmant_sh): Likewise.
(_mm_maskz_getmant_sh): Likewise.
(_mm512_getmant_ph): Likewise.
(_mm512_mask_getmant_ph): Likewise.
(_mm512_maskz_getmant_ph): Likewise.
(_mm_getmant_round_sh): Likewise.
(_mm_mask_getmant_round_sh): Likewise.
(_mm_maskz_getmant_round_sh): Likewise.
(_mm512_getmant_round_ph): Likewise.
(_mm512_mask_getmant_round_ph): Likewise.
(_mm512_maskz_getmant_round_ph): Likewise.
* config/i386/avx512fp16vlintrin.h (_mm_mask_fpclass_ph_mask):
New intrinsic.
(_mm_fpclass_ph_mask): Likewise.
(_mm256_mask_fpclass_ph_mask): Likewise.
(_mm256_fpclass_ph_mask): Likewise.
(_mm256_getexp_ph): Likewise.
(_mm256_mask_getexp_ph): Likewise.
(_mm256_maskz_getexp_ph): Likewise.
(_mm_getexp_ph): Likewise.
(_mm_mask_getexp_ph): Likewise.
(_mm_maskz_getexp_ph): Likewise.
(_mm256_getmant_ph): Likewise.
(_mm256_mask_getmant_ph): Likewise.
(_mm256_maskz_getmant_ph): Likewise.
(_mm_getmant_ph): Likewise.
(_mm_mask_getmant_ph): Likewise.
(_mm_maskz_getmant_ph): Likewise.
* config/i386/i386-builtin-types.def: Add corresponding builtin types.
* config/i386/i386-builtin.def: Add corresponding new builtins.
* config/i386/i386-expand.c
(ix86_expand_args_builtin): Handle new builtin types.
(ix86_expand_round_builtin): Ditto.
* config/i386/sse.md (vecmemsuffix): Add HF vector modes.
(<avx512>_getexp<mode><mask_name><round_saeonly_name>): Adjust
to support HF vector modes.
(avx512f_sgetexp<mode><mask_scalar_name><round_saeonly_scalar_name):
Ditto.
(avx512dq_fpclass<mode><mask_scalar_merge_name>): Ditto.
(avx512dq_vmfpclass<mode><mask_scalar_merge_name>): Ditto.
(<avx512>_getmant<mode><mask_name><round_saeonly_name>): Ditto.
(avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>):
Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add test for new builtins.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add test for new intrinsics.
* gcc.target/i386/sse-22.c: Ditto.

AVX512FP16: Add testcase for vreduceph/vreducesh/vrndscaleph/vrndscalesh.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-helper.h (_ROUND_CUR): New macro.
* gcc.target/i386/avx512fp16-vreduceph-1a.c: New test.
* gcc.target/i386/avx512fp16-vreduceph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vreducesh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vreducesh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscaleph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscaleph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscalesh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscalesh-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vreduceph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vreduceph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c: Ditto.

AVX512FP16: Add vreduceph/vreducesh/vrndscaleph/vrndscalesh.

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h (_mm512_reduce_ph):
New intrinsic.
(_mm512_mask_reduce_ph): Likewise.
(_mm512_maskz_reduce_ph): Likewise.
(_mm512_reduce_round_ph): Likewise.
(_mm512_mask_reduce_round_ph): Likewise.
(_mm512_maskz_reduce_round_ph): Likewise.
(_mm_reduce_sh): Likewise.
(_mm_mask_reduce_sh): Likewise.
(_mm_maskz_reduce_sh): Likewise.
(_mm_reduce_round_sh): Likewise.
(_mm_mask_reduce_round_sh): Likewise.
(_mm_maskz_reduce_round_sh): Likewise.
(_mm512_roundscale_ph): Likewise.
(_mm512_mask_roundscale_ph): Likewise.
(_mm512_maskz_roundscale_ph): Likewise.
(_mm512_roundscale_round_ph): Likewise.
(_mm512_mask_roundscale_round_ph): Likewise.
(_mm512_maskz_roundscale_round_ph): Likewise.
(_mm_roundscale_sh): Likewise.
(_mm_mask_roundscale_sh): Likewise.
(_mm_maskz_roundscale_sh): Likewise.
(_mm_roundscale_round_sh): Likewise.
(_mm_mask_roundscale_round_sh): Likewise.
(_mm_maskz_roundscale_round_sh): Likewise.
* config/i386/avx512fp16vlintrin.h: (_mm_reduce_ph):
New intrinsic.
(_mm_mask_reduce_ph): Likewise.
(_mm_maskz_reduce_ph): Likewise.
(_mm256_reduce_ph): Likewise.
(_mm256_mask_reduce_ph): Likewise.
(_mm256_maskz_reduce_ph): Likewise.
(_mm_roundscale_ph): Likewise.
(_mm_mask_roundscale_ph): Likewise.
(_mm_maskz_roundscale_ph): Likewise.
(_mm256_roundscale_ph): Likewise.
(_mm256_mask_roundscale_ph): Likewise.
(_mm256_maskz_roundscale_ph): Likewise.
* config/i386/i386-builtin-types.def: Add corresponding builtin types.
* config/i386/i386-builtin.def: Add corresponding new builtins.
* config/i386/i386-expand.c
(ix86_expand_args_builtin): Handle new builtin types.
(ix86_expand_round_builtin): Ditto.
* config/i386/sse.md (<mask_codefor>reducep<mode><mask_name>):
Renamed to ...
(<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
... this, and adjust for round operands.
(reduces<mode><mask_scalar_name>): Likewise, with ...
(reduces<mode><mask_scalar_name><round_saeonly_scalar_name):
... this.
(<avx512>_rndscale<mode><mask_name><round_saeonly_name>):
Adjust for HF vector modes.
(avx512f_rndscale<mode><mask_scalar_name><round_saeonly_scalar_name>):
Ditto.
(*avx512f_rndscale<mode><round_saeonly_name>): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add test for new builtins.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add test for new intrinsics.
* gcc.target/i386/sse-22.c: Ditto.

AVX512FP16: Add testcase for vrcpph/vrcpsh/vscalefph/vscalefsh.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-vrcpph-1a.c: New test.
* gcc.target/i386/avx512fp16-vrcpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vrcpsh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vrcpsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vscalefph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vscalefph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vscalefsh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vscalefsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrcpph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrcpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vscalefph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vscalefph-1b.c: Ditto.

AVX512FP16: Add vrcpph/vrcpsh/vscalefph/vscalefsh.

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h: (_mm512_rcp_ph):
New intrinsic.
(_mm512_mask_rcp_ph): Likewise.
(_mm512_maskz_rcp_ph): Likewise.
(_mm_rcp_sh): Likewise.
(_mm_mask_rcp_sh): Likewise.
(_mm_maskz_rcp_sh): Likewise.
(_mm512_scalef_ph): Likewise.
(_mm512_mask_scalef_ph): Likewise.
(_mm512_maskz_scalef_ph): Likewise.
(_mm512_scalef_round_ph): Likewise.
(_mm512_mask_scalef_round_ph): Likewise.
(_mm512_maskz_scalef_round_ph): Likewise.
(_mm_scalef_sh): Likewise.
(_mm_mask_scalef_sh): Likewise.
(_mm_maskz_scalef_sh): Likewise.
(_mm_scalef_round_sh): Likewise.
(_mm_mask_scalef_round_sh): Likewise.
(_mm_maskz_scalef_round_sh): Likewise.
* config/i386/avx512fp16vlintrin.h (_mm_rcp_ph):
New intrinsic.
(_mm256_rcp_ph): Likewise.
(_mm_mask_rcp_ph): Likewise.
(_mm256_mask_rcp_ph): Likewise.
(_mm_maskz_rcp_ph): Likewise.
(_mm256_maskz_rcp_ph): Likewise.
(_mm_scalef_ph): Likewise.
(_mm256_scalef_ph): Likewise.
(_mm_mask_scalef_ph): Likewise.
(_mm256_mask_scalef_ph): Likewise.
(_mm_maskz_scalef_ph): Likewise.
(_mm256_maskz_scalef_ph): Likewise.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/sse.md (VFH_AVX512VL): New.
(avx512fp16_rcp<mode>2<mask_name>): Ditto.
(avx512fp16_vmrcpv8hf2<mask_scalar_name>): Ditto.
(avx512f_vmscalef<mode><mask_scalar_name><round_scalar_name>):
Adjust to support HF vector modes.
(<avx512>_scalef<mode><mask_name><round_name>): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add test for new builtins.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add test for new intrinsics.
* gcc.target/i386/sse-22.c: Ditto.

AVX512FP16: Add testcase for vsqrtph/vsqrtsh/vrsqrtph/vrsqrtsh.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-vrsqrtph-1a.c: New test.
* gcc.target/i386/avx512fp16-vrsqrtph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vrsqrtsh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vrsqrtsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vsqrtph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vsqrtph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vsqrtsh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vsqrtsh-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrsqrtph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vsqrtph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vsqrtph-1b.c: Ditto.

AVX512FP16: Add vsqrtph/vrsqrtph/vsqrtsh/vrsqrtsh.

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h: (_mm512_sqrt_ph):
New intrinsic.
(_mm512_mask_sqrt_ph): Likewise.
(_mm512_maskz_sqrt_ph): Likewise.
(_mm512_sqrt_round_ph): Likewise.
(_mm512_mask_sqrt_round_ph): Likewise.
(_mm512_maskz_sqrt_round_ph): Likewise.
(_mm512_rsqrt_ph): Likewise.
(_mm512_mask_rsqrt_ph): Likewise.
(_mm512_maskz_rsqrt_ph): Likewise.
(_mm_rsqrt_sh): Likewise.
(_mm_mask_rsqrt_sh): Likewise.
(_mm_maskz_rsqrt_sh): Likewise.
(_mm_sqrt_sh): Likewise.
(_mm_mask_sqrt_sh): Likewise.
(_mm_maskz_sqrt_sh): Likewise.
(_mm_sqrt_round_sh): Likewise.
(_mm_mask_sqrt_round_sh): Likewise.
(_mm_maskz_sqrt_round_sh): Likewise.
* config/i386/avx512fp16vlintrin.h (_mm_sqrt_ph): New intrinsic.
(_mm256_sqrt_ph): Likewise.
(_mm_mask_sqrt_ph): Likewise.
(_mm256_mask_sqrt_ph): Likewise.
(_mm_maskz_sqrt_ph): Likewise.
(_mm256_maskz_sqrt_ph): Likewise.
(_mm_rsqrt_ph): Likewise.
(_mm256_rsqrt_ph): Likewise.
(_mm_mask_rsqrt_ph): Likewise.
(_mm256_mask_rsqrt_ph): Likewise.
(_mm_maskz_rsqrt_ph): Likewise.
(_mm256_maskz_rsqrt_ph): Likewise.
* config/i386/i386-builtin-types.def: Add corresponding builtin types.
* config/i386/i386-builtin.def: Add corresponding new builtins.
* config/i386/i386-expand.c
(ix86_expand_args_builtin): Handle new builtins.
(ix86_expand_round_builtin): Ditto.
* config/i386/sse.md (VF_AVX512FP16VL): New.
(sqrt<mode>2): Adjust for HF vector modes.
(<sse>_sqrt<mode>2<mask_name><round_name>): Likewise.
(<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>):
Likewise.
(<sse>_rsqrt<mode>2<mask_name>): New.
(avx512fp16_vmrsqrtv8hf2<mask_scalar_name>): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add test for new builtins.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add test for new intrinsics.
* gcc.target/i386/sse-22.c: Ditto.

c++: Fix warning on 32-bit x86

My C++17 hardware interference sizes patch caused a bogus warning on 32-bit
x86, where we have a default L1 cache line size of 0, and the front end
complained that the default constructive interference size of 64 was larger
than that.

gcc/cp/ChangeLog:

* decl.c (cxx_init_decl_processing): Don't warn if L1 cache line
size is smaller than maxalign.

Daily bump.

Fortran - ensure simplification of bounds of array-valued named constants

gcc/fortran/ChangeLog:

PR fortran/82314
* decl.c (add_init_expr_to_sym): For proper initialization of
array-valued named constants the array bounds need to be
simplified before adding the initializer.

gcc/testsuite/ChangeLog:

PR fortran/82314
* gfortran.dg/pr82314.f90: New test.

Fortran - fix handling of substring start and end indices

gcc/fortran/ChangeLog:

PR fortran/85130
* expr.c (find_substring_ref): Handle given substring start and
end indices as signed integers, not unsigned.

gcc/testsuite/ChangeLog:

PR fortran/85130
* gfortran.dg/substr_6.f90: Revert commit r8-7574, adding again
test that was erroneously considered as illegal.

Don't maintain a warning spec for 'UNKNOWN_LOCATION'/'BUILTINS_LOCATION' [PR101574]

This resolves PR101574 "gcc/sparseset.h:215:20: error: suggest parentheses
around assignment used as truth value [-Werror=parentheses]", as (bogusly)
reported at commit a61f6afbee370785cf091fe46e2e022748528307:

    In file included from [...]/source-gcc/gcc/lra-lives.c:43:
    [...]/source-gcc/gcc/lra-lives.c: In function ‘void make_hard_regno_dead(int)’:
    [...]/source-gcc/gcc/sparseset.h:215:20: error: suggest parentheses around assignment used as truth value [-Werror=parentheses]
      215 |        && (((ITER) = sparseset_iter_elm (SPARSESET)) || 1);             \
          |            ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    [...]/source-gcc/gcc/lra-lives.c:304:3: note: in expansion of macro ‘EXECUTE_IF_SET_IN_SPARSESET’
      304 |   EXECUTE_IF_SET_IN_SPARSESET (pseudos_live, i)
          |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~

gcc/
PR bootstrap/101574
* diagnostic-spec.c (warning_suppressed_at, copy_warning): Handle
'RESERVED_LOCATION_P' locations.
* warning-control.cc (get_nowarn_spec, suppress_warning)
(copy_warning): Likewise.

Clarify 'key_type_t' to 'location_t' as used for 'gcc/diagnostic-spec.h:nowarn_map'

To make it obvious what exactly the key type is.  No change in behavior.

gcc/
* diagnostic-spec.h (typedef xint_hash_t): Use 'location_t' instead of...
(typedef key_type_t): ... this.  Remove.
(nowarn_map): Document.
* diagnostic-spec.c (nowarn_map): Likewise.
* warning-control.cc (convert_to_key): Evolve functions into...
(get_location): ... these.  Adjust all users.

Simplify 'gcc/diagnostic-spec.h:nowarn_map' setup

If we've just read something from the map, we can be sure that it exists.

gcc/
* warning-control.cc (copy_warning): Remove 'nowarn_map' setup.

c++: implement C++17 hardware interference size

The last missing piece of the C++17 standard library is the hardware
intereference size constants.  Much of the delay in implementing these has
been due to uncertainty about what the right values are, and even whether
there is a single constant value that is suitable; the destructive
interference size is intended to be used in structure layout, so program
ABIs will depend on it.

In principle, both of these values should be the same as the target's L1
cache line size.  When compiling for a generic target that is intended to
support a range of target CPUs with different cache line sizes, the
constructive size should probably be the minimum size, and the destructive
size the maximum, unless you are constrained by ABI compatibility with
previous code.

From discussion on gcc-patches, I've come to the conclusion that the
solution to the difficulty of choosing stable values is to give up on it,
and instead encourage only uses where ABI stability is unimportant: in
particular, uses where the ABI is shared at most between translation units
built at the same time with the same flags.

To that end, I've added a warning for any use of the constant value of
std::hardware_destructive_interference_size in a header or module export.
Appropriate uses within a project can disable the warning.

A previous iteration of this patch included an -finterference-tune flag to
make the value vary with -mtune; this iteration makes that the default
behavior, which should be appropriate for all reasonable uses of the
variable.  The previous default of "stable-ish" seems to me likely to have
been more of an attractive nuisance; since we can't promise actual
stability, we should instead make proper uses more convenient.

JF Bastien's implementation proposal is summarized at
https://github.com/itanium-cxx-abi/cxx-abi/issues/74

I implement this by adding new --params for the two sizes.  Targets can
override these values in targetm.target_option.override() to support a range
of values for the generic target; otherwise, both will default to the L1
cache line size.

64 bytes still seems correct for all x86.

I'm not sure why he proposed 64/64 for generic 32-bit ARM, since the Cortex
A9 has a 32-byte cache line, so I'd think 32/64 would make more sense.

He proposed 64/128 for generic AArch64, but since the A64FX now has a 256B
cache line, I've changed that to 64/256.

Other arch maintainers are invited to set ranges for their generic targets
if that seems better than using the default cache line size for both values.

With the above choice to reject stability as a goal, getting these values
"right" is now just a matter of what we want the default optimization to be,
and we can feel free to adjust them as CPUs with different cache lines
become more and less common.

gcc/ChangeLog:

* params.opt: Add destructive-interference-size and
constructive-interference-size.
* doc/invoke.texi: Document them.
* config/aarch64/aarch64.c (aarch64_override_options_internal):
Set them.
* config/arm/arm.c (arm_option_override): Set them.
* config/i386/i386-options.c (ix86_option_override_internal):
Set them.

gcc/c-family/ChangeLog:

* c.opt: Add -Winterference-size.
* c-cppbuiltin.c (cpp_atomic_builtins): Add __GCC_DESTRUCTIVE_SIZE
and __GCC_CONSTRUCTIVE_SIZE.

gcc/cp/ChangeLog:

* constexpr.c (maybe_warn_about_constant_value):
Complain about std::hardware_destructive_interference_size.
(cxx_eval_constant_expression): Call it.
* decl.c (cxx_init_decl_processing): Check
--param *-interference-size values.

libstdc++-v3/ChangeLog:

* include/std/version: Define __cpp_lib_hardware_interference_size.
* libsupc++/new: Define hardware interference size variables.

gcc/testsuite/ChangeLog:

* g++.dg/warn/Winterference.H: New file.
* g++.dg/warn/Winterference.C: New test.
* g++.target/aarch64/interference.C: New test.
* g++.target/arm/interference.C: New test.
* g++.target/i386/interference.C: New test.

i386: support micro-levels in target{,_clone} attrs [PR101696]

As mentioned in the PR, we do miss supports target micro-architectures
in target and target_clone attribute. While the levels
x86-64 x86-64-v2 x86-64-v3 x86-64-v4 are supported values by -march
option, they are actually only aliases for k8 CPU. That said, they are more
closer to __builtin_cpu_supports function and we decided to implement
it there.

PR target/101696

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (cpu_indicator_init): Add support
for x86-64 micro levels for __builtin_cpu_supports.
* common/config/i386/i386-cpuinfo.h (enum feature_priority):
Add priorities for the micro-arch levels.
(enum processor_features): Add new features.
* common/config/i386/i386-isas.h: Add micro-arch features.
* config/i386/i386-builtins.c (get_builtin_code_for_version):
Support the micro-arch levels by callsing
__builtin_cpu_supports.
* doc/extend.texi: Document that the levels are support by
  __builtin_cpu_supports.

gcc/testsuite/ChangeLog:

* g++.target/i386/mv30.C: New test.
* gcc.target/i386/mvc16.c: New test.
* gcc.target/i386/builtin_target.c (CHECK___builtin_cpu_supports):
New.

Co-Authored-By: H.J. Lu <hjl.tools@gmail.com>

[aarch64] Fix target/95969: __builtin_aarch64_im_lane_boundsi interferes with gimple

This patch adds simple folding of __builtin_aarch64_im_lane_boundsi where
we are not going to error out. It fixes the problem by the removal
of the function from the IR.

OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

PR target/95969
* config/aarch64/aarch64-builtins.c (aarch64_fold_builtin_lane_check):
New function.
(aarch64_general_fold_builtin): Handle AARCH64_SIMD_BUILTIN_LANE_CHECK.
(aarch64_general_gimple_fold_builtin): Likewise.

gcc/testsuite/ChangeLog:

PR target/95969
* gcc.target/aarch64/lane-bound-1.c: New test.
* gcc.target/aarch64/lane-bound-2.c: New test.

Remove m32r{,le}-*-linux* support from GCC

m32r support never made it to glibc and the support for the Linux kernel
was removed with 4.18. It does not remove much but no reason to keep
around a port which never worked or one which the support in other
projects is gone.

OK? Checked to make sure m32r-linux and m32rle-linux were rejected
when building.

contrib/ChangeLog:

* config-list.mk: Remove m32r-linux and m32rle-linux
from the list.

gcc/ChangeLog:

* config.gcc: Add m32r-*-linux* and m32rle-*-linux*
to the Unsupported targets list.
Remove support for m32r-*-linux* and m32rle-*-linux*.
* config/m32r/linux.h: Removed.
* config/m32r/t-linux: Removed.

libgcc/ChangeLog:

* config.host: Remove m32r-*-linux* and m32rle-*-linux*.
* config/m32r/libgcc-glibc.ver: Removed.
* config/m32r/t-linux: Removed.

Fix PR lto/49664: liblto_plugin.so exports too many symbols

So right now liblto_plugin.so exports many libiberty symbols and
simple_object file symbols but really it just needs to export onload.

This fixes the problem by using "-export-symbols-regex onload" on
the libtool link line.

lto-plugin/ChangeLog:

PR lto/49664
* Makefile.am: Export only onload.
* Makefile.in: Regenerate.

aarch64: PR target/102252 Invalid addressing mode for SVE load predicate

In the testcase we generate invalid assembly for an SVE load predicate instruction.
The RTL for the insn is:
(insn 9 8 10 (set (reg:VNx16BI 68 p0)
        (mem:VNx16BI (plus:DI (mult:DI (reg:DI 1 x1 [93])
                    (const_int 8 [0x8]))
                (reg/f:DI 0 x0 [92])) [2 work_3(D)->array[offset_4(D)]+0 S8 A16]))

That addressing mode is not valid for the instruction [1] as it only accepts the addressing mode:
[<Xn|SP>{, #<imm>, MUL VL}]

This patch rejects the register index form for SVE predicate modes.

Bootstrapped and tested on aarch64-none-linux-gnu.

[1] https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions/LDR--predicate---Load-predicate-register-

gcc/ChangeLog:

PR target/102252
* config/aarch64/aarch64.c (aarch64_classify_address): Don't allow
register index for SVE predicate modes.

gcc/testsuite/ChangeLog:

PR target/102252
* g++.target/aarch64/sve/pr102252.C: New test.

Remove references to FSM threads.

Now that the jump thread back registry has been split into the generic
copier and the custom (old) copier, it becomes trivial to remove the
FSM bits from the jump threaders.

First, there's no need for an EDGE_FSM_THREAD type.  The only reason
we were looking at the threading type was to determine what type of
copier to use, and now that the copier has been split, there's no need
to even look.  However, there is one check in register_jump_thread
where we verify that only the generic copier can thread through
back-edges.  I've removed that check in favor of a flag passed to the
constructor.

I've also removed all the FSM references from the code and tests.
Interestingly, some tests weren't even testing the right thing.  They
were testing for "FSM" which would catch jump thread paths as well as
the backward threader *failing* on registering a path.  *big eye roll*

The only remaining code that was actually checking for EDGE_FSM_THREAD
was adjust_paths_after_duplication, and the checks could be written
without looking at the edge type at all.  For the record, the code
there is horrible: it's convoluted, hard to read, and doesn't have any
tests.  I'd smack myself if I could go back in time.

All that remains are the FSM references in the --param's themselves.
I think we should s/fsm/threader/, since I envision a day when we can
share the cost basis code between the threaders.  However, I don't
know what the proper procedure is for renaming existing compiler
options.

By the way, param_fsm_maximum_phi_arguments is no longer relevant
after the rewrite.  We can nuke that one right away.

Tested on x86-64 Linux.

gcc/ChangeLog:

* tree-ssa-threadbackward.c
(back_threader_profitability::profitable_path_p): Remove FSM
references.
(back_threader_registry::register_path): Same.
* tree-ssa-threadedge.c
(jump_threader::simplify_control_stmt_condition): Same.
* tree-ssa-threadupdate.c (jt_path_registry::jt_path_registry):
Add backedge_threads argument.
(fwd_jt_path_registry::fwd_jt_path_registry): Pass
backedge_threads argument.
(back_jt_path_registry::back_jt_path_registry):  Same.
(dump_jump_thread_path): Adjust for FSM removal.
(back_jt_path_registry::rewire_first_differing_edge): Same.
(back_jt_path_registry::adjust_paths_after_duplication): Same.
(back_jt_path_registry::update_cfg): Same.
(jt_path_registry::register_jump_thread): Same.
* tree-ssa-threadupdate.h (enum jump_thread_edge_type): Remove
EDGE_FSM_THREAD.
(class back_jt_path_registry): Add backedge_threads to
constructor.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/pr21417.c: Adjust for FSM removal.
* gcc.dg/tree-ssa/pr66752-3.c: Same.
* gcc.dg/tree-ssa/pr68198.c: Same.
* gcc.dg/tree-ssa/pr69196-1.c: Same.
* gcc.dg/tree-ssa/pr70232.c: Same.
* gcc.dg/tree-ssa/pr77445.c: Same.
* gcc.dg/tree-ssa/ranger-threader-4.c: Same.
* gcc.dg/tree-ssa/ssa-dom-thread-18.c: Same.
* gcc.dg/tree-ssa/ssa-dom-thread-6.c: Same.
* gcc.dg/tree-ssa/ssa-thread-12.c: Same.
* gcc.dg/tree-ssa/ssa-thread-13.c: Same.

c++: parameter pack inside constexpr if [PR101764]

Here when partially instantiating the first pack expansion, substitution
into the condition of the constexpr if yields a still-dependent tree, so
tsubst_expr returns an IF_STMT with an unsubstituted IF_COND and with
IF_STMT_EXTRA_ARGS added to.  Hence after partial instantiation the pack
expansion pattern still refers to the unlowered parameter pack 'ts' of
level 2, and it's thusly recorded in the new PACK_EXPANSION_PARAMETER_PACKS.
During the subsequent final instantiation of the regenerated lambda we
crash in tsubst_pack_expansion because it can't find an argument pack
for this unlowered 'ts', due to the level mismatch.  (Likewise when the
constexpr if is replaced by a requires-expr, which also uses the extra
args mechanism for avoiding partial instantiation.)

So essentially, a pack expansion pattern that contains an "extra args"
tree doesn't play well with partial instantiation.  This patch fixes
this by forcing such pack expansions to use the extra args mechanism as
well.

PR c++/101764

gcc/cp/ChangeLog:

* cp-tree.h (PACK_EXPANSION_FORCE_EXTRA_ARGS_P): New accessor
macro.
* pt.c (has_extra_args_mechanism_p): New function.
(find_parameter_pack_data::found_extra_args_tree_p): New data
member.
(find_parameter_packs_r): Set ppd->found_extra_args_tree_p
appropriately.
(make_pack_expansion): Set PACK_EXPANSION_FORCE_EXTRA_ARGS_P if
ppd.found_extra_args_tree_p.
(use_pack_expansion_extra_args_p): Return true if there were
unsubstituted packs and PACK_EXPANSION_FORCE_EXTRA_ARGS_P.
(tsubst_pack_expansion): Pass the pack expansion to
use_pack_expansion_extra_args_p.

gcc/testsuite/ChangeLog:

* g++.dg/cpp1z/constexpr-if35.C: New test.

c++: fix -fsanitize-coverage=trace-pc ICE [PR101331]

PR c++/101331

gcc/ChangeLog:

* asan.h (sanitize_coverage_p): Handle when fn == NULL.

gcc/testsuite/ChangeLog:

* g++.dg/pr101331.C: New test.

Adjust ssa-dom-thread-7.c on aarch64.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/ssa-dom-thread-7.c: Adjust for aarch64.

x86: Add TARGET_AVX256_[MOVE|STORE]_BY_PIECES

1. Add TARGET_AVX256_MOVE_BY_PIECES to perform move by-pieces operation
with 256-bit AVX instructions.
2. Add TARGET_AVX256_STORE_BY_PIECES to perform move and store by-pieces
operations with 256-bit AVX instructions.

They are enabled only for Intel Alder Lake and Intel processors with
AVX512.

gcc/

PR target/101935
* config/i386/i386.h (TARGET_AVX256_MOVE_BY_PIECES): New.
(TARGET_AVX256_STORE_BY_PIECES): Likewise.
(MOVE_MAX): Check TARGET_AVX256_MOVE_BY_PIECES and
TARGET_AVX256_STORE_BY_PIECES instead of
TARGET_AVX256_SPLIT_UNALIGNED_LOAD and
TARGET_AVX256_SPLIT_UNALIGNED_STORE.
(STORE_MAX_PIECES): Check TARGET_AVX256_STORE_BY_PIECES instead
of TARGET_AVX256_SPLIT_UNALIGNED_STORE.
* config/i386/x86-tune.def (X86_TUNE_AVX256_MOVE_BY_PIECES): New.
(X86_TUNE_AVX256_STORE_BY_PIECES): Likewise.

gcc/testsuite/

PR target/101935
* g++.target/i386/pr80566-1.C: Add
-mtune-ctrl=avx256_store_by_pieces.
* gcc.target/i386/pr100865-4a.c: Likewise.
* gcc.target/i386/pr100865-10a.c: Likewise.
* gcc.target/i386/pr90773-20.c: Likewise.
* gcc.target/i386/pr90773-21.c: Likewise.
* gcc.target/i386/pr90773-22.c: Likewise.
* gcc.target/i386/pr90773-23.c: Likewise.
* g++.target/i386/pr80566-2.C: Add
-mtune-ctrl=avx256_move_by_pieces.
* gcc.target/i386/eh_return-1.c: Likewise.
* gcc.target/i386/pr90773-26.c: Likewise.
* gcc.target/i386/pieces-memcpy-12.c: Replace -mtune=haswell
with -mtune-ctrl=avx256_move_by_pieces.
* gcc.target/i386/pieces-memcpy-15.c: Likewise.
* gcc.target/i386/pieces-memset-2.c: Replace -mtune=haswell
with -mtune-ctrl=avx256_store_by_pieces.
* gcc.target/i386/pieces-memset-5.c: Likewise.
* gcc.target/i386/pieces-memset-11.c: Likewise.
* gcc.target/i386/pieces-memset-14.c: Likewise.
* gcc.target/i386/pieces-memset-20.c: Likewise.
* gcc.target/i386/pieces-memset-23.c: Likewise.
* gcc.target/i386/pieces-memset-29.c: Likewise.
* gcc.target/i386/pieces-memset-30.c: Likewise.
* gcc.target/i386/pieces-memset-33.c: Likewise.
* gcc.target/i386/pieces-memset-34.c: Likewise.
* gcc.target/i386/pieces-memset-44.c: Likewise.
* gcc.target/i386/pieces-memset-37.c: Replace -mtune=generic
with -mtune-ctrl=avx256_store_by_pieces.

Use gen_lowpart_if_possible instead of gen_lowpart to avoid ICE.

gcc/ChangeLog:

PR bootstrap/102302
* expmed.c (extract_bit_field_using_extv): Use
gen_lowpart_if_possible instead of gen_lowpart to avoid ICE.

Move pointer_equiv_analyzer to new file.

We need to use the pointer equivalence tracking from evrp in the jump
threader.  Instead of moving it to some *evrp.h header, it's cleaner for
it to live in its own file, since it's completely independent and not
evrp specific.

Tested on x86-64 Linux.

gcc/ChangeLog:

* Makefile.in (OBJS): Add value-pointer-equiv.o.
* gimple-ssa-evrp.c (class ssa_equiv_stack): Move to
value-pointer-equiv.*.
(ssa_equiv_stack::ssa_equiv_stack): Same.
(ssa_equiv_stack::enter): Same.
(ssa_equiv_stack::leave): Same.
(ssa_equiv_stack::push_replacement): Same.
(ssa_equiv_stack::get_replacement): Same.
(is_pointer_ssa): Same.
(class pointer_equiv_analyzer): Same.
(pointer_equiv_analyzer::pointer_equiv_analyzer): Same.
(pointer_equiv_analyzer::~pointer_equiv_analyzer): Same.
(pointer_equiv_analyzer::set_global_equiv): Same.
(pointer_equiv_analyzer::set_cond_equiv): Same.
(pointer_equiv_analyzer::get_equiv): Same.
(pointer_equiv_analyzer::enter): Same.
(pointer_equiv_analyzer::leave): Same.
(pointer_equiv_analyzer::get_equiv_expr): Same.
(pta_valueize): Same.
(pointer_equiv_analyzer::visit_stmt): Same.
(pointer_equiv_analyzer::visit_edge): Same.
(hybrid_folder::value_of_expr): Same.
(hybrid_folder::value_on_edge): Same.
* value-pointer-equiv.cc: New file.
* value-pointer-equiv.h: New file.

gimple: allow more folding of memcpy [PR102125]

The current restriction on folding memcpy to a single element of size
MOVE_MAX is excessively cautious on most machines and limits some
significant further optimizations.  So relax the restriction provided
the copy size does not exceed MOVE_MAX * MOVE_RATIO and that a SET
insn exists for moving the value into machine registers.

Note that there were already checks in place for having misaligned
move operations when one or more of the operands were unaligned.

On Arm this now permits optimizing

uint64_t bar64(const uint8_t *rData1)
{
    uint64_t buffer;
    memcpy(&buffer, rData1, sizeof(buffer));
    return buffer;
}

from
        ldr     r2, [r0]        @ unaligned
        sub     sp, sp, #8
        ldr     r3, [r0, #4]    @ unaligned
        strd    r2, [sp]
        ldrd    r0, [sp]
        add     sp, sp, #8

to
        mov     r3, r0
        ldr     r0, [r0]        @ unaligned
        ldr     r1, [r3, #4]    @ unaligned

PR target/102125 - (ARM Cortex-M3 and newer) missed optimization. memcpy not needed operations

gcc/ChangeLog:

PR target/102125
* gimple-fold.c (gimple_fold_builtin_memory_op): Allow folding
memcpy if the size is not more than MOVE_MAX * MOVE_RATIO.

arm: expand handling of movmisalign for DImode [PR102125]

DImode is currently handled only for machines with vector modes
enabled, but this is unduly restrictive and is generally better done
in core registers.

gcc/ChangeLog:

PR target/102125
* config/arm/arm.md (movmisaligndi): New define_expand.
* config/arm/vec-common.md (movmisalign<mode>): Iterate over VDQ mode.

rtl: directly handle MEM in gen_highpart [PR102125]

gen_lowpart_general handles forming a lowpart of a MEM by using
adjust_address to rework and validate a new version of the MEM.
Do the same for gen_highpart rather than calling simplify_gen_subreg
for this case.

gcc/ChangeLog:

PR target/102125
* emit-rtl.c (gen_highpart): Use adjust_address to handle
MEM rather than calling simplify_gen_subreg.

cr16-elf is now obsoleted

As we are still building it for ./contrib/config-list.mk, let's add
--enable-obsolete so this has a chance to work.

contrib/ChangeLog:

* config-list.mk (LIST): --enable-obsolete for cr16-elf.

Fix multi-statment macro

INIT_CUMULATIVE_ARGS() expands to multiple statements, which will break right
after an `if` statement. Wrap it into a block.

gcc/ChangeLog:

* config/alpha/vms.h (INIT_CUMULATIVE_ARGS): Wrap multi-statment
define into a block.

Remove DARWIN_PREFER_DWARF and dead code

This removes the always defined DARWIN_PREFER_DWARF and the code
guarded by it being not defined, removing the possibility to
default some i386 darwin configurations to STABS when it would
not be defined.

2021-09-10  Richard Biener  <rguenther@suse.de>

* config/darwin.h (DARWIN_PREFER_DWARF): Do not define.
* config/i386/darwin.h (PREFERRED_DEBUGGING_TYPE): Do not
change based on DARWIN_PREFER_DWARF not being defined.

Fix i686-lynx build breakage

With the last adjustment I failed to remove a stray undef of
PREFERRED_DEBUGGING_TYPE from config/i386/lynx.h

2021-09-13  Richard Biener  <rguenther@suse.de>

* config/i386/lynx.h: Remove undef of PREFERRED_DEBUGGING_TYPE
to inherit from elfos.h

Add cr16-*-* to the list of obsoleted targets

This adds cr16-*-* to the list of obsoleted targets in config.gcc

2021-09-13  Richard Biener  <rguenther@suse.de>

* config.gcc: Add cr16-*-* to the list of obsoleted targets.

Default AVR to DWARF2 debug

This switches the AVR port to generate DWARF2 debugging info by
default since the support for STABS is going to be deprecated for
GCC 12.

2021-09-10  Richard Biener  <rguenther@suse.de>

* config/avr/elf.h (PREFERRED_DEBUGGING_TYPE): Remove
override, pick up DWARF2_DEBUG define from elfos.h

Always default to DWARF2 debugging for RX, even with -mas100-syntax

The RX port defaults to STABS when -mas100-syntax is used because
the AS100 assembler does not support some of the pseudo-ops used
by DWARF2 debug emission.  Since STABS is going to be deprecated
that has to change.  The following simply always uses DWARF2,
likely leaving -mas100-syntax broken when debug info is generated.

Can the RX port maintainer please sort out the situation?

2021-09-10  Richard Biener  <rguenther@suse.de>

* config/rx/rx.h (PREFERRED_DEBUGGING_TYPE): Always define to
DWARF2_DEBUG.