Aaron Ballman [Wed, 9 Nov 2022 14:19:24 +0000 (09:19 -0500)]
Fix Clang sphinx build
This addresses the issue found by:
https://lab.llvm.org/buildbot/#/builders/92/builds/35350
Tomasz Kamiński [Wed, 9 Nov 2022 13:31:49 +0000 (14:31 +0100)]
[analyzer] Fix crash for array-delete of UnknownVal values.
We now skip the destruction of array elements for `delete[] p`,
if the value of `p` is UnknownVal and does not have corresponding region.
This eliminate the crash in `getDynamicElementCount` on that
region and matches the behavior for deleting the array of
non-constant range.
Reviewed By: isuckatcs
Differential Revision: https://reviews.llvm.org/D136671
Vladislav Vinogradov [Wed, 2 Nov 2022 11:22:14 +0000 (14:22 +0300)]
[Support] Format provider improvements
Remove `std::forward` call for `iterator_range` iterator de-reference.
It fixes formatting usage for some tricky cases, like special ranges,
which de-reference to value type.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D94769
Nicolas Vasilache [Wed, 9 Nov 2022 13:09:39 +0000 (05:09 -0800)]
[mlir][Transform] Fix transform.sequence crash in the presence of propagated silenceable errors and yield operations
Differential Revision: https://reviews.llvm.org/D137708
Sven van Haastregt [Wed, 9 Nov 2022 13:17:23 +0000 (13:17 +0000)]
[OpenCL] Guard read_write image3d with cl_khr_3d_image_writes
Not all `read_write image3d_t` occurrences in opencl-c.h were guarded
with `cl_khr_3d_image_writes`. Align with `-fdeclare-opencl-builtins`.
Vladislav Vinogradov [Wed, 9 Nov 2022 13:14:39 +0000 (16:14 +0300)]
Revert "[Support] Format provider improvements"
This reverts commit
791bdba0b183371ca3e16bb8411a059b4f8636ac.
Bot failure: https://lab.llvm.org/buildbot/#/builders/223/builds/9914
Vladislav Vinogradov [Wed, 2 Nov 2022 11:22:14 +0000 (14:22 +0300)]
[Support] Format provider improvements
Remove `std::forward` call for `iterator_range` iterator de-reference.
It fixes formatting usage for some tricky cases, like special ranges,
which de-reference to value type.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D94769
Haojian Wu [Wed, 9 Nov 2022 12:03:12 +0000 (13:03 +0100)]
Fix an unused-variable warning in release build, NFC.
Tomas Matheson [Sun, 23 Oct 2022 20:44:21 +0000 (21:44 +0100)]
[ARM] Move Triple::getARMCPUForArch into ARMTargetParser
This is very backend specific so either belongs in Toolchains/ARM or in
ARMTargetParser. Since it is used in lldb, ARMTargetParser made more sense.
This is part of an effort to move information about ARM/AArch64 architecture
versions, extensions and CPUs into their respective TargetParsers.
Differential Revision: https://reviews.llvm.org/D137564
OCHyams [Wed, 9 Nov 2022 11:39:29 +0000 (11:39 +0000)]
[Assignment Tracking][10/*] salvageDebugInfo for dbg.assign intrinsics
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Plumb in salvaging for the address part of dbg.assign intrinsics.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D133293
Nikita Popov [Wed, 9 Nov 2022 11:18:18 +0000 (12:18 +0100)]
[SCCP] Add helper for getting constant range (NFC)
Add a helper for the recurring pattern of getting a constant range
if the value lattice element is one, or a full range otherwise.
Victor Campos [Wed, 19 Oct 2022 13:03:57 +0000 (14:03 +0100)]
[AArch64] Add support for the Cortex-X3 CPU
Cortex-X3 is an Armv9-A AArch64 CPU.
This patch introduces support for Cortex-X3.
Technical Reference Manual: https://developer.arm.com/documentation/101593/latest
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136589
Kai Sasaki [Wed, 9 Nov 2022 11:11:55 +0000 (12:11 +0100)]
[mlir][complex] Canonicalize complex.sub zero
Subtracting zero constant can be fold in no complex.sub operation.
Reviewed By: pifon2a
Differential Revision: https://reviews.llvm.org/D137523
OCHyams [Wed, 9 Nov 2022 10:49:55 +0000 (10:49 +0000)]
[Assignment Tracking][9/*] Don't drop DIAssignID in dropUnknownNonDebugMetadata
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
A DIAssignID attachment is debug metadata, so don't drop it.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D133292
OCHyams [Wed, 9 Nov 2022 10:41:28 +0000 (10:41 +0000)]
[Assignment Tracking][8/*] Add DIAssignID merging utilities
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Add method:
Instruction::mergeDIAssignID(
ArrayRef<const Instruction* > SourceInstructions)
which merges the DIAssignID metadata attachments on `SourceInstructions` and
`this` and replaces uses of the original IDs with the new shared one.
This is used when stores are merged, for example sinking stores out of a
if-diamond CFG or vectorizing contiguous stores.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D133291
Jean Perier [Wed, 9 Nov 2022 10:40:56 +0000 (11:40 +0100)]
[flang][NFC] move fir namespace into FortranVariableOpInterface ODS declaration
This will be needed to be able to use this interface in HLFIR ODS operation definition
and get the right namespaces.
Differential Revision: https://reviews.llvm.org/D137702
Jean Perier [Wed, 9 Nov 2022 10:37:53 +0000 (11:37 +0100)]
[flang][NFC] move HLFIR dialect definition in IR
Transforms will need to be put in a different library to avoid circular
dependencies with other parts of the compiler. So create an IR
directory, this (flat include directory, IR and Transform directories in
lib) matches how dialects like LLVM dialect are implemented.
Differential Revision: https://reviews.llvm.org/D137701
Sheng [Wed, 9 Nov 2022 10:37:03 +0000 (18:37 +0800)]
[M68k] Add support for atomic instructions
This adds support for atomic_load, atomic_store, atomic_cmpxchg
and atomic_rmw
Fixes #48236
Reviewed by: myhsu, efriedma
Differential Revision: https://reviews.llvm.org/D136525
Sheng [Wed, 9 Nov 2022 10:25:09 +0000 (18:25 +0800)]
[M68k] Replace `IsM680x0` with predicates `AtLeastM680x0`
The former is incorrect.
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D137425
Thomas Symalla [Wed, 9 Nov 2022 10:23:24 +0000 (11:23 +0100)]
[NFC][AMDGPU] Pre-commit tests for D136432.
chenglin.bi [Wed, 9 Nov 2022 10:06:21 +0000 (18:06 +0800)]
[AArch64] Support all extend/shift op for pattern: (ExtendOrShfitNode - Y) + Z --> (Z - Y) + ExtendOrShfitNode
Followup rG325a3083b5b24
Add SRL/SRA/xxx_EXTEND/AND support
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D137069
OCHyams [Tue, 8 Nov 2022 16:58:53 +0000 (16:58 +0000)]
Reapply: [Assignment Tracking][7/*] Add assignment tracking functionality to clang
Reverted in
98fa95492f3bbd5befdeb36c88a3ac5ef2740b4e.
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
This patch plumbs the AssignmentTrackingPass (AKA declare-to-assign), added in
the previous patch in this set, into the optimisation pipeline from
clang. clang/test/CodeGen/assignment-tracking/assignment-tracking.cpp is the
main test for this patch.
Note: while clang (with the help of the declare-to-assign pass) can now emit
Assignment Tracking metadata, the llvm middle and back ends don't yet
understand it.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132226
OCHyams [Wed, 9 Nov 2022 09:11:02 +0000 (09:11 +0000)]
Fix D132221 rebase: Add flags to enable Assignment Tracking
The flags were not set up properly after rebasing the patch, causing bot
failures for D132226, for example:
https://lab.llvm.org/buildbot/#/builders/109/builds/50251
David Sherwood [Mon, 7 Nov 2022 10:18:34 +0000 (10:18 +0000)]
[AArch64][SVE2] Add the SVE2.1 quadword structured load/store instructions
This patch adds the assembly/disassembly for the following instructions:
ld2q : Contiguous load two-quadword structures to two vectors
ld3q : Contiguous load three-quadword structures to three vectors
ld4q : Contiguous load four-quadword structures to four vectors
st2q : Contiguous store two-quadword structures from two vectors
st3q : Contiguous store three-quadword structures to three vectors
st4q : Contiguous store four-quadword structures to four vectors
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137554
Bjorn Pettersson [Tue, 8 Nov 2022 07:04:39 +0000 (08:04 +0100)]
[test] Avoid legacy PM default pipelines (O0,O1 etc) when running opt
Two lit tests were found running something like this:
opt -O<n> -pass-locked-to-legacy-PM ...
The expand-atomicrmw-xchg-fp.ll seem to have used -O1 just to ensure
that the -atomic-expand pass were thinking that it wasn't running at
O0 level. Same thing can be ensured by using the -codegen-opt-level=1
option, making it possible to avoid using O1 in that test case.
In the vector-reductions-expanded.ll test case it was possible to
split the RUN line into using two opt invocations. First running
"opt -O2" using the new PM, and then running "opt -expand-reductions"
using the legacy PM.
I think that given this patch we get closer to removing code related
to 'AddOptimizationPasses' in opt.cpp.
Differential Revision: https://reviews.llvm.org/D137626
Freddy Ye [Wed, 9 Nov 2022 08:12:25 +0000 (16:12 +0800)]
[X86] Support -march=sierraforest, grandridge, graniterapids.
Reviewed By: skan, pengfei, MaskRay
Differential Revision: https://reviews.llvm.org/D137153
melonedo [Tue, 16 Aug 2022 04:56:59 +0000 (12:56 +0800)]
[RISCV] Add support for static chain
The static chain parameter is a special parameter that is not passed in the usual argument registers or stack space. For example, in x64 System V ABI it is always passed in R10. Although the ABI of RISCV does not assign a register for this purpose, GCC had support for it on RISC-V a long time ago, and it is exposed via `__builtin_call_with_static_chain` intrinsic, and assign t2 for static chain parameters. This patch also chose t2 for compatibility.
In LLVM, static chain parameters are handled by the `nest` attribute of an argument to a function ([D6332](https://reviews.llvm.org/D6332)), so tests are added to ensure `nest` arguments are handled correctly.
Reviewed By: kito-cheng, MaskRay
Differential Revision: https://reviews.llvm.org/D129106
chenglin.bi [Wed, 9 Nov 2022 07:36:47 +0000 (15:36 +0800)]
[AArch64] Precommit test for D137069; NFC
Vitaly Buka [Wed, 9 Nov 2022 06:59:03 +0000 (22:59 -0800)]
[compiler-rt] Set CMP0114 policy for standalone build
Fixes sanitizer-x86_64-linux-qemu bot.
Animesh Kumar [Fri, 30 Sep 2022 17:14:42 +0000 (22:44 +0530)]
[OpenMP] Add map clause to the LIT test on use_device_addr clause
As per the OpenMP Spec, "A list item in a use_device_addr clause
must have a corresponding list item in the device data environment"
. Therefore a `map` clause is added which will make sure that the
respective list items are mapped to the device data environment
before the `use_device_addr` clause is specified. The CHECK lines
are also modified based on this change.
Differential Revision: https://reviews.llvm.org/D134974
jinge90 [Wed, 9 Nov 2022 06:24:39 +0000 (14:24 +0800)]
[libunwind] Check corrupted return address in unwind_phase2 when CET is enabled.
If CET shadow stack is enabled, we count the number of stack frames skipped
and adjust CET shadow stack based on the number in libunwind unwind_phase2.
At the same time, we can enhance security via comparing the return address in
normal stack against counterpart in CET shadow stack, if they don't match,
it means the return address stored in normal stack has been corrupted and we
will return _URC_FATAL_PHASE2_ERROR in that case.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D136667
Signed-off-by: jinge90 <ge.jin@intel.com>
Haohai Wen [Wed, 9 Nov 2022 06:08:01 +0000 (14:08 +0800)]
[X86] Add In64BitMode requirement for MMXRI
REX_W prefix is only encodable in 64bit.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D137686
chenglin.bi [Tue, 8 Nov 2022 21:07:44 +0000 (05:07 +0800)]
[TypePromotion] Replace Zext to Truncate for the case src bitwidth is larger
Fix: https://github.com/llvm/llvm-project/issues/58843
Reviewed By: samtebbs
Differential Revision: https://reviews.llvm.org/D137613
River Riddle [Tue, 8 Nov 2022 20:46:41 +0000 (12:46 -0800)]
[mlir][LLVM] Add base type and flag support to composite type
This requires defining the DIFlag enum from LLVM.
Differential Revision: https://reviews.llvm.org/D137667
Peiming Liu [Wed, 9 Nov 2022 01:42:26 +0000 (01:42 +0000)]
[mlir][sparse] fix SSA chain issue in dense2sparse conversion.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137683
Peiming Liu [Wed, 9 Nov 2022 00:43:27 +0000 (00:43 +0000)]
[mlir][sparse] extend foreach operation to iterator over sparse constant.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137679
Jakub Kuderski [Wed, 9 Nov 2022 01:34:31 +0000 (20:34 -0500)]
[mlir][arith] Add `select` support to WIE
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D137589
Fangrui Song [Wed, 9 Nov 2022 01:28:04 +0000 (17:28 -0800)]
[lld] Fix duplicate word typos. NFC
Based on lld/ part of D137338 but reflowed comments.
Peixin-Qiao [Wed, 9 Nov 2022 01:24:38 +0000 (09:24 +0800)]
[flang] Fix function result rewrite for CPTR type
Not all derived type can be taken as abstract result. The CPTR type
should be treated as return by value so to interoperable with C
functions. Fix the function result rewrite for CPTR type, but it
should be generalized for all derived types. The ABI of
interoperability with C for derived type is architecture dependent,
which should be supported later.
Reviewed By: PeteSteinfeld, jeanPerier
Differential Revision: https://reviews.llvm.org/D137548
wren romano [Wed, 9 Nov 2022 00:43:44 +0000 (16:43 -0800)]
[mlir][sparse] Factoring out NewCallParams class in SparseTensorConversion.cpp
The new class helps encapsulate the arguments to `_mlir_ciface_newSparseTensor` so that client code doesn't depend on the details of the API. (This makes way for the next differential which significantly alters the API.)
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137680
Jim Ingham [Wed, 9 Nov 2022 00:57:57 +0000 (16:57 -0800)]
Move the second instance of TestUniqueTypes.py to a unique file
name. lldb-dotest.py errors out if two tests have the same filename.
Mehdi Amini [Wed, 9 Nov 2022 00:42:41 +0000 (00:42 +0000)]
Do not build with Werror by default (Bazel build)
This seems like an anti-pattern to have -Werror on by default:
it is hostile to user as we can't ensure that all of the supported
platforms are warning-free, and any newer compiler could break the build
for a user who does not have a clear actionable way around it.
Reviewed By: GMNGeoffrey, kuhar
Differential Revision: https://reviews.llvm.org/D123481
Mehdi Amini [Thu, 3 Nov 2022 20:29:28 +0000 (20:29 +0000)]
Apply clang-tidy fixes for readability-redundant-smartptr-get in SCF.cpp (NFC)
Mehdi Amini [Thu, 3 Nov 2022 20:28:33 +0000 (20:28 +0000)]
Apply clang-tidy fixes for llvm-qualified-auto in SCF.cpp (NFC)
Rob Suderman [Tue, 8 Nov 2022 00:18:39 +0000 (16:18 -0800)]
[mlir][linalg] Fix vectorization of linalg depthwise conv for int types
Vectorization of Linalg's depthwise convolution only supports floating
point types. Previous version assumed floating point operations would
work. This version checks whether the computation is integer or floating
point and adjust the inner loop computation.
Reviewed By: hanchung
Differential Revision: https://reviews.llvm.org/D137595
Aart Bik [Tue, 8 Nov 2022 22:58:45 +0000 (14:58 -0800)]
[mlir][sparse] add sparse matmul codegen check tests
This found an insertion point bug in access pattern expansion
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D137675
Akira Hatanaka [Tue, 8 Nov 2022 22:26:51 +0000 (14:26 -0800)]
[ObjC][ARC] Fix non-deterministic behavior in ProvenanceAnalysis
ProvenanceAnalysis::relatedCheck was giving different answers depending
on the order in which the pointers were passed.
Specifically, it was returning different values when A and B were both
loads and were both referring to identifiable objects, but only one was
used by a store instruction.
Aart Bik [Tue, 8 Nov 2022 21:10:54 +0000 (13:10 -0800)]
[mlir][sparse] 3-dimensional sparse tensor insertion test
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D137668
Sam McCall [Tue, 8 Nov 2022 22:48:15 +0000 (23:48 +0100)]
[clangd] Avoid escaping issues in system-include-extractor.test
Fangrui Song [Tue, 8 Nov 2022 22:39:09 +0000 (14:39 -0800)]
[Driver] Refactor err_drv_unsupported_option_argument call sites to use llvm::opt::Arg::getSpelling
For `-foo=bar`, getSpelling return `-foo=` which is exactly what we need from
the diagnostic. Drop `-` from the err_drv_unsupported_option_argument template.
This change makes `--` long option diagnostics more convenient.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D137659
Jez Ng [Tue, 8 Nov 2022 21:33:32 +0000 (16:33 -0500)]
[lld-macho] Fix bugs around EH_Frame symbols
While extending the map file to cover unwind info, I realized we had two
issues with our EH_Frame symbols:
1. Their size was not set
2. We would create two EH_Frame symbols per frame when we only needed
one. This was because the Defined constructor would add the symbol
itself to InputSection::symbols, but we were also manually appending
the symbol to that same vector.
Note that ld64 prints "CIE" and "FDE for: <function>" instead of just
"EH_Frame", but I'm punting on that for now unless we discover that
users really depend upon it.
Reviewed By: #lld-macho, Roger
Differential Revision: https://reviews.llvm.org/D137370
Jez Ng [Tue, 8 Nov 2022 21:33:28 +0000 (16:33 -0500)]
[lld-macho] Emit map file entry for compact unwind info
Just like ld64 does.
Reviewed By: #lld-macho, Roger
Differential Revision: https://reviews.llvm.org/D137369
Jez Ng [Tue, 8 Nov 2022 21:33:22 +0000 (16:33 -0500)]
[lld-macho] Overhaul map file code
The previous map file code left out was modeled after LLD-ELF's
implementation. However, ld64's map file differs quite a bit from
LLD-ELF's. I've revamped our map file implementation so it is better
able to emit ld64-style map files.
Notable differences:
* ld64 doesn't demangle symbols in map files, regardless of whether
`-demangle` is passed. So we don't have to bother with
`getSymbolStrings()`.
* ld64 doesn't emit symbols in cstring sections; it emits just the
literal values. Moreover, it emits these literal values regardless of
whether they are labeled with a symbol.
* ld64 emits map file entries for things that are not strictly symbols,
such as unwind info, GOT entries, etc. That isn't handled in this
diff, but this redesign makes them easy to implement.
Additionally, the previous implementation sorted the symbols so as to
emit them in address order. This was slow and unnecessary -- the symbols
can already be traversed in address order by walking the list of
OutputSections. This brings significant speedups. Here's the numbers
from the chromium_framework_less_dwarf benchmark on my Mac Pro, with the
`-map` argument added to the response file:
base diff difference (95% CI)
sys_time 2.922 ± 0.059 2.950 ± 0.085 [ -0.7% .. +2.5%]
user_time 11.464 ± 0.191 8.290 ± 0.123 [ -28.7% .. -26.7%]
wall_time 11.235 ± 0.175 9.184 ± 0.169 [ -19.3% .. -17.2%]
samples 16 23
(It's worth noting that map files are written in parallel with the
output binary, but they often took longer to write than the binary
itself.)
Finally, I did further cleanups to the map-file.s test -- there was no
real need to have a custom-named section. There were also alt_entry
symbol declarations that had no corresponding definition. Either way,
neither custom-named sections nor alt_entry symbols trigger special code
paths in our map file implementation.
Reviewed By: #lld-macho, Roger
Differential Revision: https://reviews.llvm.org/D137368
Aart Bik [Fri, 4 Nov 2022 19:23:03 +0000 (12:23 -0700)]
[mlir][sparse] first general insertion implementation with pure codegen
This revision generalizes lowering the sparse_tensor.insert op into actual code that directly operates on the memrefs of a sparse storage scheme. The current insertion strategy does *not* rely on a cursor anymore, with introduces some testing overhead for each insertion (but still proportional to the rank, as before). Over time, we can optimize the code generation, but this version enables us to finish the effort to migrate from library to actual codegen.
Things to do:
(1) carefully deal with (un)ordered and (not)unique
(2) omit overhead when not needed
(3) optimize and specialize
(4) try to avoid the pointer "cleanup" (at HasInserts), and make sure the storage scheme is consistent at every insertion point (so that it can "escape" without concerns).
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D137457
River Riddle [Tue, 8 Nov 2022 03:02:18 +0000 (19:02 -0800)]
[mlir][LLVMDebugTranslation] Move the check for FusedLoc scope
Shift it to where we already check for FusedLoc, which removes the
need to cast multiple times.
River Riddle [Tue, 8 Nov 2022 03:01:14 +0000 (19:01 -0800)]
[mlir][LLVMDebugTranslation] Add inlinedAt to the key when caching locations
This avoids accidentally using the wrong inlined at scope when translating
locations.
rkayaith [Tue, 8 Nov 2022 20:42:50 +0000 (15:42 -0500)]
[mlir][NVGPU] Fix -Wunsequenced warning
llvm-project/mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp:441:25:
warning: multiple unsequenced modifications to 'asmArgIdx'
[-Wunsequenced]
ss << "$" << asmArgIdx++ << ",$" << asmArgIdx++ << ";";
^ ~~
Björn Schäpers [Fri, 4 Nov 2022 11:38:06 +0000 (12:38 +0100)]
[clang-format][NFCish] Alphabetical sort Format.(h|pp)
I've:
- Sorted the members of FormatStyle alphabetical. The enums and structs
are kept close to the member.
- Sorted the yaml io functions, based on the type they operate on.
- Sorted the initializers in getLLVMStyle(), except that penalities are
kept at the end.
- Sorted the io of FormatStyle, this changes the --dump-config behavior.
- Moved the deprecated options into the only input case, this also
changes --dump-config, it does not put the not directly used options
in the .clang-format anymore.
- Sorted the comparisons in operator==.
- Added WhiteSpaceMacros in operator==, I've not actively looked if all
other members are compared.
- This showed flawed tests (or in my opinion a flawed io operation, but
that is another discussion and change).
Differential Revision: https://reviews.llvm.org/D137409
Trass3r [Tue, 8 Nov 2022 20:44:46 +0000 (20:44 +0000)]
[Visualizers] Add natvis visualizers for various internal llvm classes
Also improve DisplayStrings for array and string types.
Differential Revision: https://reviews.llvm.org/D135685
rkayaith [Thu, 3 Nov 2022 18:29:44 +0000 (14:29 -0400)]
[mlir-opt] Add '-p' as an alias for '-pass-pipeline'
The pipeline strings have been getting more verbose over time, adding an
alias for the option should help improve the ergonomics a bit.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D137347
rkayaith [Wed, 12 Oct 2022 21:32:32 +0000 (17:32 -0400)]
[mlir][spirv] Change translation to use spirv.module
Update the SPIRV `mlir-translate` translations to translate to/from
`spirv.module` instead of `builtin.module`. This simplifies the
translation since the code no longer needs to walk the module looking
for a SPIRV module, however it requires passing `-no-implicit-module` to
all the tests.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D135819
David Green [Tue, 8 Nov 2022 19:30:26 +0000 (19:30 +0000)]
[AArch64] Allow users-facing feature names in clang target attributes
D133848 added support for the GCC format of target("..") attributes. The
supported formats to match gcc are:
// "arch=<arch>" - parsed to features as per -march=..
// "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
// "tune=<cpu>" - TuneCPU set to <cpu>
// "+feature", "+nofeature" - Add (or remove) feature.
We also support the existing formats, previously accepted by clang, for
compatibility with the existing code and intrinsics code:
// "feature", "no-feature" - Add (or remove) feature.
The clang formats would accept and use internal feature names
("fullfp16"/"neon"/"sve") as opposed to the user facing names
("fp16"/"simd"/"sve"). Usually they use the same names, but can be
different for cases like fp, fullfp16 and mte (among others).
This patch makes the clang format also except the user facing names, by
parsing the features through getArchExtFeature. There is a fallback if
the name is not recognized (like "fullfp16"), where we add the existing
string which should then be checked later for consistency. This allows
the internal names to be used as before, so long as they are recognized
as internal names. (Note that we currently don't have an implementation
of isValidFeatureName. The backend will currently give an error like
"'-sid' is not a recognized feature for this target (ignoring feature)."
This should be improved in a later patch once an implementation of
isValidFeatureName in clang is present).
Differential Revision: https://reviews.llvm.org/D137617
Adhemerval Zanella [Wed, 10 Aug 2022 14:47:07 +0000 (11:47 -0300)]
[clang][Headers] Do not define varargs macros for __need___va_list
The glibc uses the define to avoid namespace polution on headers
that requires variadic argument, where the inclusion of stdarg.h is
required to obtain the va_list definition.
For such cases only __gnuc_va_list is required.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D137268
Mingming Liu [Fri, 4 Nov 2022 21:09:13 +0000 (14:09 -0700)]
[AArch64]Combine BFXIL to ORR with right shift for ISD::OR instruction selection
- This extends the existing helper function 'isWorthFoldingIntoOrrWithLeftShift' into
'isWorthFoldingIntoOrrWithShift', and encode right-shift imm (the
encoding of left-shift imm is no-op).
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D137465
Sam McCall [Tue, 8 Nov 2022 19:18:10 +0000 (20:18 +0100)]
[include-cleaner] Missing changes from
38cccb906603
Sam McCall [Tue, 8 Nov 2022 15:33:08 +0000 (16:33 +0100)]
[include-cleaner] pass through recorded macro refs in walkUsed
Differential Revision: https://reviews.llvm.org/D137644
OCHyams [Tue, 8 Nov 2022 18:41:17 +0000 (18:41 +0000)]
Revert "[Assignment Tracking][7/*] Add assignment tracking functionality to clang"
This reverts commit
28f9636edd7d4e5f3eba1e3d0d37ec53d616481f.
Bot failure: https://lab.llvm.org/buildbot/#/builders/109/builds/50251
Paul Walker [Mon, 22 Aug 2022 16:19:48 +0000 (17:19 +0100)]
[SVE] Extend getMemVTFromNode to cover the sret variants of sve.ld2/3/4.
This enables the use of reg+imm addressing modes to match the
non-sret variants of these intrinsics.
Differential Revision: https://reviews.llvm.org/D132392
Simon Pilgrim [Tue, 8 Nov 2022 18:40:23 +0000 (18:40 +0000)]
[X86] SkylakeClientModel - fix instregex typo. NFCI.
The extra '?' is useless as it only makes a single letter optional and we can only match the SI64 pattern anyway (V?)CVT(T?)SS2SIrr has a different scheduler def
bixia1 [Mon, 7 Nov 2022 23:49:06 +0000 (15:49 -0800)]
[mlir][sparse] Add option enable-buffer-initialization to initialize the memory buffers for sparse tensors to support debugging.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137592
Daniel Thornburgh [Tue, 8 Nov 2022 17:51:52 +0000 (09:51 -0800)]
[llvm-debuginfod-find] Fix test/behavior on Windows.
OCHyams [Tue, 8 Nov 2022 16:58:53 +0000 (16:58 +0000)]
[Assignment Tracking][7/*] Add assignment tracking functionality to clang
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
This patch plumbs the AssignmentTrackingPass (AKA declare-to-assign), added in
the previous patch in this set, into the optimisation pipeline from
clang. clang/test/CodeGen/assignment-tracking/assignment-tracking.cpp is the
main test for this patch.
Note: while clang (with the help of the declare-to-assign pass) can now emit
Assignment Tracking metadata, the llvm middle and back ends don't yet
understand it.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132226
Chi Chun Chen [Tue, 8 Nov 2022 17:43:07 +0000 (11:43 -0600)]
[OpenMP][NFC] Unclaim iterators in 'map' clause and motion clauses
Jordan Rupprecht [Tue, 8 Nov 2022 17:04:04 +0000 (09:04 -0800)]
[NFC] Ignore unused vars in no-asserts builds
Adhemerval Zanella [Mon, 8 Aug 2022 20:35:12 +0000 (17:35 -0300)]
[clang][Headers] Only define FLT_EVAL_METHOD for C99 and later
It was reported by glibc conform test [1].
[1] https://sourceware.org/git/?p=glibc.git;a=blob;f=conform/data/float.h-data;h=
7b98fc03447b8918da4a0cf47d41fb3e17f4f791;hb=HEAD
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D137267
OCHyams [Mon, 7 Nov 2022 17:39:40 +0000 (17:39 +0000)]
[Assignment Tracking][6/*] Add trackAssignments function
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Add trackAssignments which adds assignment tracking metadata to a function for
a specified set of variables. The intended callers are the inliner and the
front end - those calls will be added in separate patches.
I've added a pass called declare-to-assign (AssignmentTrackingPass) that
converts dbg.declare intrinsics to dbg.assigns using trackAssignments so that
the function can be easily tested (see
llvm/test/DebugInfo/Generic/track-assignments.ll). The pass could also be used
by front ends to easily test out enabling assignment tracking.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132225
Aaron Ballman [Tue, 8 Nov 2022 16:50:10 +0000 (11:50 -0500)]
Fix call to utohexstr
This was passing a width but failed to pass the preceding boolean
argument for whether to use to upper or lowercase hex digits.
Amends
d19ba74dee0b9ab553bd8a6ef5b67ff349f4bf13
David Sherwood [Mon, 7 Nov 2022 16:49:59 +0000 (16:49 +0000)]
[AArch64][SVE2] Add the SVE2.1 pmov instructions
This patch adds the assembly/disassembly for the following instructions:
pmov : Move predicate to vector
pmov : Move vector to predicate
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137561
OCHyams [Mon, 7 Nov 2022 15:12:18 +0000 (15:12 +0000)]
Reapply: [NFC] Move getDebugValueLoc from static in Local.cpp to DebugInfo.h
Reverted in
b22d80dc6a6af6328d68f7b944627f9278ff6ffb.
Move getDebugValueLoc so that it can be accessed from DebugInfo.h for the
Assignment Tracking patch stack and remove redundant parameter Src.
Reviewed By: jryans
Differential Revision: https://reviews.llvm.org/D132357
Alexander Kornienko [Tue, 8 Nov 2022 13:03:19 +0000 (14:03 +0100)]
Revert "[clang] Instantiate alias templates with sugar"
This reverts commit
279fe6281d2ca5b2318c7437316c28750feaac8d, which causes
non-linear compilation time growth. See https://reviews.llvm.org/D136565#3914755
Alexey Bataev [Tue, 8 Nov 2022 14:16:30 +0000 (06:16 -0800)]
[SLP]Fix PR58863: Mask index beyond mask size for non-power-2 insertelement analysis.
Need to check if the insertelement mask size is reached during cost analysis to avoid compiler crash.
Differential Revision: https://reviews.llvm.org/D137639
skc7 [Tue, 8 Nov 2022 08:07:12 +0000 (13:37 +0530)]
Reapply "[SLP] Extend reordering data of tree entry to support PHInodes".
Reapplies 87a2086 (which was reverted in 656f1d8).
Fix for scalable vectors in getInsertIndex merged in 46d53f4.
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D137537
Kadir Cetinkaya [Mon, 29 Aug 2022 08:34:01 +0000 (10:34 +0200)]
[Includecleaner] Introduce RefType to ast walking
RefTypes are distinct categories for each reference to a symbol. They
are signals indicating strength of a reference, that'll enable different
decision making based on the finding being provided.
There are 3 kinds of ref types:
- Explicit, the reference is spelled in the code.
- Implicit, the reference is not directly visible in the code.
- Ambigious, the reference exists but can't be proven as used (e.g.
overloads brought in by a using decl but not used by the code).
Differential Revision: https://reviews.llvm.org/D135859
OCHyams [Mon, 7 Nov 2022 12:33:23 +0000 (12:33 +0000)]
Reapply: Fix warning: comparison of integers of different signs
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/36/builds/26925
Review & commit:
https://reviews.llvm.org/D132224
https://reviews.llvm.org/rG171f7024cc82e8702abebdedb699d37b50574be7
chenglin.bi [Tue, 8 Nov 2022 15:00:14 +0000 (23:00 +0800)]
Revert "[AArch64] Precommit test for D137069; NFC"
This reverts commit
281f2134a730f147428d75c09a28f0c5e1be95d9.
OCHyams [Mon, 7 Nov 2022 11:56:36 +0000 (11:56 +0000)]
Reapply [Assignment Tracking][5/*] Add core infrastructure for instruction reference
Previously reverted in
41f5a0004e442ae71c8e754fdadb4bd1e172fb2d. Fold in
D133576 previously reverted in
d29d5ffb6332569e85d5eda5130603bbd8664635.
---
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Overview
It's possible to find intrinsics linked to an instruction by looking at the
MetadataAsValue uses of the attached DIAssignID. That covers instruction ->
intrinsic(s) lookup. Add a global DIAssignID -> instruction(s) map which gives
us the ability to perform intrinsic -> instruction(s) lookup. Add plumbing to
keep the map up to date through optimisations and add utility functions
including two that perform those lookups. Finally, add a unittest.
Details
In llvm/lib/IR/LLVMContextImpl.h add AssignmentIDToInstrs which maps DIAssignID
* attachments to Instruction *s. Because the DIAssignID * is the key we can't
use a TrackingMDNodeRef for it, and therefore cannot easily update the mapping
when a temporary DIAssignID is replaced.
Temporary DIAssignID's are only used in IR parsing to deal with metadata
forward references. Update llvm/lib/AsmParser/LLParser.cpp to avoid using
temporary DIAssignID's for attachments.
In llvm/lib/IR/Metadata.cpp add Instruction::updateDIAssignIDMapping which is
called to remove or add an entry (or both) to AssignmentIDToInstrs. Call this
from Instruction::setMetadata and add a call to setMetadata in Intruction's
dtor that explicitly unsets the DIAssignID so that the mappging gets updated.
In llvm/lib/IR/DebugInfo.cpp and DebugInfo.h add utility functions:
getAssignmentInsts(const DbgAssignIntrinsic *DAI)
getAssignmentMarkers(const Instruction *Inst)
RAUW(DIAssignID *Old, DIAssignID *New)
deleteAll(Function *F)
deleteAssignmentMarkers(const Instruction *Inst)
These core utils are tested in llvm/unittests/IR/DebugInfoTest.cpp.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132224
Simon Pilgrim [Tue, 8 Nov 2022 14:35:30 +0000 (14:35 +0000)]
[X86] CVTTSS2SI64rm has the same scheduler def as (V)CVTSS2SI64rm
None of Haswell/Broadwell/Skylake/Icelake treat CVTTSS2SI64rm differently from CVTSS2SI64rm (or the AVX variants)
Confirmed with Agner, uops.info and Intel AoM
Rageking8 [Tue, 8 Nov 2022 14:28:25 +0000 (15:28 +0100)]
Fix dupe word typos
This revision fixes typos where there are 2 consecutive words which are duplicated.
There should be no code changes in this revision (only changes to comments and docs).
Do let me know if there are any undesirable changes in this revision. Thanks.
Sam McCall [Wed, 26 Oct 2022 00:21:06 +0000 (02:21 +0200)]
[include-cleaner] Record main-file macro occurences and includes
The occurrences are roots for finding used headers, like walkAST.
Includes are the targets we're matching used headers against.
Differential Revision: https://reviews.llvm.org/D136723
Nathan James [Tue, 8 Nov 2022 14:15:04 +0000 (14:15 +0000)]
Reland "[llvm][NFC] Use c++17 style variable type traits"
This reverts commit
632a389f96355cbe7ed8fa7b8d2ed6267c92457c.
This relands commit
1834a310d060d55748ca38d4ae0482864c2047d8.
Differential Revision: https://reviews.llvm.org/D137493
chenglin.bi [Tue, 8 Nov 2022 14:13:42 +0000 (22:13 +0800)]
[AArch64] Precommit test for D137069; NFC
Sanjay Patel [Mon, 7 Nov 2022 17:39:32 +0000 (12:39 -0500)]
[VectorCombine] add test with addrspacecast; NFC
D137341
Alvin Wong [Fri, 4 Nov 2022 22:22:50 +0000 (00:22 +0200)]
[OpenMP][mingw] Fix build for aarch64 target
This patch changes AArch64 + `__GNUC__` to use `__sync` builtins to
implement internal atomic macros just like for Unix, because mingw-w64
is missing some of the intrinsics which the MSVC codepath is using.
Then some remaining intel-only functions are removed from dllexport to
fix linking.
This should fix https://github.com/llvm/llvm-project/issues/56349.
Reviewed By: natgla
Differential Revision: https://reviews.llvm.org/D137168
Jakob Johnson [Sun, 6 Nov 2022 22:32:18 +0000 (14:32 -0800)]
[NFC][intelpt] Improve IntelPT trace bundle documentation
Mention that the LLVM/clang triple must be provided if the trace will be
consumed via `SBTraceCursor`
Test Plan:
Differential Revision: https://reviews.llvm.org/D137509
Nathan James [Tue, 8 Nov 2022 13:11:10 +0000 (13:11 +0000)]
Revert "[llvm][NFC] Use c++17 style variable type traits"
This reverts commit
1834a310d060d55748ca38d4ae0482864c2047d8.
skc7 [Mon, 7 Nov 2022 15:58:03 +0000 (21:28 +0530)]
[SLP][NFC] Restructure getInsertIndex
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D137567
Caroline Concatto [Tue, 8 Nov 2022 12:02:04 +0000 (12:02 +0000)]
[AArch64]SME2 Single and Multi vector Shift and Multiply instructions
This patch adds the assembly/disassembly for the following instructions:
SQRSHR (four registers): Multi-vector signed saturating rounding shift right narrow by immediate.
(two registers): Multi-vector signed saturating rounding shift right narrow by immediate.
SQRSHRN: Multi-vector signed saturating rounding shift right narrow by immediate and interleave.
SQRSHRU (four registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
(two registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
SQRSHRUN: Multi-vector signed saturating rounding shift right unsigned narrow by immediate and interleave.
UQRSHR (four registers): Multi-vector unsigned saturating rounding shift right narrow by immediate
(two registers): Multi-vector unsigned saturating rounding shift right narrow by immediate.
UQRSHRN: Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D136150
Johannes Reifferscheid [Tue, 8 Nov 2022 12:24:08 +0000 (13:24 +0100)]
Fix build file for PDLL tests.
Nathan James [Tue, 8 Nov 2022 12:22:50 +0000 (12:22 +0000)]
[llvm][NFC] Use c++17 style variable type traits
This was done as a test for D137302 and it makes sense to push these changes
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D137493
Rageking8 [Tue, 8 Nov 2022 12:21:23 +0000 (07:21 -0500)]
Fix duplicate word typos; NFC
This revision fixes typos where there are 2 consecutive words which are
duplicated. There should be no code changes in this revision (only
changes to comments and docs). Do let me know if there are any
undesirable changes in this revision. Thanks.