Sergey Kachkov [Wed, 25 Jan 2023 13:10:29 +0000 (16:10 +0300)]
[GVN] Support address translation through select instructions
Process cases when phi incoming in predecessor block has select
instruction, and this select address is unavailable, but there
are addresses translated from both sides of select instruction.
Differential Revision: https://reviews.llvm.org/D142705
Christian Ulmann [Mon, 27 Feb 2023 08:49:06 +0000 (09:49 +0100)]
[mlir][llvm] Stop exporting empty debug MD strings
This commit ensures that no empty debug metadata strings are exported as
these are not legal names. Additionally, this commit ensures that
non-existing strings are not accidentially imported as empty strings.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D144263
Diana Picus [Thu, 23 Feb 2023 12:01:02 +0000 (13:01 +0100)]
[AMDGPU] Run update scripts on existing tests. NFC
Update a few tests where the checks aren't exactly kosher.
Differential Revision: https://reviews.llvm.org/D144639
Christian Ulmann [Mon, 27 Feb 2023 08:31:48 +0000 (09:31 +0100)]
[mlir][llvm] Builders dont access null attr (NFC)
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D144267
Matthias Springer [Mon, 27 Feb 2023 08:35:37 +0000 (09:35 +0100)]
[mlir][SCF] Fix incorrect API usage in RewritePatterns
Incorrect API usage was detected by D144552.
Differential Revision: https://reviews.llvm.org/D144636
Jean Perier [Mon, 27 Feb 2023 08:05:11 +0000 (09:05 +0100)]
[flang][hlfir] Lower associate construct to HLFIR
- always use genExprAddr when lowering to HLFIR: it does not create
temporary for array sections without vector subscripts, so there is
no need to have custom logic.
- update mangling to deal with AssocDetailsEntity. Their name is
required in HLFIR so that it can be added to the hlfir.declare
that is created for the selector once it is lowered. This should
allow getting debug info for selector when debug info are generated
from hlfir.declare.
The rest of associate construct lowering is unchanged and shared with
the current lowering.
This patch also enables select type lowering to work properly, but some
other todos (mainly about parent component references) prevents porting
the tests for now, so this will be done later.
Differential Revision: https://reviews.llvm.org/D144740
Jean Perier [Mon, 27 Feb 2023 08:04:20 +0000 (09:04 +0100)]
[flang][hlfir] Lower allocatable assignment to HLFIR
Nothing much to do except set the right attributes on hlfir.assign.
Differential Revision: https://reviews.llvm.org/D144727
Jean Perier [Mon, 27 Feb 2023 08:03:09 +0000 (09:03 +0100)]
[flang][hlfir] add allocatable assignment semantic to hlfir.assign
Differential Revision: https://reviews.llvm.org/D144723
Nilanjana Basu [Sat, 11 Feb 2023 05:34:43 +0000 (21:34 -0800)]
[AArch64] Added tests for inserting scalar result of uaddlv neon instrinsic function into a vector
Inserting scalar result of 'uaddlv' neon intrinsic function to a destination vector currently makes use of the integer unit. Subsequent patches will eliminate the redundant use of the integer registers in a more generic way that will include this special case. This is an initial set of tests for this functionality.
Differential Revision: https://reviews.llvm.org/D143038
Lei Zhang [Mon, 27 Feb 2023 06:22:56 +0000 (06:22 +0000)]
[mlir][spirv] Fix Physical32/Physical64 support for OpenCL
We use `use64bitIndex` in the option to decide the target device
address bitwidth. This makes it consistent with index type
conversion too.
Reviewed By: kuhar
Differential Revision: https://reviews.llvm.org/D144827
Lei Zhang [Mon, 27 Feb 2023 06:15:18 +0000 (06:15 +0000)]
[mlir][spirv] Respect client API requirements for 64-bit index
Vulkan requires GPU processor ID/count builtin variables to be
32-bit scalar or vector for all the cases. Similarly there
are special requirements for OpenCL. We need to make sure those
rules are respected when converting using 64bit for index.
Reviewed By: kuhar
Differential Revision: https://reviews.llvm.org/D144819
Rahul Kayaith [Sat, 25 Feb 2023 08:51:31 +0000 (03:51 -0500)]
[mlir][python] Don't emit diagnostics when printing invalid ops
The asm printer grew the ability to automatically fall back to the
generic format for invalid ops, so this logic doesn't need to be in the
bindings anymore. The printer already handles supressing diagnostics
that get emitted while checking if the op is valid.
Reviewed By: mehdi_amini, stellaraccident
Differential Revision: https://reviews.llvm.org/D144805
Jun Zhang [Mon, 27 Feb 2023 04:22:18 +0000 (12:22 +0800)]
Precommit test for D144777, NFC
Signed-off-by: Jun Zhang <jun@junz.org>
Serge Pavlov [Mon, 27 Feb 2023 04:19:20 +0000 (11:19 +0700)]
[Clang] Copy strictfp attribute from pattern to instantiation
If a template function contained a pragma that made it strictfp, code
generation for such function crashed, because the instantiation did not
have strictfp attribute. As a solution this attribute is copied from the
template to instantiation.
Differential Revision: https://reviews.llvm.org/D143919
Craig Topper [Mon, 27 Feb 2023 03:36:34 +0000 (19:36 -0800)]
[TableGen] Use raw_svector_ostream and ListSeparator to simplify some code. NFC
Jie Fu [Mon, 27 Feb 2023 02:17:27 +0000 (10:17 +0800)]
[X86][MC] Fix -Wimplicit-fallthrough in X86MCCodeEmitter.cpp (NFC)
/data/llvm-project/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:1200:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
case X86II::RawFrm:
^
Shengchen Kan [Sat, 25 Feb 2023 05:57:34 +0000 (13:57 +0800)]
[X86][MC] Assert unexpected form in emitREXPrefix, NFCI
1. Add a variable `HasRegOp` to record if the instruction has a register operand
2. Enumerate all the formats with a register operand in the switch
2. Add a default (unreachable) label in the switch (suggested by @reames)
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D144776
Craig Topper [Mon, 27 Feb 2023 00:32:25 +0000 (16:32 -0800)]
[TableGen] Remove duplicate call to getPredicateCheck. NFC
Amara Emerson [Sun, 26 Feb 2023 23:42:57 +0000 (15:42 -0800)]
[GlobalISel] Fix an assertion failure in matchHoistLogicOpWithSameOpcodeHands().
We use this combine in the AArch64 postlegalizer combiner, which causes this
function to query the legalizer rules for the action for an invalid opcode/type
combination (G_AND and p0). Moving the legalizer query until after the validity
check in matchHoistLogicOpWithSameOpcodeHands() fixes this.
isuckatcs [Fri, 7 Oct 2022 22:23:33 +0000 (00:23 +0200)]
[clang-tidy] handle exceptions properly in `ExceptionAnalyzer`
This patch implements the exception handling rules found in
N4849 14.4 and as a result fixes many false positives in
the bugprone-exception-escape checker.
Differential Revision: https://reviews.llvm.org/D135495
Lei Zhang [Sun, 26 Feb 2023 21:23:07 +0000 (21:23 +0000)]
[mlir] NFC: Prepare GPUToSPIRV tests for supporting 64bit index
This commit just adds options to control index type bitwidth in
GPUToSPIRV conversion, and updates tests to prepare for 64bit
index conversion.
Reviewed By: kuhar
Differential Revision: https://reviews.llvm.org/D144826
LLVM GN Syncbot [Sun, 26 Feb 2023 21:40:55 +0000 (21:40 +0000)]
[gn build] Port
ff93c9beefd4
Nico Weber [Sun, 26 Feb 2023 21:40:09 +0000 (16:40 -0500)]
Alex Bradbury [Sun, 26 Feb 2023 19:17:06 +0000 (19:17 +0000)]
[WebAssembly][test] Clean up ir-locals.ll after opaque pointer conversion
The `tyname_cell` definitions at the top are now all the same, so
replace them with a single `alloca_cell` type.
Alex Bradbury [Sun, 26 Feb 2023 19:12:36 +0000 (19:12 +0000)]
[Webassembly][test] Regenerate ir-locals.ll using update_llc_test_checks.py
Preparation for further additions.
Alexey Lapshin [Sun, 26 Feb 2023 17:57:50 +0000 (18:57 +0100)]
[DWARFLinker][DWARFv5] Add support for .debug_rnglists.
This patch adds support of DWARFv5 .debug_rnglists table.
As DWARFLinker resolves relocations, it is able to always
use DW_FORM_addr instead of DW_FORM_addrx. DW_FORM_addrx
helps to minimize number of relocations, it is also used for
split DWARF. Both of these cases are not relevant for the
DWARFLinker. Thus, this patch converts all DW_FORM_addrx
forms into the DW_FORM_addr. And, as the result, it converts
range lists of DW_FORM_rnglistx form into the DW_FORM_sec_offset.
For the --update case all DW_FORM_addrx, DW_FORM_rnglistx
are preserved as is.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D143903
Noah Goldstein [Sun, 26 Feb 2023 17:25:59 +0000 (11:25 -0600)]
Add additional operations that masked instructions can combine with
Added: OR, SMAX, SMIN, UMAX, UMIN, ABS, SHL, SRL, SRA, MUL
Intentionally not generically using TLI.isBinOp as that causes
regressions as there are many binops that cannot combine with masked
instructions.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D143860
Noah Goldstein [Thu, 16 Feb 2023 17:57:39 +0000 (11:57 -0600)]
Add tests for combining mask with shuffles; NFC
Differential Revision: https://reviews.llvm.org/D144144
Noah Goldstein [Thu, 16 Feb 2023 17:57:31 +0000 (11:57 -0600)]
Widen i16 shuffle masks if vector width < 512 even with BWI
`{v}blend{d|ps|pd}` is preferable to `{v}blendw` so widen so that we
can match it.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D143789
Noah Goldstein [Thu, 16 Feb 2023 17:57:23 +0000 (11:57 -0600)]
Add more tests for promoting `blendw` -> `blendd`; NFC
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D143788
Simon Pilgrim [Sun, 26 Feb 2023 18:01:05 +0000 (18:01 +0000)]
[X86] Add additional uses tests for select(icmp(x,y),sub(x,y),sub(y,x)) -> abd(x,y) patterns
William S. Moses [Tue, 14 Feb 2023 23:36:07 +0000 (18:36 -0500)]
[LICM] Ensure LICM can hoist invariant.group
Invariant.group's are not sufficiently handled by LICM. Specifically,
if a given invariant.group loaded pointer is not overwritten between
the start of a loop, and its use in the load, it can be hoisted.
The invariant.group (on an already invariant pointer operand) ensures
the result is the same. If it is not overwritten between the start
of the loop and the load, it is therefore legal to hoist.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D144053
zhongyunde [Sun, 26 Feb 2023 17:21:24 +0000 (01:21 +0800)]
[MergeICmps] Adapt to non-eq comparisons, retry
Fix https://github.com/llvm/llvm-project/issues/59740.
NOTE: retry as we can't reproduce the break locally when first commit.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D141188
Simon Pilgrim [Sun, 26 Feb 2023 17:05:46 +0000 (17:05 +0000)]
[X86] Add vector test coverage for select(icmp(x,y),sub(x,y),sub(y,x)) -> abd(x,y) patterns
Simon Pilgrim [Sun, 26 Feb 2023 16:45:18 +0000 (16:45 +0000)]
[X86] Add scalar test coverage for select(icmp(x,y),sub(x,y),sub(y,x)) -> abd(x,y) patterns
Brad Smith [Sun, 26 Feb 2023 15:45:00 +0000 (10:45 -0500)]
[Driver][OpenBSD] Simplify command-line option handling. NFC
Simon Pilgrim [Sun, 26 Feb 2023 15:43:03 +0000 (15:43 +0000)]
[TextAPI] Use const auto& in foreach loop to avoid pass-by-value static analyzer warnings. NFCI.
Simon Pilgrim [Sun, 26 Feb 2023 15:31:58 +0000 (15:31 +0000)]
[X86] Add test showing poor bitselect between constants on BMI targets
bitselect(52,-6553,m) -> xor(and(xor(52,-6553),m),52) folds much better than or(and(52,not(m)),and(-6553,m))
Sanjay Patel [Fri, 24 Feb 2023 17:05:14 +0000 (12:05 -0500)]
[InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC
Simon Pilgrim [Sun, 26 Feb 2023 15:19:46 +0000 (15:19 +0000)]
[X86] Add PR46472 bitselect test coverage
As noted on Issue #45817 we didn't have scalar coverage for this
Piotr Zegar [Sun, 26 Feb 2023 14:54:36 +0000 (14:54 +0000)]
[clang-tidy] Improved too-small-loop-variable with bit-field support
Implemented support for bit-field members as a loop variable
or upper limit. Supporting also non bit-field integer members.
Fixes issues: https://github.com/llvm/llvm-project/issues/58614
Reviewed By: carlosgalvezp
Differential Revision: https://reviews.llvm.org/D142587
Mehdi Amini [Sat, 25 Feb 2023 03:43:20 +0000 (20:43 -0700)]
[mlir-opt] Rename internally the variables backing --no-implicit-module to ExplicitModule (NFC)
The flag name isn't the best: avoiding negative is in general more readable
and conveys the intent better.
Simon Pilgrim [Sun, 26 Feb 2023 14:00:22 +0000 (14:00 +0000)]
[X86] Add i686 and fast/slow-inc test coverage to constant select tests
Extend tests for D144449 to ensure we aren't regressing code on targets with a slow INC/DEC instruction (or i686 without CMOV)
Roy Jacobson [Sun, 12 Feb 2023 19:17:00 +0000 (21:17 +0200)]
[clang-tidy] Tweak 'rule of 3/5' checks to allow defaulting a destructor outside the class.
A somewhat common code-pattern is to default a destructor in the source file and not in the header.
For example, this is the way to use smart pointers with forward-declared classes:
```c++
struct Impl;
struct A {
~A(); // Can't be defaulted in the header.
private:
std::unique_ptr<Impl> impl;
};
```
To be able to use this check with this pattern, I modified the behavior with `AllowSoleDefaultDtor`
to not trigger on destructors if they aren't defined yet.
Since a declared destructor should still be defined somewhere in the program, this
won't miss bad classes, just diagnose on less translation units.
Reviewed By: carlosgalvezp
Differential Revision: https://reviews.llvm.org/D143851
Mark de Wever [Sat, 25 Feb 2023 14:24:58 +0000 (15:24 +0100)]
[libc++] Improves clang-tidy configuration.
The current clang-tidy settings work in the CI but not on all systems
outside the CI.
- The range 16...17 doesn't work when only clang-17 is installed.
- Running CMake a second time will fail.
This addresses these issues.
Reviewed By: philnik, #libc
Differential Revision: https://reviews.llvm.org/D144785
Younan Zhang [Wed, 15 Feb 2023 06:48:24 +0000 (14:48 +0800)]
[clangd] Hide inlay hints when using a macro as a calling argument that with a param comment
We don't want to produce inlay hints for arguments for which
user has left param name comments. But we're not decomposing
location of the parameter correctly at the moment because the
location we've passed into `SM.getDecomposedLoc` is not always
FileID.
Fixes clangd/clangd#1495
Reviewed By: nridge
Differential Revision: https://reviews.llvm.org/D144074
Simon Pilgrim [Sun, 26 Feb 2023 10:40:43 +0000 (10:40 +0000)]
[X86] Fix ambiguous operator ordering to stop -Wparentheses warning. NFCI.
Valentin Clement [Sun, 26 Feb 2023 09:44:19 +0000 (10:44 +0100)]
[flang] Do not initialize intent(out) polymorphic pointer or allocatable
Calling the runtime on disassociated pointer or unallocated
allocatable will trigger a segfault.
Reviewed By: PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D144752
Piotr Zegar [Sun, 26 Feb 2023 08:58:03 +0000 (08:58 +0000)]
[clang-tidy] Fix bugprone-copy-constructor-init documentation
Correct example, and add information about limitations.
Fixes: https://github.com/llvm/llvm-project/issues/55572
Reviewed By: carlosgalvezp
Differential Revision: https://reviews.llvm.org/D144594
Alexis Murzeau [Sun, 26 Feb 2023 08:05:54 +0000 (08:05 +0000)]
[clang-tidy] readability-identifier-naming.HungarianNotation: rename CharPrinter to CharPointer
The CharPrinter is a typo and should have been named CharPointer as it
configures the hungarian notation prefix for char pointers (char*).
As all configuration options within
readability-identifier-naming.HungarianNotation.CString.* were not read
at all in the previous clang-tidy version (fixed in D144431), this option
rename won't break existing users.
A note in release notes is added to let users know these options were
renamed.
Reviewed By: carlosgalvezp
Differential Revision: https://reviews.llvm.org/D144790
Kazu Hirata [Sun, 26 Feb 2023 07:33:50 +0000 (23:33 -0800)]
[X86] Precommit a test
This patch precommits a test for:
https://github.com/llvm/llvm-project/issues/60374
Craig Topper [Sun, 26 Feb 2023 04:07:41 +0000 (20:07 -0800)]
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
Brad Smith [Sun, 26 Feb 2023 01:33:36 +0000 (20:33 -0500)]
[Driver][FreeBSD] Further simplify the Driver handling for older FreeBSD releases
Since GCC 4.2 was removed with 10.0 and newer the respective Driver bits can be removed.
Reviewed By: dim
Differential Revision: https://reviews.llvm.org/D144778
Mehdi Amini [Sat, 25 Feb 2023 22:04:08 +0000 (17:04 -0500)]
Refactor a MlirOptMainConfig class to hold the configuration of MlirOptMain (NFC)
The list of boolean flags and others is becoming unresonnably long.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D143829
Simon Pilgrim [Sat, 25 Feb 2023 21:27:57 +0000 (21:27 +0000)]
[ScalarEvolution] Fix unused variable warnings. NFC.
Replace dyn_cast<> with isa<> as we don't actually need the variable
Simon Pilgrim [Sat, 25 Feb 2023 21:12:32 +0000 (21:12 +0000)]
[AArch64] Add coverage for select(icmp(x,y),sub(x,y),sub(y,x)) -> abd(x,y) patterns
Simon Pilgrim [Sat, 25 Feb 2023 21:04:16 +0000 (21:04 +0000)]
[PowerPC] Add coverage for select(icmp_sgt(x,y),sub(x,y),sub(y,x)) -> abds(x,y) patterns
Simon Pilgrim [Sat, 25 Feb 2023 20:06:19 +0000 (20:06 +0000)]
[PowerPC] Replace PPCISD::VABSD cases with generic ISD::ABDU(X,Y) node
A move towards using the generic ISD::ABDU nodes on more backends
Also support ISD::ABDS for v4i32 types using the existing signbit flip trick
PowerPC has a select(icmp_ugt(x,y),sub(x,y),sub(y,x)) -> abdu(x,y) combine that I intend to move to DAGCombiner in a future patch.
The ABS(SUB(X,Y)) -> PPCISD::VABSD(X,Y,1) v4i32 combine wasn't legal (https://alive2.llvm.org/ce/z/jc2hLU) - so I've removed it, having already added the legal sub nsw tests equivalent.
Differential Revision: https://reviews.llvm.org/D142313
Craig Topper [Sat, 25 Feb 2023 19:22:28 +0000 (11:22 -0800)]
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
To do this we need to remove the always matching behavior from condop.
This requires us to add more 'select' isel patterns with a bare GPR
as the condition.
Rename condop/invcondop to riscv_setne/riscv_seteq.
This centralizes the ADDI/XORI/XOR tricks into one place.
Simon Pilgrim [Sat, 25 Feb 2023 19:51:46 +0000 (19:51 +0000)]
[PPC] Fix abs(sub(x,y)) -> abs(x,y) tests
As detailed on D142313, this fold should be restricted by sub nsw
Craig Topper [Sat, 25 Feb 2023 18:39:57 +0000 (10:39 -0800)]
[RISCV] Add a check for integer setcc to RISCVDAGToDAGISel::selectCondOp
Piotr Zegar [Sat, 25 Feb 2023 16:07:04 +0000 (16:07 +0000)]
[clang-tidy] Fix false-positive in readability-container-size-empty
Ignoring std::array type when matching 'std:array == std::array()'.
In such case we shouldn't propose to use empty().
Fixes: https://github.com/llvm/llvm-project/issues/48286
Differential Revision: https://reviews.llvm.org/D144217
Craig Topper [Sat, 25 Feb 2023 18:07:26 +0000 (10:07 -0800)]
[RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size.
Craig Topper [Sat, 25 Feb 2023 17:57:57 +0000 (09:57 -0800)]
[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.
HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.
By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.
Nikolas Klauser [Sat, 25 Feb 2023 09:26:28 +0000 (10:26 +0100)]
[libc++] Add FTM for views::as_rvalue
`views::as_rvalue` was implemented in D137637, but we forgot to set the feature test macro.
Fixes #60986.
Reviewed By: Mordante, #libc
Spies: libcxx-commits, arichardson
Differential Revision: https://reviews.llvm.org/D144781
Sebastian Pop [Sat, 18 Feb 2023 01:12:33 +0000 (01:12 +0000)]
[BOLT] fix tests on arm64
The two tests were failing on arm64-linux with:
BOLT-ERROR: invalid target 'x86-64'.
Differential Revision: https://reviews.llvm.org/D144593
Aaron Ballman [Sat, 25 Feb 2023 16:04:54 +0000 (11:04 -0500)]
Remove WG14 N2829 from the C status page; NFC
This paper is about changes to the assert macro, but assert.h is not
provided by the compiler, so there's no work for Clang to do to support
this feature.
Igor Zhukov [Sat, 25 Feb 2023 14:43:37 +0000 (21:43 +0700)]
[libc++] Implement LWG-3204: `sub_match::swap` only swaps the base class
Reviewed By: Mordante, JMazurkiewicz, #libc
Differential Revision: https://reviews.llvm.org/D144629
Aaron Ballman [Sat, 25 Feb 2023 14:27:46 +0000 (09:27 -0500)]
[C2x] Implement support for revised spelling of keywords
This implements WG14 N2934
(https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2934.pdf), which
adds keywords for alignas, alignof, bool, static_assert, and
thread_local in C, as aliases for _Alignas, _Alignof, _Bool,
_Static_assert, and _Thread_local. We already supported the keywords in
C2x mode, but this completes support by adding pre-C2x compat warnings
and updates the stdalign.h header in freestanding mode.
Luo, Yuanke [Thu, 23 Feb 2023 09:02:18 +0000 (17:02 +0800)]
[X86] Fix the base pointer save/restore bug
Previous the stack slot for spilling base pointer register is allocated
after the stack realignment. When the stack is naturally aligned the
stack slot is share with other data that allocated from stack and cause
data corrupt. Another issue is the stack slot for save/restore the
callee saved register is not fixed for each function. It depends on the
register usage of them in each function.
This patch is to recalculate the offset the stack slot for base pointer
register during the prolog/epilog insert pass, and allocate the stack
slot when spilling callee saved registers.
Differential Revision: https://reviews.llvm.org/D144625
DianQK [Sat, 25 Feb 2023 11:42:58 +0000 (19:42 +0800)]
[SimplifyCFG] Improve the precision of `PtrValueMayBeModified`
The result value of `getelementptr inbounds (TY, null, not zero)` is a poison value. We can think of it as undefined behavior.
> Please let me know if there is anything I don't understand correctly.
Reviewed By: nikic, xbolva00
Differential Revision: https://reviews.llvm.org/D144563
Kiran Chandramohan [Sat, 25 Feb 2023 11:38:57 +0000 (11:38 +0000)]
[Flang][OpenMP] NFC: Remove omp prefix of test files in OpenMP Lower
For tests in the OpenMP sub-directory the `omp` prefix is removed.
Kiran Chandramohan [Sat, 25 Feb 2023 11:09:44 +0000 (11:09 +0000)]
[Flang][OpenMP] NFC: Remove omp prefix of test files in OpenMP Semantics
For tests in the OpenMP sub-directory the `omp` prefix is removed.
Kiran Chandramohan [Sat, 25 Feb 2023 10:49:47 +0000 (10:49 +0000)]
[Flang][OpenMP] NFC: Move OpenMP parser tests to a sub-directory
Now that the test files are in the OpenMP subdirectory, remove the
`omp` prefix.
Emilia Dreamer [Sat, 25 Feb 2023 10:19:13 +0000 (12:19 +0200)]
[clang-format] Don't move qualifiers past pointers-to-member
Previously, given a pointer-to-member type such as `Foo const Bar::*`,
clang-format would see the `const Bar::` part as a regular type name
with scope resolution operators, and with `QualifierAlignment: Right` it
would attempt to "fix" it, resulting in `Foo Bar::const *`, a syntax
error.
This patch no longer allows qualifiers to be moved across `::*`.
Fixes https://github.com/llvm/llvm-project/issues/60898
Reviewed By: owenpan, MyDeveloperDay, HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D144537
Emilia Dreamer [Sat, 25 Feb 2023 10:13:27 +0000 (12:13 +0200)]
[clang-format] Rewrite how indent is reduced for compacted namespaces
The previous version set the indentation directly using IndentForLevel,
however, this has a few caveats, namely:
* IndentForLevel applies to all scopes of the entire program being
formatted, but this indentation should only be adjusted for scopes
of namespaces.
* The method it used only set the correct indent amount if one wasn't
already set for a given level, meaning it didn't work correctly if
anything with indentation preceded a namespace keyword. This
includes preprocessing directives if using IndentPPDirectives.
This patch instead reduces the Level of all lines within namespaces
which are compacted by CompactNamespaces. This means they will get
correct indentation using the normal process.
Fixes https://github.com/llvm/llvm-project/issues/60843
Reviewed By: owenpan, MyDeveloperDay, HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D144296
Craig Topper [Sat, 25 Feb 2023 08:53:30 +0000 (00:53 -0800)]
Revert "foo"
This reverts commit
f07bb0012e76495d50b34fe50fe7d41a70c8685b.
Failed to squash this commit
Craig Topper [Sat, 25 Feb 2023 08:53:08 +0000 (00:53 -0800)]
Revert "[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size."
This reverts commit
7910ed1d56c349b76c82d5ebe2f2590770955ff5.
Accidentally failed to squash a commit
Craig Topper [Sat, 25 Feb 2023 08:40:09 +0000 (00:40 -0800)]
[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.
HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.
By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.
Craig Topper [Sat, 25 Feb 2023 08:32:13 +0000 (00:32 -0800)]
foo
Craig Topper [Sat, 25 Feb 2023 08:16:33 +0000 (00:16 -0800)]
[RISCV] Combine some duplicate XTHeadFMemIdx patterns. NFC
We had identical patterns for TH_FLRW, TH_FSRW, TH_FLRD, and TH_FSRD
under both IsRV32 and IsRV64.
Alex Bradbury [Sat, 25 Feb 2023 06:17:40 +0000 (06:17 +0000)]
[lld][RISCV] Avoid error when encountering unrecognised ISA extensions/versions in RISC-V attributes
This patch follows on from this RFC thread
<https://discourse.llvm.org/t/rfc-resolving-issues-related-to-extension-versioning-in-risc-v/68472/>
and the ensuing discussion in the RISC-V LLVM sync-up call. The
consensus agreed that the behaviour change in LLD introduced in D138550
that results in object files including arch attributes with unrecognised
extensions or versions of extensions is a regression and should be
treated as such. As it stands, this logic means that LLD will error out
if trying to link a RISC-V object file from LLVM HEAD (rv32i2p0/rv64i2p0)
with one from current GCC (rv32i2p1/rv64i2p1 by default).
There's a bigger discussion about exactly when to warn vs error and so
on, and how to control that, and this patch doesn't attempt to address
all those questions. It simply tries to fix the problem with a minimally
invasive change, intended to be cherry-picked for 16.0.x (ideally
16.0.0, but queued for 16.0.1 if we're too late in the release cycle).
As you can see from the test changes, although the changed logic is
mostly more permissive, it will reject some embedded arch strings that
were accepted before. Because the same logic was previously used for
parsing human-written -march as for the arch attribute (intended to be
stored in normalised form), various short-hand formats were previously
accepted. Maintaining support for such ill-formed attributes would
substantially complicate the logic, and given the previous
implementation was so much stricter in every other way, was surely a bug
rather than a design choice.
Surprisingly, the precise rules for how numbers can be embedded into
extension names isn't fully defined (there is a PR to the ISA manual
that is not yet merged
<https://github.com/riscv/riscv-isa-manual/pull/718>).
In the absence of specific criteria for rejecting extensions names that
would be ambiguous in abbreviated form,
`RISCVISAInfo::parseArchStringNormalized` just pulls out the version
information from the end of each extension description.
Differential Revision: https://reviews.llvm.org/D144353
Casey Carter [Fri, 24 Feb 2023 02:50:13 +0000 (18:50 -0800)]
[libc++][test] Silence MSVC deprecation warnings
... for implicitly-generated copy constructors and copy assignment operators.
Differential Revision: https://reviews.llvm.org/D144694
Matt Arsenault [Thu, 8 Dec 2022 03:49:27 +0000 (22:49 -0500)]
clang: Add __builtin_elementwise_fma
I didn't understand why the other builtins have promotion logic,
or how it would apply for a ternary operation. Implicit conversions
are evil to begin with, and even more so when the purpose is to get
an exact IR intrinsic. This checks all the arguments have the same type.
Mehdi Amini [Sat, 25 Feb 2023 00:37:05 +0000 (17:37 -0700)]
Add info about the "testing only" aspect of `--allow-unregistered-dialect` in the cl::opt desc (NFC)
Mehdi Amini [Sat, 25 Feb 2023 00:29:02 +0000 (17:29 -0700)]
[MLIR][doc] Clarify `allowUnregisteredDialects()` as "testing option" (NFC)
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D144615
Fangrui Song [Fri, 24 Feb 2023 23:08:24 +0000 (15:08 -0800)]
[lldb][test] Fix vCont-threads/main.cp for -std=c++11
Vitaly Buka [Thu, 20 Oct 2022 00:24:41 +0000 (17:24 -0700)]
[docs] Update compiler-rt/CODE_OWNERS.TXT
D135617 leftovers
Reviewed By: browneee, cryptoad
Differential Revision: https://reviews.llvm.org/D136308
Fangrui Song [Fri, 24 Feb 2023 22:47:55 +0000 (14:47 -0800)]
[OpenMP] Remove uses of ATOMIC_VAR_INIT
ATOMIC_VAR_INIT has a trivial definition
`#define ATOMIC_VAR_INIT(value) (value)`,
is deprecated in C17/C++20, and will be removed in newer standards in
newer GCC/Clang (e.g. https://reviews.llvm.org/D144196).
Fangrui Song [Fri, 24 Feb 2023 21:43:12 +0000 (13:43 -0800)]
Remove uses of ATOMIC_VAR_INIT
ATOMIC_VAR_INIT has a trivial definition `#define ATOMIC_VAR_INIT(value) (value)`,
is deprecated in C17/C++20, and will be removed in newer standards.
Michael Jones [Thu, 23 Feb 2023 22:52:56 +0000 (14:52 -0800)]
[libc] Clarify printf percent conversion behavior.
Almost all printf conversions ending in '%' are undefined, but they're
traditionally treated as if the complete conversion specifier is "%%".
This patch modifies the parser to more closely match that behavior.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D144679
Noah Goldstein [Fri, 24 Feb 2023 08:27:34 +0000 (02:27 -0600)]
Add transform for `(and/or (icmp eq/ne A,-1),(icmp eq/ne A,-1+C))`->`(and/or (icmp eq/ne (and ~A,-1+C),0))`
This works of `-1+C` is a negative power of 2.
This can be more useful than the `AddAnd` case as `~A` does not
necessarily require materializing a constant. This makes the transform
worth it for X86 vector types.
Alive2 Links:
EQ: https://alive2.llvm.org/ce/z/P6u8cq
NE: https://alive2.llvm.org/ce/z/_Kkqp1
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D144284
Noah Goldstein [Fri, 17 Feb 2023 03:49:06 +0000 (21:49 -0600)]
Make `(and/or (icmp eq/ne A,C0), (icmp eq/ne A,C1))` where `IsPow(dif(C0,C1))` work for more patterns.
`(and/or (icmp eq/ne A,C0), (icmp eq/ne A,C1))` can be lowered to
`(icmp eq/ne (and (sub A, (smin C0, C1)), (not (sub (smax C0, C1), (smin C0, C1)))), 0)`
generically if `(sub (smax C0, C1), (smin C0,C1))` is a power of 2.
This covers the existing case of `(and/or (icmp eq/ne A, C_Pow2),(icmp eq/ne A, -C_Pow2))`
as well as other cases.
Alive2 Links:
EQ: https://alive2.llvm.org/ce/z/mLJiUW
NE: https://alive2.llvm.org/ce/z/TKnzUr
Differential Revision: https://reviews.llvm.org/D144283
Noah Goldstein [Fri, 17 Feb 2023 17:56:55 +0000 (11:56 -0600)]
Add tests for (or/and (icmp eq/ne A, C0), (icmp eq/ne A, C1)) where IsPow2(dif(C0, C1)); NFC
Differential Revision: https://reviews.llvm.org/D144282
Noah Goldstein [Thu, 23 Feb 2023 00:36:49 +0000 (18:36 -0600)]
Add transforms for `(max/min (xor X, Pow2), X)` -> `(and/or X, Pow2/~Pow2)`
X ^ Pow2 is guranteed to flip one bit. We can use this to speedup
max/min by just selecting X with/without (or/andnot) the flipped bit
respectively.
Alive2 Links:
smax-neg: https://alive2.llvm.org/ce/z/j3QYFs
smin-neg: https://alive2.llvm.org/ce/z/bFYnQW
smax-pos: https://alive2.llvm.org/ce/z/4xYSxR
smin-pos: https://alive2.llvm.org/ce/z/H3RPKj
umax : https://alive2.llvm.org/ce/z/P4oRcX
umin : https://alive2.llvm.org/ce/z/vWZG6p
Differential Revision: https://reviews.llvm.org/D144606
Noah Goldstein [Thu, 23 Feb 2023 00:36:38 +0000 (18:36 -0600)]
Add tests for transforming `(max/min (xor X, Pow2), X)`; NFC
Differential Revision: https://reviews.llvm.org/D144605
Noah Goldstein [Thu, 16 Feb 2023 17:56:27 +0000 (11:56 -0600)]
Add tests for shuffle as shift/rotate; NFC
Differential Revision: https://reviews.llvm.org/D143857
Noah Goldstein [Thu, 16 Feb 2023 17:56:11 +0000 (11:56 -0600)]
Add Extend shuffle pattern to vNf32 shuffles.
There are some cases where its useful for float types, not quite as
hot as in the integer case, but still better than alternatives.
Differential Revision: https://reviews.llvm.org/D143785
Noah Goldstein [Thu, 16 Feb 2023 17:55:58 +0000 (11:55 -0600)]
Prioritize lowering V{4|16}F32 with blend.
Blend is often fastest available instruction so it should be higher
priority for v4f32 and an option for v16f32.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D143856
Alexey Bataev [Fri, 24 Feb 2023 00:58:01 +0000 (16:58 -0800)]
[SLP]Improve handling gathers/buildvectors with undefs.
If have just one non-undef scalar in the buildvector/gather node, we try
to put it to be the very first element, which is profitable in most
cases. Do the preliminary estimation, if this more profitable during
graph rotation and do same for all elements, including extractelements.
Differential Revision: https://reviews.llvm.org/D144689