Nico Weber [Sat, 3 Dec 2022 12:52:00 +0000 (07:52 -0500)]
[gn build] Add LoongArch target
Differential Revision: https://reviews.llvm.org/D139256
David Blaikie [Tue, 6 Dec 2022 01:15:52 +0000 (01:15 +0000)]
DebugInfo: Add/support new DW_LANG codes for recent C and C++ versions
This may be a breaking change for consumers if they're trying to detect
if code is C or C++, since it'll start using new codes that they may not
be ready to recognize, in which case they may fall back to non-C
handling.
Differential Revision: https://reviews.llvm.org/D138597
Félix Cloutier [Tue, 6 Dec 2022 21:00:12 +0000 (13:00 -0800)]
[Clang][Sema] Fix attribute((format)) bug on non-variadic functions
The [initial implementation][1] of __attribute__((format)) on non-variadic functions
accidentally only accepted one data argument. This worked:
```c
__attribute__((format(printf, 1, 2)))
void f(const char *, int);
```
but this didn't:
```c
__attribute__((format(printf, 1, 2)))
void f(const char *, int, int);
```
This is due to an oversight in changing the way diagnostics are emitted for
`attribute((format))`, and to a coincidence in the handling of the variadic case. Test
cases only covered the case that worked by coincidence.
Before the previous change, using `__attribute__((format))` on a non-variadic function at
all was an error and clang bailed out. After that change, it only generates a GCC
compatibility warning. However, as execution falls through, it hits a second diagnostic
when the first data argument is neither 0 nor the last parameter of the function.
This change updates that check to allow any parameter after the format string to be the
first data argument when the function is non-variadic. When the function is variadic, it
still needs to be the index of the `...` "parameter". Attribute documentation is updated
to reflect the change and new tests are added to verify that it works with _two_ data
parameters.
[1]: https://reviews.llvm.org/D112579
Radar-Id: rdar://
102069446
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D137603
Valentin Clement [Tue, 6 Dec 2022 21:01:14 +0000 (22:01 +0100)]
[flang] Support fir.class in scalar user defined assignment lowering
Support fir.class in genScalarUserDefinedAssignmentCall so
emboxing is done correctly.
Reviewed By: jeanPerier, PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D139435
Krzysztof Parzyszek [Mon, 5 Dec 2022 23:19:30 +0000 (15:19 -0800)]
[YAML] Convert Optional to std::optional
Amy Kwan [Tue, 6 Dec 2022 17:52:52 +0000 (11:52 -0600)]
[NFC][PowerPC] Add NFC fixes to PPCInstrinfo.cpp when getting the defined machine instruction.
This patch adds the following NFC fixes to PPCInstrInfo.cpp when getting the DefMI:
- Fix documentation error to state that we want to flag a use of register
between the def and the MI (in post-RA)
- Setting the DefMI to null if the DefMI is neither an LI or and ADDI
(while still being in SSA form).
In terms of setting the DefMI to null, this change aims to account for the
scenario of when we end up going through all operands on the machine instruction
MI and updating OpNoForForwarding accordingly once an ADDI is found as the DefMI.
It is possible that once an ADDI is found, we will continue to go through all
operands in attempts to find an LI, but end up looking at every operand until
we reach the end if we have not yet found an LI. In the case where the end is
reached and we never end up finding an LI/ADDI, DefMI would be pointing to the
last operand of MI while OpNoForForwarding would still be pointing at the
previous ADDI operand found. We reset DefMI to avoid having DefMI point to an
instruction that differs from the one represented by OpNoForForwarding.
Differential Revision: https://reviews.llvm.org/D137483
Wheest [Tue, 6 Dec 2022 20:13:20 +0000 (12:13 -0800)]
[mlir] [docs] Broken link in MLIR Toy docs
In the Ch6 of the Toy Example for MLIR, there is a broken link. If ones goes to [the page for Chapter 6](https://mlir.llvm.org/docs/Tutorials/Toy/Ch-6/), and click on the link "Conversion to the LLVM IR Dialect", one will see it takes you to a page that no longer exists.
I believe this should actually be [this link](https://mlir.llvm.org/docs/TargetLLVMIR/).
Note to reviewers that this is my first submitted patch to LLVM, and using the phabricator system, so there is a higher risk that I have made an error, and brief feedback on these patch notes would be appreciated.
Reviewer rational: Users who git blame say contributed to the tutorial.
I believe that automated tests on these markdown docs could reduce the risk of this kind of error occurring again. For example, [this Python package](https://pypi.org/project/linkcheckmd/) checks for broken markdown links. However, I am unsure where in the existing testing infrastructure this could go, I am only somewhat familiar with the C++ side.
Reviewed By: Mogball
Differential Revision: https://reviews.llvm.org/D133977
Hanhan Wang [Mon, 5 Dec 2022 23:52:35 +0000 (15:52 -0800)]
[mlir][tensor] Adapt FoldTensorCastProducerOp pattern on DPS interface.
This revision adapts the pattern in LinAlg to work on DPS interface, and
adds it to canonicalization patterns of tensor dialect. The
InsertSliceOp is skipped in the pattern because it has its own logic
about folding tensor.cast ops.
Reviewed By: pifon2a
Differential Revision: https://reviews.llvm.org/D139375
Kevin Gleason [Tue, 6 Dec 2022 19:56:53 +0000 (11:56 -0800)]
Use consistent spacing before custom directives for op and attr/type assemblyFormat.
Currently, assemblyFormat `custom<A>($a) custom<B>($b)` has different spacing
if used for Ops vs Attrs/Types. Ops insert a space if needed before the custom directive,
while attributes and types do not.
This leads to the following two patterns in attributes / types:
```
# 1. Whitespace literal
let assemblyFormat = "... ` ` custom<A>($a)"
# 2. Custom printer code includes spacing
void printB(...) {
printer << ' ' << b;
}
```
Moving this spacing into the generated code allows for some cleanup in mlir and
improves the consistency of custom directives.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D138235
Roman Lebedev [Tue, 6 Dec 2022 19:54:22 +0000 (22:54 +0300)]
[exegesis] Attempt to workaround GCC7 compiler bug
https://lab.llvm.org/staging/#/builders/235/builds/731/steps/5/logs/FAIL__Building_CXX_object_tools_llvm-exegesis_lib_
Jonas Paulsson [Tue, 6 Dec 2022 19:36:45 +0000 (13:36 -0600)]
[SystemZ] Add "REQUIRES: systemz-registered-target" on test.
The clang test that emits assembly needs this line as well.
Felipe de Azevedo Piovezan [Thu, 1 Dec 2022 18:47:10 +0000 (13:47 -0500)]
[CodeExtractor] Correctly propagate scope information post extraction
When a new function "NewF" is created with instructions extracted from
another function "OldF", the CodeExtractor only preserves debug
line/column of the extracted instructions. However:
1. Any inlinedAt nodes are dropped.
2. The scope chain is replaced with a single node, the Subprogram of NewF.
Both of these are incorrect: most of the debug metadata from the
original instructions should be preserved. We only need to update the
Subprogram found at the scope of the last node of the inline chain; this
Subprogram used to be OldF but now should be NewF.
Differential Revision: https://reviews.llvm.org/D139217
Fangrui Song [Tue, 6 Dec 2022 19:05:04 +0000 (19:05 +0000)]
[libunwind] Use .irp directives. NFC
The repeated instructions make the file long and difficult to read.
Simplify them with .irp directives.
Reviewed By: #libunwind, compnerd
Differential Revision: https://reviews.llvm.org/D139368
Adrian Prantl [Tue, 6 Dec 2022 18:54:46 +0000 (10:54 -0800)]
Add missing include
Jonas Paulsson [Mon, 28 Jun 2021 23:18:39 +0000 (18:18 -0500)]
[SystemZ] Emit a .gnu_attribute for an externally visible vector abi.
On SystemZ, the vector ABI changes depending on the presence of hardware
vector support. Therefore, each binary compiled with a visible vector ABI
(e.g. one that calls an external function with a vector argument) should be
marked with a .gnu_attribute describing this.
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D105067
David Goldman [Fri, 2 Dec 2022 15:04:51 +0000 (10:04 -0500)]
[clang][Tooling] Add support for generating #import edits
And make use of this from clangd's CodeComplete and IncludeFixer, although currently they are both restricted only to #include symbols.
Differential Revision: https://reviews.llvm.org/D128677
David Goldman [Fri, 2 Dec 2022 15:04:31 +0000 (10:04 -0500)]
[clangd] Add new IncludeDirective to IncludeHeaderWithReferences
The IncludeDirective contains both Include (the current behavior) and Import,
which we can use in the future to provide #import suggestions for
Objective-C files/symbols.
Differential Revision: https://reviews.llvm.org/D128457
Sanjay Patel [Tue, 6 Dec 2022 18:12:10 +0000 (13:12 -0500)]
[InstCombine] fold add-carry of bools to logic
((zext BoolX) + (zext BoolY)) >> 1 --> zext (BoolX && BoolY)
https://alive2.llvm.org/ce/z/LvZFKj
This was noted as a missing fold in D138814.
Sanjay Patel [Tue, 6 Dec 2022 16:53:06 +0000 (11:53 -0500)]
[InstCombine] add tests for bool math; NFC
This pattern came up in D138814.
Craig Topper [Tue, 6 Dec 2022 18:31:13 +0000 (10:31 -0800)]
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
With C extension, li with a 6 bit immediate followed by slli is 4 bytes.
The lui+addi(w) sequence is at least 6 bytes.
The two sequences probably have similar execution latency. The exception
being if the target supports lui+addi(w) macrofusion.
Since the execution latency is probably the same I didn't restrict
this to C extension.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D139135
Mircea Trofin [Tue, 6 Dec 2022 18:21:13 +0000 (10:21 -0800)]
Reapply "[mlgo] Dependency-free training mode logger"
This reverts commit
8abe7b11f74bea63d3134c144137b72146da0c7b.
Added the missing cast which was causing a build problem on certain compilers.
Peter Rong [Sat, 3 Dec 2022 01:06:40 +0000 (17:06 -0800)]
[ARM] IselLowering unsigned overflow to crash using APInt in PerformSHLSimplify
This diff fixes issue https://github.com/llvm/llvm-project/issues/59317
We should check if bitwidth is lower than the shift amount before we subtract them to avoid unsigned overflow.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D139238
Krzysztof Parzyszek [Tue, 6 Dec 2022 17:53:37 +0000 (09:53 -0800)]
Process: convert Optional to std::optional
This applies to GetEnv and FindInEnvPath.
Roman Lebedev [Tue, 6 Dec 2022 17:47:20 +0000 (20:47 +0300)]
Revert "[OpenMP] Use `add_llvm_library` to build the target `PluginInterface` in `plugins-nextgen`"
This is still not working for me:
```
-- Configuring done
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.amdgpu" which requires target "elf_common" that is not in any export set.
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.cuda" which requires target "elf_common" that is not in any export set.
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.x86_64" which requires target "elf_common" that is not in any export set.
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.cuda.nextgen" which requires target "elf_common" that is not in any export set.
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.cuda.nextgen" which requires target "PluginInterface" that is not in any export set.
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.x86_64.nextgen" which requires target "elf_common" that is not in any export set.
CMake Error: install(EXPORT "LLVMExports" ...) includes target "omptarget.rtl.x86_64.nextgen" which requires target "PluginInterface" that is not in any export set.
-- Generating done
```
This reverts commit
e682a76c3bf61c52628d79d6ec4db221430768c0.
Mitch Phillips [Tue, 6 Dec 2022 17:44:07 +0000 (09:44 -0800)]
Revert "[mlir] Add hoisting of transfer ops in affine loops"
This reverts commit
825da072a8ede585be9d23829f7ac483f2dbae78.
Reason: Broke the sanitizer buildbots. See original review for more
details: https://reviews.llvm.org/D137600
Adrian Prantl [Tue, 6 Dec 2022 17:43:55 +0000 (09:43 -0800)]
Add missing include
Roman Lebedev [Tue, 6 Dec 2022 17:04:26 +0000 (20:04 +0300)]
[SCEV] `MatchBinaryOp()`: try to recognize `or` as `add`-in-disguise (w/ no common bits set)
LLVM *loves* to convert `add` of operands with no common bits
into an `or`. But SCEV really doesn't deal with `or` that well,
so try extra hard to recognize this `or` as an `add`.
I believe, previously this wasn't being done because of the recursive
of this, but now that the `createSCEV()` is not recursive,
this should be fine. Unless this is *too* costly compile-time wise...
https://alive2.llvm.org/ce/z/EfapCo
Craig Topper [Tue, 6 Dec 2022 17:25:20 +0000 (09:25 -0800)]
[RISCV] Restrict when RISCVMatInt will retry SLLI as a last step. NFC
The main algorithm will already end with a SLLI when there are 12
or more trailing zeros. We only need to retry when there are less
than 12 trailing zeros since the main algorithm will pick an ADDI
or ADDIW at the end for those cases.
Florian Hahn [Tue, 6 Dec 2022 17:20:46 +0000 (17:20 +0000)]
Revert "[mlgo] Dependency-free training mode logger"
This reverts commit
c5ff6f72342e0a4b0ba2ec9f603bedca86721e80.
This breaks building on macOS:
FAILED: lib/Analysis/CMakeFiles/LLVMAnalysis.dir/TensorSpec.cpp.o
/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/c++ -DBUILD_EXAMPLES -DGTEST_HAS_RTTI=0 -D_DEBUG -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/clang-build/lib/Analysis -I/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/lib/Analysis -I/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/clang-build/include -I/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/include -fPIC -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -O3 -DNDEBUG -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX11.1.sdk -mmacosx-version-min=10.14 -fno-exceptions -fno-rtti -UNDEBUG -std=c++17 -MD -MT lib/Analysis/CMakeFiles/LLVMAnalysis.dir/TensorSpec.cpp.o -MF lib/Analysis/CMakeFiles/LLVMAnalysis.dir/TensorSpec.cpp.o.d -o lib/Analysis/CMakeFiles/LLVMAnalysis.dir/TensorSpec.cpp.o -c /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/lib/Analysis/TensorSpec.cpp
In file included from /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/lib/Analysis/TensorSpec.cpp:16:
In file included from /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/include/llvm/Analysis/TensorSpec.h:16:
/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/include/llvm/Support/JSON.h:354:29: error: non-constant-expression cannot be narrowed from type 'unsigned long' to 'int64_t' (aka 'long long') in initializer list [-Wc++11-narrowing]
create<int64_t>(int64_t{I});
^
/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/lib/Analysis/TensorSpec.cpp:55:18: note: in instantiation of function template specialization 'llvm::json::Value::Value<unsigned long, void, void, void>' requested here
OS.value(D);
^
/Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm-project/llvm/include/llvm/Support/JSON.h:354:29: note: insert an explicit cast to silence this issue
create<int64_t>(int64_t{I});
^
static_cast<int64_t>( )
1 error generated.
https://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/33120/consoleFull#-
145995569149ba4694-19c4-4d7e-bec5-
911270d8a58c
Florian Hahn [Tue, 6 Dec 2022 17:11:54 +0000 (17:11 +0000)]
[ConstraintElim] Add addition GEP tests with signed predicates.
Arthur Eubanks [Mon, 5 Dec 2022 21:15:02 +0000 (13:15 -0800)]
[llvm-c][test] Remove typed pointer support from llvm-c-test echo
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D139364
Peiming Liu [Tue, 6 Dec 2022 01:25:38 +0000 (01:25 +0000)]
Revert "Revert "[mlir][sparse] Refactoring: abstract sparse tensor memory scheme into a SparseTensorDescriptor class.""
This reverts commit
10033a179f0c73f28f051ac70b058a0c61882e3a. Plus, it fixed windows warnings and gcc errors
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D139384
Kazu Hirata [Tue, 6 Dec 2022 17:10:25 +0000 (09:10 -0800)]
[ADT, Support] Move operator<< to raw_ostream.h (NFC)
Without this patch, operator<< for Optional<T> and std::optional<T>
are in Optional.h. This means that a C++ source file must include
Optional.h even if it just needs to stream std::optional<T> and has
nothing to do with Optional<T>, which is counter-intuitive.
This patch moves the operator<< to raw_ostream.h.
As a bonus, we get to resolve a circular dependency. Optional.h no
longer needs to forward-declare raw_ostream. That is, raw_ostream.h
depends on Optional.h, not vice versa.
As a preparation for this patch, I've checked in
77609717410372e8c43aca49a268511378f58297 to forward-declare
raw_ostream in those header files that were relying on the forward
declaration of raw_ostream in Optional.h.
Differential Revision: https://reviews.llvm.org/D139290
Jay Foad [Tue, 6 Dec 2022 16:34:10 +0000 (16:34 +0000)]
[AMDGPU] Add MC tests for s_endpgm's optional immediate operand
Differential Revision: https://reviews.llvm.org/D139438
Nico Weber [Tue, 6 Dec 2022 17:01:36 +0000 (12:01 -0500)]
Revert "[amdgpu] Reimplement LDS lowering"
This reverts commit
982017240d7f25a8a6969b8b73dc51f9ac5b93ed.
Breaks check-llvm, see https://reviews.llvm.org/D139433#3974862
bixia1 [Mon, 5 Dec 2022 23:57:30 +0000 (15:57 -0800)]
[mlir][crunner] Add support for random number generation.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D139374
Shilei Tian [Tue, 6 Dec 2022 16:36:07 +0000 (11:36 -0500)]
[OpenMP] Use `add_llvm_library` to build the target `PluginInterface` in `plugins-nextgen`
This patch uses `add_llvm_library` to build the target `PluginInterface` since it can handle LLVM dependences much better. One temporary drawback of using this is that currently LLVM CMake macro doesn't support object libraries very well (there was a try a couple years ago but it was reverted later https://github.com/llvm/llvm-project/commit/
29e57229497711a3a294f437b59afa6ddc36a3d8). After switching to that, `CXX_VISIBILITY_PRESET` can not be set correctly, which can cause runtime error that a function call from one plugin could go to another. As a consequence, `PluginInterface` is built as a static library for now. I have asked the question in CMake community (https://discourse.cmake.org/t/set-target-properties-doesnt-work-properly/7016). Once that issue is solved, I'll switch it back to object library. It is not necessarily too bad to use static library, especially `BUILDTREE_ONLY` is already set such that `PluginInterface.a` will not be installed.
Reviewed By: jhuber6
Differential Revision: https://reviews.llvm.org/D139371
Sanjay Patel [Tue, 6 Dec 2022 16:17:52 +0000 (11:17 -0500)]
[SDAG] try to convert bit set/clear to signbit test when trunc is free
(X & Pow2MaskC) == 0 --> (trunc X) >= 0
(X & Pow2MaskC) != 0 --> (trunc X) < 0
This was noted as a regression in the post-commit feedback for D112634
(where we canonicalized IR differently).
For x86, this saves a few instruction bytes. AArch64 seems neutral.
Differential Revision: https://reviews.llvm.org/D139363
Sanjay Patel [Mon, 5 Dec 2022 19:15:58 +0000 (14:15 -0500)]
[AArch64][RISCV][x86] add tests for masked val equality with 0; NFC
Mark de Wever [Mon, 5 Dec 2022 17:23:51 +0000 (18:23 +0100)]
[libc++][CI] Upgrades clang-format version used.
The version used is now determined by Buildkite instead of using the
hard-coded version in the Docker image.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D139341
Jon Chesterfield [Tue, 6 Dec 2022 16:10:42 +0000 (16:10 +0000)]
[amdgpu] Reimplement LDS lowering
Renames the current lowering scheme to "module" and introduces two new
ones, "kernel" and "table", plus a "hybrid" that chooses between those three
on a per-variable basis.
Unit tests are set up to pass with the default lowering of "module" or "hybrid"
with this patch defaulting to "module", which will be a less dramatic codegen
change relative to the current. This reflects the sparsity of test coverage for
the table lowering method. Hybrid is better than module in every respect and
will be default in a subsequent patch.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D139433
Roman Lebedev [Tue, 6 Dec 2022 16:26:31 +0000 (19:26 +0300)]
[exegesis] ParallelSnippetGenerator: SingleStaticRegPerOperand if 2+ use regs
For instrs with tied operands, that strategy will not produce anything
different from `SingleStaticReg` unless there are at least two registers.
Dmitry Makogon [Tue, 6 Dec 2022 16:16:48 +0000 (23:16 +0700)]
[Test] Add test exposing crash in SimplifyCFG when hoisting llvm.deoptimize
Mircea Trofin [Mon, 5 Dec 2022 21:41:27 +0000 (13:41 -0800)]
[mlgo] Dependency-free training mode logger
This is the next step in dropping the dependency on protobuf.
The simple logger produces an output consisting of lines of json
strings. Tensor values - which should constitute the bulk of the data -
are serialized as raw byte buffers. This allows for light-weight reading
of the values.
The next step is to switch the training logic to the new logging format,
following which the protobuf-based logger will be dropped, together with
the training dependency on protobuf.
Subsequent changes will also stop buffering and stream, instead - the
buffering model is just as a convenient point-in-time.
Differential Revision: https://reviews.llvm.org/D139370
Nikita Popov [Tue, 6 Dec 2022 15:56:19 +0000 (16:56 +0100)]
[BasicAA] Guard against empty successors list (PR59360)
Succs can be empty here if a phi predecessor is unreachable.
Fixes https://github.com/llvm/llvm-project/issues/59360
Sander de Smalen [Tue, 6 Dec 2022 12:45:00 +0000 (12:45 +0000)]
[AArch64][SVE2p1] Make use of REVD instruction.
Reversing double-words within a quard-word is possible using the REVD instruction
when SVE2p1 is enabled.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D139119
Nikita Popov [Tue, 6 Dec 2022 15:35:24 +0000 (16:35 +0100)]
[ConstantRange] Fix nsw nowrap region for 1 bit integers (PR59301)
The special case for V=1 was incorrect for one bit types, where
1 is also -1. Remove it, and use getNonEmpty() to handle the full
range case instead.
Adjust the exhaustive nowrap tests to test both 5 bit and 1 bit
types.
Fixes https://github.com/llvm/llvm-project/issues/59301.
chenglin.bi [Tue, 6 Dec 2022 15:28:04 +0000 (23:28 +0800)]
[AArch64] Transform shift+and to shift+shift to select more shifted register
and (shl/srl/sra, x, c), mask --> shl (srl/sra, x, c1), c2
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D138904
Florian Hahn [Tue, 6 Dec 2022 15:27:57 +0000 (15:27 +0000)]
[ConstraintElim] Add tests for GEPs with signed predicates.
Nico Weber [Tue, 6 Dec 2022 15:22:47 +0000 (10:22 -0500)]
Revert "[Driver][test] Fix test by creating empty archive instead of empty file"
This reverts commit
6b992bcce0c5a86f57c83dd8d0ac9e63bcfc5521.
Test fails on macOS where ar doesn't want to create empty archives,
see https://reviews.llvm.org/D137275#3974489
Nico Weber [Tue, 6 Dec 2022 15:22:35 +0000 (10:22 -0500)]
Revert "[clang] Tweak test to tolerate clang being called "clang" instead of "clang-15""
This reverts commit
af95441ba7f3ca61c925409e58ee7e5486d84033.
Necessary to revert
6b992bcce0c5a86f57c83dd8d0ac9e63bcfc5521.
Nico Weber [Tue, 6 Dec 2022 15:17:35 +0000 (10:17 -0500)]
Unbreak check-all on macOS after
dbe8c2c316c40
`${X86_64}` expands to `x86_64;x86_64h` on macOS, so
get_test_cc_for_arch(${X86_64} METADATA_TEST_TARGET_CC METADATA_TEST_TARGET_CFLAGS)
calls the macro get_test_cc_for_arch() with the four arguments
`x86_64`, `x86_64h`, `METADATA_TEST_TARGET_CC`, and `METADATA_TEST_TARGET_CFLAGS`.
This writes the compiler into a variable called x86_64h, the cflags into a
variable called METADATA_TEST_TARGET_CC, and silently ignores the fourth
parameter.
As a fix, just pass `x86_64` instead of `${X86_64}`. Hopefully
that won't break anything on other platforms.
Roman Lebedev [Tue, 6 Dec 2022 14:55:35 +0000 (17:55 +0300)]
[llvm-exegesis] parallel snippet generator: avoid Read-After-Write pitfail for instrs w/ tied variables
As it is being discussed in https://github.com/llvm/llvm-project/issues/59325,
at least for the instructions with tied variables,
when trying to parallelize the instructions,
register selection is rather bad, and may either
use a register which we have used for def,
or vice versa.
That introduces serialization, and leads to
overly pessimistic inverse throughput measurement.
The new implementation avoids that,
New result:
```
$ ninja llvm-exegesis && ./bin/llvm-exegesis --mode=inverse_throughput --opcode-name=VFMADD132PDr --max-configs-per-opcode=9182
ninja: no work to do.
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-4af034.o
---
mode: inverse_throughput
key:
instructions:
- 'VFMADD132PDr XMM3 XMM3 XMM4 XMM8'
- 'VFMADD132PDr XMM5 XMM5 XMM14 XMM7'
- 'VFMADD132PDr XMM10 XMM10 XMM11 XMM15'
- 'VFMADD132PDr XMM13 XMM13 XMM15 XMM15'
- 'VFMADD132PDr XMM12 XMM12 XMM11 XMM1'
- 'VFMADD132PDr XMM0 XMM0 XMM6 XMM9'
- 'VFMADD132PDr XMM2 XMM2 XMM15 XMM11'
config: ''
register_initial_values:
- 'XMM3=0x0'
- 'XMM4=0x0'
- 'XMM8=0x0'
- 'MXCSR=0x0'
- 'XMM5=0x0'
- 'XMM14=0x0'
- 'XMM7=0x0'
- 'XMM10=0x0'
- 'XMM11=0x0'
- 'XMM15=0x0'
- 'XMM13=0x0'
- 'XMM12=0x0'
- 'XMM1=0x0'
- 'XMM0=0x0'
- 'XMM6=0x0'
- 'XMM9=0x0'
- 'XMM2=0x0'
cpu_name: znver3
llvm_triple: x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
- { key: inverse_throughput, value: 0.6403, per_snippet_value: 4.4821 }
error: ''
info: instruction has tied variables, avoiding Read-After-Write issue, picking random def and use registers not aliasing each other, randomizing registers for uses
assembled_snippet: 4883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F1C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F24244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F04244883C4104883EC04C70424801F0000C5F8AE14244883C4044883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F2C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F34244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F3C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F14244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F1C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F3C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F2C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F24244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F34244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F0C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F14244883C410C4C2D998D8C4E28998EFC442A198D7C4428198EFC462A198E1C4C2C998C1C4C28198D3C4C2D998D8C4E28998EFC442A198D7C4428198EFC462A198E1C4C2C998C1C4C28198D3C4C2D998D8C4E28998EFC442A198D7C4428198EFC462A198E1C4C2C998C1C4C28198D3C4C2D998D8C4E28998EFC442A198D7C4428198EFC462A198E1C4C2C998C1C4C28198D3C3
...
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-f05c2f.o
---
mode: inverse_throughput
key:
instructions:
- 'VFMADD132PDr XMM15 XMM15 XMM11 XMM2'
- 'VFMADD132PDr XMM5 XMM5 XMM11 XMM2'
- 'VFMADD132PDr XMM14 XMM14 XMM11 XMM2'
- 'VFMADD132PDr XMM4 XMM4 XMM11 XMM2'
- 'VFMADD132PDr XMM8 XMM8 XMM11 XMM2'
- 'VFMADD132PDr XMM3 XMM3 XMM11 XMM2'
- 'VFMADD132PDr XMM10 XMM10 XMM11 XMM2'
- 'VFMADD132PDr XMM7 XMM7 XMM11 XMM2'
- 'VFMADD132PDr XMM13 XMM13 XMM11 XMM2'
- 'VFMADD132PDr XMM9 XMM9 XMM11 XMM2'
- 'VFMADD132PDr XMM1 XMM1 XMM11 XMM2'
- 'VFMADD132PDr XMM6 XMM6 XMM11 XMM2'
- 'VFMADD132PDr XMM0 XMM0 XMM11 XMM2'
- 'VFMADD132PDr XMM12 XMM12 XMM11 XMM2'
config: ''
register_initial_values:
- 'XMM15=0x0'
- 'XMM11=0x0'
- 'XMM2=0x0'
- 'MXCSR=0x0'
- 'XMM5=0x0'
- 'XMM14=0x0'
- 'XMM4=0x0'
- 'XMM8=0x0'
- 'XMM3=0x0'
- 'XMM10=0x0'
- 'XMM7=0x0'
- 'XMM13=0x0'
- 'XMM9=0x0'
- 'XMM1=0x0'
- 'XMM6=0x0'
- 'XMM0=0x0'
- 'XMM12=0x0'
cpu_name: znver3
llvm_triple: x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
- { key: inverse_throughput, value: 0.5312, per_snippet_value: 7.4368 }
error: ''
info: instruction has tied variables, avoiding Read-After-Write issue, picking random def and use registers not aliasing each other, one unique register for each use position
assembled_snippet: 4883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F3C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F1C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F14244883C4104883EC04C70424801F0000C5F8AE14244883C4044883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F2C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F34244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F24244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F1C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F14244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F3C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F2C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F0C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F34244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F24244883C410C462A198FAC4E2A198EAC462A198F2C4E2A198E2C462A198C2C4E2A198DAC462A198D2C4E2A198FAC462A198EAC462A198CAC4E2A198CAC4E2A198F2C4E2A198C2C462A198E2C462A198FAC4E2A198EAC462A198F2C4E2A198E2C462A198C2C4E2A198DAC462A198D2C4E2A198FAC462A198EAC462A198CAC4E2A198CAC4E2A198F2C4E2A198C2C462A198E2C462A198FAC4E2A198EAC462A198F2C4E2A198E2C462A198C2C4E2A198DAC462A198D2C4E2A198FAC462A198EAC462A198CAC4E2A198CAC4E2A198F2C4E2A198C2C462A198E2C462A198FAC4E2A198EAC462A198F2C4E2A198E2C462A198C2C4E2A198DAC462A198D2C4E2A198FAC462A198EAC462A198CAC4E2A198CAC4E2A198F2C4E2A198C2C462A198E2C3
...
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-c32060.o
---
mode: inverse_throughput
key:
instructions:
- 'VFMADD132PDr XMM10 XMM10 XMM6 XMM6'
- 'VFMADD132PDr XMM8 XMM8 XMM6 XMM6'
- 'VFMADD132PDr XMM12 XMM12 XMM6 XMM6'
- 'VFMADD132PDr XMM9 XMM9 XMM6 XMM6'
- 'VFMADD132PDr XMM7 XMM7 XMM6 XMM6'
- 'VFMADD132PDr XMM1 XMM1 XMM6 XMM6'
- 'VFMADD132PDr XMM0 XMM0 XMM6 XMM6'
- 'VFMADD132PDr XMM5 XMM5 XMM6 XMM6'
- 'VFMADD132PDr XMM11 XMM11 XMM6 XMM6'
- 'VFMADD132PDr XMM2 XMM2 XMM6 XMM6'
- 'VFMADD132PDr XMM15 XMM15 XMM6 XMM6'
- 'VFMADD132PDr XMM3 XMM3 XMM6 XMM6'
- 'VFMADD132PDr XMM14 XMM14 XMM6 XMM6'
- 'VFMADD132PDr XMM4 XMM4 XMM6 XMM6'
- 'VFMADD132PDr XMM13 XMM13 XMM6 XMM6'
config: ''
register_initial_values:
- 'XMM10=0x0'
- 'XMM6=0x0'
- 'MXCSR=0x0'
- 'XMM8=0x0'
- 'XMM12=0x0'
- 'XMM9=0x0'
- 'XMM7=0x0'
- 'XMM1=0x0'
- 'XMM0=0x0'
- 'XMM5=0x0'
- 'XMM11=0x0'
- 'XMM2=0x0'
- 'XMM15=0x0'
- 'XMM3=0x0'
- 'XMM14=0x0'
- 'XMM4=0x0'
- 'XMM13=0x0'
cpu_name: znver3
llvm_triple: x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
- { key: inverse_throughput, value: 0.5311, per_snippet_value: 7.9665 }
error: ''
info: instruction has tied variables, avoiding Read-After-Write issue, picking random def and use registers not aliasing each other, reusing the same register for all uses
assembled_snippet: 4883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F14244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F34244883C4104883EC04C70424801F0000C5F8AE14244883C4044883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F24244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F0C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F3C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F2C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F1C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F14244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F3C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F1C244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F34244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F24244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F2C244883C410C462C998D6C462C998C6C462C998E6C462C998CEC4E2C998FEC4E2C998CEC4E2C998C6C4E2C998EEC462C998DEC4E2C998D6C462C998FEC4E2C998DEC462C998F6C4E2C998E6C462C998EEC462C998D6C462C998C6C462C998E6C462C998CEC4E2C998FEC4E2C998CEC4E2C998C6C4E2C998EEC462C998DEC4E2C998D6C462C998FEC4E2C998DEC462C998F6C4E2C998E6C462C998EEC462C998D6C462C998C6C462C998E6C462C998CEC4E2C998FEC4E2C998CEC4E2C998C6C4E2C998EEC462C998DEC4E2C998D6C462C998FEC4E2C998DEC462C998F6C4E2C998E6C462C998EEC462C998D6C462C998C6C462C998E6C462C998CEC4E2C998FEC4E2C998CEC4E2C998C6C4E2C998EEC462C998DEC4E2C998D6C462C998FEC4E2C998DEC462C998F6C4E2C998E6C462C998EEC3
...
```
Reviewed By: courbet
Differential Revision: https://reviews.llvm.org/D139283
Paul Robinson [Mon, 5 Dec 2022 22:05:09 +0000 (14:05 -0800)]
[ARM/Darwin] Convert tests to check 'target='
Part of the project to eliminate special handling for triples in lit
expressions.
Jay Foad [Tue, 6 Dec 2022 14:50:02 +0000 (14:50 +0000)]
[AMDGPU] Remove FIXME that was addressed by D99413
Michael Maitland [Thu, 3 Nov 2022 17:44:10 +0000 (10:44 -0700)]
[RISCV][Codegen] Account for LMUL in Vector Mask instructions
It is likley that subtargets act differently for vector fixed-point arithmetic instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.
Differential Revision: https://reviews.llvm.org/D137427
Jonathan Peyton [Tue, 6 Dec 2022 14:31:31 +0000 (08:31 -0600)]
[OpenMP][libomp] Cleanup version script and exported symbols
This patch fixes issues seen once https://reviews.llvm.org/D135402 is applied.
The exports_so.txt file attempts to export functions which may not exist
depending on which features are enabled/disabled in the OpenMP
runtime library. There are not many of these so exporting dummy
symbols is feasible.
* Export dummy __kmp_reset_stats() function when stats is disabled.
* Export dummy debugging data when USE_DEBUGGER is disabled
* Export dummy __kmp_itt_[fini|init]_ittlib() functions
when ITT Notify is disabled
* Export dummy __kmp_reap_monitor() function when KMP_USE_MONITOR
is disabled
* Remove __kmp_launch_monitor and __kmp_launch_worker from being exported.
They have been static symbols since library inception.
Fixes: https://github.com/llvm/llvm-project/issues/58858
Differential Revision: https://reviews.llvm.org/D138049
Emmmer [Mon, 5 Dec 2022 14:55:15 +0000 (22:55 +0800)]
[LLDB][RISCV] Add RV32FC instruction support for EmulateInstructionRISCV
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D139390
Kadir Cetinkaya [Thu, 17 Nov 2022 12:38:43 +0000 (13:38 +0100)]
[include-cleaner] Make use of locateSymbol in WalkUsed and HTMLReport
Depens on D135953
Differential Revision: https://reviews.llvm.org/D138200
Valentin Clement [Tue, 6 Dec 2022 14:02:14 +0000 (15:02 +0100)]
[flang] Set correct box type when emboxing temporary in array value copy pass
In some cases, the base type is already a fir.box type. This patch updates
the code to set the result box type to fir.box<T>, where T is the type
of the allocated temp.
This was reported in https://github.com/llvm/llvm-project/issues/59342
Reviewed By: jeanPerier, tblah
Differential Revision: https://reviews.llvm.org/D139401
Matt Arsenault [Sun, 4 Dec 2022 00:32:41 +0000 (19:32 -0500)]
ValueTracking: Teach CannotBeOrderedLessThanZero about copysign
LLVM GN Syncbot [Tue, 6 Dec 2022 13:50:56 +0000 (13:50 +0000)]
[gn build] Port
d09d834bb980
LLVM GN Syncbot [Tue, 6 Dec 2022 13:50:55 +0000 (13:50 +0000)]
[gn build] Port
bc0617795f8b
Nico Weber [Tue, 6 Dec 2022 13:50:37 +0000 (08:50 -0500)]
[clang] Tweak test to tolerate clang being called "clang" instead of "clang-15"
Nico Weber [Tue, 6 Dec 2022 13:43:48 +0000 (08:43 -0500)]
Revert "Store OptTable::Info::Name as a StringRef"
This reverts commit
8ae18303f97d5dcfaecc90b4d87effb2011ed82e.
Breaks buildling lldb, see https://reviews.llvm.org/D139274#3974171
Nico Weber [Tue, 6 Dec 2022 13:43:30 +0000 (08:43 -0500)]
Revert "Quick fix to unbreak tblgen past
8ae18303f97d"
This reverts commit
e50a60d7349de151bd2b06d85a79201ebc372d8a.
Prerequisite for reverting
8ae18303f97d5.
Nico Weber [Tue, 6 Dec 2022 13:40:14 +0000 (08:40 -0500)]
Revert "[BOLT] Fix blocks layout reverse iterators"
This reverts commit
7bb0cbfc322826e7bd41a74d5d71da138603b31f.
Doesn't build at least on macOS, see https://reviews.llvm.org/D139335#3974169
Benjamin Kramer [Tue, 6 Dec 2022 13:34:18 +0000 (14:34 +0100)]
Quick fix to unbreak tblgen past
8ae18303f97d
llvm/tools/llvm-objdump/llvm-objdump.cpp:128:38: error: constexpr variable 'ObjdumpInfoTable' must be initialized by a constant expression
static constexpr opt::OptTable::Info ObjdumpInfoTable[] = {
^ ~
ObjdumpOpts.inc:30:45: note: non-constexpr function 'substr' cannot be used in a constant expression
OPTION(prefix_0, llvm::StringRef("<input>").substr(0), INPUT, Input, INVALID, INVALID, nullptr, 0, 0, nullptr, nullptr, nullptr)
^
Nikolas Klauser [Thu, 17 Nov 2022 20:34:29 +0000 (21:34 +0100)]
[libc++] Fix memory leaks when throwing inside std::vector constructors
Fixes #58392
Reviewed By: ldionne, #libc
Spies: alexfh, hans, joanahalili, dblaikie, libcxx-commits
Differential Revision: https://reviews.llvm.org/D138601
Matt Arsenault [Sat, 3 Dec 2022 17:27:34 +0000 (12:27 -0500)]
InstCombine: Fold fabs (copysign x, y) -> fabs x
Matt Arsenault [Sat, 3 Dec 2022 16:11:56 +0000 (11:11 -0500)]
InstCombine: Add baseline tests for copysign with fneg/fabs
serge-sans-paille [Sun, 4 Dec 2022 08:33:14 +0000 (09:33 +0100)]
Store OptTable::Info::Name as a StringRef
This avoids implicit conversion to StringRef at several points, which in
turns avoid redundant calls to strlen.
As a side effect, this greatly simplifies the implementation of
StrCmpOptionNameIgnoreCase.
It also eventually gives a consistent, humble speedup in compilation
time.
https://llvm-compile-time-tracker.com/compare.php?from=
5f5b942823474e98e43a27d515a87ce140396c53&to=
60e13b778119fc32d50dc38ff1a564a87146e9c6&stat=instructions:u
Differential Revision: https://reviews.llvm.org/D139274
Matt Arsenault [Mon, 5 Dec 2022 18:51:01 +0000 (13:51 -0500)]
LangRef: Clarify semantics of lround/llround and lrint/llrint
Haojian Wu [Tue, 6 Dec 2022 12:56:16 +0000 (13:56 +0100)]
Fix a -Wunused-variable warning in release build, NFC
Jean Perier [Tue, 6 Dec 2022 12:53:08 +0000 (13:53 +0100)]
[flang] Allow conversion from hlfir.expr to fir::ExtendedValue
For now at least, the plan is to keep hlfir.expr usage limited as
sub-expression operand, assignment rhs, and a few other contexts (
e.g. Associate statements). The rest of lowering (statements lowering
in the bridge) will still expect to get and manipulate characters and
arrays in memory. That means that hlfir.expr must be converted to
variable in converter.genExprAddr/converter.genExprBox.
This is done using an hlfir.associate, and generating the related
hlfir.end_associate in the statement context.
hlfir::getFirBase of is updated to avoid bringing in the HLFIR
fir.boxchar/fir.box into FIR when the entity was created with
hlfir::AssociateOp.
Differential Revision: https://reviews.llvm.org/D139328
bipmis [Tue, 6 Dec 2022 12:49:05 +0000 (12:49 +0000)]
Add tests which can be matched to umull
Manuel Brito [Tue, 6 Dec 2022 12:39:38 +0000 (12:39 +0000)]
[Clang][CodeGen] Use poison instead of undef for extra argument in __builtin_amdgcn_mov_dpp [NFC]
Differential Revision: https://reviews.llvm.org/D138755
Adrian Kuegel [Tue, 6 Dec 2022 12:29:47 +0000 (13:29 +0100)]
[mlir][SparseTensor] Apply ClangTidyLegacy finding (NFC).
Converting integer literal to bool, use bool literal instead.
Archibald Elliott [Wed, 30 Nov 2022 19:33:54 +0000 (19:33 +0000)]
[AArch64] Implement __arm_rsr128/__arm_wsr128
This only contains the SelectionDAG implementation. GlobalISel to
follow.
The broad approach is:
- Introduce new builtins for 128-bit wide instructions.
- Lower these to @llvm.read_register.i128/@llvm.write_register.i128
- Introduce target-specific ISD nodes which have legal operands (two
i64s rather than an i128). These are named AArch64::{MRRS, MSRR} to
match the instructions they are for. These are a little complex as
they need to match the "shape" of what they're replacing or the
legaliser complains.
- Select these using the existing tryReadRegister/tryWriteRegister to
share the MDString parsing code, and introduce additional code to
ensure these are selected into the right MRRS/MSRR instructions. What
makes this hard is ensuring that the two i64s end up in an XSeqPair
register pair, because SelectionDAG doesn't care that much about
register classes if it can avoid doing so.
The main change to existing code is the reorganisation of
tryReadRegister and tryWriteRegister to try to keep the string parsing
code separate from the instruction creating code.
This also includes the changes to clang to define and use the ACLE
feature macro named `__ARM_FEATURE_SYSREG128`.
Contributors:
Sam Elliott
Lucas Prates
Differential Revision: https://reviews.llvm.org/D139086
Ties Stuij [Tue, 6 Dec 2022 10:56:43 +0000 (10:56 +0000)]
[AArch64] implement GPR (U/S)(MIN/MAX) instruction SDag support
Using SelectionDag, lower umin, umax, smin, smax intrinsics to corresponding
UMIN, UMAX, SMIN, SMAX instructions when feat CSSC is available.
See specs for corresponding immediate and register versions in:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D138813
Nikita Popov [Wed, 26 Oct 2022 09:55:46 +0000 (11:55 +0200)]
[IR] Don't assume readnone/readonly intrinsics are willreturn
This removes our "temporary" hack to assume that readnone/readonly
intrinsics are also willreturn. An explicit willreturn annotation,
usually via default intrinsic attributes, is now required.
Differential Revision: https://reviews.llvm.org/D137630
Ties Stuij [Tue, 6 Dec 2022 10:44:05 +0000 (10:44 +0000)]
[AArch64] lower abs intrinsic to new ABS instruction in SelDag
When feature CSSC is available, the SelectionDag abs intrinsic should map to the
new scalar ABS instruction.
Additionally, the SIMDTwoScalarD tablegen defm includes a pattern match for
scalar i64, which we don't want to use when CSSC is enabled.
spec:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/ABS--Absolute-value-
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D138812
David Spickett [Mon, 5 Dec 2022 10:10:42 +0000 (10:10 +0000)]
[LLVM][ARM] Correct llvm feature for vfpv3d16 host feature
d16 was removed in https://reviews.llvm.org/D60691.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D139304
David Spickett [Tue, 6 Dec 2022 10:30:38 +0000 (10:30 +0000)]
[lld-macho] Fix map file test on 32 bit hosts
The test added in https://reviews.llvm.org/D137368 has been failing
on our 32 bit arm bots:
https://lab.llvm.org/buildbot/#/builders/178/builds/3460
You get this for the strings:
<<dead>> 0x883255000000003 [ 10] literal string: Hello, it's me
Instead of the expected:
<<dead>> 0x0000000F [ 3] literal string: Hello, it's me
This is because unlike symbols whose size is a uint64_t, strings
use a StringRef whose size is size_t. size_t changes size between
32 and 64 bit platforms.
This fixes the test by using %z to print the size of the strings,
this works for 32 and 64 bit.
Ties Stuij [Tue, 6 Dec 2022 10:42:06 +0000 (10:42 +0000)]
[AArch64] SelectionDag codegen for gpr CTZ instruction
When feature CSSC is available we should use instruction CTZ in SelectionDag
where applicable:
- CTTZ intrinsics are lowered to using the gpr CTZ instruction
- BITREVERSE -> CTLZ instruction pattern gets replaced by CTZ
spec:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/CTZ--Count-Trailing-Zeros-
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D138811
Kristina Bessonova [Fri, 18 Nov 2022 17:56:51 +0000 (19:56 +0200)]
[llvm-objdump] Avoid using mapping symbols as branch target labels
The main motivation for this change is to avoid ambiguity because
mapping symbol names may not be unique across a binary and do not allow uniquely
identifying target address. So that mapping symbols used as branch target
labels make llvm-objdump output less readable.
Another point is that mapping symbols sometimes appear in
non-allocatable sections, like debug info sections which make objdump
output even more confusing.
For example, a small AArch64 executable may contain plenty of `$d[.*]`
symbols and none of them would be useful as a label for resolving
a branch or a memory operand target address:
```
0000000000000254 l .note.ABI-tag
0000000000000000 $d
00000000000008d4 l .eh_frame
0000000000000000 $d
0000000000000868 l .rodata
0000000000000000 $d
0000000000011028 l .data
0000000000000000 $d
0000000000010db8 l .fini_array
0000000000000000 $d
0000000000010db0 l .init_array
0000000000000000 $d
00000000000008e8 l .eh_frame
0000000000000000 $d
0000000000011034 l .bss
0000000000000000 $d
```
Note that GNU objdump doesn't use mapping symbols as branch target
labels for all targets that support such symbols (ARM, AArch64, CSKY).
Differential Revision: https://reviews.llvm.org/D139131
Javier Setoain [Mon, 7 Nov 2022 21:27:36 +0000 (21:27 +0000)]
[mlir] Add hoisting of transfer ops in affine loops
The only way to do this with the current hoisting strategy is by
lowering Affine to Scf first, but that prevents further passes on
Affine.
Differential Revision: https://reviews.llvm.org/D137600
Max Kazantsev [Tue, 6 Dec 2022 09:35:45 +0000 (16:35 +0700)]
[SCEVExpander] Support cost evaluation of several SCEVs with same budget
This is a follow-up from discussion in D138412. Sometimes we want to evaluate
the cost of expansion of several SCEVs together with same budget. For example,
if one of them is a bit above cheap limit, and the second one is free, then
we still want to expand. Checking each of them with "cheap" limit is a bit more
pessimistic.
Differential Revision: https://reviews.llvm.org/D138475
Reviewed By: lebedev.ri
HanSheng Zhang [Tue, 6 Dec 2022 09:59:02 +0000 (10:59 +0100)]
[Verifier]Remove API declaration that has never been implemented
Close https://github.com/llvm/llvm-project/issues/59244
Reviewed By: t.p.northover
Differential Revision: https://reviews.llvm.org/D138889
HanSheng Zhang [Tue, 6 Dec 2022 09:55:17 +0000 (10:55 +0100)]
[CMake]Allow user specified CPack Options
This should allow downstream vendors to install multiple LLVM distributions in parallel.
Should we also patch the default values to allow multiple upstream llvm distribution?
Reviewed By: thieta
Differential Revision: https://reviews.llvm.org/D138632
Juan Manuel MARTINEZ CAAMAÑO [Tue, 6 Dec 2022 09:22:52 +0000 (04:22 -0500)]
[NFC] Remove const from return value of function
Sergey Kachkov [Wed, 19 Oct 2022 15:12:33 +0000 (18:12 +0300)]
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
Cannonical frame address after RVV stack adjustment is sp + StackSize +
RVVStackSize * vlenb, and since vlenb is unknown at compile-time (but it
is a constant for particular HW implementation), emit
.cfi_def_cfa_expression so libunwind can read VLENB CSR register at
run-time and obtain correct frame address.
Fixes https://github.com/llvm/llvm-project/issues/58356 (but additional
run-time support for reading CSR may be required)
Differential Revision: https://reviews.llvm.org/D136263
Vlad Serebrennikov [Tue, 6 Dec 2022 09:42:07 +0000 (12:42 +0300)]
[clang] Add test for CWG600
P1787: //CWG600 is resolved by explaining that accessibility affects naming a member in the sense of the ODR.//
Wording: see changes to [class.access] p1 and p4.
Additional references: [[ http://eel.is/c++draft/basic.def.odr#8.sentence-2 | basic.def.odr/8 ]]: //A function is odr-used if it is named by a potentially-evaluated expression or conversion.//
Reviewed By: #clang-language-wg, aaron.ballman
Differential Revision: https://reviews.llvm.org/D139173
Corentin Jabot [Fri, 2 Dec 2022 18:35:13 +0000 (19:35 +0100)]
[Clang] make_cxx_dr_status download the issue list automatically
if none is provided
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D139212
Vlad Serebrennikov [Tue, 6 Dec 2022 09:38:38 +0000 (12:38 +0300)]
[clang] Mark CWG554 as N/A
P1787: //CWG554 is resolved by using the word “scope” instead of “declarative region”, consistent with its very common use in phrases like “namespace scope”.//
Reviewed By: #clang-language-wg, cor3ntin, aaron.ballman, shafik
Differential Revision: https://reviews.llvm.org/D139172
David Spickett [Mon, 5 Dec 2022 11:53:06 +0000 (11:53 +0000)]
[LLVM][Release] Prevent empty runtime name in release script
Unlike projects, runtimes doesn't have a default set of names.
This means you get a leading space at the start, which gets converted
to a ';' giving ";<runtime name>;<runtime name>".
CMake then errors because the "" before the first ';' is treated
as a runtime name and of course it's not a valid name.
Fix this by removing the leading spaces from runtimes before we
insert the ';'.
Reviewed By: ldionne
Differential Revision: https://reviews.llvm.org/D139306
chenglin.bi [Tue, 6 Dec 2022 09:35:08 +0000 (17:35 +0800)]
[Instcombine] Add baseline tests for logic-and/logic-or factorization; NFC
Vlad Serebrennikov [Tue, 6 Dec 2022 09:33:56 +0000 (12:33 +0300)]
[clang] Add test for CWG405
P1787: //CWG405 is resolved by stating that argument-dependent lookup (sometimes) occurs after an ordinary unqualified lookup (making statements like “finding a variable prevents argument-dependent lookup” formally correct).//
Wording: see changes to [basic.lookup.argdep] p1 and p3
This issue seems a duplicate of CWG218, even though it is not officially recognized. A part of a test for CWG218 is reused here, adding cross-references.
Reviewed By: #clang-language-wg, aaron.ballman
Differential Revision: https://reviews.llvm.org/D139095
Tobias Hieta [Tue, 22 Nov 2022 09:10:36 +0000 (10:10 +0100)]
[CodeView] Add support for local S_CONSTANT records
CodeView doesn't have the ability to represent variables
in other ways than as in registers or memory values, but
LLVM very often transforms simple values into constants,
consider this program:
int f () { int i = 123; return i; }
LLVM will transform `i` into a constant value and just
leave behind a llvm.dbg.value, this can't be represented
as a S_LOCAL record in CodeView. But we can represent it
as a S_CONSTANT record.
This patch checks if the location of a debug value is null,
then we will insert a S_CONSTANT record instead of a S_LOCAL
value with the flag "OptimizedAway".
In lld we then output the S_CONSTANT in the right scope, before
they where always inserted in the global stream, now we check
the scope before inserting it.
This has shown to improve debugging for our developers
internally.
Fixes to llvm/llvm-project#55958
Reviewed By: aganea
Differential Revision: https://reviews.llvm.org/D138995
Vlad Serebrennikov [Tue, 6 Dec 2022 08:56:01 +0000 (11:56 +0300)]
[clang] Add test for CWG952
P1787: // [[ https://wg21.link/cwg952 | CWG952 ]] is resolved by refining the definition of “naming class” per Richard’s suggestion in [[ https://lists.isocpp.org/core/2020/09/9963.php | “CWG1621 and [class.static/2”]].//
Wording:
- [class.static]/2 removed;
- [class.access.base]/5 rephrased.
Currently behavior is the following: unqualified names undergo //unqualified name lookup// [1], which perform //unqualified search// in immediate scope [2]. This scope is the scope the definition of //naming class// [3] refers to. `A::I` is not //accessible// when named in classes `C` and `D` per [3]. In particular, the last item regarding base class ([class.access.base]/5.4) is not applicable, because class `A` is not //accessible// in both classes `C` and `D` per [4].
References:
1. [[ https://eel.is/c++draft/basic.lookup#unqual-4.sentence-2 | basic.lookup.unqual/4 ]]
2. [[ https://eel.is/c++draft/basic.lookup#unqual-3 | basic.lookup.unqual/3 ]]
3. [[ https://eel.is/c++draft/class.access#base-5.sentence-4 | class.access.base/5 ]]
4. [[ https://eel.is/c++draft/class.access#base-4 | class.access.base/4 ]]
Reviewed By: #clang-language-wg, erichkeane, aaron.ballman
Differential Revision: https://reviews.llvm.org/D139326