Feng Liu [Wed, 22 Apr 2020 21:14:29 +0000 (14:14 -0700)]
[mlir/Quant] Allows to use 32 bits storage type
Differential Revision: https://reviews.llvm.org/D78671
Mircea Trofin [Thu, 23 Apr 2020 16:14:08 +0000 (09:14 -0700)]
[llvm][NFC] Factor out cost-model independent inling decision
Summary:
llvm::getInlineCost starts off by determining whether inlining should
happen or not because of user directives or easily determinable
unviability. This CL refactors this functionality as a reusable API.
Reviewers: davidxl, eraman
Reviewed By: davidxl, eraman
Subscribers: hiraditya, haicheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73825
Christopher Tetreault [Thu, 23 Apr 2020 16:52:49 +0000 (09:52 -0700)]
[SVE] Make VectorType::getNumElements() complain for scalable vectors
Summary:
Piggy-back off of TypeSize's STRICT_FIXED_SIZE_VECTORS flag and:
- if it is defined, assert that the vector is not scalable
- if it is not defined, complain if the vector is scalable
Reviewers: efriedma, sdesmalen, c-rhodes
Reviewed By: sdesmalen
Subscribers: hiraditya, mgorny, tschuett, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78576
Mircea Trofin [Thu, 23 Apr 2020 16:15:04 +0000 (09:15 -0700)]
[llvm][NFC][CallSite] Removed CallSite from few implementation details
Reviewers: dblaikie, craig.topper
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78724
Vedant Kumar [Thu, 23 Apr 2020 17:20:01 +0000 (10:20 -0700)]
[DirectoryWatcher] Do not use FSEvents on non-macOS platforms
The FSEvents APIs are available on iOS6+: however, the DirectoryWatcher
code isn't wired up to really use FSEvents on embedded platforms.
I've duplicated code from DirectoryWatcher-not-implemented.cpp here and
used TargetConditionals instead of adding cmakery to check try_compile;
I couldn't get that to work properly.
Vedant Kumar [Thu, 23 Apr 2020 16:48:47 +0000 (09:48 -0700)]
MachineBasicBlock: Avoid copy in skipDebugInstructions{Forward,Backward}, NFC
Valeriy Savchenko [Thu, 23 Apr 2020 15:32:10 +0000 (18:32 +0300)]
[analyzer] Consider array subscripts to be interesting lvalues.
Static analyzer has a mechanism of clearing redundant nodes when
analysis hits a certain threshold with a number of nodes in exploded
graph (default is 1000). It is similar to GC and aims removing nodes
not useful for analysis. Unfortunately nodes corresponding to array
subscript expressions (that actively participate in data propagation)
get removed during the cleanup. This might prevent the analyzer from
generating useful notes about where it thinks the data came from.
This fix is pretty much consistent with the way analysis works
already. Lvalue "interestingness" stands for the analyzer's
possibility of tracking values through them.
Differential Revision: https://reviews.llvm.org/D78638
MaheshRavishankar [Thu, 23 Apr 2020 16:44:23 +0000 (09:44 -0700)]
[mlir][StandardToSPIRV] Fix test cases where DCE removes all the code.
Differential Revision: https://reviews.llvm.org/D78727
Simon Pilgrim [Thu, 23 Apr 2020 16:05:43 +0000 (17:05 +0100)]
X86MCTargetDesc.h - replace FormattedStream.h include with forward declaration. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 16:02:19 +0000 (17:02 +0100)]
X86TargetObjectFile.h - remove unnecessary TargetLoweringObjectFile.h include. NFC.
We already include TargetLoweringObjectFileImpl.h which includes it and we only use its types as part of TargetLoweringObjectFile* overridden methods.
Vedant Kumar [Thu, 23 Apr 2020 16:23:21 +0000 (09:23 -0700)]
Rename a shadowed variable causing build failure on gcc<5.5
See discussion here: https://reviews.llvm.org/D78265
Tim Keith [Thu, 23 Apr 2020 16:14:58 +0000 (09:14 -0700)]
[flang] Remove unused variable
Reviewers: sscalpone, jdoerfert, DavidTruby
Reviewed By: sscalpone
Subscribers: llvm-commits
Tags: #flang, #llvm
Differential Revision: https://reviews.llvm.org/D78725
Peter Smith [Thu, 23 Apr 2020 15:58:50 +0000 (16:58 +0100)]
Revert "[LLD][ELF][ARM] Fix ARM Exidx order for non monotonic section order"
This reverts commit
f969c2aa657e28633ece63a5430e551f0b8beb98.
There are some msan buildbot failures sanitzer-x86_64-linux-fast that
I need to investigate.
Differential Revision: https://reviews.llvm.org/D78422
Simon Pilgrim [Thu, 23 Apr 2020 15:21:18 +0000 (16:21 +0100)]
[RISCV] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 15:19:37 +0000 (16:19 +0100)]
[WebAssembly] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 15:17:45 +0000 (16:17 +0100)]
[XCore] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 15:08:16 +0000 (16:08 +0100)]
[NVPTX] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 14:15:38 +0000 (15:15 +0100)]
[Sparc] Remove unused forward declarations. NFC.
Tim Keith [Wed, 22 Apr 2020 22:26:29 +0000 (15:26 -0700)]
[flang][NFC] Refactor derived type instantiation
Summary:
Move InstantiateComponent and InstantiateIntrinsicType from symbol.cpp
to type.cpp as that is where they are called.
Put both in InstantiateHelper class to better isolate them.
Add CreateDerivedTypeSpec in InstantiateHelper.
Add non-const forms for AsIntrinsic and AsDerived to avoid const_cast.
No functional changes.
Reviewers: DavidTruby, klausler, PeteSteinfeld, jdoerfert
Reviewed By: klausler
Subscribers: llvm-commits
Tags: #flang, #llvm
Differential Revision: https://reviews.llvm.org/D78678
Krzysztof Parzyszek [Thu, 23 Apr 2020 14:39:43 +0000 (09:39 -0500)]
[Hexagon] Add missing live-in registers in some codegen tests
Victor Huang [Thu, 23 Apr 2020 15:24:38 +0000 (10:24 -0500)]
[PowerPC][Future] Add missing changes for PC Realtive addressing
1. Use Subtarget.isUsingPCRelativeCalls() in LowerConstantPool to
check if using PCRelative addressing.
2. Change MO_GOT_FLAG = 32 to MO_GOT_FLAG = 8 in PPC.h to use
consecutive bits.
Differential Revision: https://reviews.llvm.org/D78406
Mircea Trofin [Wed, 22 Apr 2020 20:19:15 +0000 (13:19 -0700)]
[llvm][NFC][CallSite] Remove CallSite from TypeMetadataUtils & related
Reviewers: craig.topper, dblaikie
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78666
Nicolas Vasilache [Thu, 23 Apr 2020 15:00:03 +0000 (11:00 -0400)]
[mlir][EDSC] Retire ValueHandle
The EDSC discussion [thread](https://llvm.discourse.group/t/evolving-builder-apis-based-on-lessons-learned-from-edsc/879) points out that ValueHandle has become an unnecessary level of abstraction since MLIR switch from `Value *` to `Value` everywhere.
This revision removes this level of indirection.
Raphael Isemann [Thu, 23 Apr 2020 14:58:49 +0000 (16:58 +0200)]
[lldb] Make RNBSocketTest compile again after socket modernization
Commit
c9e6b7010c6998b6 changed the API but didn't update this
macOS-specific test.
Peter Smith [Sat, 18 Apr 2020 09:09:06 +0000 (10:09 +0100)]
[LLD][ELF][ARM] Fix ARM Exidx order for non monotonic section order
The contents of the .ARM.exidx section must be ordered by SHF_LINK_ORDER
rules. We don't need to know the precise address for this order, but we
do need to know the relative order of sections. We have been using the
sectionIndex for this purpose, this works when the OutputSection order
has a monotonically increasing virtual address, but it is possible to
write a linker script with non-monotonically increasing virtual address.
For these cases we need to evaluate the base address of the OutputSection
so that we can order the .ARM.exidx sections properly.
This change moves the finalisation of .ARM.exidx till after the first
call to AssignAddresses. This permits us to sort on virtual address which
is linker script safe. It also permits a fix for part of pr44824 where
we generate .ARM.exidx section for the vector table when that table is so
far away it is out of range of the .ARM.exidx section. This fix will come
in a follow up patch.
Differential Revision: https://reviews.llvm.org/D78422
Xing GUO [Thu, 23 Apr 2020 14:46:58 +0000 (22:46 +0800)]
[doc] Fix broken link. NFC.
Pavel Labath [Thu, 23 Apr 2020 14:27:01 +0000 (16:27 +0200)]
[lldb/Core] Avoid more Communication::Disconnect races
Calling Disconnect while the read thread is running is racy because the
thread can also call Disconnect. This is a follow-up to
b424b0bf, which
reorders other occurences of Disconnect/StopReadThread I can find, and also
adds an assertion to guard against new occurences being introduced.
Kadir Cetinkaya [Thu, 23 Apr 2020 14:09:23 +0000 (16:09 +0200)]
[clangd] Delete remapped buffers in tests
These buffers normally get freed after being used in a CompilerInstance.
but tests don't make use of those, so we need to free them explicitly.
Marcel Koester [Wed, 8 Apr 2020 08:31:18 +0000 (10:31 +0200)]
[mlir] Extended Liveness analysis to support nested regions.
The current Liveness analysis does not support operations with nested regions.
This causes issues when querying liveness information about blocks nested within
operations. Furthermore, the live-in and live-out sets are not computed properly
in these cases.
Differential Revision: https://reviews.llvm.org/D77714
Sanjay Patel [Thu, 23 Apr 2020 13:59:41 +0000 (09:59 -0400)]
[InstCombine] substitute equivalent constant to reduce logic-of-icmps
(X == C) && (Y Pred1 X) --> (X == C) && (Y Pred1 C)
(X != C) || (Y Pred1 X) --> (X != C) || (Y Pred1 C)
This cooperates/overlaps with D78430, but it is a more general transform
that gets us most of the expected simplifications and several other
improvements.
http://volta.cs.utah.edu:8080/z/5gxjjc
PR45618:
https://bugs.llvm.org/show_bug.cgi?id=45618
Differential Revision: https://reviews.llvm.org/D78582
Sander de Smalen [Thu, 23 Apr 2020 14:04:12 +0000 (15:04 +0100)]
[SveEmitter] Use llvm.aarch64.sve.ld1/st1 for contiguous load/store builtins
This patch changes the codegen of the builtins for contiguous loads
to map onto the SVE specific IR intrinsics llvm.aarch64.sve.ld1/st1.
Reviewers: SjoerdMeijer, efriedma, kmclaughlin, rengolin
Reviewed By: efriedma
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78673
Pavel Labath [Mon, 20 Apr 2020 12:38:31 +0000 (14:38 +0200)]
[lldb/DWARF] Trust CU DW_AT_low/high_pc information when building address tables
Summary:
The code in DWARFCompileUnit::BuildAddressRangeTable tries hard to avoid
relying on DW_AT_low/high_pc for compile unit range information, and
this logic is a big cause of llvm/lldb divergence in the lowest layers
of dwarf parsing code.
The implicit assumption in that code is that this information (as opposed to
DW_AT_ranges) is unreliable. However, I have not been able to verify
that assumption. It is definitely not true for all present-day
compilers (gcc, clang, icc), and it was also not the case for the
historic compilers that I have been able to get a hold of (thanks Matt
Godbolt).
All compiler included in my research either produced correct
DW_AT_ranges or .debug_aranges entries, or they produced no DW_AT_hi/lo
pc at all. The detailed findings are:
- gcc >= 4.4: produces DW_AT_ranges and .debug_aranges
- 4.1 <= gcc < 4.4: no DW_AT_ranges, no DW_AT_high_pc, .debug_aranges
present. The upper version range here is uncertain as godbolt.org does
not have intermediate versions.
- gcc < 4.1: no versions on godbolt.org
- clang >= 3.5: produces DW_AT_ranges, and (optionally) .debug_aranges
- 3.4 <= clang < 3.5: no DW_AT_ranges, no DW_AT_high_pc, .debug_aranges
present.
- clang <= 3.3: no DW_AT_ranges, no DW_AT_high_pc, no .debug_aranges
- icc >= 16.0.1: produces DW_AT_ranges
- icc < 16.0.1: no functional versions on godbolt.org (some are present
but fail to compile)
Based on this analysis, I believe it is safe to start trusting
DW_AT_low/high_pc information in dwarf as well as remove the code for
manually reconstructing range information by traversing the DIE
structure, and just keep the line table fallback. The only compilers
where this will change behavior are pre-3.4 clangs, which are almost 7
years old now. However, the functionality should remain unchanged
because we will be able to reconstruct this information from the line
table, which seems to be needed for some line-tables-only scenarios
anyway (haven't researched this too much, but at least some compilers
seem to emit DW_AT_ranges even in these situations).
In addition, benchmarks showed that for these compilers computing the
ranges via line tables is noticably faster than doing so via the DIE
tree.
Other advantages include simplifying the code base, removing some
untested code (the only test changes are recent tests with overly
reduced synthetic dwarf), and increasing llvm convergence.
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D78489
Pavel Labath [Thu, 23 Apr 2020 13:55:39 +0000 (15:55 +0200)]
[lldb/Utility] Improve error_code->Status conversion
Both entities have the notion of error "namespaces". Map the errno
namespace correctly.
Simon Pilgrim [Thu, 23 Apr 2020 13:35:00 +0000 (14:35 +0100)]
[PowerPC] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 13:23:40 +0000 (14:23 +0100)]
[Mips] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 13:12:01 +0000 (14:12 +0100)]
LanaiMCTargetDesc.h - remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 13:09:22 +0000 (14:09 +0100)]
[MSP430] Remove unused forward declarations. NFC.
Tim Keith [Wed, 22 Apr 2020 23:19:38 +0000 (16:19 -0700)]
[flang] Add missing check for unresolved name
Summary:
The name in an InputItem isn't necessarily resolved if an error occurred,
so it needs to be checked.
Fixes https://bugs.llvm.org/show_bug.cgi?id=45477
Reviewers: klausler, PeteSteinfeld, DavidTruby, jdoerfert, sscalpone
Reviewed By: klausler, sscalpone
Subscribers: llvm-commits
Tags: #llvm, #flang
Differential Revision: https://reviews.llvm.org/D78685
Sanjay Patel [Thu, 23 Apr 2020 13:10:23 +0000 (09:10 -0400)]
[InstSimplify] fold and/or of compares with equality to min/max constant
I found 12 (6 if we compress the DeMorganized forms) patterns for logic-of-compares
with a min/max constant while looking at PR45510:
https://bugs.llvm.org/show_bug.cgi?id=45510
The variations on those forms multiply the test cases by 8 (unsigned/signed, swapped
compare operands, commuted logic operands).
We have partial logic to deal with these for the unsigned min (zero) case, but
missed everything else.
We are deferring the majority of these patterns to InstCombine to allow more general
handling (see D78582).
We could use ConstantRange instead of predicate+constant matching here. I don't
expect there's any noticeable compile-time impact for either form.
Here's an abuse of Alive2 to show the 12 basic signed variants of the patterns in
one function:
http://volta.cs.utah.edu:8080/z/5Vpiyg
declare void @use(i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1)
define void @src(i8 %x, i8 %y) {
%m1 = icmp eq i8 %x, 127
%c1 = icmp slt i8 %x, %y
%r1 = and i1 %m1, %c1 ; (X == MAX) && (X < Y) --> false
%m2 = icmp ne i8 %x, 127
%c2 = icmp sge i8 %x, %y
%r2 = or i1 %m2, %c2 ; (X != MAX) || (X >= Y) --> true
%m3 = icmp eq i8 %x, -128
%c3 = icmp sgt i8 %x, %y
%r3 = and i1 %m3, %c3 ; (X == MIN) && (X > Y) --> false
%m4 = icmp ne i8 %x, -128
%c4 = icmp sle i8 %x, %y
%r4 = or i1 %m4, %c4 ; (X != MIN) || (X <= Y) --> true
%m5 = icmp eq i8 %x, 127
%c5 = icmp sge i8 %x, %y
%r5 = and i1 %m5, %c5 ; (X == MAX) && (X >= Y) --> X == MAX
%m6 = icmp ne i8 %x, 127
%c6 = icmp slt i8 %x, %y
%r6 = or i1 %m6, %c6 ; (X != MAX) || (X < Y) --> X != MAX
%m7 = icmp eq i8 %x, -128
%c7 = icmp sle i8 %x, %y
%r7 = and i1 %m7, %c7 ; (X == MIN) && (X <= Y) --> X == MIN
%m8 = icmp ne i8 %x, -128
%c8 = icmp sgt i8 %x, %y
%r8 = or i1 %m8, %c8 ; (X != MIN) || (X > Y) --> X != MIN
%m9 = icmp ne i8 %x, 127
%c9 = icmp slt i8 %x, %y
%r9 = and i1 %m9, %c9 ; (X != MAX) && (X < Y) --> X < Y
%m10 = icmp eq i8 %x, 127
%c10 = icmp sge i8 %x, %y
%r10 = or i1 %m10, %c10 ; (X == MAX) || (X >= Y) --> X >= Y
%m11 = icmp ne i8 %x, -128
%c11 = icmp sgt i8 %x, %y
%r11 = and i1 %m11, %c11 ; (X != MIN) && (X > Y) --> X > Y
%m12 = icmp eq i8 %x, -128
%c12 = icmp sle i8 %x, %y
%r12 = or i1 %m12, %c12 ; (X == MIN) || (X <= Y) --> X <= Y
call void @use(i1 %r1, i1 %r2, i1 %r3, i1 %r4, i1 %r5, i1 %r6, i1 %r7, i1 %r8, i1 %r9, i1 %r10, i1 %r11, i1 %r12)
ret void
}
define void @tgt(i8 %x, i8 %y) {
%m5 = icmp eq i8 %x, 127
%m6 = icmp ne i8 %x, 127
%m7 = icmp eq i8 %x, -128
%m8 = icmp ne i8 %x, -128
%c9 = icmp slt i8 %x, %y
%c10 = icmp sge i8 %x, %y
%c11 = icmp sgt i8 %x, %y
%c12 = icmp sle i8 %x, %y
call void @use(i1 0, i1 1, i1 0, i1 1, i1 %m5, i1 %m6, i1 %m7, i1 %m8, i1 %c9, i1 %c10, i1 %c11, i1 %c12)
ret void
}
Differential Revision: https://reviews.llvm.org/D78430
Sanjay Patel [Wed, 22 Apr 2020 13:49:36 +0000 (09:49 -0400)]
[InstCombine] add test for logic-of-icmps that should simplify (D78582); NFC
Kumar Harsh [Thu, 23 Apr 2020 12:04:23 +0000 (17:34 +0530)]
Add extension links for VSCode
The clang-format docs were missing mention or links for the VSCode extension, which have been added.
Simon Pilgrim [Thu, 23 Apr 2020 12:52:36 +0000 (13:52 +0100)]
RuntimeDyldELF.h - make the object namespace explicit for ELFObjectFileBase. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 12:41:02 +0000 (13:41 +0100)]
[ObjCARC] Remove unused forward declarations. NFC.
Simon Pilgrim [Thu, 23 Apr 2020 12:10:55 +0000 (13:10 +0100)]
XCOFF.h - replace StringRef.h include with forward declaration. NFC.
Move StringRef.h include to XCOFF.cpp
Jonathan Coe [Thu, 23 Apr 2020 10:38:52 +0000 (11:38 +0100)]
[clang-format] Handle C# property accessors when parsing lines
Summary:
Improve C# `{ get; set; } = default;` formatting by handling it in the UnwrappedLineParser rather than trying to merge lines later.
Remove old logic to merge lines.
Update tests as formatting output has changed (as intended).
Reviewers: krasimir, MyDeveloperDay
Reviewed By: krasimir
Subscribers: cfe-commits
Tags: #clang-format, #clang
Differential Revision: https://reviews.llvm.org/D78642
Pavel Labath [Thu, 23 Apr 2020 11:54:11 +0000 (13:54 +0200)]
[lldb/Host] Modernize some socket functions
return Expected<Socket> instead of a Status object plus a Socket*&
argument.
Alex Richardson [Thu, 23 Apr 2020 12:02:12 +0000 (13:02 +0100)]
[UpdateTestChecks] Make generation of UTC_ARGS: comment more robust
We now use the argparse Action objects to determine the name of the flags.
This fixes cases where the key for the stored result ('dest') is not the
same as the command line flag (e.g. --enable/--disable).
Also add a test that --disabled can be part of the initial UTC_ARGS.
This is split out from D78478
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D78617
Alex Richardson [Thu, 23 Apr 2020 12:01:30 +0000 (13:01 +0100)]
Use FrameIndexTy for stack protector
Using getValueType() is not correct for architectures extended with CHERI since
we need a pointer type and not the value that is loaded. While stack
protector is useless when you have CHERI (since CHERI provides much
stronger security guarantees), we still have a test to check that we can
generate correct code for checks. Merging
b281138a1b67ca4405b77d774adc3de72742e7a2
into our tree broke this test. Fix by using TLI.getFrameIndexTy().
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D77785
Xing GUO [Thu, 23 Apr 2020 12:06:21 +0000 (20:06 +0800)]
[dsymutil][doc] Improve documentation.
This change helps improve `dsymutil` documentation.
- Add missing options
- Re-arrange options in alphabetical order
- Wrap inline options in double-back-quote
- `-v` is for `--version` not `--verbose`
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D78479
River Riddle [Thu, 23 Apr 2020 11:40:42 +0000 (04:40 -0700)]
[mlir][Standard] Allow select to use an i1 for vector and tensor values
It currently requires that the condition match the shape of the selected value, but this is only really useful for things like masks. This revision allows for the use of i1 to mean that all of the vector/tensor is selected. This also matches the behavior of LLVM select. A benefit of this change is that transformations that want to generate selects, like those on the CFG, don't have to special case vector/tensor. Previously the only way to generate a select from an i1 was to use a splat, but that doesn't support dynamically shaped/unranked tensors.
Differential Revision: https://reviews.llvm.org/D78690
River Riddle [Thu, 23 Apr 2020 11:40:33 +0000 (04:40 -0700)]
[mlir][Standard] Add support for canonicalizing branches to passthrough blocks
This revision adds support for canonicalizing the following:
```
br ^bb1
^bb1
br ^bbN(...)
br ^bbN(...)
```
Differential Revision: https://reviews.llvm.org/D78683
River Riddle [Thu, 23 Apr 2020 11:40:25 +0000 (04:40 -0700)]
[mlir][Standard] Add a canonicalization to simplify cond_br when the successors are identical
This revision adds support for canonicalizing the following:
```
cond_br %cond, ^bb1(A, ..., N), ^bb1(A, ..., N)
br ^bb1(A, ..., N)
```
If the operands to the successor are different and the cond_br is the only predecessor, we emit selects for the branch operands.
```
cond_br %cond, ^bb1(A), ^bb1(B)
%select = select %cond, A, B
br ^bb1(%select)
```
Differential Revision: https://reviews.llvm.org/D78682
River Riddle [Thu, 23 Apr 2020 11:40:16 +0000 (04:40 -0700)]
[mlir][Standard] Add canonicalization for collapsing pass through cond_br successors.
This revision adds support for the following canonicalization:
```
cond_br %cond, ^bb1, ^bb2
^bb1
br ^bbN(...)
^bb2
br ^bbK(...)
cond_br %cond, ^bbN(...), ^bbK(...)
```
Differential Revision: https://reviews.llvm.org/D78681
Simon Pilgrim [Thu, 23 Apr 2020 11:33:57 +0000 (12:33 +0100)]
[VPlan] Remove unused forward declarations. NFC.
Move VPlan.h include from VPlanVerifier.h down to VPlanVerifier.cpp
Jay Foad [Tue, 21 Apr 2020 16:15:10 +0000 (17:15 +0100)]
[AMDGPU] Use RegClass helper functions in getRegForInlineAsmConstraint.
This avoids more long lists of register classes that have to be updated
every time we add a new one. NFC.
Differential Revision: https://reviews.llvm.org/D78570
Serguei Katkov [Wed, 22 Apr 2020 08:50:04 +0000 (15:50 +0700)]
[CaptureTracking] Replace hardcoded constant to option. NFC.
The motivation is to be able to play with the option and change if it is required.
Reviewers: fedor.sergeev, apilipenko, rnk, jdoerfert
Reviewed By: fedor.sergeev
Subscribers: hiraditya, dantrushin, llvm-commits
Differential Revision: https://reviews.llvm.org/D78624
Florian Hahn [Thu, 23 Apr 2020 10:55:00 +0000 (11:55 +0100)]
[VPlan] Add & use VPValue operands for VPWidenRecipe (NFC).
This patch adds VPValue version of the instruction operands to
VPWidenRecipe and uses them during code-generation.
Similar to D76373 this reduces ingredient def-use usage by ILV as
a step towards full VPlan-based def-use relations.
Reviewers: rengolin, Ayal, gilr
Reviewed By: gilr
Differential Revision: https://reviews.llvm.org/D76992
Jay Foad [Wed, 22 Apr 2020 10:08:08 +0000 (11:08 +0100)]
[AMDGPU] Use SGPR instead of SReg classes
12994a70cf7 did this for 128-bit classes:
SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds
the additional non-allocatable TTMP registers. There's no point in
allocating SReg_128 vregs. This shrinks the size of the classes
regalloc needs to consider, which is usually good.
This patch extends it to all classes > 64 bits, for consistency.
Differential Revision: https://reviews.llvm.org/D78622
Raphael Isemann [Thu, 23 Apr 2020 10:06:27 +0000 (12:06 +0200)]
[lldb] Fix typo in breakpoint set -r description
Sander de Smalen [Thu, 23 Apr 2020 09:53:23 +0000 (10:53 +0100)]
[AArch64] Define ACLE FP conversion intrinsics with more specific predicate.
This patch changes the FP conversion intrinsics to take a predicate
that matches the number of lanes for the vector with the widest element
type as opposed to using <vscale x 16 x i1>.
For example:
```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)```
now uses <vscale x 4 x i1> instead of <vscale x 16 x i1>
And similar for:
```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)```
where the predicate now matches the wider type, so <vscale x 2 x i1>.
Reviewers: efriedma, SjoerdMeijer, paulwalker-arm, rengolin
Reviewed By: efriedma
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78402
Sander de Smalen [Thu, 23 Apr 2020 09:45:13 +0000 (10:45 +0100)]
[SveEmitter] Add builtins for FP conversions
This adds the flag IsOverloadCvt which tells CGBulitin to use
the result type and the type of the last operand as the
overloaded types for the LLVM IR intrinsic.
This also adds the flag IsFPConvert, which is needed to avoid
converting the predicate of the operation from svbool_t to
a predicate with fewer lanes, as the LLVM IR intrinsics use
the <vscale x 16 x i1> as the predicate.
Reviewers: SjoerdMeijer, efriedma
Reviewed By: efriedma
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78239
Djordje Todorovic [Thu, 23 Apr 2020 07:49:02 +0000 (09:49 +0200)]
[dexter] Require python >= 3.6
The documentation says we need python >= 3.6. Running it with an older
version, we get verbose output from python interpreter.
This patch fixes that as:
$ python2 dexter.py list-debuggers
You need python 3.6 or later to run DExTer
Differential Revision: https://reviews.llvm.org/D78621
Georgii Rymar [Wed, 22 Apr 2020 11:50:58 +0000 (14:50 +0300)]
[obj2yaml] - Zero initialize program headers. NFCI.
It allows to simplify the current code and also
might help for the code around.
It is also consistent with what we do for another headers,
e.g. section headers, elf file header etc.
Differential revision: https://reviews.llvm.org/D78627
Kazuaki Ishizaki [Thu, 23 Apr 2020 09:36:03 +0000 (18:36 +0900)]
[mlir] NFC: fix broken links in doc of operation definitions
Differential Revision: https://reviews.llvm.org/D78696
Andi-Bogdan Postelnicu [Fri, 10 Apr 2020 16:25:31 +0000 (19:25 +0300)]
[clang-tidy] Add option to use alpha checkers from clang-analyzer when using `run-clang-tidy.py`
Summary: Add option to use alpha checkers from clang-analyzer when using `run-clang-tidy.py`.
Reviewers: JonasToth
Subscribers: xazax.hun, baloghadamsoftware, a.sidorin, Szelethus, donat.nagy, dkrupp, Charusso, ASDenysPetrov, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77882
Amara Emerson [Thu, 23 Apr 2020 08:34:57 +0000 (01:34 -0700)]
[AArch64][GlobalISel] Set the current debug loc when missing in some cases.
Alexander Belyaev [Wed, 22 Apr 2020 15:23:38 +0000 (17:23 +0200)]
[MLIR] Lower GenericAtomicRMWOp to llvm.cmpxchg.
Summary:
Lowering is pretty much a copy of AtomicRMWOp -> llvm.cmpxchg
pattern.
Differential Revision: https://reviews.llvm.org/D78647
Haojian Wu [Thu, 23 Apr 2020 07:25:01 +0000 (09:25 +0200)]
Revert "clang-format: support aligned nested conditionals formatting"
This reverts
3d61b1120e8267aa39f4c9a33d618dbaec4ec6fa,
5daa25fd7a184524759b6ad065a8bd7e95aa149a
The clang-format test (FormatTest.ConfigurableUseOfTab) is failing in the buildbot:
http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/31811/steps/ninja%20check%201/logs/stdio
Craig Topper [Thu, 23 Apr 2020 05:21:54 +0000 (22:21 -0700)]
[ArgumentPromotion] Remove unnecessary getScalarType() before casting to PointerType. NFC
I don't believe this pass deals with vectors of pointers. I think
this getScalarType() was added during a mechanical opaque pointer
change of the interface to GetElementPtrInst::getIndexedType.
Kazuaki Ishizaki [Thu, 23 Apr 2020 05:28:16 +0000 (14:28 +0900)]
[mlir] NFC: Fix trivial typo under Dialects
Differential Revision: https://reviews.llvm.org/D78090
Kazuaki Ishizaki [Thu, 23 Apr 2020 05:26:07 +0000 (14:26 +0900)]
[llvm] NFC: Fix trivial typo in rst and td files
Differential Revision: https://reviews.llvm.org/D77469
Puyan Lotfi [Thu, 23 Apr 2020 04:05:08 +0000 (00:05 -0400)]
Revert "[NFC] Refactoring PropertyAttributeKind for ObjCPropertyDecl and ObjCDeclSpec."
This reverts commit
2aa044ed088ae41461ad7029c055014df6c60976.
Reverting due to bot failure in lldb.
Puyan Lotfi [Wed, 22 Apr 2020 21:32:20 +0000 (17:32 -0400)]
[NFC] Refactoring PropertyAttributeKind for ObjCPropertyDecl and ObjCDeclSpec.
This is a code clean up of the PropertyAttributeKind and
ObjCPropertyAttributeKind enums in ObjCPropertyDecl and ObjCDeclSpec that are
exactly identical. This non-functional change consolidates these enums
into one. The changes are to many files across clang (and comments in LLVM) so
that everything refers to the new consolidated enum in DeclObjCCommon.h.
Differential Revision: https://reviews.llvm.org/D77233
Sean Silva [Thu, 23 Apr 2020 02:56:59 +0000 (19:56 -0700)]
Isolate zero_whitespace parser test into its own file.
Summary:
This test is in a different file because it contains a literal NUL
character, which causes various tools to treat it as a binary file.
Hence it is useful to have this test kept in a separate, rarely-changing
file.
Differential Revision: https://reviews.llvm.org/D78689
Aditya Nandakumar [Thu, 23 Apr 2020 00:15:00 +0000 (17:15 -0700)]
[GISel]: Relax opcode checking at the top level to enable CSE
Loosen the restriction on what kinds of opcodes can be CSEd as
targets may want to CSE some generic target specific pseudos.
NFC as far as this change is concerned as CSEConfig still pretty much is
a subset of this check.
Differential Revision: https://reviews.llvm.org/D78684
Aaron Puchert [Thu, 23 Apr 2020 00:26:02 +0000 (02:26 +0200)]
[NFC] Correct typo in comment after D76038
Vedant Kumar [Fri, 17 Apr 2020 23:01:25 +0000 (16:01 -0700)]
[AArch64CollectLOH] Debug insts should not break LOH collection [14/14]
Fix an issue where the presence of debug instructions could break
collection of linker optimization hints.
Vedant Kumar [Thu, 16 Apr 2020 22:03:31 +0000 (15:03 -0700)]
[AArch64PreLegalizerCombiner] Fix debug invariance issue in matchFConstantToConstant [13/14]
Fix an issue where the FConstantToConstant combine could fail if debug
instructions were present.
Vedant Kumar [Sat, 18 Apr 2020 01:11:46 +0000 (18:11 -0700)]
[AArch64LoadStoreOptimizer] Skip debug insts during pattern matching [12/14]
Do not count the presence of debug insts against the limit set by
LdStLimit, and allow the optimizer to find matching insts by skipping
over debug insts.
Differential Revision: https://reviews.llvm.org/D78411
Vedant Kumar [Thu, 16 Apr 2020 00:49:53 +0000 (17:49 -0700)]
[AArch64ConditionOptimizer] Fix missed optimization due to debug insts [11/14]
Summary:
The findSuitableCompare method can fail if debug instructions are
present in the MBB -- fix this by using helpers to skip over debug
insts.
Reviewers: aemerson, paquette
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78265
Vedant Kumar [Thu, 16 Apr 2020 00:40:26 +0000 (17:40 -0700)]
[AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14]
Summary:
This fixes several instances in which condbr optimization was missed
due to a debug instruction appearing as a bogus NZCV clobber.
Reviewers: aemerson, paquette
Subscribers: kristof.beyls, hiraditya, jfb, danielkiss, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78264
Vedant Kumar [Thu, 16 Apr 2020 00:10:53 +0000 (17:10 -0700)]
[AArch64] Clean up assorted usage of hasOneUse/use_instructions [9/14]
Summary:
Use the variants of these APIs which skip over debug instructions. This
is mostly a cleanup, but it does fix a debug-variance issue which causes
addsub-shifted.ll and addsub_ext.ll to fail when debug info is inserted
by -mir-debugify.
Reviewers: aemerson, paquette
Subscribers: kristof.beyls, hiraditya, jfb, danielkiss, llvm-commits, aprantl
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78262
Vedant Kumar [Tue, 14 Apr 2020 21:27:48 +0000 (14:27 -0700)]
[AArch64ConditionalCompares] Ignore debug insts in findConvertibleCompare [8/14]
Summary:
Fix an issue where the presence of debug info could disable the ccmp
optimization due to findConvertibleCompare failing too early (the error
is "Can't create ccmp with multiple uses", where the "use" is a
DBG_VALUE inst).
Depends on D78151.
Reviewers: t.p.northover, paquette, aemerson
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78156
Vedant Kumar [Tue, 14 Apr 2020 21:50:03 +0000 (14:50 -0700)]
[AArch64InstrInfo] Ignore debug insts in areCFlagsAccessedBetweenInstrs [7/14]
Summary:
Fix an issue where the presence of debug info could disable a peephole
optimization due to areCFlagsAccessedBetweenInstrs returning the wrong
result.
In test/CodeGen/AArch64/arm64-csel.ll, the issue was found in the
function @foo5, in which the first compare could successfully be
optimized but not the second.
Reviewers: t.p.northover, eastig, paquette
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, dsanders, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78157
Vedant Kumar [Thu, 16 Apr 2020 00:54:46 +0000 (17:54 -0700)]
[AArch64InstrInfo] Ignore debug insts in canInstrSubstituteCmpInstr [6/14]
Summary:
Fix an issue where the presence of debug info could disable a peephole
optimization in optimizeCompareInstr due to canInstrSubstituteCmpInstr
returning the wrong result.
Depends on D78137.
Reviewers: t.p.northover, eastig, paquette
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, llvm-commits, dsanders
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78151
Vedant Kumar [Thu, 16 Apr 2020 22:23:57 +0000 (15:23 -0700)]
[GIsel][LegalizerHelper] Account for debug insts when creating mem libcalls [5/14]
Summary:
While lowering memory intrinsics, GIsel attempts to form a tail call to
a library routine.
There might be a DBG_LABEL or something after the intrinsic call,
though: in that case, GIsel should still be able to form the tail call,
and should also delete the debug insts after the tail call as the
transform makes them invalid.
Reviewers: dsanders, aemerson
Subscribers: hiraditya, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78335
Vedant Kumar [Wed, 15 Apr 2020 23:32:25 +0000 (16:32 -0700)]
[GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/14]
Summary:
Fix an issue which could result in ElideBrByInvertingCond or
CombineIndexedLoadStore being missed when debug info is present. In both
cases the fix is s/hasOneUse/hasOneNonDbgUse/.
Reviewers: aemerson, dsanders
Subscribers: hiraditya, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78254
Vedant Kumar [Wed, 15 Apr 2020 23:01:31 +0000 (16:01 -0700)]
[GIsel][CombinerHelper] Don't consider debug insts in dominance queries [3/14]
Summary:
This fixes several issues where the presence of debug instructions could
disable certain combines, due to dominance queries finding uses/defs that
don't actually exist.
Reviewers: dsanders, fhahn, paquette, aemerson
Subscribers: hiraditya, arphaman, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78253
Vedant Kumar [Tue, 14 Apr 2020 18:35:25 +0000 (11:35 -0700)]
[GISel][RegBankSelect] Hide assertion failure from LLT::getScalarSizeInBits [2/14]
Summary:
It looks like RegBankSelect can try to assign a bank based on a
DBG_VALUE instead of ignoring it. This eventually leads to an assert
in AArch64RegisterBankInfo::getInstrMapping because there is some info
missing from the DBG_VALUE MachineOperand (I see: `Assertion failed:
(RawData != 0 && "Invalid Type"), function getScalarSizeInBits`).
I'm not 100% sure it's safe to insert DBG_VALUE instructions right
before RegBankSelect (that's what -debugify-and-strip-all-safe is
doing). Any advice appreciated.
Depends on D78135.
Reviewers: ab, qcolombet, dsanders, aprantl
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78137
Vedant Kumar [Thu, 16 Apr 2020 00:54:39 +0000 (17:54 -0700)]
[MachineBasicBlock] Add helpers for skipping debug instructions [1/14]
Summary:
These helpers are exercised by follow-up commits in this patch series,
which is all about removing CodeGen differences with vs. without debug
info in the AArch64 backend.
Reviewers: fhahn, aprantl, jpaquette, paquette
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78260
Vedant Kumar [Tue, 14 Apr 2020 23:02:25 +0000 (16:02 -0700)]
[ARM] Mark some tests as not safe for -debugify-and-strip-all, NFC
These tests contain debug instructions which get checked, so we can't
insert synthetic debug info and expect the tests to pass.
The rest of the ARM backend tests appear to be fair game.
Vedant Kumar [Sat, 18 Apr 2020 00:53:14 +0000 (17:53 -0700)]
[Debugify] Do not require named metadata to be present when stripping
This allows -mir-strip-debug to be run without -debugify having run
before.
Vedant Kumar [Mon, 13 Apr 2020 23:15:37 +0000 (16:15 -0700)]
[MachineDebugify] Insert synthetic DBG_VALUE instructions
Summary:
Teach MachineDebugify how to insert DBG_VALUE instructions. This can
help find bugs causing CodeGen differences when debug info is present.
DBG_VALUE instructions are only emitted when -debugify-level is set to
locations+variables.
There is essentially no attempt made to match up DBG_VALUE register
operands with the local variables they ought to correspond to. I'm not
sure how to improve the situation. In some cases (MachineMemOperand?)
it's possible to find the IR instruction a MachineInstr corresponds to,
but in general this seems to call for "undoing" the work done by ISel.
Reviewers: dsanders, aprantl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78135
Jonas Devlieghere [Wed, 22 Apr 2020 23:51:56 +0000 (16:51 -0700)]
[lldb/Target] Avoid race between Communication::Disconnect calls.
Avoid a race between the Disconnect call in `Communication::ReadThread`
and the one in `Process::ShouldBroadcastEvent` by reordering the calls
to Disconnect and StopReadThread in `Process::ShouldBroadcastEvent`.
In D77295 Pavel suggested that that might explain the broken pipe I was
seeing. Indeed, changing the order resolved the issue.
Muhammad Omair Javaid [Wed, 22 Apr 2020 23:35:30 +0000 (04:35 +0500)]
Revert "get rid of PythonInteger::GetInteger()"
This reverts commit
7375212172951d2fc283c81d03c1a8588c3280c6.
This causes multiple test failures on LLDB AArch64 Linux buildbot.
http://lab.llvm.org:8011/builders/lldb-aarch64-ubuntu/builds/3695
Differential Revision: https://reviews.llvm.org/D78462
Mark Lacey [Mon, 30 Mar 2020 19:52:14 +0000 (12:52 -0700)]
Add a policy to enable computing SchedDFSResult.
Summary:
Make GenericScheduler compute SchedDFSResult on initialization if
the policy is set. This makes it possible to create classes
that extend GenericScheduler and rely on the results of SchedDFSResult,
e.g. to perform subtree scheduling.
NFC unless the policy is set.
Subscribers: MatzeB, hiraditya, javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78432
Juneyoung Lee [Wed, 22 Apr 2020 23:08:16 +0000 (08:08 +0900)]
[ValueTracking] Let analyses assume a value cannot be partially poison
Summary:
This is RFC for fixes in poison-related functions of ValueTracking.
These functions assume that a value can be poison bitwisely, but the semantics
of bitwise poison is not clear at the moment.
Allowing a value to have bitwise poison adds complexity to reasoning about
correctness of optimizations.
This patch makes the analysis functions simply assume that a value is
either fully poison or not, which has been used to understand the correctness
of a few previous optimizations.
The bitwise poison semantics seems to be only used by these functions as well.
In terms of implementation, using value-wise poison concept makes existing
functions do more precise analysis, which is what this patch contains.
Reviewers: spatel, lebedev.ri, jdoerfert, reames, nikic, nlopes, regehr
Reviewed By: nikic
Subscribers: fhahn, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78503
Alexander Shaposhnikov [Wed, 22 Apr 2020 23:05:07 +0000 (16:05 -0700)]
[llvm-objcopy][MachO] Add missing license header
Add missing license header to Object.cpp.
NFC.
Juneyoung Lee [Wed, 22 Apr 2020 23:06:53 +0000 (08:06 +0900)]
Revert "RFC: [ValueTracking] Let analyses assume a value cannot be partially poison"
This reverts commit
80faa8c3af856df93faf909f21cdcc397bed068f.
Juneyoung Lee [Mon, 20 Apr 2020 15:35:45 +0000 (00:35 +0900)]
RFC: [ValueTracking] Let analyses assume a value cannot be partially poison
Summary:
This is RFC for fixes in poison-related functions of ValueTracking.
These functions assume that a value can be poison bitwisely, but the semantics
of bitwise poison is not clear at the moment.
Allowing a value to have bitwise poison adds complexity to reasoning about
correctness of optimizations.
This patch makes the analysis functions simply assume that a value is
either fully poison or not, which has been used to understand the correctness
of a few previous optimizations.
The bitwise poison semantics seems to be only used by these functions as well.
In terms of implementation, using value-wise poison concept makes existing
functions do more precise analysis, which is what this patch contains.
Reviewers: spatel, lebedev.ri, jdoerfert, reames, nikic, nlopes, regehr
Reviewed By: nikic
Subscribers: fhahn, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78503