platform/kernel/u-boot.git
7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Fri, 16 Dec 2016 17:46:36 +0000 (12:46 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoKconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig
Fabio Estevam [Thu, 15 Dec 2016 21:30:40 +0000 (19:30 -0200)]
Kconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig

Move USE_ARCH_MEMCPY/MEMSET options to Kconfig.

Make it "default y" for the ARMv7 architecture and make it
depend on !ARM64 && !SPL.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
7 years agoARMv8: LS1043A: Enable LS1043A default PSCI support
macro.wave.z@gmail.com [Thu, 8 Dec 2016 03:58:26 +0000 (11:58 +0800)]
ARMv8: LS1043A: Enable LS1043A default PSCI support

A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8: Setup PSCI memory and device tree
macro.wave.z@gmail.com [Thu, 8 Dec 2016 03:58:25 +0000 (11:58 +0800)]
ARMv8: Setup PSCI memory and device tree

Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8: Add basic PSCI framework
macro.wave.z@gmail.com [Thu, 8 Dec 2016 03:58:24 +0000 (11:58 +0800)]
ARMv8: Add basic PSCI framework

This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8: Enable SMC instruction
macro.wave.z@gmail.com [Thu, 8 Dec 2016 03:58:23 +0000 (11:58 +0800)]
ARMv8: Enable SMC instruction

PSCI implementation needs the SMC instruction to be enabled.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8: Add secure sections for PSCI text and data
macro.wave.z@gmail.com [Thu, 8 Dec 2016 03:58:22 +0000 (11:58 +0800)]
ARMv8: Add secure sections for PSCI text and data

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and
ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here
in Kconfig too.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
macro.wave.z@gmail.com [Thu, 8 Dec 2016 03:58:21 +0000 (11:58 +0800)]
ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition

NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agodriver: fsl-mc: qbman: Add QBMAN 4.1 support
Priyanka Jain [Wed, 7 Dec 2016 06:34:05 +0000 (12:04 +0530)]
driver: fsl-mc: qbman: Add QBMAN 4.1 support

LS2080A SoC family has QBMAN ver 4.0 whereas newer
SoCs like LS2088A, LS1088A has QBMAN ver 4.1
QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively.

Add support of
to check QBMAN version based on SoC SVR
update dqrr_size accordingly
update code to support larger dqrr_size

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043a: dts: Fix the ranges table of IFC node
Hou Zhiqiang [Tue, 6 Dec 2016 07:27:49 +0000 (15:27 +0800)]
armv8: ls1043a: dts: Fix the ranges table of IFC node

Corrected the ranges table of the IFC node.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043ardb: dts: Fix the unit-address of some I2C device nodes
Hou Zhiqiang [Tue, 6 Dec 2016 07:27:48 +0000 (15:27 +0800)]
armv8: ls1043ardb: dts: Fix the unit-address of some I2C device nodes

The unit-address should be the same as the I2C address of the device.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl/board/ddr: optimize board-specific cpo for erratum A-009942
Shengzhou Liu [Tue, 15 Nov 2016 09:15:21 +0000 (17:15 +0800)]
fsl/board/ddr: optimize board-specific cpo for erratum A-009942

Optimize board-specific cpo for erratum A-009942 on b4860qds,
ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb,
t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb,
t4qds, t4rdb boards.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl/ddr: Enable erratum-a009942 workaround for B/T-series
Shengzhou Liu [Tue, 15 Nov 2016 09:15:20 +0000 (17:15 +0800)]
fsl/ddr: Enable erratum-a009942 workaround for B/T-series

Enable ERRATUM_A009942 workaround for B-series and T-series platforms.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agotravis-ci: Add zynq_zc702 target support
Michal Simek [Wed, 14 Dec 2016 08:47:23 +0000 (09:47 +0100)]
travis-ci: Add zynq_zc702 target support

It depends on qemu v2.8.0-rc3 which includes device loader property.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
7 years agoMAINTAINERS: DFU: Change e-mail address for DFU maintainer
Lukasz Majewski [Mon, 12 Dec 2016 16:07:07 +0000 (17:07 +0100)]
MAINTAINERS: DFU: Change e-mail address for DFU maintainer

Despite I leave Samsung by the end of the year, I'm going to maintain DFU
in u-boot.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
7 years agoMAINTAINERS: ONENAND: MTD: Mark Samsung's OneNAND as orphaned
Lukasz Majewski [Mon, 12 Dec 2016 15:18:30 +0000 (16:18 +0100)]
MAINTAINERS: ONENAND: MTD: Mark Samsung's OneNAND as orphaned

Since I leave Samsung by the end of the year, I will not have access to
OneNAND devices anymore.

Hence the custodian position has been marked as "Orphaned".

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
7 years agoMerge git://www.denx.de/git/u-boot-marvell
Tom Rini [Mon, 12 Dec 2016 12:19:28 +0000 (07:19 -0500)]
Merge git://www.denx.de/git/u-boot-marvell

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-uniphier
Tom Rini [Mon, 12 Dec 2016 12:18:53 +0000 (07:18 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier

7 years agoarm64: mvebu: Enable hush parser in A8K default configuration
Konstantin Porotchkin [Sun, 4 Dec 2016 16:34:15 +0000 (18:34 +0200)]
arm64: mvebu: Enable hush parser in A8K default configuration

Enable hush parser in Armada-7040 and Armada-8040 DB default
configurations.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Enable PCIe support in Armada-7040 configuration
Konstantin Porotchkin [Sun, 4 Dec 2016 16:34:14 +0000 (18:34 +0200)]
arm64: mvebu: Enable PCIe support in Armada-7040 configuration

Enable PCIe bus support in Armada-7040 DB default configuration

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Add L3 cache flush functionality to A8K family
Konstantin Porotchkin [Sun, 4 Dec 2016 16:34:13 +0000 (18:34 +0200)]
arm64: mvebu: Add L3 cache flush functionality to A8K family

Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Enable pin control support in A8K default config
Konstantin Porotchkin [Thu, 8 Dec 2016 10:22:32 +0000 (12:22 +0200)]
arm64: mvebu: Enable pin control support in A8K default config

Enable mvebu pin control support in the default configuration
files for Armada-7040 and Armada-8040 development boards

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Enable BUBT command support in A8K default config
Konstantin Porotchkin [Thu, 8 Dec 2016 10:22:31 +0000 (12:22 +0200)]
arm64: mvebu: Enable BUBT command support in A8K default config

Enable mvebu "bubt" command support in the default configuration
file for Armada-7040 and Armada-8040 development boards

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Add pin control nodes to A8K family DTS files
Konstantin Porotchkin [Thu, 8 Dec 2016 10:22:30 +0000 (12:22 +0200)]
arm64: mvebu: Add pin control nodes to A8K family DTS files

Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: pinctrl: Add pin control driver for A8K family
Konstantin Porotchkin [Thu, 8 Dec 2016 10:22:29 +0000 (12:22 +0200)]
arm64: mvebu: pinctrl: Add pin control driver for A8K family

Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Add bubt command for flash image burn
Konstantin Porotchkin [Thu, 8 Dec 2016 10:22:28 +0000 (12:22 +0200)]
arm64: mvebu: Add bubt command for flash image burn

Add support for mvebu bubt command for flash image
load, check and burn on boot device.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Modify the A8K SPI and I2C config in DTS
Konstantin Porotchkin [Thu, 8 Dec 2016 10:22:27 +0000 (12:22 +0200)]
arm64: mvebu: Modify the A8K SPI and I2C config in DTS

Align the Armada-8040-db and Armada-7040-db SPI and I2C
DTS settings with latest DB settings:
- 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO)
- 8040-db: disable cps_i2c0 on CP1
- 8040-db: enable spi1 on CP1 (the new location of the boot flash)
  The spi1 on CP1 is aliased as spi0 since this is the way
  the driver enumerates it.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoARM: uniphier: remove BLK select
Masahiro Yamada [Sat, 10 Dec 2016 01:52:25 +0000 (10:52 +0900)]
ARM: uniphier: remove BLK select

This is a user configurable option, but "select BLK" forces users to
enable it.

Even with this commit, BLK is still enabled by "default y if DM_MMC"
for UniPhier SoCs; the difference is users can disable it if they
do not need it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: dts: uniphier: sync Device Tree with Linux
Masahiro Yamada [Mon, 5 Dec 2016 09:31:39 +0000 (18:31 +0900)]
ARM: dts: uniphier: sync Device Tree with Linux

Sync with the latest kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoimgtec: Update MAINTAINERS for more config files
Tom Rini [Fri, 9 Dec 2016 14:28:37 +0000 (09:28 -0500)]
imgtec: Update MAINTAINERS for more config files

Cover all of the boston and malta variations.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoarm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Jyri Sarha [Fri, 9 Dec 2016 10:29:13 +0000 (12:29 +0200)]
arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agocalimain: Update maintainers and their email addresses
Christian Riesch [Thu, 8 Dec 2016 22:56:37 +0000 (23:56 +0100)]
calimain: Update maintainers and their email addresses

Signed-off-by: Christian Riesch <christian@riesch.at>
Cc: Manfred Rudigier <manfred.rudigier@omicronenergy.com>
Cc: Christoph RĂ¼disser <christoph.ruedisser@omicronenergy.com>
7 years agoARM: uniphier: disable CONFIG_ARCH_FIXUP_FDT_MEMORY
Masahiro Yamada [Mon, 5 Dec 2016 09:31:38 +0000 (18:31 +0900)]
ARM: uniphier: disable CONFIG_ARCH_FIXUP_FDT_MEMORY

Do not overwrite the memory nodes in the kernel DT where some parts
of the memory region might be carved out.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: remove unneeded parentheses
Masahiro Yamada [Mon, 5 Dec 2016 09:31:37 +0000 (18:31 +0900)]
ARM: uniphier: remove unneeded parentheses

Just a cosmetic cleanup.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: remove unneeded initializer
Masahiro Yamada [Mon, 5 Dec 2016 09:31:36 +0000 (18:31 +0900)]
ARM: uniphier: remove unneeded initializer

This will be used to store the return value of readl().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agotravis-ci: Switch to building QEMU
Tom Rini [Wed, 7 Dec 2016 16:20:40 +0000 (11:20 -0500)]
travis-ci: Switch to building QEMU

First, there are a number of features in newer QEMU that will allow us
to test a wider range of platforms, so we want to use at least v2.8.0.
Second, making use of a PPA for QEMU fails from time to time.  So we
change to checking out and building a copy of QEMU when we know that we
are going to use test.py and need QEMU to be installed.  This adds
around 4 minutes per test.py job that we run.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agotools: mkimage: Use fstat instead of stat to avoid malicious hacks
Michal Simek [Tue, 6 Dec 2016 16:17:01 +0000 (17:17 +0100)]
tools: mkimage: Use fstat instead of stat to avoid malicious hacks

The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e8015509312240b1ee15f2ff74510939a45d)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).

Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c2a28360029c1c48247648fac4455c9)
where file wasn't checked that it is regular file.

Reported-by: Coverity (CID: 154711, 154712)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodavinci: omapl138_lcdk: boot from zImage
Fabien Parent [Tue, 6 Dec 2016 14:45:09 +0000 (15:45 +0100)]
davinci: omapl138_lcdk: boot from zImage

Stop booting legacy uImage and now boot zImage.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodefconfigs: am57xx_hs_evm: Add default OPTEE load address
Andrew F. Davis [Mon, 5 Dec 2016 22:21:26 +0000 (16:21 -0600)]
defconfigs: am57xx_hs_evm: Add default OPTEE load address

Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current AM57xx EVMs.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodefconfigs: dra7xx_hs_evm: Add default OPTEE load address
Andrew F. Davis [Mon, 5 Dec 2016 22:21:25 +0000 (16:21 -0600)]
defconfigs: dra7xx_hs_evm: Add default OPTEE load address

Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current DRA7xx EVMs.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodavinci: omapl138_lcdk: fix bad NAND ECC config
Fabien Parent [Mon, 5 Dec 2016 18:15:21 +0000 (19:15 +0100)]
davinci: omapl138_lcdk: fix bad NAND ECC config

The configuration used to error correction was not in line with what
linux and the ROM code is using. Fix it by using the correct
configuration. Now u-boot and the SPL are able to read correctly
anything written by them.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodavinci: omapl138_lcdk: increase u-boot load size
Fabien Parent [Mon, 5 Dec 2016 18:15:20 +0000 (19:15 +0100)]
davinci: omapl138_lcdk: increase u-boot load size

A size of 0x200 seems way too short for u-boot. Increase the size
to 512k.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agocmd: pci: add option to parse and display BAR information
Yehuda Yitschak [Thu, 1 Dec 2016 15:14:18 +0000 (17:14 +0200)]
cmd: pci: add option to parse and display BAR information

Currently the PCI command only allows to see the BAR register
values but not the size and actual base address.
This little extension parses the BAR registers and displays
the base, size and type of each BAR.

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agospl: sandbox: Drop spl_board_announce_boot_device()
Simon Glass [Wed, 30 Nov 2016 22:30:56 +0000 (15:30 -0700)]
spl: sandbox: Drop spl_board_announce_boot_device()

This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: uniphier: Drop spl_board_announce_boot_device()
Simon Glass [Wed, 30 Nov 2016 22:30:55 +0000 (15:30 -0700)]
spl: uniphier: Drop spl_board_announce_boot_device()

This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: sunxi: Drop spl_board_announce_boot_device()
Simon Glass [Wed, 30 Nov 2016 22:30:54 +0000 (15:30 -0700)]
spl: sunxi: Drop spl_board_announce_boot_device()

This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: Drop announce_boot_device()
Simon Glass [Wed, 30 Nov 2016 22:30:53 +0000 (15:30 -0700)]
spl: Drop announce_boot_device()

This task can be handled by inline code now. Drop this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: Pass the loader into spl_load_image()
Simon Glass [Wed, 30 Nov 2016 22:30:52 +0000 (15:30 -0700)]
spl: Pass the loader into spl_load_image()

Rather than have this function figure out the correct loader again, pass
it in as a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: Move the loading code into its own function
Simon Glass [Wed, 30 Nov 2016 22:30:51 +0000 (15:30 -0700)]
spl: Move the loading code into its own function

Create a boot_from_devices() function to handle trying each device. This
helps to reduce the size of the already-large board_init_r() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: Add a name to the SPL load-image methods
Simon Glass [Wed, 30 Nov 2016 22:30:50 +0000 (15:30 -0700)]
spl: Add a name to the SPL load-image methods

It is useful to name each method so that we can print out this name when
using the method. Currently this happens using a separate function. In
preparation for unifying this, add a name to each method.

The name is only available if we have libcommon support (i.e can use
printf()).

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agospl: Use a single underscore in the SPL_LOAD_IMAGE_METHOD() macro
Simon Glass [Wed, 30 Nov 2016 22:30:49 +0000 (15:30 -0700)]
spl: Use a single underscore in the SPL_LOAD_IMAGE_METHOD() macro

A double underscore is normally reserved for compiler predefines. Use a
single underscore instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoam57xx: Set tps659038 PMIC GPIO7 pad mux value to POWERHOLD
Keerthy [Wed, 30 Nov 2016 09:32:53 +0000 (15:02 +0530)]
am57xx: Set tps659038 PMIC GPIO7 pad mux value to POWERHOLD

The GPIO7 pad mux should be programmed to POWERHOLD value
as per board design. In cases where the PMIC is shut off the
mux is set to GPIO7 mode. So during initialization to be on the
safer side set the mode to POWERHOLD.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: omap5_uevm_defconfig: Enable LPAE mode
Keerthy [Wed, 30 Nov 2016 09:31:57 +0000 (15:01 +0530)]
configs: omap5_uevm_defconfig: Enable LPAE mode

Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: armv7: add us timer for bootstage
Patrick Delaunay [Tue, 22 Nov 2016 16:31:33 +0000 (17:31 +0100)]
arm: armv7: add us timer for bootstage

solve issue when bootstage is used with armV7 generic timer
first call of timer_get_boot_us() use the function get_timer()
before timer initialization (arch.timer_rate_hz = 0)
=> div by 0

Commit-notes

When I activate bootstage on ARMV7 architecture with platform
using the generic armv7 timer defined in file
./arch/arm/cpu/armv7m/timer.c

I have a issue because gd->arch.timer_rate_hz = 0

For me the get_timer() function should not used before timer_init
(which initialize gd->arch.timer_rate_hz) at least for the ARMV7
timer.

But in the init sequence, the first bootstage fucntion is called
before timer_init and this function use the timer function.

For me it is a error in the generic init sequence :
mark_bootstage is called before timer_init.

static init_fnc_t init_sequence_f[] = {
....
    arch_cpu_init_dm,
    mark_bootstage,        /* need timer, go after init dm */
...
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
        defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
        defined(CONFIG_SPARC)
    timer_init,        /* initialize timer */
#endif
.......

To solve the issue for all the paltform, we can move timer_init()
call just before mark_bootstage() in this array...

It should be ok for ARMV7 but I don't sure for other platform
impacted
- the other ARM platform or ARMV7 wich don't use generic timer
- MIPS BLACKFIN NDS32 or SPARC

and I don't sure of impact for other function called
(board_early_init_f for example....)

=> This patch solve issue only in timer armv7
   get_boot_us() can be called everytime without div by 0 issue
   (gd->arch.timer_rate_hz is not used)

END

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
7 years agoRevert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"
Tom Rini [Fri, 9 Dec 2016 12:56:54 +0000 (07:56 -0500)]
Revert "Merge branch 'master' of git://denx.de/git/u-boot-microblaze"

This reverts commit 3edc0c252257e4afed163a3a74aba24a5509b198, reversing
changes made to bb135a0180c31fbd7456021fb9700b49bba7f533.

7 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Fri, 9 Dec 2016 12:10:39 +0000 (07:10 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze

7 years agonet/phy/vitesse: Rework RGMII skew configuration for VSC8601
Alex [Tue, 22 Nov 2016 18:55:13 +0000 (10:55 -0800)]
net/phy/vitesse: Rework RGMII skew configuration for VSC8601

The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.

Tested on custom board with AM3352 SOC and VSC801 PHY.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: usb: r8152: Use ALLOC_CACHE_ALIGN_BUFFER() to allocate the buffers
Stefan Roese [Tue, 22 Nov 2016 15:14:23 +0000 (16:14 +0100)]
net: usb: r8152: Use ALLOC_CACHE_ALIGN_BUFFER() to allocate the buffers

Testing on theadorable (Armada XP) has shown, that using this driver
results in many cache misaligned warning, such as:

CACHE: Misaligned operation at range [7fabd8fc7fabd900]

This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the
buffers on a cache aligned boundary. This fixes all warnings seen on the
Armada XP platform.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ted Chen <tedchen@realtek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: fman: fix 2.5G SGMII settings
shaohui xie [Tue, 15 Nov 2016 06:36:47 +0000 (14:36 +0800)]
net: fman: fix 2.5G SGMII settings

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: phy: realtek: Only force master mode on rtl8211b/c
oliver@schinagl.nl [Tue, 8 Nov 2016 16:38:59 +0000 (17:38 +0100)]
net: phy: realtek: Only force master mode on rtl8211b/c

Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.

The bug that define tried to solve was a buggy PLL in the RTL8211C only.

The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: phy: realtek: make define more consistent
oliver@schinagl.nl [Tue, 8 Nov 2016 16:38:58 +0000 (17:38 +0100)]
net: phy: realtek: make define more consistent

All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: phy: realtek: Use the BIT() macro
oliver@schinagl.nl [Tue, 8 Nov 2016 16:38:57 +0000 (17:38 +0100)]
net: phy: realtek: Use the BIT() macro

The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: phy: micrel: Fix error handling
Marek Vasut [Mon, 14 Nov 2016 14:08:42 +0000 (15:08 +0100)]
net: phy: micrel: Fix error handling

Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.

drivers/net/phy/micrel.c: In function â€˜ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this â€˜for’ clause does not guard... [-Wmisleading-indentation]
  for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
  ^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the â€˜for’
   if (ret)
   ^~
drivers/net/phy/micrel.c: In function â€˜ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this â€˜for’ clause does not guard... [-Wmisleading-indentation]
  for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
  ^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the â€˜for’
   if (ret)
   ^~

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: xilinx: Use mdio_register_seq() to support multiple instances
Michal Simek [Thu, 8 Dec 2016 09:25:44 +0000 (10:25 +0100)]
net: xilinx: Use mdio_register_seq() to support multiple instances

axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.

Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>

7 years agocommon: miiphyutil: Add helper function for mdio bus name
Michal Simek [Thu, 8 Dec 2016 09:06:26 +0000 (10:06 +0100)]
common: miiphyutil: Add helper function for mdio bus name

The most of ethernet drivers are using this mdio registration sequence.
strcpy(priv->bus->name, "emac");
mdio_register(priv->bus);
Where driver can be used only with one MDIO bus because only unique
name should be used.

Other drivers are using unique device name for MDIO registration to
support multiple instances.
snprintf(priv->bus->name, sizeof(bus->name), "%s", name);

With DM dev->seq is used more even in logs
(like random MAC address generation:
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
       dev->name, dev->seq, pdata->enetaddr);
)
where eth%d prefix is used.

Simplify driver code to register mdio device with dev->seq number
to simplify mdio registration and reduce code duplication across
all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
For example:

Board: Xilinx Zynq
Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id

Warning: ethernet@e000b000 (eth0) using random MAC address -
7a:fc:90:53:6a:41
eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr ffffffff, interface
rgmii-id

Warning: ethernet@e000c000 (eth3) using random MAC address -
1a:ff:d7:1a:a1:b2
, eth3: ethernet@e000c000
** Bad device size - mmc 0 **
Checking if uenvcmd is set ...
Hit any key to stop autoboot:  0
Zynq> mdio list
eth0:
17 - Marvell 88E1111S <--> ethernet@e000b000
eth3:
17 - Marvell 88E1111S <--> ethernet@e000c000
Zynq>

7 years agoARM64: zynqmp: Add updated psu_init_gpl* files
Michal Simek [Wed, 30 Nov 2016 10:09:56 +0000 (11:09 +0100)]
ARM64: zynqmp: Add updated psu_init_gpl* files

With origin files there was an issue with serdes setting for SCSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
7 years agozynqmp works
Michal Simek [Tue, 6 Dec 2016 15:31:53 +0000 (16:31 +0100)]
zynqmp works

7 years agoARM: zynq: Replace dram_init* functions with board_init_f safe ones
Nathan Rossi [Sun, 4 Dec 2016 09:33:22 +0000 (19:33 +1000)]
ARM: zynq: Replace dram_init* functions with board_init_f safe ones

The dram_init* functions for the zynq board are not safe for use from
the board_init_f stage due to its use of the 'tmp' static variable.

This incorrect use of a static variable was causing rare issues where
the dram_init function would overwrite some parts the __rel_dyn section
which caused obscure failures.

Using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the "image" variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.

   Uncompressing Invalid Image ... Unimplemented compression type 23

It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow.

This change removes the existing code and copies the implementation of
the dram_init and dram_init_banksize from the
arch/arm/mach-uniphier/dram_init.c source. This version of these
functions does not use static variables and behaves the same (reading
banks from fdt, and using the first bank as the ram_size).

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
7 years agotravis-ci: Add zynq_zc702 target support
Michal Simek [Wed, 23 Nov 2016 09:56:00 +0000 (10:56 +0100)]
travis-ci: Add zynq_zc702 target support

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use embded option because of qemu

Use my repo till Stephen merge it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
7 years agotools: mkimage: Use fstat instead of stat to avoid malicious hacks
Michal Simek [Tue, 6 Dec 2016 15:38:13 +0000 (16:38 +0100)]
tools: mkimage: Use fstat instead of stat to avoid malicious hacks

The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e8015509312240b1ee15f2ff74510939a45d)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).

Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c2a28360029c1c48247648fac4455c9)
where file wasn't checked that it is regular file.

Reported-by: Coverity (CID: 154711, 154712)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Series-to: trini
Series-cc: u-boot

7 years agoblock: Move ceva driver to DM
Michal Simek [Thu, 8 Sep 2016 13:06:22 +0000 (15:06 +0200)]
block: Move ceva driver to DM

This patch also includes ARM64 zynqmp changes:
- Remove platform non DM initialization
- Remove hardcoded sata base address

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Series-to: sjg, agraf@suse.de
Series-cc: uboot
Series-version: 4
Series-changes: 2
- make ceva_init_sata static
- Move SATA_CEVA to defconfig
- Initalized max_lun and max_id platdata

Series-changes: 3
- Extend Kconfig help description
- sort dm.h
- Remove SPL undefinition from board file
- Fix Kconfig dependecies

7 years agodm: Add support for scsi/sata based devices
Michal Simek [Thu, 8 Sep 2016 13:06:45 +0000 (15:06 +0200)]
dm: Add support for scsi/sata based devices

All sata based drivers are bind and corresponding block
device is created. Based on this find_scsi_device() is able
to get back block device based on scsi_curr_dev pointer.

intr_scsi() is commented now but it can be replaced by calling
find_scsi_device() and scsi_scan().

scsi_dev_desc[] is commented out but common/scsi.c heavily depends on
it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol
is reassigned to a block description allocated by uclass.
There is only one block description by device now but it doesn't need to
be correct when more devices are present.

scsi_bind() ensures corresponding block device creation.
uclass post_probe (scsi_post_probe()) is doing low level init.

SCSI/SATA DM based drivers requires to have 64bit base address as
the first entry in platform data structure to setup mmio_base.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Series-changes: 2
- Use CONFIG_DM_SCSI instead of mix of DM_SCSI and DM_SATA
  Ceva sata has never used sata commands that's why keep it in
  SCSI part only.
- Separate scsi_scan() for DM_SCSI and do not change cmd/scsi.c
- Extend platdata

Series-changes: 3
- Fix scsi_scan return path
- Fix header location uclass-internal.h
- Add scsi_max_devs under !DM_SCSI
- Add new header device-internal because of device_probe()
- Redesign block device creation algorithm
- Use device_unbind in error path
- Create block device with id and lun numbers (lun was there in v2)
- Cleanup dev_num initialization in block device description
  with fixing parameters in blk_create_devicef
- Create new Kconfig menu for SATA/SCSI drivers
- Extend description for DM_SCSI
- Fix Kconfig dependencies
- Fix kernel doc format in scsi_platdata
- Fix ahci_init_one - vendor variable

Series-changes: 4
- Fix Kconfig entry
- Remove SPL ifdef around SCSI uclass
- Clean ahci_print_info() ifdef logic

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Tue, 6 Dec 2016 13:07:20 +0000 (08:07 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

7 years agousb: xhci-pci: Add DM support
Stefan Roese [Mon, 18 Jul 2016 10:51:39 +0000 (12:51 +0200)]
usb: xhci-pci: Add DM support

This patch adds DM support to the xHCI PCI driver. Enabling its use
e.g. in x86 platforms.

Status: On the congatec BayTrail SoM, xHCI still does not work
correctly with this patch. Some internal timeouts lead to resets (BUG).
Additional work is needed here. I'm posting this version as WIP so that
other developers interested in this support might use it as a start.
I might get back to it in a few weeks as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoMAINTAINERS: Fix ALTERA SOCFPGA Files
Jagan Teki [Fri, 25 Nov 2016 17:47:28 +0000 (23:17 +0530)]
MAINTAINERS: Fix ALTERA SOCFPGA Files

Replace arch/arm/cpu/armv7/socfpga/ path with
arch/arm/mach-socfpga/ and removed board file path
since board/altera has different boards with relevant
board maintainers.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
7 years agoMAINTAINERS: socfpga: update email address for Dinh Nguyen
Dinh Nguyen [Tue, 29 Nov 2016 15:03:13 +0000 (09:03 -0600)]
MAINTAINERS: socfpga: update email address for Dinh Nguyen

With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
7 years agoqts-filter.sh: strip DOS line endings and handle continuation lines
Bill Randle [Sat, 19 Nov 2016 04:23:33 +0000 (20:23 -0800)]
qts-filter.sh: strip DOS line endings and handle continuation lines

Some Altera Quartus generated files have long lines that are split with a '\' at
the end of the line. It also wOn Windows, rites files in DOS format, which can
confuse some of the processing scripts in this file. This patch solves both issues.

Signed-off-by: Bill Randle <bill.randle@gmail.com>
Cc: Marek Vasut <marex@denx.de>
7 years agoARM: socfpga: Add boot0 hook to prevent SPL corruption
Marek Vasut [Wed, 16 Nov 2016 16:20:23 +0000 (17:20 +0100)]
ARM: socfpga: Add boot0 hook to prevent SPL corruption

Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.

The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:

ffff0040 <data_abort>:
ffff0040:       ebfffffe        bl      ffff0040 <data_abort>

ffff0044 <reset>:
ffff0044:       ea000012        b       ffff0094 <save_boot_params>

ffff0048 <save_boot_params_ret>:
ffff0048:       e10f0000        mrs     r0, CPSR
ffff004c:       e200101f        and     r1, r0, #31
ffff0050:       e331001a        teq     r1, #26

Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.

Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
7 years agosocfpga: add support for Terasic DE1-SoC board
Anatolij Gustschin [Mon, 14 Nov 2016 15:07:10 +0000 (16:07 +0100)]
socfpga: add support for Terasic DE1-SoC board

Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
7 years agoPrepare v2017.01-rc1 v2017.01-rc1
Tom Rini [Mon, 5 Dec 2016 23:36:23 +0000 (18:36 -0500)]
Prepare v2017.01-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Mon, 5 Dec 2016 22:00:23 +0000 (17:00 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoarmv8: QSPI: Add AHB bus 16MB+ size support
Yuan Yao [Thu, 1 Dec 2016 02:13:52 +0000 (10:13 +0800)]
armv8: QSPI: Add AHB bus 16MB+ size support

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl/usb: enable the errata-a005697 for ls1012a
jerry.huang@nxp.com [Thu, 1 Dec 2016 03:44:25 +0000 (11:44 +0800)]
fsl/usb: enable the errata-a005697 for ls1012a

Enable the errata-a005697 for ls1012a

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agols1021a: QSPI: update the node for QSPI support
Yuan Yao [Wed, 30 Nov 2016 03:26:20 +0000 (11:26 +0800)]
ls1021a: QSPI: update the node for QSPI support

Add the name for register space and memory space.
<0x1550000 0x10000 > is the QSPI register space.
<0x40000000 0x4000000> is the QSPI memory space.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080a: Add serdes1 protocol 0x3b support
Priyanka Jain [Tue, 29 Nov 2016 11:15:05 +0000 (16:45 +0530)]
armv8: ls2080a: Add serdes1 protocol 0x3b support

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
Shengzhou Liu [Mon, 21 Nov 2016 03:36:48 +0000 (11:36 +0800)]
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum

- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl/ddr: Fix compiling warning
Shengzhou Liu [Mon, 21 Nov 2016 03:36:47 +0000 (11:36 +0800)]
fsl/ddr: Fix compiling warning

Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agotravis-ci: Build mvebu boards (arm & aarch64) in separate job
Stefan Roese [Thu, 1 Dec 2016 12:52:08 +0000 (13:52 +0100)]
travis-ci: Build mvebu boards (arm & aarch64) in separate job

Its easier to watch the output of the build process when the platforms
specific boards are grouped in a separate job. This patch adds a job
for all mvebu boards (arm and aarch64).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodavinci: omapl138_lcdk: increase PLL0 frequency
Bartosz Golaszewski [Thu, 1 Dec 2016 11:07:43 +0000 (12:07 +0100)]
davinci: omapl138_lcdk: increase PLL0 frequency

The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.

Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: baltos: enable booting from USB
Yegor Yefremov [Thu, 1 Dec 2016 11:52:18 +0000 (12:52 +0100)]
arm: baltos: enable booting from USB

First of all U-Boot would search for a USB mass storage device
with either uEnv.txt or kernel-fit.itb and boot.

If USB mass storage device is not available or doesn't provide
these files then MMC will be tried.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: baltos: active mPCIe slot
Yegor Yefremov [Thu, 1 Dec 2016 11:52:17 +0000 (12:52 +0100)]
arm: baltos: active mPCIe slot

Baltos devices provide a mPCIe slot, whose power is turned off by
default. This patch activates mPCIe slot in U-Boot, so that for example
GSM modem can be already available in user space.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: baltos: remove TI board leftover
Yegor Yefremov [Thu, 1 Dec 2016 11:52:16 +0000 (12:52 +0100)]
arm: baltos: remove TI board leftover

Remove unneeded pinmux configurations and TI EEPROM struct.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoARM: DRA7: AMxx: Make sure that the SPL always reads the configuration EEPROM
Jean-Jacques Hiblot [Thu, 1 Dec 2016 09:37:03 +0000 (10:37 +0100)]
ARM: DRA7: AMxx: Make sure that the SPL always reads the configuration EEPROM

The bootrom may corrupt the area of SRAM used to store the ti_common_eeprom
structure. This patch makes sure that it's always read after a reset, even
if a valid MAGIC number is found in the SRAM.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodm: spl: mmc: Fix EXT SPL support
Michal Simek [Thu, 1 Dec 2016 10:09:01 +0000 (11:09 +0100)]
dm: spl: mmc: Fix EXT SPL support

The patch
"dm: spl: mmc: Support CONFIG_BLK in SPL MMC"
(sha1: 87bce4e5c0b55452d70830928b2d7b98fa24d4e3)
converted FAT part of spl_mmc_do_fs_boot() but forget to update also EXT
part by 's/&mmc->block_dev/mmc_get_blk_desc(mmc)/'.
This patch is fixing compilation error when CONFIG_SPL_EXT_SUPPORT
is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoMerge git://www.denx.de/git/u-boot-i2c
Tom Rini [Mon, 5 Dec 2016 16:02:01 +0000 (11:02 -0500)]
Merge git://www.denx.de/git/u-boot-i2c

7 years agosata: sata_mv: Fix misaligned cache warnings
Stefan Roese [Fri, 18 Nov 2016 16:21:51 +0000 (17:21 +0100)]
sata: sata_mv: Fix misaligned cache warnings

This patch fixes the warnings about misaligned cache on Armada XP:

CACHE: Misaligned operation at range [7facb4007facb460]

Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Restrict memory size to a usable maximum
Stefan Roese [Fri, 11 Nov 2016 07:18:44 +0000 (08:18 +0100)]
arm64: mvebu: Restrict memory size to a usable maximum

Not all memory is mapped in the MMU. So we need to restrict the memory
size so that U-Boot does not try to access it. Also, the internal
registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB
are mapped for system memory. This is what we pass to the U-Boot
subsystem here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
7 years agoarm64: mvebu: Add PCI support to DB-88F8040 board
Stefan Roese [Thu, 27 Oct 2016 11:36:45 +0000 (13:36 +0200)]
arm64: mvebu: Add PCI support to DB-88F8040 board

This patch adds PCI support to the Marvell Armada-8K devel board.
Additionally the Intel E1000 ethernet driver is enabled so that
network support is available on this board, even without the
internal network interfaces being supported (yet).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
7 years agoarm64: mvebu: Add regions for PCI spaces to the memory map
Stefan Roese [Thu, 27 Oct 2016 11:34:03 +0000 (13:34 +0200)]
arm64: mvebu: Add regions for PCI spaces to the memory map

To use the PCIe driver, its controller memory and the PCIe regions need
to get mapped in the MMU. Otherwise these areas can't be accessed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
7 years agopci: mvebu: Add PCIe driver for Armada-8K
Shadi Ammouri [Thu, 27 Oct 2016 11:29:41 +0000 (13:29 +0200)]
pci: mvebu: Add PCIe driver for Armada-8K

This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>