Davide Italiano [Wed, 22 Nov 2017 03:04:55 +0000 (03:04 +0000)]
[SCCP] Pick the right lattice value for constants.
After the dataflow algorithm proves that an argument is constant,
it replaces it value with the integer constant and drops the lattice
value associated to the DEF.
e.g. in the example we have @f() that's called twice:
call @f(undef, ...)
call @f(2, ...)
`undef` MEET 2 = 2 so we replace the argument and all its uses with
the constant 2.
Shortly after, tryToReplaceWithConstantRange() tries to get the lattice
value for the argument we just replaced, causing an assertion.
This function is a little peculiar as it runs when we're doing replacement
and not as part of the solver but still queries the solver.
The fix is that of checking whether we replaced the value already and
get a temporary lattice value for the constant.
Thanks to Zhendong Su for the report!
Fixes PR35357.
llvm-svn: 318817
Petr Hosek [Wed, 22 Nov 2017 01:38:31 +0000 (01:38 +0000)]
[Driver] Make the use of relax relocations a per target option
The support for relax relocations is dependent on the linker and
different toolchains within the same compiler can be using different
linkers some of which may or may not support relax relocations.
Give toolchains the option to control whether they want to use relax
relocations in addition to the existing (global) build system option.
Differential Revision: https://reviews.llvm.org/D39831
llvm-svn: 318816
Erich Keane [Wed, 22 Nov 2017 00:54:01 +0000 (00:54 +0000)]
[X86] Update CPUSupports code to reuse LLVM .def file [NFC]
llvm-svn: 318815
Craig Topper [Tue, 21 Nov 2017 23:36:42 +0000 (23:36 +0000)]
[X86] Move the information about the feature bits used by compiler-rt and shared by Host.cpp to a .def file and TargetParser.h so clang can make use of it.
Since we keep Host.cpp and compiler-rt relatively in sync, clang can use this information as a proxy.
llvm-svn: 318814
Eugene Zelenko [Tue, 21 Nov 2017 23:26:08 +0000 (23:26 +0000)]
[AST] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 318813
Billy Robert O'Neal III [Tue, 21 Nov 2017 23:03:02 +0000 (23:03 +0000)]
Replace assert(true) in tests with actual asserts. Reviewed as https://reviews.llvm.org/D40324
In
a17cd7c641c34b6c4bd4845a4d4fb590cb6c238c Marshall added assert(true) to the vector<bool>::size tests, which break on C1XX:
D:\Contest\gl0qojfu.5pe\src\qa\vc\libs\libcxx\upstream\test\std\containers\sequences\vector.bool\size.pass.cpp(62): error C2220: warning treated as error - no 'object' file generated
d:\contest\gl0qojfu.5pe\src\qa\vc\libs\libcxx\upstream\test\std\containers\sequences\vector.bool\size.pass.cpp(33) : warning C6326: Potential comparison of a constant with another constant.
d:\contest\gl0qojfu.5pe\src\qa\vc\libs\libcxx\upstream\test\std\containers\sequences\vector.bool\size.pass.cpp(52) : warning C6326: Potential comparison of a constant with another constant.
The corresponding test for vector::size asserts assert(c.size() == 3);, so I changed it to do that here.
llvm-svn: 318812
Richard Trieu [Tue, 21 Nov 2017 22:53:19 +0000 (22:53 +0000)]
[OpenMP] Fix tests after r318789
Update use of __tgt_target that had some 32bit types updated to 64bit.
llvm-svn: 318811
Martin Storsjo [Tue, 21 Nov 2017 22:41:15 +0000 (22:41 +0000)]
Remove a broken win32 locale function redirection
One can't replace vsscanf(_l) with a sscanf(_l) that doesn't
take a va_list.
This has been untouched since it was added in SVN r140728, so
apparently it hasn't been used since. One reason for this mistake
originally might have been that there was no _vsscanf_l until MSVC
2015.
Since it's unused, just remove this define.
Differential Revision: https://reviews.llvm.org/D40323
llvm-svn: 318810
Aaron Ballman [Tue, 21 Nov 2017 22:24:13 +0000 (22:24 +0000)]
Silence some MSVC warnings about not all control paths returning a value; NFC.
llvm-svn: 318809
Billy Robert O'Neal III [Tue, 21 Nov 2017 22:16:57 +0000 (22:16 +0000)]
Add missing test_macros.h inclusion.
llvm-svn: 318808
Krzysztof Parzyszek [Tue, 21 Nov 2017 22:13:16 +0000 (22:13 +0000)]
[Hexagon] Add HexagonSubtarget::getVectorLength()
llvm-svn: 318807
Michael Kruse [Tue, 21 Nov 2017 22:11:10 +0000 (22:11 +0000)]
[CodeGen] Detect empty domain because of parameters context.
Isl does not allow generating isl_ast_expr from an isl_pw_aff that has an
empty domain (i.e. has no pieces). We already detected the case if the
isl_pw_aff comes with an empty domain.
isl_ast_build also considers the domain empty if it is disjoint with the
parameter context (e.g. parameters values that we exclude by runtime
versioning).
Intersect the access relation domain with the parameter context to
also detect such practically empty access domains. The effective
pointer used in the generated code is unimportand because it will never
be executed.
This fixes llvm.org/PR35362
llvm-svn: 318806
Peter Collingbourne [Tue, 21 Nov 2017 22:06:20 +0000 (22:06 +0000)]
Object: Improve COFF irsymtab comdat representation.
Change the representation of COFF comdats so that a COFF linker
is able to accurately resolve comdats between IR and native object
files. Specifically, apply name mangling to comdat names consistently
with native object files, and do not export comdats with an internal
leader because they do not affect symbol resolution.
Differential Revision: https://reviews.llvm.org/D40278
llvm-svn: 318805
Billy Robert O'Neal III [Tue, 21 Nov 2017 21:37:26 +0000 (21:37 +0000)]
Change (void) casts to TEST_IGNORE_NODISCARD, as requested by Eric. Reviewed as https://reviews.llvm.org/D40065
llvm-svn: 318804
Evandro Menezes [Tue, 21 Nov 2017 21:33:52 +0000 (21:33 +0000)]
[TableGen] Improve error reporting
When searching for a resource unit, use the reference location instead of
the definition location in case of an error.
Differential revision: https://reviews.llvm.org/D40263
llvm-svn: 318803
Kostya Kortchinsky [Tue, 21 Nov 2017 21:14:00 +0000 (21:14 +0000)]
[scudo] Make getNumberOfCPUs Fuchsia compliant v2
Summary:
This change allows Fuchsia to boot properly using the Scudo allocator.
A first version of this commit was reverted by rL317834 because it broke Android
builds for toolchains generated with older NDKs. This commit introduces a
fall back to solve that issue.
Reviewers: cryptoad, krytarowski, rnk, alekseyshl
Reviewed By: cryptoad, krytarowski, alekseyshl
Subscribers: llvm-commits, srhines, kubamracek, krytarowski
Differential Revision: https://reviews.llvm.org/D40121
llvm-svn: 318802
Krzysztof Parzyszek [Tue, 21 Nov 2017 21:05:51 +0000 (21:05 +0000)]
[Hexagon] Make sure that RDF does not remove EH_LABELs
Since EH_LABELs (and other labels) no longer have "side-effects", they
should be checked for separately.
llvm-svn: 318801
Craig Topper [Tue, 21 Nov 2017 21:05:21 +0000 (21:05 +0000)]
[X86] Allow vpclmulqdq instructions to be commuted during isel to allow load folding.
The commuting patterns for the AVX version actually still had priority over the new patterns.
llvm-svn: 318800
Craig Topper [Tue, 21 Nov 2017 21:05:18 +0000 (21:05 +0000)]
[X86] Add BITALG, VAES, VBMI2, VNNI, VPCLMULQDQ, and VPOPCNTDQ instructions to icelake CPU.
This is based on table 1-1 of the October 2017 revision of IntelĀ® Architecture Instruction Set Extensions and Future Features Programming Reference
llvm-svn: 318799
Sam McCall [Tue, 21 Nov 2017 19:37:35 +0000 (19:37 +0000)]
[clangd] avoid divide by literal zero to satisfy msvc
llvm-svn: 318798
Nirav Dave [Tue, 21 Nov 2017 19:28:13 +0000 (19:28 +0000)]
Avoid unecessary opsize byte in segment move to memory
Segment moves to memory are always 16-bit. Remove invalid 32 and 64
bit variants.
Recommiting with missing clang inline assembly test change.
Fixes PR34478.
Reviewers: rnk, craig.topper
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39847
llvm-svn: 318797
Aaron Ballman [Tue, 21 Nov 2017 19:25:38 +0000 (19:25 +0000)]
The offsetof macro is intended to work with subobjects rather than simple identifiers designating a member, making the -Wextended-offsetof diagnostic obsolete as this construct is not an extension. Implements WG14 DR496.
llvm-svn: 318796
Michael Kruse [Tue, 21 Nov 2017 19:25:26 +0000 (19:25 +0000)]
Run polly-update-format. NFC.
polly-check-format has been failing since at least r318517,
due to more than one cause.
llvm-svn: 318795
Aaron Ballman [Tue, 21 Nov 2017 19:22:34 +0000 (19:22 +0000)]
Add an AST matcher for hasDefaultArgument() to match on parameter declarations that have a default value.
Patch by Julie Hockett.
llvm-svn: 318794
Sam McCall [Tue, 21 Nov 2017 19:10:22 +0000 (19:10 +0000)]
[clangd] use u8 strings in tests to avoid problems on windows
llvm-svn: 318793
Craig Topper [Tue, 21 Nov 2017 18:50:41 +0000 (18:50 +0000)]
[X86] Sort bits in getHostCPUFeatures again.
llvm-svn: 318792
Sam McCall [Tue, 21 Nov 2017 18:40:43 +0000 (18:40 +0000)]
[clangd] Add JSON tests with invalid unicode
llvm-svn: 318791
George Rokos [Tue, 21 Nov 2017 18:26:41 +0000 (18:26 +0000)]
[Clang][OpenMP] New clang/libomptarget map interface: new function signatures, libomptarget-side
This is the libomptarget-side patch which changes the __tgt_* API function signatures in preparation for the new map interface.
Changes are: Device IDs 32bits --> 64bits, Flags 32bits --> 64bits
Differential revision: https://reviews.llvm.org/D40313
llvm-svn: 318790
George Rokos [Tue, 21 Nov 2017 18:25:12 +0000 (18:25 +0000)]
[Clang][OpenMP] New clang/libomptarget map interface: new function signatures, clang-side
This clang patch changes the __tgt_* API function signatures in preparation for the new map interface.
Changes are: Device IDs 32bits --> 64bits, Flags 32bits --> 64bits
Differential revision: https://reviews.llvm.org/D40281
llvm-svn: 318789
Chad Rosier [Tue, 21 Nov 2017 18:08:34 +0000 (18:08 +0000)]
[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.
This partially reverts r298851. The the underlying issue is that we don't
currently model the dependency between mrs (read system register) and
msr (write system register) instructions.
Something like the below should never be reordered:
msr TPIDR_EL0, x0 ;; set thread pointer
mrs x8, TPIDR_EL0 ;; read thread pointer
but was being reordered after r298851. The functional part of the patch
that wasn't reverted needed to remain in place in order to not break
r299462.
PR35317
llvm-svn: 318788
Hans Wennborg [Tue, 21 Nov 2017 18:00:01 +0000 (18:00 +0000)]
Fix r318786
llvm-svn: 318787
Nuno Lopes [Tue, 21 Nov 2017 17:53:19 +0000 (17:53 +0000)]
removed unused private method decl. NFC
llvm-svn: 318786
Hans Wennborg [Tue, 21 Nov 2017 17:30:34 +0000 (17:30 +0000)]
Add -finstrument-function-entry-bare flag
This is an instrumentation flag that's similar to
-finstrument-functions, but it only inserts calls on function entry, the
calls are inserted post-inlining, and they don't take any arugments.
This is intended for users who want to instrument function entry with
minimal overhead.
(-pg would be another alternative, but forces frame pointer emission and
affects link flags, so is probably best left alone to be used for
generating gcov data.)
Differential revision: https://reviews.llvm.org/D40276
llvm-svn: 318785
Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
Rename test/Transforms/CountingFunctionInserter -> EntryExitInstrumenter
The pass was renamed in r318195.
llvm-svn: 318784
Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
EntryExitInstrumenter: support __cyg_profile_func_enter_bare
It works just like __cyg_profile_func_enter but takes no arguments.
llvm-svn: 318783
Sam McCall [Tue, 21 Nov 2017 17:18:30 +0000 (17:18 +0000)]
[clangd] Include the right header for std::isxdigit
llvm-svn: 318782
Alexey Bataev [Tue, 21 Nov 2017 17:08:48 +0000 (17:08 +0000)]
[OPENMP] Initial support for asynchronous data update, NFC.
OpenMP 5.0 introduces asynchronous data update/dependecies clauses on
target data directives. Patch adds initial support for outer task
regions to use task-based codegen for future async target data
directives.
llvm-svn: 318781
Sam McCall [Tue, 21 Nov 2017 17:02:24 +0000 (17:02 +0000)]
[clangd] Satisfy GCC: 'changes meaning of Error'
llvm-svn: 318780
Jonas Hahnfeld [Tue, 21 Nov 2017 16:49:11 +0000 (16:49 +0000)]
Fix test/OpenMP/nvptx_data_sharing.cpp
This was an oversight that stayed in the test from development.
llvm-svn: 318779
Sam McCall [Tue, 21 Nov 2017 16:44:16 +0000 (16:44 +0000)]
[clangd] Fix dumb && || bug from r318774
llvm-svn: 318778
Oliver Stannard [Tue, 21 Nov 2017 16:20:25 +0000 (16:20 +0000)]
[ARM] Remove pre-UAL FLDM/FSTM aliases
These are pre-UAL syntax, and we don't support any other pre-UAL instructions,
with the exception of FLDMX/FSTMX, which don't have a UAL equivalent. Therefore
there's no reason to keep them or their AsmParser hacks around.
With the AsmParser hacks removed, the FLDMX and FSTMX instructions get the same
operand diagnostics as the UAL instructions.
Differential revision: https://reviews.llvm.org/D39196
llvm-svn: 318777
Aleksei Sidorin [Tue, 21 Nov 2017 16:08:41 +0000 (16:08 +0000)]
[ASTImporter] Support new AST nodes:
* UnresolvedUsingType
* EmptyDecl
* NamespaceAliasDecl
* UsingDecl
* UsingShadowDecl
* UsingDirectiveDecl
* UnresolvedUsingValueDecl
* UnresolvedUsingTypenameDecl
Refactor error handling in ImportTemplateArgumentLoc() method.
Add a test for inline namespaces.
llvm-svn: 318776
Kostya Kortchinsky [Tue, 21 Nov 2017 16:08:07 +0000 (16:08 +0000)]
[sanitizer] Define SANITIZER_USE_GETAUXVAL for Android
Summary:
Android for API level >= 21 has `getauxval`. Enable `SANITIZER_USE_GETAUXVAL`
when those requirements are met. Correct a typo in the header.
Reviewers: alekseyshl
Reviewed By: alekseyshl
Subscribers: srhines, llvm-commits, kubamracek
Differential Revision: https://reviews.llvm.org/D40260
llvm-svn: 318775
Sam McCall [Tue, 21 Nov 2017 16:00:53 +0000 (16:00 +0000)]
[clangd] Add parsing and value inspection to JSONExpr.
Summary:
This will replace the places where we're using YAMLParser to parse JSON now:
- the new marshalling code (T::parse()) should handle fewer cases and require
fewer explicit casts
- we'll early-reject invalid JSON that YAMLParser accepts
- we'll be able to fix protocol-parsing bugs caused by the fact that YAML can
only parse forward
I plan to do the conversion as soon as this lands, but I don't want it in one
patch as the protocol.cpp changes are conflict-prone.
Reviewers: ioeric
Subscribers: ilya-biryukov, cfe-commits
Differential Revision: https://reviews.llvm.org/D40182
llvm-svn: 318774
Gheorghe-Teodor Bercea [Tue, 21 Nov 2017 15:54:54 +0000 (15:54 +0000)]
[OpenMP] Add implicit data sharing support when offloading to NVIDIA GPUs using OpenMP device offloading
Summary:
This patch is part of the development effort to add support in the current OpenMP GPU offloading implementation for implicitly sharing variables between a target region executed by the team master thread and the worker threads within that team.
This patch is the first of three required for successfully performing the implicit sharing of master thread variables with the worker threads within a team. The remaining two patches are:
- Patch D38978 to the LLVM NVPTX backend which ensures the lowering of shared variables to an device memory which allows the sharing of references;
- Patch (coming soon) is a patch to libomptarget runtime library which ensures that a list of references to shared variables is properly maintained.
A simple code snippet which illustrates an implicit data sharing situation is as follows:
```
#pragma omp target
{
// master thread only
int v;
#pragma omp parallel
{
// worker threads
// use v
}
}
```
Variable v is implicitly shared from the team master thread which executes the code in between the target and parallel directives. The worker threads must operate on the latest version of v, including any updates performed by the master.
The code generated in this patch relies on the LLVM NVPTX patch (mentioned above) which prevents v from being lowered in the thread local memory of the master thread thus making the reference to this variable un-shareable with the workers. This ensures that the code generated by this patch is correct.
Since the parallel region is outlined the passing of arguments to the outlined regions must preserve the original order of arguments. The runtime therefore maintains a list of references to shared variables thus ensuring their passing in the correct order. The passing of arguments to the outlined parallel function is performed in a separate function which the data sharing infrastructure constructs in this patch. The function is inlined when optimizations are enabled.
Reviewers: hfinkel, carlo.bertolli, arpith-jacob, Hahnfeld, ABataev, caomhin
Reviewed By: ABataev
Subscribers: cfe-commits, jholewinski
Differential Revision: https://reviews.llvm.org/D38976
llvm-svn: 318773
Alina Sbirlea [Tue, 21 Nov 2017 15:45:46 +0000 (15:45 +0000)]
Add MemorySSA as loop dependency, disabled by default [NFC].
Summary:
First step in adding MemorySSA as dependency for loop pass manager.
Adding the dependency under a flag.
New pass manager: MSSA pointer in LoopStandardAnalysisResults can be null.
Legacy and new pass manager: Use cl::opt EnableMSSALoopDependency. Disabled by default.
Reviewers: sanjoy, davide, gberry
Subscribers: mehdi_amini, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D40274
llvm-svn: 318772
Oliver Stannard [Tue, 21 Nov 2017 15:34:15 +0000 (15:34 +0000)]
[ARM] Don't omit non-default predication code
This was causing the (invalid) predicated versions of the NEON VRINTX and
VRINTZ instructions to be accepted, with the condition code being ignored.
Also, there is no NEON VRINTR instruction, so that part of the check was not
necessary.
Differential revision: https://reviews.llvm.org/D39193
llvm-svn: 318771
Oliver Stannard [Tue, 21 Nov 2017 15:16:50 +0000 (15:16 +0000)]
[Asm] Improve "too few operands" errors
- We can still emit this error if the actual instruction has two or more
operands missing compared to the expected one.
- We should only emit this error once per instruction.
Differential revision: https://reviews.llvm.org/D36746
llvm-svn: 318770
Oliver Stannard [Tue, 21 Nov 2017 15:12:05 +0000 (15:12 +0000)]
[Asm] Finish matching once end of formal and actual lists reached (NFC)
This is NFC, as the matcher would continue looping up to the maximum
number of operands with no effect, but this should improve performance a
bit, and makes the debug trace clearer.
Differential revision: https://reviews.llvm.org/D36744
llvm-svn: 318769
Sander de Smalen [Tue, 21 Nov 2017 15:07:43 +0000 (15:07 +0000)]
Revert r318759 due to make check-all failure on Windows
llvm-svn: 318768
Jonas Hahnfeld [Tue, 21 Nov 2017 15:06:28 +0000 (15:06 +0000)]
Add target triples to openmp-offload-gpu.c
This might fix the failure on Green Dragon.
llvm-svn: 318767
Oliver Stannard [Tue, 21 Nov 2017 15:06:01 +0000 (15:06 +0000)]
[ARM] Add diagnostics for SPR/DPR lists
Differential revision: https://reviews.llvm.org/D39195
llvm-svn: 318766
Erik Pilkington [Tue, 21 Nov 2017 15:04:08 +0000 (15:04 +0000)]
[demangler] Document some features that the demangler doesn't yet support, NFC
llvm-svn: 318765
Alexey Bataev [Tue, 21 Nov 2017 14:49:13 +0000 (14:49 +0000)]
[InstCombine] Test for PR35354: unable to vectorize loop with std::max
on floats, NFC.
llvm-svn: 318764
Jonas Hahnfeld [Tue, 21 Nov 2017 14:44:45 +0000 (14:44 +0000)]
[OpenMP] Consistently use cubin extension for nvlink
This was previously done in some places, but for example not for
bundling so that single object compilation with -c failed. In
addition cubin was used for all file types during unbundling which
is incorrect for assembly files that are passed to ptxas.
Tighten up the tests so that we can't regress in that area.
Differential Revision: https://reviews.llvm.org/D40250
llvm-svn: 318763
Sam Kolton [Tue, 21 Nov 2017 14:11:59 +0000 (14:11 +0000)]
[AMDGPU] SDWA: remove omod src operand for VOP2b instructions
Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding
Reviewers: rampitec, dp
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D40172
llvm-svn: 318761
Alex Bradbury [Tue, 21 Nov 2017 12:41:41 +0000 (12:41 +0000)]
[RISCV][NFC] Remove unnecessary {} around single statement if block
Almost too trivial to worry about, but it seems worth having consistency with
upcoming commits.
llvm-svn: 318760
Sander de Smalen [Tue, 21 Nov 2017 12:26:06 +0000 (12:26 +0000)]
[TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.
This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate.
Reviewers: craig.topper, olista01, rengolin, stoklund
Reviewed By: olista01
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40011
llvm-svn: 318759
Simon Pilgrim [Tue, 21 Nov 2017 12:02:18 +0000 (12:02 +0000)]
[X86][XOP] Add missing scheduler classes to XOP instructions
All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables.
llvm-svn: 318758
Alex Bradbury [Tue, 21 Nov 2017 12:00:19 +0000 (12:00 +0000)]
[RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
As pointed out in post-commit review of r318738, `return ReplaceNode(..)` when
both ReplaceNode and the current function return void is confusing. This patch
moves to using a more obvious early return, and moves to just using an if to
catch the one case we currently care about. A future patch that adds further
custom instruction selection can introduce a switch.
llvm-svn: 318757
Martell Malone [Tue, 21 Nov 2017 11:30:20 +0000 (11:30 +0000)]
[ARM] Use SEH exceptions on thumbv7-windows
Reviewers: mstorsjo
Differential Revision: https://reviews.llvm.org/D40286
llvm-svn: 318756
Martell Malone [Tue, 21 Nov 2017 11:28:29 +0000 (11:28 +0000)]
[MINGW] normalize WIN32 macros
move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h
move WIN32, WIN64 and __MINGW64__ to addMinGWDefines
fixes __MINGW64__ not being defined for aarch64
adds WIN32 definition for x64
Reviewers: mstorsjo
Differential Revision: https://reviews.llvm.org/D40285
llvm-svn: 318755
Aleksei Sidorin [Tue, 21 Nov 2017 11:27:47 +0000 (11:27 +0000)]
[Analyzer] Stable iteration on indirect goto LabelDecl's to avoid non-determinism (attempt 2)
CFG wass built in non-deterministic order due to the fact that indirect
goto labels' declarations (LabelDecl's) are stored in the llvm::SmallSet
container. LabelDecl's are pointers, whose order is not deterministic,
and llvm::SmallSet sorts them by their non-deterministic addresses after
"small" container is exceeded. This leads to non-deterministic processing
of the elements of the container.
The fix is to use llvm::SmallSetVector that was designed to have
deterministic iteration order.
Patch by Ilya Palachev!
Differential Revision: https://reviews.llvm.org/D40073
llvm-svn: 318754
Aleksei Sidorin [Tue, 21 Nov 2017 11:20:07 +0000 (11:20 +0000)]
[Analyzer] Revert r318750 because incorrect files were added for commit.
Sorry for the noise.
llvm-svn: 318753
Ivan A. Kosarev [Tue, 21 Nov 2017 11:18:06 +0000 (11:18 +0000)]
[CodeGen] Generate TBAA type descriptors in a more reliable manner
This patch introduces a couple of helper functions that make it
possible to handle the caching logic in a single place.
Differential Revision: https://reviews.llvm.org/D39953
llvm-svn: 318752
Simon Pilgrim [Tue, 21 Nov 2017 11:17:11 +0000 (11:17 +0000)]
[X86][LWP] Add missing LWP itinerary class to lwpins instructions
It's on all other LWP instruction but I missed it from lwpins, despite similar scheduling behaviour.
llvm-svn: 318751
Aleksei Sidorin [Tue, 21 Nov 2017 11:05:28 +0000 (11:05 +0000)]
[Analyzer] Non-determinism: stable iteration on indirect goto LabelDecl's
CFG wass built in non-deterministic order due to the fact that indirect
goto labels' declarations (LabelDecl's) are stored in the llvm::SmallSet
container. LabelDecl's are pointers, whose order is not deterministic,
and llvm::SmallSet sorts them by their non-deterministic addresses after
"small" container is exceeded. This leads to non-deterministic processing
of the elements of the container.
The fix is to use llvm::SmallSetVector that was designed to have
deterministic iteration order.
Patch by Ilya Palachev!
Differential Revision: https://reviews.llvm.org/D40073
llvm-svn: 318750
Eugene Leviant [Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)]
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
This patch fixes instregex for interger vector add/sub instructions
Differential revision: https://reviews.llvm.org/D40254
llvm-svn: 318749
Coby Tayree [Tue, 21 Nov 2017 10:32:42 +0000 (10:32 +0000)]
[x86][icelake]BITALG
vpopcnt{b,w}
Differential Revision: https://reviews.llvm.org/D40213
llvm-svn: 318748
Diana Picus [Tue, 21 Nov 2017 10:17:02 +0000 (10:17 +0000)]
[ARM GlobalISel] Add comment for r318398. NFC.
Mention the purpose of the BICri tests added by r318398, as requested in
post-commit review.
llvm-svn: 318747
Coby Tayree [Tue, 21 Nov 2017 10:04:28 +0000 (10:04 +0000)]
[x86][icelake]VNNI
Introducing Vector Neural Network Instructions, consisting of:
vpdpbusd{s}
vpdpwssd{s}
Differential Revision: https://reviews.llvm.org/D40208
llvm-svn: 318746
Coby Tayree [Tue, 21 Nov 2017 09:48:44 +0000 (09:48 +0000)]
[x86][icelake]vbmi2
introducing vbmi2, consisting of
vpcompress{b,w}
vpexpand{b,w}
vpsh{l,r}d{w,d,q}
vpsh{l,r}dv{w,d,q}
Differential Revision: https://reviews.llvm.org/D40206
llvm-svn: 318745
Hamza Sood [Tue, 21 Nov 2017 09:42:42 +0000 (09:42 +0000)]
[Modules TS] Added module re-export support.
This implements [dcl.modules.export] from the C++ Modules TS, which lets a module re-export another module with the "export import" syntax.
Differential Revision: https://reviews.llvm.org/D40270
llvm-svn: 318744
NAKAMURA Takumi [Tue, 21 Nov 2017 09:41:01 +0000 (09:41 +0000)]
SLPVectorizer.cpp: Avoid std::stable_sort(properlyDominates()).
properlyDominates() shouldn't be used as sort key. It causes different output between stdlibc++ and libc++.
Instead, I introduced RPOT. In most cases, it works for CSE.
llvm-svn: 318743
Kamil Rytarowski [Tue, 21 Nov 2017 09:36:07 +0000 (09:36 +0000)]
Correct NetBSD support in pthread_once(3)/TSan
Summary:
The pthread_once(3)/NetBSD type is built with the following structure:
struct __pthread_once_st {
pthread_mutex_t pto_mutex;
int pto_done;
};
Set the pto_done position as shifted by __sanitizer::pthread_mutex_t_sz
from the beginning of the pthread_once struct.
This corrects deadlocks when the pthread_once(3) function
is used.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, dvyukov, vitalybuka
Reviewed By: dvyukov
Subscribers: llvm-commits, kubamracek, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D40262
llvm-svn: 318742
Coby Tayree [Tue, 21 Nov 2017 09:30:33 +0000 (09:30 +0000)]
[x86][icelake]vpclmulqdq introduction
an icelake promotion of pclmulqdq
Differential Revision: https://reviews.llvm.org/D40101
llvm-svn: 318741
Coby Tayree [Tue, 21 Nov 2017 09:11:41 +0000 (09:11 +0000)]
[x86][icelake]VAES introduction
an icelake promotion of AES
Differential Revision: https://reviews.llvm.org/D40078
llvm-svn: 318740
Coby Tayree [Tue, 21 Nov 2017 08:50:10 +0000 (08:50 +0000)]
[x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blob
Differential Revision: https://reviews.llvm.org/D38445
llvm-svn: 318739
Alex Bradbury [Tue, 21 Nov 2017 08:23:08 +0000 (08:23 +0000)]
[RISCV] Use register X0 (ZERO) for constant 0
The obvious approach of defining a pattern like the one below actually doesn't
work:
`def : Pat<(i32 0), (i32 X0)>;`
As was noted when Lanai made this change (https://reviews.llvm.org/rL288215),
attempting to handle the constant 0 in tablegen leads to assertions due to a
physical register being used where a virtual register is expected.
llvm-svn: 318738
Alex Bradbury [Tue, 21 Nov 2017 08:11:03 +0000 (08:11 +0000)]
[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
Martell Malone [Tue, 21 Nov 2017 08:09:59 +0000 (08:09 +0000)]
[MS] add an init test for thumbv7-windows-msvc
llvm-svn: 318736
Alex Bradbury [Tue, 21 Nov 2017 07:51:32 +0000 (07:51 +0000)]
[RISCV] Implement lowering of ISD::SELECT
Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and
ultimately the integer RISC-V conditional branch instructions), we choose to
expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch
will be created in the case where an ISD::SELECT condition value is created by
an ISD::SETCC node, which operates on XLen types. Other datatypes such as
floating point don't have conditional branch instructions, and lowering
ISD::SELECT allows more flexibility for handling these cases.
Differential Revision: https://reviews.llvm.org/D29937
llvm-svn: 318735
Dean Michael Berris [Tue, 21 Nov 2017 07:29:21 +0000 (07:29 +0000)]
[XRay][compiler-rt] Migrate basic mode logging to the XRay framework
Summary:
Before this patch, XRay's basic (naive mode) logging would be
initialised and installed in an adhoc manner. This patch ports the
implementation of the basic (naive mode) logging implementation to use
the common XRay framework.
We also make the following changes to reduce the variance between the
usage model of basic mode from FDR (flight data recorder) mode:
- Allow programmatic control of the size of the buffers dedicated to
per-thread records. This removes some hard-coded constants and turns
them into runtime-controllable flags and through an Options
structure.
- Default the `xray_naive_log` option to false. For now, the only way
to start basic mode is to set the environment variable, or set the
default at build-time compiler options. Because of this change we've
had to update a couple of tests relying on basic mode being always
on.
- Removed the reliance on a non-trivially destructible per-thread
resource manager. We use a similar trick done in D39526 to use
pthread_key_create() and pthread_setspecific() to ensure that the
per-thread cleanup handling is performed at thread-exit time.
We also radically simplify the code structure for basic mode, to move
most of the implementation in the `__xray` namespace.
Reviewers: pelikan, eizan, kpw
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40164
llvm-svn: 318734
Dean Michael Berris [Tue, 21 Nov 2017 07:16:57 +0000 (07:16 +0000)]
[XRay] Use optimistic logging model for FDR mode
Summary:
Before this change, the FDR mode implementation relied on at thread-exit
handling to return buffers back to the (global) buffer queue. This
introduces issues with the initialisation of the thread_local objects
which, even through the use of pthread_setspecific(...) may eventually
call into an allocation function. Similar to previous changes in this
line, we're finding that there is a huge potential for deadlocks when
initialising these thread-locals when the memory allocation
implementation is also xray-instrumented.
In this change, we limit the call to pthread_setspecific(...) to provide
a non-null value to associate to the key created with
pthread_key_create(...). While this doesn't completely eliminate the
potential for the deadlock(s), it does allow us to still clean up at
thread exit when we need to. The change is that we don't need to do more
work when starting and ending a thread's lifetime. We also have a test
to make sure that we actually can safely recycle the buffers in case we
end up re-using the buffer(s) available from the queue on multiple
thread entry/exits.
This change cuts across both LLVM and compiler-rt to allow us to update
both the XRay runtime implementation as well as the library support for
loading these new versions of the FDR mode logging. Version 2 of the FDR
logging implementation makes the following changes:
* Introduction of a new 'BufferExtents' metadata record that's outside
of the buffer's contents but are written before the actual buffer.
This data is associated to the Buffer handed out by the BufferQueue
rather than a record that occupies bytes in the actual buffer.
* Removal of the "end of buffer" records. This is in-line with the
changes we described above, to allow for optimistic logging without
explicit record writing at thread exit.
The optimistic logging model operates under the following assumptions:
* Threads writing to the buffers will potentially race with the thread
attempting to flush the log. To avoid this situation from occuring,
we make sure that when we've finalized the logging implementation,
that threads will see this finalization state on the next write, and
either choose to not write records the thread would have written or
write the record(s) in two phases -- first write the record(s), then
update the extents metadata.
* We change the buffer queue implementation so that once it's handed
out a buffer to a thread, that we assume that buffer is marked
"used" to be able to capture partial writes. None of this will be
safe to handle if threads are racing to write the extents records
and the reader thread is attempting to flush the log. The optimism
comes from the finalization routine being required to complete
before we attempt to flush the log.
This is a fairly significant semantics change for the FDR
implementation. This is why we've decided to update the version number
for FDR mode logs. The tools, however, still need to be able to support
older versions of the log until we finally deprecate those earlier
versions.
Reviewers: dblaikie, pelikan, kpw
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39526
llvm-svn: 318733
Craig Topper [Tue, 21 Nov 2017 06:28:15 +0000 (06:28 +0000)]
[X86] Simplify type constraints for AVX2 masked gather.
We don't need separate 32 and 64 node types. We can use SDTCisInt and SDTCisSameSizeAs to ensure the mask size the result type and is integer.
llvm-svn: 318732
Serguei Katkov [Tue, 21 Nov 2017 06:03:43 +0000 (06:03 +0000)]
Revert "[CGP] Enable complex addr mode (2nd attempt)"
Revert the patch rl318728 causing buildbot hangs-ups.
llvm-svn: 318731
Craig Topper [Tue, 21 Nov 2017 06:01:20 +0000 (06:01 +0000)]
[X86] Simplify the predicates for avx2 masked gather patterns.
We don't need a dyn_cast and we only need to check the type of the index. The base ptr is guaranteed to be scalar.
llvm-svn: 318730
Rafael Espindola [Tue, 21 Nov 2017 05:35:45 +0000 (05:35 +0000)]
move static function. NFC
llvm-svn: 318729
Serguei Katkov [Tue, 21 Nov 2017 05:31:47 +0000 (05:31 +0000)]
[CGP] Enable complex addr mode (2nd attempt)
2nd attempt to enable complex addr modes after
fix of the crash by rL318638.
llvm-svn: 318728
Yaxun Liu [Tue, 21 Nov 2017 02:29:54 +0000 (02:29 +0000)]
[AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type
DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type,
which causes less performant ISA in amdgcn---amdgiz target since the default pointer
type is i64 whereas the desired shift amount type is i32.
This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger.
The X86 change is necessary since splitting i512 requires shifting amount of 256, which
cannot be held by i8.
Differential Revision: https://reviews.llvm.org/D40148
llvm-svn: 318727
Rafael Espindola [Tue, 21 Nov 2017 01:52:44 +0000 (01:52 +0000)]
Split a rename_handle out of rename on windows.
llvm-svn: 318725
Richard Trieu [Tue, 21 Nov 2017 01:45:17 +0000 (01:45 +0000)]
Add default values for member functions.
Initialize IsVis2 and IsVis3 in SparcSubtarget::initializeSubtargetDependencies.
MSan detected uninitialized read of IsVis3 after r318704. Initializing the
variables to false will prevent undefined behavior.
llvm-svn: 318724
Reid Kleckner [Tue, 21 Nov 2017 01:25:56 +0000 (01:25 +0000)]
[MS] Increase default new alignment for win64 and test it
Summary:
This raises __STDCPP_DEFAULT_NEW_ALIGNMENT__ from 8 to 16 on Win64.
This matches platforms that follow the usual `2 * sizeof(void*)`
alignment requirement for malloc. We might want to consider making that
the default rather than relying on long double alignment.
Fixes PR35356
Reviewers: STL_MSFT, rsmith
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D40277
llvm-svn: 318723
Zachary Turner [Tue, 21 Nov 2017 01:20:28 +0000 (01:20 +0000)]
Re-revert "Refactor debuginfo-tests."
This is still breaking greendragon.
At this point I give up until someone can fix the greendragon
bots, and I will probably abandon this effort in favor of using
a private github repository.
llvm-svn: 318722
Peter Collingbourne [Tue, 21 Nov 2017 01:14:14 +0000 (01:14 +0000)]
COFF: Emit a COFF symbol table if /debug:dwarf is specified.
This effectively reverts r318548 and r318635 while keeping the
functionality behind the flag and preserving the bug fix from r318548.
Differential Revision: https://reviews.llvm.org/D40264
llvm-svn: 318721
David Blaikie [Tue, 21 Nov 2017 01:09:18 +0000 (01:09 +0000)]
ASTMatchers{,Macros}.h: Add some extra macros to use for decl/def of matchers
Fix ODR violations caused by using internal linkage variables in
non-internal inline functions. (also removes duplicate definitions, etc)
llvm-svn: 318720
David Blaikie [Tue, 21 Nov 2017 01:09:17 +0000 (01:09 +0000)]
FormatInternal.h: Add missing includes.
llvm-svn: 318719
David Blaikie [Tue, 21 Nov 2017 01:09:10 +0000 (01:09 +0000)]
Make some headers modular by adding missing includes/forward decls.
llvm-svn: 318718
Walter Lee [Tue, 21 Nov 2017 01:01:32 +0000 (01:01 +0000)]
[sanitizers] Add init function to set alignment of low level allocator
ASan requires that the min alignment be at least the shadow
granularity, so add an init function to do that.
Differential Revision: https://reviews.llvm.org/D39473
llvm-svn: 318717
Craig Topper [Tue, 21 Nov 2017 00:33:26 +0000 (00:33 +0000)]
[X86] Remove 'mm3now' from isValidFeatureName.
The correct spelling is '3dnow' which is already in the list.
llvm-svn: 318716