Samuel Pitoiset [Fri, 5 Jan 2018 16:18:52 +0000 (17:18 +0100)]
radv/gfx9: do not load VGPR1 when GS uses points or lines
VGPR1 is only needed for topology that needs 3 offsets like
triangles or quads.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 4 Jan 2018 14:19:47 +0000 (15:19 +0100)]
radv: make shader BOs read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 13:22:17 +0000 (14:22 +0100)]
radv: make descriptor BOs read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 13:20:50 +0000 (14:20 +0100)]
radv: make the indirect GFX config BO read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 13:28:46 +0000 (14:28 +0100)]
radv/winsys: make IBs read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 12:57:07 +0000 (13:57 +0100)]
radv/winsys: add RADEON_FLAG_READ_ONLY
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 12:51:46 +0000 (13:51 +0100)]
radv/winsys: rework radv_amdgpu_bo_va_op()
Needed for the following commit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Igor Gnatenko [Mon, 1 Jan 2018 21:49:00 +0000 (22:49 +0100)]
link mesautil with pthreads
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_setname':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:66: undefined reference to `pthread_setname_np'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_join':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:336: undefined reference to `pthread_join'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:48: undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:296: undefined reference to `pthread_create'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask'
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `call_once':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:96: undefined reference to `pthread_once'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_get_time_nano':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:84: undefined reference to `pthread_getcpuclockid'
collect2: error: ld returned 1 exit status
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Igor Gnatenko <ignatenko@redhat.com>
Alex Smith [Fri, 5 Jan 2018 11:09:19 +0000 (11:09 +0000)]
anv: Allow PMA optimization to be enabled in secondary command buffers
This was never enabled in secondary buffers because hiz_enabled was
never set to true for those.
If the app provides a framebuffer in the inheritance info when beginning
a secondary buffer, we can determine if HiZ is enabled and therefore
allow the PMA optimization to be enabled within the command buffer.
This improves performance by ~13% on an internal benchmark on Skylake.
v2: Use anv_cmd_buffer_get_depth_stencil_view().
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Florian Will [Fri, 5 Jan 2018 14:33:31 +0000 (15:33 +0100)]
glsl: Respect std430 layout in lower_buffer_access
Respect the std430 rules for determining offset and size of struct
members when using a std430 buffer. std140 rules lead to wrong buffer
offsets in that case.
Fixes my test case attached in Bugzilla. No piglit changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104492
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Karol Herbst [Sun, 7 Jan 2018 20:42:19 +0000 (21:42 +0100)]
nir: fix st_nir_assign_var_locations for patch variables
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ilia Mirkin [Sat, 24 Jun 2017 04:51:13 +0000 (00:51 -0400)]
nvc0: enable bindless on kepler
All the functionality is in. Maxwell will take a little bit more
enablement work.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 24 Jun 2017 04:44:35 +0000 (00:44 -0400)]
nvc0: add bindless image support for kepler
A part of the driver constbuf area is allocated for bindless images. Any
update requires uploading to all driver constbufs. This also extends the
driver constbuf to 64KB, up from 2KB.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 22 Jun 2017 03:13:20 +0000 (23:13 -0400)]
nvc0: add support for bindless textures on kepler+
This keeps a list of resident textures (per context), and dumps that
list into the active buffer list when submitting. We also treat bindless
texture fetches slightly differently, wrt the meaning of indirect, and
not requiring the SAMPLER file to be used.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 24 Jun 2017 00:44:56 +0000 (20:44 -0400)]
nv50/ir: use the image info in the instruction rather than decl
In preparation for bindless images, we have to retrieve the
target/format info from the instruction directly, as there will be no
declaration. Furthermore, for bound images, this information is still
available in the instruction, so we can drop the declaration-based
mechanism entirely.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 8 Apr 2017 04:05:18 +0000 (00:05 -0400)]
nvc0/ir: safen up lowering logic against overwriting reused values
I'm fairly sure both of the changed sites are OK as-is, but they're
fragile, so this is just safening them up. Since this is happening
pre-ssa, we don't want to be overwriting values that may potentially get
used later on.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 30 Dec 2017 06:07:30 +0000 (01:07 -0500)]
nvc0: update tic in-place when buffer address changes
This is helpful for bindless, where changing TIC id's is undesirable.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 1 Jan 2018 19:54:17 +0000 (14:54 -0500)]
nvc0: ensure that pushbuf keeps ref to old text/tls bos
If we free the bo, then the PTE may get deallocated immediately. We have
to make sure that the submission includes a ref to the old bo so that it
remains mapped for the duration of the command execution.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Kenneth Graunke [Fri, 5 Jan 2018 20:27:41 +0000 (12:27 -0800)]
i965: Torch public intel_batchbuffer_emit_dword/float helpers.
intel_batchbuffer_emit_float is dead code, it should go.
intel_batchbuffer_emit_dword only had one user, which had bungled using
them by forgetting to call intel_batchbuffer_require_space first. So it
seems wise to delete these unsafe helpers.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 5 Jan 2018 20:07:20 +0000 (12:07 -0800)]
i965: Require space for MI_BATCHBUFFER_END.
intel_batchbuffer_emit_dword doesn't reserve space for the DWord it
emits. In the past, we had some reserved batch space to ensure this
worked. With the switch to growing batches, we need to actually request
space so that we grow if necessary.
Fixes:
2c46a67b4138631217141f (i965: Delete BATCH_RESERVED handling.)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sun, 7 Jan 2018 01:32:04 +0000 (17:32 -0800)]
i965: Shut up a few unused variable warnings.
If asserts are disabled, you get pointless warnings about devinfo
being used (it's used to assert on devinfo->gen).
Marek Olšák [Tue, 2 Jan 2018 02:59:43 +0000 (03:59 +0100)]
ac: add ac_build_fmin/fmax helpers
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Wed, 13 Dec 2017 18:14:36 +0000 (19:14 +0100)]
mesa: remove dd_function_table::GetCompressedTexSubImage and clean it up
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Neil Roberts [Fri, 5 Jan 2018 10:38:58 +0000 (11:38 +0100)]
mesa: Tidy up the 4.6 section of GL4x.xml
The enums are moved to the top and indented like the rest of the file.
Comments are added to split up the function aliases by corresponding
extension. This should make no functional difference.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Pitoiset [Fri, 5 Jan 2018 09:03:03 +0000 (10:03 +0100)]
radv: remove unused radv_color_buffer_info::cb_clear_valueX
Found by inspection.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alex Smith [Thu, 4 Jan 2018 18:01:45 +0000 (18:01 +0000)]
anv: Take write mask into account in has_color_buffer_write_enabled
If we have a color attachment, but its writes are masked, this would
have still returned true. This is inconsistent with how HasWriteableRT
in 3DSTATE_PS_BLEND is set, which does take the mask into account.
This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA
if the fragment shader does use UAVs, meaning the fragment shader may
not be invoked because HasWriteableRT is false. Specifically, this was
seen to occur when the shader also enables early fragment tests: the
fragment shader was not invoked despite passing depth/stencil.
Fix by taking the color write mask into account in this function. This
is consistent with how things are done on i965.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Neil Roberts [Fri, 24 Nov 2017 15:53:15 +0000 (16:53 +0100)]
mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parameters
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Pitoiset [Thu, 28 Dec 2017 21:55:27 +0000 (22:55 +0100)]
radv: enable denorms for 64-bit and 16-bit floats
Similar to RadeonSI.
This fixes:
dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat
dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:57:35 +0000 (20:57 +0100)]
amd/common: correctly detect if we need ring buffers
When allocate_user_sgprs() was called, ctx->stage was actually
unset and 0 is for the vertex shader. This doesn't change
anything for now because of the spill support thing.
Though, the number of user SGPRs has to be fixed for merged
shaders on GFX9. It was broken before anyway.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 4 Jan 2018 15:24:22 +0000 (16:24 +0100)]
amd/common: use ac_image_load when lod is zero
This might decrease VGPR spilling, because we no longer
have to use v4i32 for 2D fetches when level == 0. We now
use v2i32 for those cases.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Thu, 4 Jan 2018 15:24:51 +0000 (16:24 +0100)]
radv: limit the scissor bug workaround to Vega 10 and Raven
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alejandro Piñeiro [Thu, 4 Jan 2018 16:13:07 +0000 (17:13 +0100)]
glsl/standalone: set MaxTransformFeedbackBuffers
Using 4, as it is the default value on mesa. See mesa/main/config.h
and the following commit that introduced the value:
15ac66e331abdab12e882d80a6b4f647bc905298
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Alejandro Piñeiro [Thu, 4 Jan 2018 16:04:33 +0000 (17:04 +0100)]
glsl/standalone: set MaxVertexStreams
ARB_transform_feedback3 sets a minimum of 1, ARB_gpu_shader5 a minimum
of 4. It shouldn't matter too much, so choosing the later.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Alejandro Piñeiro [Thu, 4 Jan 2018 15:51:19 +0000 (16:51 +0100)]
glsl/standalone: set MaxUniformBufferBindings
Used to handle how many ubo you can define on the context. Minimimum
defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL
4.6 (12 per stage at each moment).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Alejandro Piñeiro [Thu, 4 Jan 2018 15:38:00 +0000 (16:38 +0100)]
glsl/standalone: point which arguments are mandatory
Every now and then I execute the standalone compiler, get the
non-version error, and need to remember what I'm doing wrong
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 13 Dec 2017 07:46:56 +0000 (18:46 +1100)]
ac: rework ac_llvm_extract_elem()
Simplifies the logic a little and asserts index is 0.
Suggested-by: Nicolai Hähnle <nhaehnle@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 02:32:17 +0000 (13:32 +1100)]
st/glsl_to_nir/radeonsi: enable tessellation shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 00:45:09 +0000 (11:45 +1100)]
gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 7 Dec 2017 02:11:32 +0000 (13:11 +1100)]
radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 06:34:32 +0000 (17:34 +1100)]
ac/radeonsi: add load_tess_coord() to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 06:02:30 +0000 (17:02 +1100)]
radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 05:02:34 +0000 (16:02 +1100)]
radeonsi/nir: gather tess properties
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 03:36:11 +0000 (14:36 +1100)]
ac/radeonsi: add tcs_rel_ids to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 03:18:34 +0000 (14:18 +1100)]
radeonsi: add unpack_llvm_param() helper
This allows us to pass the llvm param directly rather than looking
it up.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 02:30:33 +0000 (13:30 +1100)]
ac: add {tcs,tes}_patch_id to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 01:04:02 +0000 (12:04 +1100)]
radeonsi: add nir support for tcs outputs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 01:54:47 +0000 (12:54 +1100)]
ac: move some helpers to ac_llvm_build.c
We will call these from the radeonsi NIR backend.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 00:51:51 +0000 (11:51 +1100)]
ac: add store_tcs_outputs() to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 5 Dec 2017 01:56:12 +0000 (12:56 +1100)]
radeonsi: add si_nir_load_input_tcs()
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 02:14:49 +0000 (13:14 +1100)]
radeonsi: add get_dw_address_from_generic_indices() helper
This will be used by both the tgsi and nir backends.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 5 Dec 2017 01:04:05 +0000 (12:04 +1100)]
ac: call load_tcs_input() via the abi
This also enables some code sharing with tes.
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 4 Dec 2017 23:31:49 +0000 (10:31 +1100)]
ac: add load_tes_inputs() to the abi
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 23 Nov 2017 02:04:46 +0000 (13:04 +1100)]
radeonsi: add si_nir_load_input_tes()
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tim Rowley [Thu, 4 Jan 2018 16:08:48 +0000 (10:08 -0600)]
swr/rast: fix invalid sign masks in avx512 simdlib code
Should be 0x80000000 instead of 0x8000000.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Bas Nieuwenhuizen [Thu, 4 Jan 2018 01:11:51 +0000 (02:11 +0100)]
radv: Use correct flush bits for flushing L2 during CB/DB flushes.
Copied from radeonsi.
Putting in the correct metadata flush commands for eventually not
flushing L2 on CB/DB switch.
Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
at the moment.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 4 Jan 2018 00:45:15 +0000 (01:45 +0100)]
radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.
These are just shaders reads, so we need to invalidate L1.
Fixes:
6dbb0eaccc "radv: handle subpass cache flushes"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:57 +0000 (20:56 +0100)]
radv/gfx9: reduce the number of input VGPRs for the GS stage
This can still be improved, but let's start with this.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:56 +0000 (20:56 +0100)]
amd/common: scan if gl_PrimitiveID is used before translating to LLVM
It makes more sense to move all scan stuff in the same place.
Also, we don't really need to duplicate the uses_primid field
for each stages.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:55 +0000 (20:56 +0100)]
amd/common: scan if gl_InvocationID is used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Herring [Wed, 3 Jan 2018 16:16:23 +0000 (10:16 -0600)]
egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter
Commit
2f421651aca9 ("egl: let each platform decided how to handle
LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
function parameter.:
src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared identifier 'disp'
Rather than just fixing 'disp', rename the function parameter 'dpy' to
'disp' to align with the other EGL platforms' implementations.
Fixes:
2f421651aca9 ("egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Alex Smith [Thu, 4 Jan 2018 11:28:46 +0000 (11:28 +0000)]
anv: Add missing unlock in anv_scratch_pool_alloc
Fixes hangs seen due to the lock not being released here.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Sat, 30 Dec 2017 05:28:51 +0000 (00:28 -0500)]
mesa/bindless: fix missing image _Layer initialization
Some later code relies on _Layer to set first/last_layer. Make sure it's
always initialized.
Detected by valgrind's conditional jump/move with uninit value logic.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Józef Kucia [Sun, 31 Dec 2017 09:19:15 +0000 (10:19 +0100)]
radeonsi: fix alpha-to-coverage if color writes are disabled
If alpha-to-coverage is enabled, we have to compute alpha
even if color writes are disabled.
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Wed, 3 Jan 2018 23:19:41 +0000 (00:19 +0100)]
ac: rename has_sync_file to has_fence_to_handle.
sync_files are in linux since 4.7, while the amdgpu fence_to_handle
ioctl is only in 4.15.
In particular we don't need it for sync_file in radv, because
everything happens via syncobjs, which got support earlier than
fence_to_handle.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Mon, 1 Jan 2018 23:04:14 +0000 (00:04 +0100)]
ac/nir: Handle loading data from compact arrays.
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 2 Jan 2018 02:32:14 +0000 (03:32 +0100)]
radv: Allow writing 0 scissors.
When rasterization is disabled we can have that few.
Fixes:
76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Wed, 3 Jan 2018 20:58:49 +0000 (21:58 +0100)]
radv: Use correct HTILE expanded words.
Seems like users are actually hitting 0xFFFFFFFF actually making
things broken for them, and the mad max regression is fixed, so
lets put this in once more.
v2: Use 0xf for depth-only htile. (Dave)
Fixes:
af2844116fd "radv: Revert HTILE reset word to 0xFFFFFFFF."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Thu, 28 Dec 2017 14:59:19 +0000 (15:59 +0100)]
ac: rename has_syncobj_wait -> has_syncobj_wait_for_submit
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Fri, 29 Dec 2017 18:45:28 +0000 (10:45 -0800)]
braodcom/vc5: Fix internal type/bpp for RGB10_A2UI images.
I found that we were getting GPU hangs on most tests rendering to them,
and the simulator was assertion failing.
Eric Anholt [Thu, 28 Dec 2017 22:41:47 +0000 (14:41 -0800)]
broadcom/vc5: Try to fix up compressed texture load/store.
We were trying to load/store the logical width/height number of compressed
blocks. As long as the textures were large, single-level, and the
load/store at (0,0), it kind of worked.
Eric Anholt [Fri, 29 Dec 2017 00:42:53 +0000 (16:42 -0800)]
broadcom/vc5: Fix image_h value for CPU-side tiling on miplevels > 1.
Fixes overflow that caused failure in
dEQP-GLES3.functional.texture.filtering.2d.sizes.128x128_linear.
Eric Anholt [Fri, 29 Dec 2017 00:01:09 +0000 (16:01 -0800)]
broadcom/vc5: Fix discard_if during control flow.
I want to do the SETMSF.IFA to discard only if execute == 0 and cond, so
our dest of the PUSHZ needs to be nonzero if execute or !cond are nonzero.
Fixes dEQP-GLES3.functional.shaders.discard.dynamic_loop_dynamic.
Eric Anholt [Thu, 28 Dec 2017 23:42:14 +0000 (15:42 -0800)]
broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.
Apparently the other funcs will have observable differences when early Z
is enabled.
Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
Eric Anholt [Thu, 28 Dec 2017 23:29:04 +0000 (15:29 -0800)]
broadcom/vc5: Don't emit component 3/4 F16 TLB writes for float/vec2.
Fixes a simulator assertion failure on
dEQP-GLES3.functional.fragment_out.array.fixed.r8_highp_float.
Eric Anholt [Thu, 28 Dec 2017 23:12:20 +0000 (15:12 -0800)]
nir: Add a helper to get the uvec4 type.
I needed this in the vc5 compiler.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Thu, 28 Dec 2017 21:01:37 +0000 (13:01 -0800)]
broadcom/vc5: Introduce enums for internal depth/type, with V3D prefixes.
Eric Anholt [Thu, 28 Dec 2017 20:59:33 +0000 (12:59 -0800)]
broadcom/xml: Fix up safe name confusion with prefixing.
For enums we were doubling the underscore if the value had a numeric first
character of its name (which safe_name() adds an underscore to). A little
helper function cleans up the other instance of prefixing while also
fixing this.
Eric Anholt [Thu, 28 Dec 2017 00:43:10 +0000 (16:43 -0800)]
broadcom/vc5: Turn the decimate mode field into an enum in the XML.
Eric Anholt [Thu, 28 Dec 2017 00:36:09 +0000 (16:36 -0800)]
broadcom/vc5: Turn the output image format into an enum.
Eric Anholt [Thu, 28 Dec 2017 00:20:12 +0000 (16:20 -0800)]
broadcom/vc5: Turn the CLE XML's memory format into an enum.
Eric Anholt [Wed, 27 Dec 2017 23:38:57 +0000 (15:38 -0800)]
broadcom/vc5: Emit flat shade flags for varying components > 24.
This means that with no flatshading we'll emit the single-byte
ZERO_ALL_FLAT_SHADE_FLAGS, and otherwise emit a set of FLAT_SHADE_FLAGS to
get all the bits we need set.
There's a _SET enum in the packet we could use to possibly set entire
ranges of the bitfield without using another packet, but this at least
fixes the conformance failure.
Eric Anholt [Wed, 27 Dec 2017 23:12:37 +0000 (15:12 -0800)]
broadcom/vc5: Emit proper flatshading code for glShadeModel(GL_FLAT).
In updating the simulator, behavior changed slightly so that our old code
wasn't getting glxgears's flatshading interpolated right. Emit flat
shading code just like we would for a normal flat-shaded varying, by
passing a flag in the shader key for glShadeModel(GL_FLAT) state and
customizing the color inputs based on that.
Eric Anholt [Fri, 29 Dec 2017 19:48:41 +0000 (11:48 -0800)]
braodcom/vc5: Rely on OVRTMUOUT always being set.
It seems that the HW team has decided that it's the only supported mode,
and it's the mode I actually meant to be using but forgot. Our table of
return_32_bit should have matched the default non-OVRTMUOUT behavior, so
this change should be invisible.
However, the change revealed that some my return_size checks for swizzling
were a bit confused in the shadow case, so I had to move them to draw time
once we have both the sampler and the view together.
Fixes assertion failures in the updated simulator, where the non-OVRTMUOUT
support has been removed.
Eric Anholt [Tue, 2 Jan 2018 19:26:58 +0000 (11:26 -0800)]
broadcom/vc5: Move texture return channel setup into the compiler.
The compiler decides how many LDTMUs we're going to emit, and that must
match the P1 flags. This brings the return channel counting to a single
place (so all that's passed into the compiler is "how many return channels
you may request from this texture's format), and was a necessary step for
shadow samplers once we stop using OVRTMUOUT=0.
Eric Anholt [Thu, 21 Dec 2017 01:19:23 +0000 (17:19 -0800)]
broadcom/vc5: Switch to setting the primitive list format in the RCL.
This means that we get a single copy of it emitted, instead of once at the
start of each tile (though it's still executed once per tile). Fixes
assertion failures with the updated simulator.
Eric Anholt [Thu, 21 Dec 2017 00:51:29 +0000 (16:51 -0800)]
broadcom/vc5: Switch to using the C++ interface for the simulator.
In newer versions they've removed the C interface, so make one here. This
also isolates the Mesa codebase from the simulator codebase, so we don't
have conflicts over things like "unreachable"
Mario Kleiner [Fri, 15 Dec 2017 22:05:09 +0000 (23:05 +0100)]
mesa: Add GL_UNSIGNED_INT_2_10_10_10_REV OES read type for BGRX1010102.
As Marek noted, the GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV type
combo is also good for readback of BGRX1010102 framebuffers, not
only for BGRA1010102 framebuffers for use with glReadPixels()
under GLES, so add it for the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES
query.
Successfully tested on gallium r600 driver with a (quickly hacked
for RGBA 10 10 10 0) dEQP testcase
dEQP-EGL.functional.wide_color.window_1010102_colorspace_default.
Suggested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:08 +0000 (23:05 +0100)]
st/dri: Add option to control exposure of 10 bpc color configs.
Some clients may not like rgb10 fbconfigs and visuals.
Support driconf option 'allow_rgb10_configs' on gallium
to allow per application enable/disable.
The option defaults to enabled.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:07 +0000 (23:05 +0100)]
st/dri: Add support for BGR[A/X]1010102 formats.
Exposes RGBA 10 10 10 2 and 10 10 10 0 visuals and
fbconfigs for rendering.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:06 +0000 (23:05 +0100)]
st/dri: Support texture_from_pixmap for BGR[A/X]1010102 formats.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:05 +0000 (23:05 +0100)]
st/dri2: Add buffer handling for BGR[A/X]1010102 formats.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:04 +0000 (23:05 +0100)]
st/dri2: Add format translations for BGR[A/X]1010102 formats.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:03 +0000 (23:05 +0100)]
st/mesa: Handle BGR[A/X]1010102 formats.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:02 +0000 (23:05 +0100)]
egl/wayland: Add Wayland shm swrast support for RGB10 winsys buffers.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:01 +0000 (23:05 +0100)]
egl/wayland: Add Wayland dmabuf support for RGB10 winsys buffers. (v2)
Successfully tested under Weston 3.0.
Photometer confirms 10 rgb bits from rendering to display.
v2: Rebased onto master for dri2_teardown_wayland().
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:05:00 +0000 (23:05 +0100)]
egl/wayland: Add Wayland drm support for RGB10 winsys buffers.
Successfully tested under Weston 3.0.
Photometer confirms 10 rgb bits from rendering to display.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:04:59 +0000 (23:04 +0100)]
egl/x11: Handle depth 30 drawables for EGL_KHR_image_pixmap.
Enables eglCreateImageKHR() with target set to
EGL_NATIVE_PIXMAP_KHR to handle color depth 30
X11 drawables.
Note that in theory the drawable depth 32 case in the
current implementation is ambiguous: A depth 32 drawable
could be of format ARGB8888 or ARGB2101010, therefore an
assignment of __DRI_IMAGE_FORMAT_ARGB8888 for a pixmap of
ARGB2101010 format would be wrong. In practice however, the
X-Server (as of v1.19) does not provide any depth 32 visuals
for ARGB2101010 EGL/GLX configs. Those are associated with
depth 30 visuals without an alpha channel instead. Therefore
the switch-case depth 32 branch is only executed for ARGB8888
pixmaps and we get away with this.
Tested with KDE Plasma 5 under X11, DRI2 and DRI3/Present,
selecting EGL + OpenGL compositing and different fbconfigs
with/without 2 bit alpha channel. glxinfo confirms use of
depth 30 visuals for ARGB2101010 only.
Suggested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:04:58 +0000 (23:04 +0100)]
egl/x11: Handle depth 30 drawables under software rasterizer.
For fixing eglCreateWindowSurface() under swrast, as tested
with LIBGL_ALWAYS_SOFTWARE=1.
Suggested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:04:57 +0000 (23:04 +0100)]
egl/x11: Match depth 30 RGB visuals to 32-bit RGBA EGLConfigs.
Similar to the matching of 24 bit RGB visuals to 32-bit
RGBA EGLConfigs, so X11 compositors won't alpha-blend any
config with a destination alpha buffer during compositing.
Additionally this fixes failure to select ARGB2101010
configs via eglChooseConfig() with EGL_ALPHA_BITS 2 on
a depth 30 X-Screen. The X-Server doesn't provide any
visuals of depth 32 for ARGB2101010 configs, it only
provides depth 30 visuals. Therefore if we'd only match
ARGB2101010 configs to depth 32 RGBA visuals, we would
not ever get a visual for such a config.
This was apparent in piglit tests for egl configs, which
are fixed by this commit.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Mario Kleiner [Fri, 15 Dec 2017 22:04:56 +0000 (23:04 +0100)]
mesa: Add GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV for OES read type.
This format + type combo is good for BGRA1010102 framebuffers
for use with glReadPixels() under GLES, so add it for the
GL_IMPLEMENTATION_COLOR_READ_TYPE_OES query.
Allows successful testing of 10 bpc / depth 30 rendering with dEQP test
case dEQP-EGL.functional.wide_color.window_1010102_colorspace_default.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>