Valentin Clement [Wed, 4 Nov 2020 20:47:40 +0000 (15:47 -0500)]
[flang][openacc] Lower update directive
This patch upstream the lowering of Update directive that was initially done in
https://github.com/flang-compiler/f18-llvm-project/pull/528
Reviewed By: schweitz
Differential Revision: https://reviews.llvm.org/D90472
Eric Astor [Wed, 4 Nov 2020 20:43:18 +0000 (15:43 -0500)]
Fix -Wsign-compare issue in MasmParser.cpp
Eric Astor [Wed, 4 Nov 2020 20:28:22 +0000 (15:28 -0500)]
[ms] [llvm-ml] Lex MASM strings, including escaping
Allow single-quoted strings and double-quoted character values, as well as doubled-quote escaping.
Reviewed By: thakis
Differential Revision: https://reviews.llvm.org/D89731
Cameron McInally [Wed, 4 Nov 2020 20:16:49 +0000 (14:16 -0600)]
[SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL
Hook up legalizations for VECREDUCE_SEQ_FMUL. This is following up on the VECREDUCE_SEQ_FADD work from D90247.
Differential Revision: https://reviews.llvm.org/D90644
Mircea Trofin [Tue, 3 Nov 2020 23:20:40 +0000 (15:20 -0800)]
[NFC] Use Register/MCRegister
Differential Revision: https://reviews.llvm.org/D90724
Valentin Clement [Wed, 4 Nov 2020 20:17:15 +0000 (15:17 -0500)]
[flang][openacc] Lower enter data directive
This patch upstream the lowering of Enter Data directive that was initially done in
https://github.com/flang-compiler/f18-llvm-project/pull/526
Reviewed By: schweitz
Differential Revision: https://reviews.llvm.org/D90470
Edd Dawson [Tue, 3 Nov 2020 14:11:21 +0000 (14:11 +0000)]
[lld][ELF][test] test LTO-removed symbols are not in symtab
Differential Revision: https://reviews.llvm.org/D90680
Louis Dionne [Wed, 4 Nov 2020 20:01:59 +0000 (15:01 -0500)]
[libc++] Remove stray setting of use_system_cxx_lib left behind
Louis Dionne [Wed, 4 Nov 2020 19:46:25 +0000 (14:46 -0500)]
[libc++] Move availability-related Lit configuration to the DSL
The implementation is not really satisfactory, but it's better than
being in the legacy config, which causes other issues.
Craig Topper [Wed, 4 Nov 2020 19:37:58 +0000 (11:37 -0800)]
[RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.
The operations in these patterns shouldn't be effected by sign
bits. And the pattern is starting from a sign_extend_inreg so
we aren't expecting sign bits to be passed through either.
Differential Revision: https://reviews.llvm.org/D90739
Valentin Clement [Wed, 4 Nov 2020 19:34:23 +0000 (14:34 -0500)]
[flang][openacc] Lower exit data directive
This patch upstream the lowering of Exit Data construct that was initially done in
https://github.com/flang-compiler/f18-llvm-project/pull/527
Reviewed By: schweitz
Differential Revision: https://reviews.llvm.org/D90467
Nikita Popov [Sat, 3 Oct 2020 15:28:12 +0000 (17:28 +0200)]
[MemorySSA] Use provided memory location even if instruction is call
If getClobberingMemoryAccess() is called with an explicit
MemoryLocation, but the starting access happens to be a call, the
provided location is currently ignored, and alias analysis queries
will be performed against the call instruction instead. Something
similar happens if the starting access is a load with a MemoryDef.
Change the implementation to not set Q.Inst in the first place if
we want to perform a MemoryLocation-based query, to make sure it
can't be turned into an Instruction-based query along the way...
Additionally, remove the special handling that lifetime.start
intrinsics currently get. They simply report NoAlias for clobbers
between lifetime.start and other calls, but that's obviously not
right if the other call is something like a memset or memcpy. The
default behavior we get from getModRefInfo() will already do the
right thing here.
Differential Revision: https://reviews.llvm.org/D88782
Steven Wan [Wed, 4 Nov 2020 18:40:02 +0000 (13:40 -0500)]
Add info about the cherry-picked commit and contributor
Steven Wan [Thu, 15 Oct 2020 22:16:09 +0000 (18:16 -0400)]
[PowerPC] Rename mftbl to mftb
`mftb` and `mftbl` are equivalent, there is no need to have two names for doing the same thing, rename `mftbl` to only have `mftb`.
Differential Revision: https://reviews.llvm.org/D89506
Alexandre Eichenberger [Wed, 4 Nov 2020 18:51:10 +0000 (13:51 -0500)]
[mlir][std] Add SignedCeilDivIOp and SignedFloorDivIOp with std to std lowering triggered by -std-expand-divs option. The new operations support positive/negative nominator/denominator numbers.
Differential Revision: https://reviews.llvm.org/D89726
Signed-off-by: Alexandre Eichenberger <alexe@us.ibm.com>
Craig Topper [Wed, 4 Nov 2020 19:01:52 +0000 (11:01 -0800)]
[RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.
fsl/fsr take their shift amount in $rs2 or an immediate. The
sources are $rs1 and $rs3.
fshl/fshr ISD opcodes both concatenate operand 0 in the high bits and
operand 1 in the lower bits. fshl returns the high bits after
shifting and fshr returns the low bits. So a shift amount of 0
returns operand 0 for fshl and operand 1 for fshr.
fsl/fsr concatenate their operands in different orders such that
$rs1 will be returned for a shift amount of 0. So $rs1 needs to
come from operand 0 of fshl and operand 1 of fshr.
Differential Revision: https://reviews.llvm.org/D90735
Duncan P. N. Exon Smith [Thu, 29 Oct 2020 19:11:40 +0000 (15:11 -0400)]
Basic: Split out DirectoryEntry.h, NFC
Move `DirectoryEntry` and `DirectoryEntryRef` into their own header,
similar to the creation of FileEntry.h. No functionality change here,
just preparing to include it in more places to allow wider adoption of
`DirectoryEntryRef` without requiring all of `FileManager.h`.
Differential Revision: https://reviews.llvm.org/D90478
Fraser Cormack [Tue, 21 Apr 2020 15:23:11 +0000 (16:23 +0100)]
[DAGCombine] Fix bug in load scalarization
Summary:
For vector element types which are not byte-sized, we would generate
incorrect scalar offsets and produce incorrect codegen.
This optimization could potentially be supported in the future, e.g. by
loading in bytes, then shifting and masking out the remaining bits of
the vector element. However, without an upstream target to test against
it's best to avoid the bad codegen in the simplest possible way.
Related to this bug:
https://bugs.llvm.org/show_bug.cgi?id=27600
Reviewed by: foad
Differential Revision: https://reviews.llvm.org/D78568
Louis Dionne [Wed, 4 Nov 2020 19:07:59 +0000 (14:07 -0500)]
[libc++] NFC: Remove trailing whitespace
Mehdi Amini [Wed, 4 Nov 2020 06:26:46 +0000 (06:26 +0000)]
Refactor PyPrintAccumulatorm, PyFileAccumulator, and PySinglePartStringAccumulator from IRModules.cpp to PybindUtils.h
These are reusable utilities across bindings.
Differential Revision: https://reviews.llvm.org/D90737
Mehdi Amini [Wed, 4 Nov 2020 06:25:05 +0000 (06:25 +0000)]
Move MlirStringCallback declaration from mlir-c/IR.h to mlir-c/Support.h (NFC)
This is a generic utility that can be reused beyond the IR bindings.
Differential Revision: https://reviews.llvm.org/D90736
cchen [Wed, 4 Nov 2020 18:36:38 +0000 (12:36 -0600)]
[OpenMP] target nested `use_device_ptr() if()` and is_device_ptr trigger asserts
Clang now asserts for the below case:
```
void clang::CodeGen::CGOpenMPRuntime::createOffloadEntriesAndInfoMetadata(): Assertion `std::get<0>(E) && "All ordered entries must exist!"' failed.
```
The reason why Clang hit the assert is because in
`emitTargetDataCalls`, both `BeginThenGen` and `BeginElseGen` call
`registerTargetRegionEntryInfo` and try to register the Entry in
OffloadEntriesTargetRegion with same key. If changing the expression in
if clause to any constant expression, then the assert disappear. (https://godbolt.org/z/TW7haj)
The assert itself is to avoid
user from accessing elements out of bound inside `OrderedEntries` in
`createOffloadEntriesAndInfoMetadata`.
In this patch, I add a check in `registerTargetRegionEntryInfo` to avoid
register the target region more than once.
A test case that triggers assert: https://godbolt.org/z/4cnGW8
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D90704
Craig Topper [Wed, 4 Nov 2020 18:35:05 +0000 (10:35 -0800)]
[RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns.
riscv_sllw/srlw only reads the lower 32 bits of the first operand.
And the lower 5 bits of the second operands. Whether the upper
32 bits of the input are sign bits or not doesn't matter.
Also use ineg and not to shorten the patterns.
Differential Revision: https://reviews.llvm.org/D90668
Rahul Joshi [Wed, 4 Nov 2020 16:14:05 +0000 (08:14 -0800)]
[MLIR] Refactor memref type -> LLVM Type conversion
- Eliminate duplicated information about mapping from memref -> its descriptor fields
by consolidating that mapping in two functions: getMemRefDescriptorFields and
getUnrankedMemRefDescriptorFields.
- Change convertMemRefType() and convertUnrankedMemRefType() to use these
functions.
- Remove convertMemrefSignature and convertUnrankedMemrefSignature.
Differential Revision: https://reviews.llvm.org/D90707
Rahul Joshi [Wed, 4 Nov 2020 16:20:46 +0000 (08:20 -0800)]
[MLIR] Remove NoSideEffect from std.global_memref op.
- Also spell "isUninitialized" correctly.
Differential Revision: https://reviews.llvm.org/D90768
Arnold Schwaighofer [Wed, 21 Oct 2020 21:41:47 +0000 (14:41 -0700)]
Start of an llvm.coro.async implementation
This patch adds the `async` lowering of coroutines.
This will be used by the Swift frontend to lower async functions. In
contrast to the `retcon` lowering the frontend needs to be in control
over control-flow at suspend points as execution might be suspended at
these points.
This is very much work in progress and the implementation will change as
it evolves with the frontend. As such the documentation is lacking
detail as some of it might change.
rdar://
70097093
Reapply with fix for memory sanitizer failure and sphinx failure.
Differential Revision: https://reviews.llvm.org/D90612
Sean Silva [Tue, 3 Nov 2020 01:18:46 +0000 (17:18 -0800)]
[mlir] Make linalg-bufferize a composable bufferization pass
Previously, linalg-bufferize was a "finalizing" bufferization pass (it
did a "full" conversion). This wasn't great because it couldn't be used
composably with other bufferization passes like std-bufferize and
scf-bufferize.
This patch makes linalg-bufferize a composable bufferization pass.
Notice that the integration tests are switched over to using a pipeline
of std-bufferize, linalg-bufferize, and (to finalize the conversion)
func-bufferize. It all "just works" together.
While doing this transition, I ran into a nasty bug in the 1-use special
case logic for forwarding init tensors. That logic, while
well-intentioned, was fundamentally flawed, because it assumed that if
the original tensor value had one use, then the converted memref could
be mutated in place. That assumption is wrong in many cases. For
example:
```
%0 = some_tensor : tensor<4xf32>
br ^bb0(%0, %0: tensor<4xf32>, tensor<4xf32>)
^bb0(%bbarg0: tensor<4xf32>, %bbarg1: tensor<4xf32>)
// %bbarg0 is an alias of %bbarg1. We cannot safely write
// to it without analyzing uses of %bbarg1.
linalg.generic ... init(%bbarg0) {...}
```
A similar example can happen in many scenarios with function arguments.
Even more sinister, if the converted memref is produced by a
`std.get_global_memref` of a constant global memref, then we might
attempt to write into read-only statically allocated storage! Not all
memrefs are writable!
Clearly, this 1-use check is not a local transformation that we can do
on the fly in this pattern, so I removed it.
The test is now drastically shorter and I basically rewrote the CHECK
lines from scratch because:
- the new composable linalg-bufferize just doesn't do as much, so there
is less to test
- a lot of the tests were related to the 1-use check, which is now gone,
so there is less to test
- the `-buffer-hoisting -buffer-deallocation` is no longer mixed in, so
the checks related to that had to be rewritten
Differential Revision: https://reviews.llvm.org/D90657
Sean Silva [Mon, 2 Nov 2020 23:12:55 +0000 (15:12 -0800)]
[mlir] Fix materializations for unranked tensors.
Differential Revision: https://reviews.llvm.org/D90656
Craig Topper [Wed, 4 Nov 2020 18:15:30 +0000 (10:15 -0800)]
[RISCV] Check all 64-bits of the mask in SelectRORIW.
We need to ensure the upper 32 bits of the mask are zero.
So that the srl shifts zeroes into the lower 32 bits.
Differential Revision: https://reviews.llvm.org/D90585
Mehdi Amini [Wed, 4 Nov 2020 18:08:34 +0000 (18:08 +0000)]
Switch from C-style comments `/* ... */` to C++ style `//` (NFC)
This is mostly a scripted update, it may not be perfect.
function replace() {
FROM=$1
TO=$2
git grep "$FROM" $REPO_PATH |cut -f 1 -d : | sort -u | \
while read file; do
sed -i "s#$FROM#$TO#" $file ;
done
}
replace '|\*===----------------------------------------------------------------------===\*|$' '//===----------------------------------------------------------------------===//'
replace '^/\* =' '//=='
replace '^/\*=' '//='
replace '^\\\*=' '//='
replace '^|\*' '//'
replace ' \*|$' ''
replace '=\*\\$' '=//'
replace '== \*/$' '===//'
replace '==\*/$' '==//'
replace '^/\*\*\(.*\)\*/$' '///\1'
replace '^/\*\(.*\)\*/$' '//\1'
replace '//============================================================================//' '//===----------------------------------------------------------------------===//'
Differential Revision: https://reviews.llvm.org/D90732
Christopher Tetreault [Wed, 4 Nov 2020 17:16:09 +0000 (09:16 -0800)]
[UBSan] Cannot negate smallest negative signed integer
Silence warning Undefined Behavior Sanitzer warning:
runtime error: negation of -
9223372036854775808 cannot be represented in type 'int64_t' (aka 'long'); cast to an unsigned type to negate this value to itself
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D90710
Craig Topper [Wed, 4 Nov 2020 17:59:14 +0000 (09:59 -0800)]
[RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI
We don't need custom matching, we just a need a predicate to check
the immediate is greater than 32. We can use the existing ImmSub32
to adjust the immediate.
I've also used the new predicate in the other location that used
ImmSub32. I tried to create a test case where we would break without
the greater than 32 check on that pattern, but DAG combine defeated me.
Still seemed safer to have it.
Differential Revision: https://reviews.llvm.org/D90546
Joe Nash [Tue, 3 Nov 2020 22:26:29 +0000 (17:26 -0500)]
[AMDGPU] Resolve pseudo registers at encoding uses
Pseudo-registers allow different register encodings
between gpu generations. Make sure we resolve the
pseudo regs to real regs whenever we get their
hardware encoding.
Using the correct encodings revealed a register
bank conflict and an unnecessary write dependency.
Tests have been updated to match.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D90721
Change-Id: I73c154cd24aecc820993b50bebaf4df97a5710ca
Fangrui Song [Wed, 4 Nov 2020 17:54:04 +0000 (09:54 -0800)]
Revert "[GlobalISel] GISelKnownBits::computeKnownBitsImpl - Replace TargetOpcode::G_MUL handling with the common KnownBits::computeForMul implementation"
This reverts commit
0b8711e1af97d6c82dc9d25c12c5a06af060cc56 which broke GlobalISelTests AArch64GISelMITest.TestKnownBits
Arthur Eubanks [Sun, 1 Nov 2020 06:08:15 +0000 (23:08 -0700)]
[NewPM] Don't run before pass instrumentation on required passes
This allows those instrumentation to log when they decide to skip a
pass. This provides extra helpful info for optnone functions and also
will help with opt-bisect.
Have OptNoneInstrumentation print when it skips due to seeing optnone.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D90545
Sebastian Neubauer [Thu, 29 Oct 2020 16:52:22 +0000 (17:52 +0100)]
[AMDGPU] Fix iterating in SIFixSGPRCopies
The insertion of waterfall loops splits the current basic block into
three blocks. So the basic block that we iterate over must be updated.
This failed assert(!NodePtr->isKnownSentinel()) in ilist_iterator for
divergent calls in branches before.
Differential Revision: https://reviews.llvm.org/D90596
Fangrui Song [Wed, 4 Nov 2020 17:39:14 +0000 (09:39 -0800)]
[llvm-objcopy] Make --set-section-flags work with --add-section
This matches behavior GNU objcopy and can simplify clang-offload-bundler
(which currently works around the issue by invoking llvm-objcopy twice).
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D90438
Alexander Shaposhnikov [Wed, 4 Nov 2020 08:30:43 +0000 (00:30 -0800)]
[llvm-objcopy][MachO] Make isValidMachOCannonicalName static
This diff makes the function isValidMachOCannonicalName static.
NFC.
Test plan: make check-all
Mehdi Amini [Wed, 4 Nov 2020 00:08:35 +0000 (00:08 +0000)]
Add facilities to print/parse a pass pipeline through the C API
This also includes and exercise a register function for individual
passes.
Differential Revision: https://reviews.llvm.org/D90728
Simon Pilgrim [Wed, 4 Nov 2020 17:15:54 +0000 (17:15 +0000)]
[KnownBits] KnownBits::computeForMul - avoid unnecessary APInt copies. NFCI.
Use const references instead.
Simon Pilgrim [Wed, 4 Nov 2020 17:06:19 +0000 (17:06 +0000)]
[GlobalISel] GISelKnownBits::computeKnownBitsImpl - Replace TargetOpcode::G_MUL handling with the common KnownBits::computeForMul implementation
Avoid code duplication
Nabeel Omer [Wed, 4 Nov 2020 16:57:19 +0000 (16:57 +0000)]
[Dexter] add visual studio 2019 debugger support
Adds visual studio debugger support to dexter via option --debugger vs2019
Differential Revision: https://reviews.llvm.org/D89803
Author: Nabeel Omer <nabeel.omer@sony.com>
Nabeel Omer [Wed, 4 Nov 2020 16:54:36 +0000 (16:54 +0000)]
[Dexter] add an optnone attribute debug experience test for loops.
adds a test that checks debugging experience in functions that are marked
__attribute__((optnone)) and have loops inside them.
Differential Revision: https://reviews.llvm.org/D89873
Author: Nabeel Omer <nabeel.omer@sony.com>
Louis Dionne [Wed, 4 Nov 2020 16:43:47 +0000 (11:43 -0500)]
[libc++] Remove the ability to not install the support headers
Those are part of the library, and shipping them just adds a tiny bit of
size to the distribution. This was originally added in
b422ecc7de0b to
make it possible to match the Makefile build, which doesn't exist anymore.
The upside is build system simplification.
Arnold Schwaighofer [Wed, 4 Nov 2020 16:25:24 +0000 (08:25 -0800)]
Revert "Start of an llvm.coro.async implementation"
This reverts commit
ea606cced0583d1dbd4c44680601d1d4e9a56e58.
This patch causes memory sanitizer failures sanitizer-x86_64-linux-fast.
Louis Dionne [Wed, 4 Nov 2020 16:19:52 +0000 (11:19 -0500)]
[libc++] Split off part of a test that require signals into a separate test
This will allow running the basic test on all platforms, and the part that
requires signals on platforms that support them only.
Vy Nguyen [Wed, 4 Nov 2020 15:13:47 +0000 (10:13 -0500)]
Fix breakage in D89615 (due to cmake version 3.16.5)
Differential Revision: https://reviews.llvm.org/D90764
Kadir Cetinkaya [Wed, 4 Nov 2020 08:48:23 +0000 (09:48 +0100)]
[clangd] Cleanup dependencies around RemoteIndex
RemoteIndexClient implementations only depends on clangdSupport for
logging functionality and has no dependence on clangDeamon itself. This clears
out that link time dependency and enables depending on it in clangDeamon itself,
so that we can have other index implementations that makes use of the
RemoteIndex.
Differential Revision: https://reviews.llvm.org/D90746
LLVM GN Syncbot [Wed, 4 Nov 2020 15:36:49 +0000 (15:36 +0000)]
[gn build] Port
d1b2a523191
Balázs Kéri [Wed, 4 Nov 2020 14:09:09 +0000 (15:09 +0100)]
[clang-tidy] Add signal-handler-check for SEI CERT rule SIG30-C
SIG30-C. Call only asynchronous-safe functions within signal handlers
First version of this check, only minimal list of functions is allowed
("strictly conforming" case), for C only.
Differential Revision: https://reviews.llvm.org/D87449
Arnold Schwaighofer [Wed, 21 Oct 2020 21:41:47 +0000 (14:41 -0700)]
Start of an llvm.coro.async implementation
This patch adds the `async` lowering of coroutines.
This will be used by the Swift frontend to lower async functions. In
contrast to the `retcon` lowering the frontend needs to be in control
over control-flow at suspend points as execution might be suspended at
these points.
This is very much work in progress and the implementation will change as
it evolves with the frontend. As such the documentation is lacking
detail as some of it might change.
rdar://
70097093
Differential Revision: https://reviews.llvm.org/D90612
Eric Astor [Wed, 4 Nov 2020 15:00:51 +0000 (10:00 -0500)]
[ms] [llvm-ml] Enable support for MASM-style macro procedures
Allows the MACRO directive to define macro procedures with parameters and macro-local symbols.
Supports required and optional parameters (including default values), and matches ml64.exe for its macro-local symbol handling (up to 65536 macro-local symbols in any translation unit).
Reviewed By: thakis
Differential Revision: https://reviews.llvm.org/D89729
Pavel Labath [Wed, 4 Nov 2020 15:25:38 +0000 (16:25 +0100)]
[lldb] Remove [US]IntValueIsValidForSize from CommandObjectMemory
Use llvm::is(U)IntN (MathExtras.h) instead.
Pavel Labath [Wed, 4 Nov 2020 14:13:44 +0000 (15:13 +0100)]
[lldb/Utility] Delete Scalar::[US]IntValueIsValidForSize
It's unused, and the same functionality is available in llvm (is(U)IntN
in MathExtras.h).
Simon Pilgrim [Wed, 4 Nov 2020 14:21:51 +0000 (14:21 +0000)]
Use isa<> instead of dyn_cast<> to avoid unused variable warning. NFCI.
Simon Pilgrim [Wed, 4 Nov 2020 14:20:19 +0000 (14:20 +0000)]
Fix gcc braces warning. NFCI.
gcc warns that the EXPECT_TRUE macro isn't surrounded by if() {} - we already do this in other cases in the file.
Louis Dionne [Wed, 4 Nov 2020 15:14:13 +0000 (10:14 -0500)]
[libc++] NFCI: Refactor chrono.cpp to make it easier to support new platforms
Also simplify a few conditionals along the way for readability.
Aaron Ballman [Wed, 4 Nov 2020 15:06:44 +0000 (10:06 -0500)]
Add a floating-point suffix to silence warnings; NFC
This silences about 6000 warnings about truncating from double to float
with Visual Studio.
etiotto [Wed, 4 Nov 2020 14:49:52 +0000 (09:49 -0500)]
[compiler-rt][AIX]: Link compiler-rt profile library when -fprofile-generate is specified
This patch enhances the clang driver to link the runtime profile
library on AIX when the -fprofile-generate option is used.
Reviewed By: phosek
Differentail Revision: https://reviews.llvm.org/D90641
Vy Nguyen [Wed, 4 Nov 2020 14:54:07 +0000 (09:54 -0500)]
[NFC]Remove unused variable
Accidentally committed in D89615
Vy Nguyen [Sat, 17 Oct 2020 05:57:02 +0000 (01:57 -0400)]
Disable emulated-tls for compiler-rt+tests on Android if ELF_TLS is presence.
This is necessary for enabling LSAN on Android (D89251) because:
- LSAN will have false negatives if run with emulated-tls.
- Bionic ELF-TLS is not compatible with Gold (hence the need for LLD)
Differential Revision: https://reviews.llvm.org/D89615
Paul C. Anagnostopoulos [Fri, 30 Oct 2020 15:40:42 +0000 (11:40 -0400)]
[TableGen] Add !interleave operator to concatenate a list of values with delimiters
Add a test. Use it in some TableGen files.
Differential Revision: https://reviews.llvm.org/D90469
Paul C. Anagnostopoulos [Sat, 31 Oct 2020 14:40:53 +0000 (10:40 -0400)]
[TableGen] [IR] Eliminate unnecessary recursive help class.
Differential Revision: https://reviews.llvm.org/D90532
Pavel Labath [Tue, 3 Nov 2020 15:15:15 +0000 (16:15 +0100)]
[lldb] Improve RegisterValue::GetScalarValue
Using Scalar::SetValueFromData, we make the code simpler, handle
big-endian systems properly, _and_ avoid type aliasing issues.
Louis Dionne [Wed, 4 Nov 2020 13:47:48 +0000 (08:47 -0500)]
[libc++] Remove test that is irrelevant since
f1a96de1bc8d
We don't want to give the impression that we allow running arbitrary
shell commands under %{exec}, which isn't the case.
Louis Dionne [Tue, 3 Nov 2020 19:45:52 +0000 (14:45 -0500)]
[libc++] Don't run tests in a shell in the default executor
Sanjay Patel [Tue, 3 Nov 2020 23:32:17 +0000 (18:32 -0500)]
[InstSimplify] allow vector folds for icmp Pred (1 << X), 0x80
Sanjay Patel [Tue, 3 Nov 2020 22:45:07 +0000 (17:45 -0500)]
[InstSimplify] add vector cmp tests; NFC
Roman Lebedev [Wed, 4 Nov 2020 11:33:11 +0000 (14:33 +0300)]
[Reassociate] Guard `add`-like `or` conversion into an `add` with profitability check
This is slightly better compile-time wise,
since we avoid potentially-costly knownbits analysis that will
ultimately not allow us to actually do anything with said `add`.
Nicolas Vasilache [Wed, 4 Nov 2020 11:19:51 +0000 (11:19 +0000)]
[mlir][std] Add DimOp folding for dim(tensor_load(m)) -> dim(m).
Differential Revision: https://reviews.llvm.org/D90755
Frederik Gossen [Wed, 4 Nov 2020 11:02:08 +0000 (11:02 +0000)]
[MLIR] Support walks over regions and blocks
Relands
- [MLIR] Support walks over regions and blocks
(
dbae3d50f114a8ec0a7c3211e3b1b9fb6ef22dbd)
- [MLIR] Use llvm::is_one_of in walk templates
(
56299b1e58bf3720dff2fe60163739ee1554a371)
Differential Revision: https://reviews.llvm.org/D90753
Clement Courbet [Wed, 4 Nov 2020 12:22:01 +0000 (13:22 +0100)]
[llvm-exegesis] Fix rGaf658d920e2b
Add missing header.
```
../../llvm/tools/llvm-exegesis/lib/X86/Target.cpp(606,14): error: use of undeclared identifier '__readeflags'
Eflags = __readeflags();
```
LLVM GN Syncbot [Wed, 4 Nov 2020 12:00:24 +0000 (12:00 +0000)]
[gn build] Port
73b6cb67dcd
LLVM GN Syncbot [Wed, 4 Nov 2020 12:00:24 +0000 (12:00 +0000)]
[gn build] Port
1124bf4ab77
Nico Weber [Wed, 4 Nov 2020 12:00:05 +0000 (07:00 -0500)]
[gn build] try to port
707d69ff32309b
Simon Moll [Wed, 4 Nov 2020 11:41:11 +0000 (12:41 +0100)]
[VE] Add +vpu attribute
`+vpu` controls whether VEISelLowering adds any vregs. This defaults to
`-vpu` to have scalar code generation out of the box. We bring up
vector isel under the `+vpu` flag. Once vector isel is stable we switch
to `+vpu` and advertise vregs and vops in TTI.
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D90465
Kerry McLaughlin [Wed, 4 Nov 2020 11:08:10 +0000 (11:08 +0000)]
[SVE][CodeGen] Lower scalable integer vector reductions
This patch uses the existing LowerFixedLengthReductionToSVE function to also lower
scalable vector reductions. A separate function has been added to lower VECREDUCE_AND
& VECREDUCE_OR operations with predicate types using ptest.
Lowering scalable floating-point reductions will be addressed in a follow up patch,
for now these will hit the assertion added to expandVecReduce() in TargetLowering.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D89382
Nicolas Vasilache [Wed, 4 Nov 2020 10:01:26 +0000 (10:01 +0000)]
[mlir][SCF] Add canonicalization pattern for scf::For to eliminate yields that just forward.
For instance:
```
func @for_yields_3(%lb : index, %ub : index, %step : index) -> (i32, i32, i32) {
%a = call @make_i32() : () -> (i32)
%b = call @make_i32() : () -> (i32)
%r:3 = scf.for %i = %lb to %ub step %step iter_args(%0 = %a, %1 = %a, %2 = %b) -> (i32, i32, i32) {
%c = call @make_i32() : () -> (i32)
scf.yield %0, %c, %2 : i32, i32, i32
}
return %r#0, %r#1, %r#2 : i32, i32, i32
}
```
Canonicalizes as:
```
func @for_yields_3(%arg0: index, %arg1: index, %arg2: index) -> (i32, i32, i32) {
%0 = call @make_i32() : () -> i32
%1 = call @make_i32() : () -> i32
%2 = scf.for %arg3 = %arg0 to %arg1 step %arg2 iter_args(%arg4 = %0) -> (i32) {
%3 = call @make_i32() : () -> i32
scf.yield %3 : i32
}
return %0, %2, %1 : i32, i32, i32
}
```
Differential Revision: https://reviews.llvm.org/D90745
Simon Pilgrim [Wed, 4 Nov 2020 10:59:56 +0000 (10:59 +0000)]
[DAG] computeKnownBits - Replace ISD::MUL handling with the common KnownBits::computeForMul implementation
Jon Chesterfield [Wed, 4 Nov 2020 11:28:35 +0000 (11:28 +0000)]
[libomptarget][nfc] Build amdgcn deviceRTL with nogpulib
Sebastian Neubauer [Wed, 14 Oct 2020 15:14:25 +0000 (17:14 +0200)]
[AMDGPU] Set rsrc1 flags for graphics shaders
Before they were only set for compute kernels and compute shaders but
not for other shaders.
Differential Revision: https://reviews.llvm.org/D89399
Sebastian Neubauer [Wed, 14 Oct 2020 12:11:47 +0000 (14:11 +0200)]
[AMDGPU] Fix ieee mode default value
Previously, the default value for ieee mode was
- on for compute kernels and compute shaders,
- off for all shaders except compute shaders.
This commit changes the default to be
- on for compute kernels,
- off for shaders.
This aligns the default value with the settings that are actually in
use. To my knowledge, all users of shader calling conventions (mesa and
llpc) disable the ieee mode by default.
Differential Revision: https://reviews.llvm.org/D89388
Vitaly Buka [Wed, 4 Nov 2020 10:31:16 +0000 (02:31 -0800)]
[NFC][UBSAN] Replace "count 0" with FileCheck
Unrelated system warnings may confuse "check 0"
Andrzej Warzynski [Wed, 4 Nov 2020 10:30:19 +0000 (10:30 +0000)]
[mlir] Fix failing shared libraries build
Failing buildbot: http://lab.llvm.org:8011/#/builders/33/builds/478
Patch that introduced the breaking change: https://reviews.llvm.org/D90667
Stefan Gränitz [Wed, 4 Nov 2020 10:02:59 +0000 (10:02 +0000)]
[JITLink][ELF] Omit temporary labels in tests
Oneshot temporary labels for declaring function size can be omitted. Follow-up from D90331.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D90676
Qiu Chaofan [Wed, 4 Nov 2020 09:57:14 +0000 (17:57 +0800)]
[Clang] Add more fp128 math library function builtins
Since glibc has supported math library functions conforming IEEE 128-bit
floating point types on some platform (like ppc64le), we can fix clang's
math builtins missing this type.
Reviewed By: bkramer
Differential Revision: https://reviews.llvm.org/D90593
Clement Courbet [Mon, 2 Nov 2020 13:25:14 +0000 (14:25 +0100)]
[llvm-exegesis][X86] Save and restore eflags.
This is needed to benchmark instruction that touch EFLAGS (e.g. STD: set direction flag).
Differential Revision: https://reviews.llvm.org/D90742
Kadir Cetinkaya [Fri, 30 Oct 2020 11:06:16 +0000 (12:06 +0100)]
[clangd] Pass parameters to config apply functions
This will enable some fragments to apply their features selectively.
Depends on D90270.
Differential Revision: https://reviews.llvm.org/D90455
Pavel Labath [Tue, 3 Nov 2020 16:22:35 +0000 (17:22 +0100)]
[lldb] Delete Value::Vector class
This class and it's surroundings contain a lot of shady code, but as far
as I can tell all of that code is unreachable (there is no code actually
setting the value to eValueTypeVector).
According to history this class was introduced in 2012 in
r167033/
0665a0f09. At that time, the code seemed to serve some purpose,
and it had two entry points (in Value::SetContext and
ClangExpressionDeclMap::LookupDecl). The first entry point was deleted
in D17897 and the second one in r179842/
44342735.
The stated purpose of the patch introducing this class was to fix
TestRegisters.py, and "expr $xmm0" in particular. Both of these things
function perfectly well these days without this class.
Vitaly Buka [Wed, 4 Nov 2020 09:14:13 +0000 (01:14 -0800)]
[sanitizer] Remove ANDROID_NDK_VERSION
Clement Courbet [Wed, 4 Nov 2020 09:09:07 +0000 (10:09 +0100)]
[llvm-exegesis] Fix unused variable warning.
David Green [Wed, 4 Nov 2020 09:00:03 +0000 (09:00 +0000)]
[ARM] Remove unused variable. NFC
Vitaly Buka [Tue, 3 Nov 2020 04:45:57 +0000 (20:45 -0800)]
[sanitizer] Remove -Wno-non-virtual-dtor
Warning should be fixed with
d48f2d7c02743571075bb7812bb4c9e634e51ed1
Vy Nguyen [Wed, 4 Nov 2020 00:10:35 +0000 (16:10 -0800)]
Use LLD for Android compiler-rt
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D90720
Sander de Smalen [Tue, 3 Nov 2020 16:44:20 +0000 (16:44 +0000)]
[NFCI] Replace AArch64StackOffset by StackOffset.
This patch replaces the AArch64StackOffset class by the generic one
defined in TypeSize.h.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D88983
Clement Courbet [Wed, 4 Nov 2020 07:56:27 +0000 (08:56 +0100)]
Re-land "[llvm-exegesis] Save target state before running the benchmark."
The X86 exegesis target is never executed run on non-X86 hosts, disable
X86 instrinsic code on non-X86 targets.
This reverts commit
8cfc872129a99782ab07a19171bf8eace85589ae.
Alex Zinenko [Wed, 4 Nov 2020 08:42:32 +0000 (09:42 +0100)]
[mlir] Add a simpler lowering pattern for WhileOp representing a do-while loop
When the "after" region of a WhileOp is merely forwarding its arguments back to
the "before" region, i.e. WhileOp is a canonical do-while loop, a simpler CFG
subgraph that omits the "after" region with its extra branch operation can be
produced. Loop rotation from general "while" to "if { do-while }" is left for a
future canonicalization pattern when it becomes necessary.
Differential Revision: https://reviews.llvm.org/D90604
Alex Zinenko [Wed, 4 Nov 2020 08:42:04 +0000 (09:42 +0100)]
[mlir] Add lowering to CFG for WhileOp
The lowering is a straightforward inlining of the "before" and "after" regions
connected by (conditional) branches. This plugs the WhileOp into the
progressive lowering scheme. Future commits may choose to target WhileOp
instead of CFG when lowering ForOp.
Differential Revision: https://reviews.llvm.org/D90603
Alex Zinenko [Wed, 4 Nov 2020 08:41:55 +0000 (09:41 +0100)]
[mlir] Add a generic while/do-while loop to the SCF dialect
The new construct represents a generic loop with two regions: one executed
before the loop condition is verifier and another after that. This construct
can be used to express both a "while" loop and a "do-while" loop, depending on
where the main payload is located. It is intended as an intermediate
abstraction for lowering, which will be added later. This form is relatively
easy to target from higher-level abstractions and supports transformations such
as loop rotation and LICM.
Differential Revision: https://reviews.llvm.org/D90255
Nathan Ridge [Mon, 19 Oct 2020 05:22:21 +0000 (01:22 -0400)]
[clangd] Store the containing symbol for refs
This is needed to implement call hierarchy.
Differential Revision: https://reviews.llvm.org/D89670