Francisco Jerez [Fri, 2 Sep 2016 02:34:18 +0000 (19:34 -0700)]
i965/fs: Drop fs_inst::overwrites_reg() in favor of regions_overlap().
fs_inst::overwrites_reg is rather easy to misuse because it cannot
tell how large the register region starting at 'reg' is, so in cases
where the destination region starts after 'reg' it may give a
misleading result. regions_overlap() is somewhat more verbose to use
but handles arbitrary overlap correctly so it should generally be used
instead.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:36:59 +0000 (21:36 -0700)]
i965/fs: Fix LOAD_PAYLOAD handling in register coalesce is_nop_mov().
is_nop_mov() was broken for LOAD_PAYLOAD instructions in two ways: On
the one hand the original destination register offset wasn't being
taken into account which would give incorrect results if it was
already non-zero, and on the other hand all source registers were
being treated as if they had a size of 32B, which is almost never the
case in SIMD16 programs for non-header sources.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:20:18 +0000 (21:20 -0700)]
i965/fs: Fix can_propagate_from() source/destination overlap check.
The previous overlap condition only made sure that the VGRF numbers or
GRF-aligned offsets were different without taking the amount of data
written and read by the instruction into consideration. Use the
regions_overlap() helper instead.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:16:14 +0000 (21:16 -0700)]
i965/fs: Compare full register offsets in cmod propagation pass.
This could potentially have misoptimized a program in cases where
inst->src[0] had a non-zero sub-GRF offset.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 02:32:37 +0000 (19:32 -0700)]
i965/fs: Don't consider LOAD_PAYLOAD with stride > 1 source to behave like a raw copy.
Noticed the problem by inspection while typing in the previous commit.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:05:51 +0000 (21:05 -0700)]
i965/fs: Don't consider LOAD_PAYLOAD with sub-GRF offset to behave like a raw copy.
This was likely the original intention, and at least register coalesce
relies on it.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 00:57:34 +0000 (17:57 -0700)]
i965/vec4: Take into account misalignment in regs_written() and regs_read().
Unlike the FS counterpart of this commit this was likely not (yet) a
bug, but let's fix it already in preparation for implementing support
for sub-GRF offsets in the VEC4 back-end.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 21:36:32 +0000 (14:36 -0700)]
i965/fs: Take into account misalignment in regs_written() and regs_read().
There was a workaround for this in fs_inst::size_read() for the
SHADER_OPCODE_MOV_INDIRECT instruction and FIXED_GRF register file
*only*. We should take this possibility into account for the sources
and destinations of all instructions on all optimization passes that
need to quantize dataflow in 32B increments by adding the amount of
misalignment to the size read or written from the regs_read() and
regs_written() helpers respectively.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 21:33:55 +0000 (14:33 -0700)]
i965/fs: Take into account trailing padding in regs_written() and regs_read().
This fixes regs_written() and regs_read() to return a more accurate
value when the padding left between components due to a stride value
greater than one causes the region bounds given by size_written or
size_read to overflow into the next register. This could become a
problem in optimization passes that keep track of dataflow using
fixed-size arrays with register granularity, because the overflow
register (not actually accessed by the region) may not have been
allocated at all which could lead to undefined memory access.
An alternative to this would be to subtract the trailing padding
already during the calculation of fs_inst::size_read and
::size_written, but that would break code that currently assumes that
::size_read and _written are whole multiples of the component size,
and would be hard to maintain looking forward because size_written is
assigned from a bunch of different places.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:41:08 +0000 (13:41 -0700)]
i965/fs: Handle fixed HW GRF subnr in reg_offset().
This will be useful later on when we start using reg_offset() on fixed
hardware registers.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:25:18 +0000 (21:25 -0700)]
i965/fs: Handle arbitrary offsets in brw_reg_from_fs_reg for MRF/VGRF registers.
This restriction seemed rather artificial... Removing it actually
simplifies things slightly.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:02:55 +0000 (13:02 -0700)]
i965/fs: Return more accurate read size for LINTERP from fs_inst::size_read.
The LINTERP virtual instruction only reads three scalar components
from the first 16B of the second source, we can now teach size_read()
about it since its return value is represented with byte granularity.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 23:23:44 +0000 (16:23 -0700)]
i965/fs: Return more accurate read size from fs_inst::size_read for IMM and UNIFORM files.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 8 Sep 2016 00:00:30 +0000 (17:00 -0700)]
i965/vec4: Replace vec4_instruction::regs_read with ::size_read using byte units.
The previous regs_read value can be recovered by rewriting each
reference of regs_read() like 'x = i.regs_read(j)' to 'x =
DIV_ROUND_UP(i.size_read(j), reg_unit)'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 8 Sep 2016 00:00:07 +0000 (17:00 -0700)]
i965/fs: Replace fs_inst::regs_read with ::size_read using byte units.
The previous regs_read value can be recovered by rewriting each
reference of regs_read() like 'x = i.regs_read(j)' to 'x =
DIV_ROUND_UP(i.size_read(j), reg_unit)'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sun, 4 Sep 2016 01:19:59 +0000 (18:19 -0700)]
i965/ir: Drop backend_instruction::regs_written field.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 01:00:21 +0000 (18:00 -0700)]
i965/vec4: Replace vec4_instruction::regs_written with ::size_written field in bytes.
The previous regs_written field can be recovered by rewriting each
rvalue reference of regs_written like 'x = i.regs_written' to 'x =
DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference
like 'i.regs_written = x' to 'i.size_written = x * reg_unit'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:38:20 +0000 (13:38 -0700)]
i965/fs: Replace fs_inst::regs_written with ::size_written field in bytes.
The previous regs_written field can be recovered by rewriting each
rvalue reference of regs_written like 'x = i.regs_written' to 'x =
DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference
like 'i.regs_written = x' to 'i.size_written = x * reg_unit'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 23:55:46 +0000 (16:55 -0700)]
i965/vec4: Add wrapper functions for vec4_instruction::regs_read and ::regs_written.
This is in preparation for dropping vec4_instruction::regs_read and
::regs_written in favor of more accurate alternatives expressed in
byte units. The main reason these wrappers are useful is that a
number of optimization passes implement dataflow analysis with
register granularity, so these helpers will come in handy once we've
switched register offsets and sizes to the byte representation. The
wrapper functions will also make sure that GRF misalignment (currently
neglected by most of the back-end) is taken into account correctly in
the calculation of regs_read and regs_written.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 23:59:35 +0000 (16:59 -0700)]
i965/fs: Add wrapper functions for fs_inst::regs_read and ::regs_written.
This is in preparation for dropping fs_inst::regs_read and
::regs_written in favor of more accurate alternatives expressed in
byte units. The main reason these wrappers are useful is that a
number of optimization passes implement dataflow analysis with
register granularity, so these helpers will come in handy once we've
switched register offsets and sizes to the byte representation. The
wrapper functions will also make sure that GRF misalignment (currently
neglected by most of the back-end) is taken into account correctly in
the calculation of regs_read and regs_written.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 22:11:21 +0000 (15:11 -0700)]
i965/fs: Replace fs_reg::subreg_offset with fs_reg::offset expressed in bytes.
The fs_reg::subreg_offset and ::offset fields are now redundant, the
sub-GRF offset can just be added to the single ::offset field
expressed in byte units. The current subreg_offset value can be
recovered by applying the following rule: Replace each rvalue
reference of subreg_offset like 'x = r.subreg_offset' with 'x =
r.offset % reg_unit', and each lvalue reference like 'r.subreg_offset
= x' with 'r.offset = ROUND_DOWN_TO(r.offset, reg_unit) + x'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 21:19:27 +0000 (14:19 -0700)]
i965/ir: Remove backend_reg::reg_offset.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 20:10:36 +0000 (13:10 -0700)]
i965/vec4: Replace dst/src_reg::reg_offset with dst/src_reg::offset expressed in bytes.
The dst/src_reg::offset field in byte units introduced in the previous
patch is a more straightforward alternative to an offset
representation split between ::reg_offset and ::subreg_offset fields.
The split representation makes it too easy to forget about one of the
offsets while dealing with the other, which has led to multiple FS
back-end bugs in the past. To make the matter worse the unit
reg_offset was expressed in was rather inconsistent, for uniforms it
would be expressed in either 4B or 16B units depending on the
back-end, and for most other things it would be expressed in 32B
units.
This encodes reg_offset as a new offset field expressed consistently
in byte units. Each rvalue reference of reg_offset in existing code
like 'x = r.reg_offset' is rewritten to 'x = r.offset / reg_unit', and
each lvalue reference like 'r.reg_offset = x' is rewritten to
'r.offset = r.offset % reg_unit + x * reg_unit'.
Because the change affects a lot of places and is rather non-trivial
to verify due to the inconsistent value of reg_unit, I've tried to
avoid making any additional changes other than applying the rewrite
rule above in order to keep the patch as simple as possible, sometimes
at the cost of introducing obvious stupidity (e.g. algebraic
expressions that could be simplified given some knowledge of the
context) -- I'll clean those up later on in a second pass.
v2: Fix division by the wrong reg_unit in the UNIFORM case of
convert_to_hw_regs(). (Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 19:42:20 +0000 (12:42 -0700)]
i965/fs: Replace fs_reg::reg_offset with fs_reg::offset expressed in bytes.
The fs_reg::offset field in byte units introduced in this patch is a
more straightforward alternative to the current register offset
representation split between fs_reg::reg_offset and ::subreg_offset.
The split representation makes it too easy to forget about one of the
offsets while dealing with the other, which has led to multiple
back-end bugs in the past. To make the matter worse the unit
reg_offset was expressed in was rather inconsistent, for uniforms it
would be expressed in either 4B or 16B units depending on the
back-end, and for most other things it would be expressed in 32B
units.
This encodes reg_offset as a new offset field expressed consistently
in byte units. Each rvalue reference of reg_offset in existing code
like 'x = r.reg_offset' is rewritten to 'x = r.offset / reg_unit', and
each lvalue reference like 'r.reg_offset = x' is rewritten to
'r.offset = r.offset % reg_unit + x * reg_unit'.
Because the change affects a lot of places and is rather non-trivial
to verify due to the inconsistent value of reg_unit, I've tried to
avoid making any additional changes other than applying the rewrite
rule above in order to keep the patch as simple as possible, sometimes
at the cost of introducing obvious stupidity (e.g. algebraic
expressions that could be simplified given some knowledge of the
context) -- I'll clean those up later on in a second pass.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Eero Tamminen [Wed, 14 Sep 2016 14:28:28 +0000 (15:28 +0100)]
glsl: grammar fix
Signed-off-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 14 Sep 2016 19:43:16 +0000 (12:43 -0700)]
docs: Mention AEP in release notes
Kenneth Graunke [Wed, 14 Sep 2016 00:07:36 +0000 (17:07 -0700)]
i965: Enable ANDROID_extension_pack_es31a on Gen9+.
AEP requires ASTC, which is currently only enabled on Skylake and later.
(It may be possible to extend this to Cherryview/Braswell in the future,
but earlier hardware doesn't have ASTC support.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Tue, 13 Sep 2016 22:14:28 +0000 (15:14 -0700)]
nir: Report progress from nir_lower_phis_to_scalar.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 13 Sep 2016 22:14:28 +0000 (15:14 -0700)]
nir: Report progress from nir_lower_alu_to_scalar.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 13 Sep 2016 22:17:29 +0000 (15:17 -0700)]
nir: Call nir_metadata_preserve from nir_lower_alu_to_scalar().
This is mandatory.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 8 Sep 2016 19:49:49 +0000 (15:49 -0400)]
nir/lower_tex: fix typo with sample_dim
Numeric 2 is actually GLSL_SAMPLER_DIM_3D, which I don't think is what
was intended.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 8 Sep 2016 18:07:06 +0000 (14:07 -0400)]
nir: move tex_instr_remove_src
I want to re-use this in a different pass, so move to nir.h
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 8 Sep 2016 18:05:39 +0000 (14:05 -0400)]
nir/lower_tex: remove tex_instr_find_src()
Turns out it already exists.. so don't duplicate it.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kyle Brenneman [Mon, 12 Sep 2016 20:15:10 +0000 (16:15 -0400)]
egl: Add storage for EGL_KHR_debug's state to EGL objects
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:46:04 +0000 (17:46 -0400)]
egl: Factor out _eglGetSyncAttribCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:44:36 +0000 (17:44 -0400)]
egl: Factor out _eglWaitSyncCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:40:29 +0000 (17:40 -0400)]
egl: Lock the display in _eglCreateSync's callers
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:38:13 +0000 (17:38 -0400)]
egl: Factor out _eglCreateImageCommon (v2)
v2:
- Pass disp to RETURN_EGL_ERROR so we unlock the display
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:35:22 +0000 (17:35 -0400)]
egl: Factor out _eglWaitClientCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:25:56 +0000 (17:25 -0400)]
egl: Use _eglCreatePixmapSurfaceCommon consistently
This moves the native pixmap fixup to a helper function so we don't
repeat ourselves.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:04:38 +0000 (17:04 -0400)]
egl: Use _eglCreateWindowSurfaceCommon consistently
This moves the native window fixup to a helper function so we don't
repeat ourselves.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 20:42:56 +0000 (16:42 -0400)]
egl: Factor out _eglGetPlatformDisplayCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:12:52 +0000 (17:12 -0400)]
egl: Fix typo
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Adam Jackson [Fri, 9 Sep 2016 17:45:09 +0000 (13:45 -0400)]
egl: Tear down images and syncs at eglTerminate
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Kyle Brenneman [Wed, 6 Jul 2016 16:33:42 +0000 (10:33 -0600)]
egl: Update eglext.h (v2)
Updated eglext.h to revision 33111 from the Khronos repository.
v2:
- Don't (re)move extension includes from eglext.h (Emil Velikov)
- Bump to revision 33111 (Adam Jackson)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Brendan King [Tue, 13 Sep 2016 16:31:05 +0000 (17:31 +0100)]
configure.ac: fix the name of the Wayland Scanner pc file
The Wayland Scanner pkg-config file is called wayland-scanner.pc.
Fixes:
153539bd9d4445b50411 ("configure: rework wayland_scanner
handling (fix make distcheck)")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Brendan King <Brendan.King@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Tue, 13 Sep 2016 16:32:39 +0000 (17:32 +0100)]
gbm: remove left-over array
e7c8c85785b3a8f29e3f ("gbm: Removed unused function.") forgot to remove
the global array used only by that function.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Martina Kollarova [Thu, 8 Sep 2016 12:12:42 +0000 (15:12 +0300)]
gallium: fix return value check
A possible error (-1) was being lost because it was first converted to an
unsigned int and only then checked.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Martina Kollarova <martina.kollarova@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Marek Olšák [Tue, 13 Sep 2016 15:33:23 +0000 (17:33 +0200)]
radeonsi: reload PS inputs with direct indexing at each use (v2)
The LLVM compiler can CSE interp intrinsics thanks to
LLVMReadNoneAttribute.
26011 shaders in 14651 tests
Totals:
SGPRS: 1146340 -> 1132676 (-1.19 %)
VGPRS: 727371 -> 711730 (-2.15 %)
Spilled SGPRs: 2218 -> 2078 (-6.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size:
35841268 ->
36009732 (0.47 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 222559 -> 224779 (1.00 %)
Wait states: 0 -> 0 (0.00 %)
v2: don't call load_input for fragment shaders in emit_declaration
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 13 Sep 2016 12:30:50 +0000 (14:30 +0200)]
radeonsi: get rid of constant buffer preloading
26011 shaders in 14651 tests
Totals:
SGPRS: 1152636 -> 1146340 (-0.55 %)
VGPRS: 728198 -> 727371 (-0.11 %)
Spilled SGPRs: 3776 -> 2218 (-41.26 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size:
35835152 ->
35841268 (0.02 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 222372 -> 222559 (0.08 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Tue, 13 Sep 2016 12:25:44 +0000 (14:25 +0200)]
radeonsi: get rid of img/buf/sampler descriptor preloading (v2)
26011 shaders in 14651 tests
Totals:
SGPRS: 1251920 -> 1152636 (-7.93 %)
VGPRS: 728421 -> 728198 (-0.03 %)
Spilled SGPRs: 16644 -> 3776 (-77.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size:
36001064 ->
35835152 (-0.46 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 222221 -> 222372 (0.07 %)
Wait states: 0 -> 0 (0.00 %)
v2: merge codepaths where possible
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 13 Sep 2016 11:37:16 +0000 (13:37 +0200)]
radeonsi: rename get_sampler_desc -> load_sampler_desc
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Tue, 13 Sep 2016 11:28:09 +0000 (13:28 +0200)]
radeonsi: cosmetic changes in si_shader.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Tue, 13 Sep 2016 11:12:33 +0000 (13:12 +0200)]
radeonsi: load streamout buffer descriptors before use (v2)
v2: inline the code and remove the conditional that's a no-op now
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Thu, 8 Sep 2016 19:56:11 +0000 (12:56 -0700)]
vc4: Implement job shuffling
Track rendering to each FBO independently and flush rendering only when
necessary. This lets us avoid the overhead of storing and loading the
frame when an application momentarily switches to rendering to some other
texture in order to continue rendering the main scene.
Improves glmark -b desktop:effect=shadow:windows=4 by 27%
Improves glmark -b
desktop:blur-radius=5:effect=blur:passes=1:separable=true:windows=4
by 17%
While I haven't tested other apps, this should help X rendering a lot, and
I've heard GLBenchmark needed it too.
Eric Anholt [Thu, 8 Sep 2016 20:02:22 +0000 (13:02 -0700)]
vc4: Handle resolve skipping at job submit time.
This is done in vc4_flush currently, but I'm going to make the job always
track the surfaces it might be rendering to instead of putting in the
destinations at flush time.
Eric Anholt [Mon, 6 Apr 2015 20:17:58 +0000 (13:17 -0700)]
vc4: Move the render job state into a separate structure.
This is a preparation step for having multiple jobs being queued up at the
same time.
Eric Anholt [Wed, 7 Sep 2016 19:40:39 +0000 (12:40 -0700)]
vc4: Always unref the current job surfaces at job reset time.
Drops some tricky logic in vc4_flush() trying to update the pointers, and
fixes a broken lack of unref for MSAA surfaces at context destroy time.
Eric Anholt [Thu, 8 Sep 2016 21:03:29 +0000 (14:03 -0700)]
vc4: Move job-submit skip cases to vc4_job_submit().
For calling job_submit() directly, I need the skipping here.
Eric Anholt [Thu, 8 Sep 2016 21:01:15 +0000 (14:01 -0700)]
vc4: Move bin CL trailer to job_submit() time.
To implement job shuffling, I want to be able to call submit() on specific
jobs, turning vc4_flush() into the context's flush-all-jobs hook.
Eric Anholt [Fri, 9 Sep 2016 05:40:44 +0000 (22:40 -0700)]
vc4: Simplify the DISCARD_RANGE handling
It's really just an upgrade to attempting WHOLE_RESOURCE. Pulling the
logic out caught two bugs in it: We would try to do so on cubemaps (even
though we're only mapping 1 of the 6 slices), and we would break
persistent coherent mappings by trying to reallocate when we shouldn't.
Eric Anholt [Fri, 9 Sep 2016 23:26:02 +0000 (16:26 -0700)]
vc4: Fix incorrect clearing of Z/stencil when cleared separately.
The clear of Z or stencil will end up clearing the other as well, instead
of masking. There's no way around this that I know of, so if we are
clearing just one then we need to draw a quad.
Fixes a regression in the job-shuffling code, where the clear values move
to the job and don't just have the last clear's value laying around when
you do glClear(DEPTH) and then glClear(STENCIL) separately
(ext_framebuffer_multisample-clear 4 depth)).
This causes regressions in ext_framebuffer_multisample/multisample-blit
depth and ext_framebuffer_multisample/no-color depth, but these were
formerly false positives due to the reference image also being black. Now
the reference and test images are both being drawn, and it looks like
there's an incorrect resolve of depth during blitting to an MSAA FBO.
Ilia Mirkin [Sun, 28 Aug 2016 19:40:19 +0000 (15:40 -0400)]
glsl: add core plumbing for GL_ANDROID_extension_pack_es31a
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sun, 28 Aug 2016 23:53:02 +0000 (19:53 -0400)]
mesa: introduce glPrimitiveBoundingBoxARB entrypoint
This requires a bit of rejiggering, since normally ES entrypoints alias
core ones, not vice-versa.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sun, 28 Aug 2016 23:51:45 +0000 (19:51 -0400)]
mesa: add a GLES3.2 enums section, and expose new MS line width params
This also exposes them for ARB_ES3_2_compatibility.
While both specs refer to the new MS line width parameters being
separate from the existing AA line widths, reality begs to differ. It's
the same on all hardware currently supported by mesa. Should hardware
come along that wants these to be different, they're easy enough to
separate out.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Sirisha Gandikota [Tue, 13 Sep 2016 23:19:31 +0000 (16:19 -0700)]
aubinator: Remove bogus "end" parameter in gen_disasm_disassemble()
Earlier, the loop pretends to loop over instructions from "start" to "end",
but the callers always pass 8192 for end, which is some huge bogus
value. The real loop termination condition is send-with-EOT or 0. (Ken)
Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Sirisha Gandikota [Tue, 13 Sep 2016 23:19:30 +0000 (16:19 -0700)]
aubinator: Make gen_disasm_disassemble handle split sends
Skylake adds new SENDS and SENDSC opcodes, which should be
handled in the send-with-EOT check. Make an is_send() helper
that checks if the opcode is SEND/SENDC/SENDS/SENDSC (Ken)
v2: Make is_send() much more crispier, Mix declaration and
code to make the code compact (Ken)
Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Sirisha Gandikota [Tue, 13 Sep 2016 23:19:29 +0000 (16:19 -0700)]
aubinator: Simplify print_dword_val() method
Remove the float/dword union and use the iter->p[f->start / 32]
directly as printf formatter %08x expects uint32_t (Ken)
v2: Make the cleanup much more crispier (Ken)
Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 13 Sep 2016 21:02:32 +0000 (14:02 -0700)]
anv/image: Set correct base_array_layer and array_len for storage images
Since Vulkan doesn't allow single-slice 3D storage images, we need to just
set the base_array_layer and array_len to the full size of the 3-D LOD.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Tue, 13 Sep 2016 19:55:25 +0000 (12:55 -0700)]
Revert "intel/isl: Ignore base_array_layer and array_len for 3D storage..."
This reverts commit
3943888c94beca69e575b8d3d1ec7a6cbf474ee4. It turns out
that commit was pretty-much bogus since it breaks binding a 3-D texture as a
2-D storage image. The correct fix for the Vulkan CTS tests needs to be in
the Vulkan driver itself rather than ISL.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Wed, 31 Aug 2016 00:49:56 +0000 (17:49 -0700)]
anv: Use blorp for doing MSAA resolves
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Tue, 30 Aug 2016 23:56:25 +0000 (16:56 -0700)]
anv: Use blorp for ClearColorImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Tue, 30 Aug 2016 23:23:59 +0000 (16:23 -0700)]
anv: Delete meta_blit2d
Everything that we were once using the blit2d framework for is now done
with blorp.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Sat, 10 Sep 2016 02:21:18 +0000 (19:21 -0700)]
anv/blorp: Add a gcd_pow2_u64 helper and use it for buffer alignments
This is a lot cleaner and easier to read than the old piles of if
statements.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 30 Aug 2016 22:43:46 +0000 (15:43 -0700)]
anv: Use blorp for CopyBuffer and UpdateBuffer
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sun, 28 Aug 2016 04:05:13 +0000 (21:05 -0700)]
anv: Use blorp for CopyImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 27 Aug 2016 19:57:01 +0000 (12:57 -0700)]
anv: Use blorp for CopyBufferToImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 24 Aug 2016 03:19:57 +0000 (20:19 -0700)]
anv: Use blorp for CopyImageToBuffer
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 23 Aug 2016 05:33:06 +0000 (22:33 -0700)]
anv: Use blorp to implement VkBlitImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Wed, 31 Aug 2016 00:49:32 +0000 (17:49 -0700)]
anv: Make image_get_surface_for_aspect_mask const
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Tue, 23 Aug 2016 04:37:28 +0000 (21:37 -0700)]
anv: Add initial blorp support
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 24 Aug 2016 00:23:29 +0000 (17:23 -0700)]
intel/anv: Use #defines for all __gen_ helpers
This allows us to #undef them later if we don't want them to persist
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 23 Aug 2016 02:08:33 +0000 (19:08 -0700)]
anv: Generalize emit_urb_setup
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 20 Aug 2016 13:11:41 +0000 (06:11 -0700)]
anv/pipeline: Roll compute_urb_partition into emit_urb_setup
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 24 Aug 2016 00:20:34 +0000 (17:20 -0700)]
intel/blorp: Use #defines for all __gen_ helpers
This allows us to #undef them later if we don't want them to persist
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 8 Sep 2016 17:26:15 +0000 (10:26 -0700)]
intel/isl: Divide QPitch by 2 for 3-D stencil textures on SKL+
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Thu, 8 Sep 2016 17:23:47 +0000 (10:23 -0700)]
isl/state: Don't set QPitch for GEN4_3D surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Wed, 24 Aug 2016 03:51:26 +0000 (20:51 -0700)]
intel/blorp: Rework alloc_binding_table
The original blorp_alloc_binding_table helper was supposed to return the
binding table offset and map along with the surface state maps. This isn't
quite what we want, however. What we really want is the binding table
offsets, surface state offsets, and surface state maps. In the GL driver,
the binding table map *is* an array of surface state offsets. However, in
Vulkan, this isn't quite true as the entries in the binding table are
surface state offsets combined with another binding table block offset.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Marek Olšák [Thu, 8 Sep 2016 17:12:00 +0000 (19:12 +0200)]
tgsi/scan: don't set interp flags for inputs only used by INTERP instructions
radeonsi depends on the interp flags a little bit too much.
This fixes 9 randomly failing tests:
GL45-CTS.shader_multisample_interpolation.render.interpolate_at_centroid.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 11 Sep 2016 23:38:53 +0000 (01:38 +0200)]
radeonsi: fix FP64 UBO loads with indirect uniform block indexing
No known tests.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 11 Sep 2016 19:49:24 +0000 (21:49 +0200)]
winsys/amdgpu: don't assume GTT if the VRAM flag isn't set
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 11 Sep 2016 15:57:31 +0000 (17:57 +0200)]
radeonsi: clean up CP DMA emit code
Unify the clear and copy paths, clean up the definitions.
It looks more like a rework. It's a preparation for GDS support,
which might or might not come.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 12 Sep 2016 18:23:55 +0000 (20:23 +0200)]
radeonsi: print the IB and buffer list in VM fault reports
This is a fallout from reworking the debug flags.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 12 Sep 2016 10:49:34 +0000 (12:49 +0200)]
radeonsi: add sampler view BOs to the BO list last
If si_sampler_view_add_buffer ends up flushing, then the code
in begin_new_cs would previously have added the buffer(s) for
whatever was previously bound to that slot. Now it would add only
the new buffer.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 9 Sep 2016 23:21:11 +0000 (01:21 +0200)]
radeonsi: export SampleMask from pixel shaders at full rate
Heaven and Valley write gl_SampleMask and not Z.
Use 16_ABGR instead of 32_ABGR if Z isn't written.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 12 Sep 2016 10:47:13 +0000 (12:47 +0200)]
gallium/radeon: set new r600_resource fields correctly in other places too
This was missed in:
commit
0d2e43fcb1198a6e67c85feadb1ca8c360ddc284
Author: Marek Olšák <marek.olsak@amd.com>
Date: Thu Aug 18 16:30:00 2016 +0200
gallium/radeon: derive buffer placement and flags only at initialization
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 10 Sep 2016 08:16:54 +0000 (10:16 +0200)]
ddebug: dump shader buffers and images
this was unimplemented
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 10 Sep 2016 07:50:42 +0000 (09:50 +0200)]
ddebug: fix a crash in resource_get_handle
broken recently
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jan Vesely [Tue, 13 Sep 2016 00:47:37 +0000 (20:47 -0400)]
radeon: Don't check DCC on pipe buffers
Fixes segfaults in EG compute since:
commit
21de3be8e62b2b093569a99550e6356ed2f106b4
radeonsi: fix texture format reinterpretation with DCC
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Andy Furniss [Tue, 13 Sep 2016 17:52:31 +0000 (13:52 -0400)]
vl/util: Fix YV12/I420 convert to NV12 U/V reversal
Fix VAAPI YV12/I420 convert to NV12 U/V reversal.
Input order is YVU when this is called.
Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>