Jason Ekstrand [Fri, 15 Apr 2022 21:16:03 +0000 (16:16 -0500)]
nir: Gather samplers_used separately from textures
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15988>
Jason Ekstrand [Fri, 15 Apr 2022 20:32:29 +0000 (15:32 -0500)]
shader_info: Make images_used a bitset
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15988>
Jason Ekstrand [Fri, 15 Apr 2022 20:52:54 +0000 (15:52 -0500)]
nir: Stop assuming shader_info::textures_used is 32-bit
This isn't a hot path. We don't need to be manually using the
INSIDE_WORD version which will assert if we ever get a bigger texture
index.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15988>
Jason Ekstrand [Fri, 15 Apr 2022 20:40:13 +0000 (15:40 -0500)]
nir: Set image_buffers and msaa_images in lower_samplers_as_deref
This is where we set images_used so it's less likely that things will
accidentally get out-of-sync.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15988>
Icecream95 [Fri, 10 Dec 2021 10:51:06 +0000 (23:51 +1300)]
pan/mdg: Fix multiple spilt writes in the same bundle
If two instructions in a single bundle both write to a spilt
destination, then we need to reuse the fill and spill instructions,
otherwise the value will be overwritten.
This and the rest of this set of Midgard bug fixes were found from a
vertex shader in Firefox WebRender that is used when a video is
clipped, for example by setting the border-radius CSS property.
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
Icecream95 [Fri, 10 Dec 2021 10:50:00 +0000 (23:50 +1300)]
pan/mdg: Return the instruction from mir_insert_instruction_*_scheduled
We can't return a pointer to the bundle itself because it might move
about in memory.
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
Icecream95 [Fri, 10 Dec 2021 10:46:37 +0000 (23:46 +1300)]
pan/mdg: Fix disassembly of store instructions
The mask does apply for store instructions, so pass it onto
print_vec_swizzle after converting it to the right format.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
Icecream95 [Fri, 10 Dec 2021 10:40:01 +0000 (23:40 +1300)]
pan/mdg: Fix mask usage when filling before a spill
Check the bytemask against 0xFFFF rather than 0xF so that the fill is
skipped for a .xyzw write rather than a .x write.
Set the mask on the store to 0xF when doing a read so that all
components are written back.
Fixes:
31d26ebf1b9 ("pan/mdg: Fill from TLS before spilling non-SSA nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
Icecream95 [Fri, 10 Dec 2021 10:44:25 +0000 (23:44 +1300)]
pan/mdg: Use MAX2 to set min_alignment
If a value is written in a vector CSEL but then written again by other
instructions, it still needs full alignment, so set min_alignment
using MAX2 to avoid ever reducing it.
Fixes:
1798f6bfc33 ("pan/midgard: Fix masks/alignment for 64-bit loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
Icecream95 [Mon, 9 May 2022 22:40:49 +0000 (10:40 +1200)]
pan/mdg: Keep min_bound at 16 when alignment requires it
Otherwise LCRA will try to divide by zero when calculating m_max.
Fixes:
553c2cf16b7 ("pan/mdg: Set RA bounds for fp16")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16382>
Pierre-Eric Pelloux-Prayer [Tue, 3 May 2022 13:34:38 +0000 (15:34 +0200)]
u_threaded: clear non-async debug callback correctly
The following sequence:
glEnable(GL_DEBUG_OUTPUT_KHR);
glEnable(GL_DEBUG_OUTPUT_SYNCHRONOUS_KHR);
glDebugMessageCallbackKHR(my_callback, NULL);
Will cause the 2nd call to be ignored - but since the callback
function used by _mesa_update_debug_callback is always the
same (_debug_message), this means we'll keep using it, causing
"my_callback" to be called from driver-internal threads.
So instead of skipping the 2nd call, make sure we pass the
information to the driver.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5206
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16300>
Martin Roukala (né Peres) [Mon, 2 May 2022 13:33:35 +0000 (16:33 +0300)]
ci: add ACO_DEBUG to the list of variables to pass down for testing
This parameter is used by radv-ci to perform extra validation while
running VKCTS.
This change catches more issues, which are will be addressed in !16248:
- dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i8vec2,Crash
- dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_u8vec2,Crash
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Suggested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16277>
Pierre-Eric Pelloux-Prayer [Thu, 5 May 2022 15:02:37 +0000 (17:02 +0200)]
radeonsi/tests: reformat with black
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16347>
Pierre-Eric Pelloux-Prayer [Thu, 5 May 2022 13:48:29 +0000 (15:48 +0200)]
radeonsi/tests: add a heuristic to pick the baseline
When the baseline for the exact GPU tested isn't available,
try to make a reasonnable guess: look for another baseline
from a GPU in the same class.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16347>
Pierre-Eric Pelloux-Prayer [Thu, 21 Apr 2022 14:50:39 +0000 (16:50 +0200)]
radeonsi/tests: allow empty line and comments in csv files
This will help describe why tests are failing.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16347>
Jordan Justen [Thu, 21 Apr 2022 09:48:58 +0000 (02:48 -0700)]
nir/divergence: handle more *_intel intrinsics
v2: fix topo/btd (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16421>
Timur Kristóf [Thu, 5 May 2022 18:50:11 +0000 (20:50 +0200)]
radv: Only emit what is appropriate to the queue family for preambles.
This makes the function easier to read and follow.
Also prepares for some future changes when we'll want to
submit to multiple queues at once.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 18:40:13 +0000 (20:40 +0200)]
radv: Don't use pointers to pointers when updating the preambles.
Instead, just use the pointers from the queue structure.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 18:16:30 +0000 (20:16 +0200)]
radv: Rename fill_geom_tess_rings to radv_fill_shader_rings.
This function already handles more than just the geometry and tess
rings, and it will include more things in the future, such as
the task shader rings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 18:09:27 +0000 (20:09 +0200)]
radv: Don't create continue preamble when it's not needed.
Previously we would always create it, but would return NULL when
it wasn't needed. Now, don't create it when not needed.
Additionally, don't create the continue preamble when we can use
IB BOs, because then we never use a continue preamble.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 18:04:46 +0000 (20:04 +0200)]
radv: Refactor cache flush code for the initial preambles.
The "initial" and "initial full flush" preambles both need a
cache flush with a slight difference. Improve the readability of
this code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 17:17:42 +0000 (19:17 +0200)]
radv: Initialize BO pointers when creating preambles.
This aims to improve the readability of this function.
Initialize the BO pointers to the queue's current pointers
at the beginning instead of in the else branches later.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 16:58:34 +0000 (18:58 +0200)]
radv: Simplify some boolean code in radv_get_preamble_cs.
Hopefully this will make it easier to read and understand.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 16:58:01 +0000 (18:58 +0200)]
radv: Move up early exit for transfer queues in radv_get_preamble_cs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 16:37:20 +0000 (18:37 +0200)]
radv: Move normal (non-empty) queue submit to a separate function.
Also move the preamble update into this function, as that is only needed
by this code path and not needed for empty submits.
With this change, the goal is to make radv_queue_submit easier to
read and understand. This prepares it for future work when we'll
add the capability to submit to multiple queues at the same time.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 14:02:21 +0000 (16:02 +0200)]
radv: Move empty queue submit code path to a separate function.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 13:11:23 +0000 (15:11 +0200)]
radv: Move queue submit sparse bindings to a separate function.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Timur Kristóf [Thu, 5 May 2022 17:50:10 +0000 (19:50 +0200)]
radv: Minor formatting fix in radv_device.c file.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
Iago Toral Quiroga [Tue, 10 May 2022 06:04:24 +0000 (08:04 +0200)]
v3dv: drop unsused struct
This is no longer needed since we ported to using the common sync
framework.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16417>
Marek Olšák [Thu, 5 May 2022 19:56:46 +0000 (15:56 -0400)]
ac/gpu_info: fix incorrect IP versions reported by the kernel
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Marek Olšák [Thu, 5 May 2022 19:14:55 +0000 (15:14 -0400)]
ac/gpu_info: print all IP versions reported by the kernel
It's incorrect for GFX. This is what I get on Radeon 6800:
IP GFX 10.0 queues:1
IP COMP 10.0 queues:4
IP SDMA 5.2 queues:2
IP VCN_DEC 3.0 queues:1
IP VCN_ENC 3.0 queues:1
IP VCN_JPG 3.0 queues:1
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Marek Olšák [Thu, 5 May 2022 18:41:06 +0000 (14:41 -0400)]
ac/gpu_info: remove dead GDS query code
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Marek Olšák [Thu, 5 May 2022 18:26:05 +0000 (14:26 -0400)]
ac/gpu_info: simplify HW IP querying
Use a loop, don't check the DRM versions, and handle failures as
unsupported.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Marek Olšák [Thu, 5 May 2022 17:57:49 +0000 (13:57 -0400)]
amd: replace num_rings[type] with ip[type].num_queues
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Marek Olšák [Thu, 5 May 2022 17:49:29 +0000 (13:49 -0400)]
amd: rename RING_* enums to AMD_IP_*
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Marek Olšák [Thu, 5 May 2022 17:41:37 +0000 (13:41 -0400)]
amd: rename ring_type --> amd_ip_type and match the kernel enum values
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
Mike Blumenkrantz [Tue, 26 Apr 2022 15:36:23 +0000 (11:36 -0400)]
zink: use descriptor surfaces for notemplates ref updating
basically the same codepath as samplerviews now, and fixes
some issues with invalid mem access
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16167>
Mike Blumenkrantz [Tue, 26 Apr 2022 15:09:06 +0000 (11:09 -0400)]
zink: add more image usage for null surfaces
without null descriptor features, these can be used for all sorts of things
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16167>
Mike Blumenkrantz [Tue, 26 Apr 2022 15:07:23 +0000 (11:07 -0400)]
zink: fix null buffer/surface formats
4-component formats are needed here in order to return the correct
alpha value in invalid load scenarios
cc: mesa-stable
fixes:
spec@arb_shader_image_load_store@invalid
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16167>
Mike Blumenkrantz [Wed, 4 May 2022 13:01:56 +0000 (09:01 -0400)]
lavapipe: enqueue pipeline destruction
this avoids races in llvmpipe related to modification of per-context shader
variant lists, which causes massive amounts of flakiness in ci
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16331>
Mike Blumenkrantz [Tue, 12 Apr 2022 21:42:15 +0000 (17:42 -0400)]
zink: delete nir_lower_dynamic_bo_access
no longer used
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15906>
Mike Blumenkrantz [Tue, 12 Apr 2022 21:26:53 +0000 (17:26 -0400)]
zink: implement indirect buffer indexing
this compacts all buffers in the shader into an array that can be
used in a single descriptor, thus handling the case of indirect indexing
while also turning constant indexing into indirect (with const offsets)
since there's no sane way to distinguish
a "proper" implementation of this would be to skip gl_nir_lower_buffers
and nir_lower_explicit_io altogether and retain the derefs, but that would
require a ton of legwork of other nir passes which only operate on the
explicit io intrinsics
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15906>
Mike Blumenkrantz [Wed, 13 Apr 2022 14:21:51 +0000 (10:21 -0400)]
zink: flatten push descriptor template into normal template array
this simplifies some code
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15906>
Mike Blumenkrantz [Wed, 13 Apr 2022 14:20:00 +0000 (10:20 -0400)]
zink: decouple descriptor templates from layouts
the same layout will in the future have multiple templates
depending on which resources are being updated
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15906>
Mike Blumenkrantz [Thu, 21 Apr 2022 16:24:01 +0000 (12:24 -0400)]
zink: semi-handle 1D sparse texture rewrites for drivers that don't support them
nvidia can't do this, but also nothing uses it, so I've gone ahead and
done the bare minimum here to make cts pass
I think the work to do the shader rewrites should be easy, but without a test
case, I see no point in spending the time for it
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16100>
Mike Blumenkrantz [Fri, 22 Apr 2022 01:34:20 +0000 (21:34 -0400)]
zink: bump number of image binds that can be batched to 50
this is big enough to batch all the cts binds into a single submit
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16100>
Mike Blumenkrantz [Thu, 21 Apr 2022 15:47:01 +0000 (11:47 -0400)]
zink: fix multisample conditional in sparse image query
you stare at the code for so long without truly seeing it
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16100>
Mike Blumenkrantz [Thu, 21 Apr 2022 15:45:46 +0000 (11:45 -0400)]
zink: set all usage flags when querying sparse features
they're allocated through TexStorage, so they can do everything
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16100>
Mike Blumenkrantz [Thu, 21 Apr 2022 15:45:15 +0000 (11:45 -0400)]
zink: pass sparse bind bo offset through for texture binds
should fix partial binding with textures
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16100>
Mike Blumenkrantz [Thu, 21 Apr 2022 14:36:56 +0000 (10:36 -0400)]
zink: pass sparse backing page offset to binding function
this is the offset of the memory block being bound
cc: mesa-stable
fixes:
KHR-GL46.sparse_buffer_tests.BufferStorageTest
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16100>
Mike Blumenkrantz [Wed, 27 Apr 2022 14:11:37 +0000 (10:11 -0400)]
zink: scale depth bias by factor of 2
this is enough to fix CTS
affects/fixes:
dEQP-GLES3.functional.polygon_offset.default_render_with_units
dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units
dEQP-GLES3.functional.polygon_offset.fixed24_render_with_units
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16195>
Emma Anholt [Thu, 5 May 2022 23:28:34 +0000 (16:28 -0700)]
glsl: Make all drivers take the GLSLOptimizeConservatively path.
Now that all consumers of GLSL use NIR, make the remaining drivers take
the path that relies on NIR to really do optimization.
nouveau steam shader-db runtime -6.69631% +/- 1.29235% (n=12).
No change on shader-db there.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16364>
Marek Olšák [Fri, 6 May 2022 02:35:59 +0000 (22:35 -0400)]
radeonsi: remove tautologies when setting CU_EN
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Ruijing Dong [Wed, 16 Mar 2022 14:43:29 +0000 (10:43 -0400)]
radeonsi/vcn: update av1 decoding to support vcn4
Apply changes of vcn4 on av1 decoding.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Ruijing Dong [Thu, 10 Mar 2022 17:13:09 +0000 (12:13 -0500)]
radeonsi/vcn: Add support of array_mode for gfx11
Update array_mode for gfx11 in vcn decoder.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 17:07:30 +0000 (12:07 -0500)]
radeonsi/vcn: add jpeg decode support for gfx11
Add jpeg decode support for gfx11.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 4 May 2022 00:24:48 +0000 (20:24 -0400)]
amd: add chip identification for gfx1100-1103
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:50:40 +0000 (19:50 -0500)]
radeonsi/vcn: enable vcn 4.0 encode for gfx11 asic
Enable VCN 4.0 encode for supported Asics.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:49:08 +0000 (19:49 -0500)]
radeonsi/vcn: add session init ib for vcn 4.0
Implement session init ib based on new interface for VCN 4.0.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 01:14:30 +0000 (20:14 -0500)]
radeonsi/vcn: add encode context ib for vcn 4.0
Implement encode context ib based on new reconstructed picture and
interface for VCN 4.0, and modify dpb setup accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:32:53 +0000 (19:32 -0500)]
radeonsi/vcn: add vcn 4.0 encode fw interface version
Add major and minor encode FW interface version for VCN 4.0.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:29:16 +0000 (19:29 -0500)]
radeonsi/vcn: add vcn 4.0 encode support
Add new file "radeon_vcn_enc_4_0.c" for VCN 4.0 encode.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 16:46:48 +0000 (11:46 -0500)]
radeonsi/vcn: add decode software ring support for gfx11
Add decode software ring support for gfx11.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 16:42:29 +0000 (11:42 -0500)]
radeonsi/gfx11: update codec support for gfx11
Update codec support for gfx11.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 16:39:45 +0000 (11:39 -0500)]
amd: update headers to support decode software ring
Update headers to support decode software ring.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 23:36:47 +0000 (19:36 -0400)]
radeonsi/gfx11: add a workaround for CB perf counters
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 19:16:22 +0000 (15:16 -0400)]
radeonsi: inline si_cp_dma_prefetch in si_draw_vbo for lower overhead
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 30 Mar 2022 05:57:38 +0000 (01:57 -0400)]
radeonsi/gfx11: limit CP DMA to max 32KB sizes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 19:05:50 +0000 (15:05 -0400)]
radeonsi/gfx11: mark streamout as unimplemented for now
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 19:04:44 +0000 (15:04 -0400)]
radeonsi/gfx11: resolve MSAA using u_blitter
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 28 Apr 2022 12:38:49 +0000 (08:38 -0400)]
radeonsi/gfx11: don't count the non-existent scratch_byte_offset SGPR
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 22 Apr 2022 16:12:42 +0000 (12:12 -0400)]
radeonsi/gfx11: change LDS allocation granularity for PS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 2 Apr 2022 05:51:44 +0000 (01:51 -0400)]
radeonsi/gfx11: update the initialization of SGPR0/1 registers for HS and GS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 2 Apr 2022 01:47:03 +0000 (21:47 -0400)]
radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Wed, 22 Dec 2021 20:33:48 +0000 (02:03 +0530)]
ac,radeonsi/gfx11: swizzle MRT0/1 for dual source blending
If dual source blending is enabled, use export targets 21 and 22.
Also we have to swap odd/even lanes between export target 21 and 22.
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh Mohan Marimuthu [Thu, 10 Feb 2022 19:54:56 +0000 (01:24 +0530)]
radeonsi/gfx11: export alpha through mrtz for alpha-to-coverage if mrtz is there
If both mrtz and alpha-to-coverage are enabled, the alpha channel must
be exported through mrtz.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Indrajit Kumar Das [Fri, 28 Jan 2022 05:55:01 +0000 (11:25 +0530)]
radeonsi/gfx11: VRS changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 22 Jan 2022 17:42:51 +0000 (12:42 -0500)]
radeonsi/gfx11: TF_RING_SIZE changed to a per-SE size
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 22 Jan 2022 14:57:20 +0000 (09:57 -0500)]
radeonsi/gfx11: don't use FLUSH_AND_INV_DB_META
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 22 Jan 2022 14:56:39 +0000 (09:56 -0500)]
radeonsi/gfx11: emit SQ_NON_EVENT for tessellation at the end of IBs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 21 Jan 2022 09:05:25 +0000 (04:05 -0500)]
radeonsi/gfx11: don't set non-existent CP_COHER_START_DELAY
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Wed, 22 Dec 2021 14:43:25 +0000 (20:13 +0530)]
radeonsi/gfx11: program db render control register
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 21 Sep 2021 15:36:01 +0000 (11:36 -0400)]
radeonsi/gfx11: scattered register deltas
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 11 May 2021 04:50:43 +0000 (00:50 -0400)]
radeonsi/gfx11: implement attributes through memory
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 17 Dec 2021 17:30:58 +0000 (12:30 -0500)]
radeonsi/gfx11: don't set COMPR for exports, use 0x3 channel mask instead
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh Mohanmarimuthu [Tue, 5 Oct 2021 19:14:42 +0000 (00:44 +0530)]
radeonsi/gfx11: use PIXEL_PIPE_STATE_DUMP event instead of ZPASS_DONE
Use PIXEL_PIPE_STATE_CONTROL/DUMP event instead of ZPASS_DONE for gfx11.
Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 23 Sep 2021 11:01:46 +0000 (07:01 -0400)]
radeonsi/gfx11: don't set non-existent SPI_SHADER_USER_DATA_VS_x
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 22 Sep 2021 09:07:26 +0000 (05:07 -0400)]
ac,radeonsi/gfx11: set SWIZZLE_ENABLE correctly
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 22 Sep 2021 08:37:34 +0000 (04:37 -0400)]
ac,radeonsi/gfx11: remove FMASK loads
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 01:03:54 +0000 (21:03 -0400)]
radeonsi/gfx11: add CB deltas
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 18 Dec 2021 14:07:48 +0000 (09:07 -0500)]
radeonsi/gfx11: buffer descriptor changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 12:13:34 +0000 (14:13 +0200)]
radeonsi/gfx11: image descriptor changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 11:42:24 +0000 (13:42 +0200)]
radeonsi/gfx11: register changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 11:40:28 +0000 (13:40 +0200)]
radeonsi/gfx11: add assert in legacy vs path
Only ngg should be used.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 24 Aug 2021 07:23:06 +0000 (12:53 +0530)]
radeonsi/gfx11: program inst_pref_size for compute
For gfx11, program INST_PREF_SIZE value in SPI registers.
v2: move INST_PREF_SIZE reg programming (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 16 Sep 2021 01:30:04 +0000 (21:30 -0400)]
radeonsi/gfx11: program inst_pref_size for graphics
For gfx11, program INST_PREF_SIZE value in SPI registers.
v4: fix mask value, code indendation (Marek Olšák)
v3: improve code for readability (Indrajit Das, Marek Olšák)
v2: ngg is always enabled in gfx11 (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Sun, 22 Aug 2021 12:17:08 +0000 (17:47 +0530)]
radeonsi/gfx11: instruction cache line size is 128 bytes
In gfx11, instruction cache line size is 128 bytes. This patch makes
the neccessary code changes.
v2: instruction store line size is 64 bytes (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 20 Jul 2021 19:12:59 +0000 (00:42 +0530)]
radeonsi/gfx11: interp changes for 16bit
make interp 16bit changes for gfx11
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 20 Jul 2021 18:46:57 +0000 (00:16 +0530)]
radeonsi/gfx11: interp changes for 32bit
make interp 32bit changes for gfx11
v2: fix coding indentation issue (Pierre-Eric)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 15 Jun 2021 09:35:06 +0000 (15:05 +0530)]
radeonsi/gfx11: make flat_scratch changes for compute
make flat_scratch gen11 changes for compute
v5: optimize the code for size (Pierre-Eric)
v4: remove type cast from 64bit to 32bit (Marek Olšák)
use radeon_set_sh_reg_seq (Marek Olšák)
combine RSRC and scratch reg write packets (Marek Olšák)
v3: fix coding guidelines (Marek Olšák)
v2: do not skip si_resource_reference() call (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
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