platform/kernel/linux-starfive.git
4 years agodrm/amd/pm: update driver if file for sienna cichlid
Likun Gao [Tue, 22 Sep 2020 03:10:37 +0000 (11:10 +0800)]
drm/amd/pm: update driver if file for sienna cichlid

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: drop redundant watermarks bitmap setting
Evan Quan [Mon, 21 Sep 2020 02:14:06 +0000 (10:14 +0800)]
drm/amd/pm: drop redundant watermarks bitmap setting

As this is already set inside the implementation of
smu_set_watermarks_table().

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: decouple the watermark table setting from socclk/uclk dpms
Evan Quan [Fri, 18 Sep 2020 08:39:13 +0000 (16:39 +0800)]
drm/amd/pm: decouple the watermark table setting from socclk/uclk dpms

As they have no real dependence. And for Navi1x, the socclk/uclk dpms
are enabled after DAL initialization.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: correct the pmfw version check for Navi14
Evan Quan [Fri, 18 Sep 2020 03:34:17 +0000 (11:34 +0800)]
drm/amd/pm: correct the pmfw version check for Navi14

Otherwise, that will be always true for Navi14.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: update athub interrupt harvesting handle
Stanley.Yang [Tue, 15 Sep 2020 08:15:05 +0000 (16:15 +0800)]
drm/amdgpu: update athub interrupt harvesting handle

GCEA/MMHUB EA error should not result to DF freeze, this is
fixed in next generation, but for some reasons the GCEA/MMHUB
EA error will result to DF freeze in previous generation,
diver should avoid to indicate GCEA/MMHUB EA error as hw fatal
error in kernel message by read GCEA/MMHUB err status registers.

Changed from V1:
    make query_ras_error_status function more general
    make read mmhub er status register more friendly

Changed from V2:
    move ras error status query function into do_recovery workqueue

Changed from V3:
    remove useless code from V2, print GCEA error status
    instance number

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: Removed fixed clock in auto mode DPM
Sudheesh Mavila [Tue, 15 Sep 2020 07:18:20 +0000 (12:48 +0530)]
drm/amd/pm: Removed fixed clock in auto mode DPM

SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM.

Suggested-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: optimize the mclk dpm policy settings
Evan Quan [Thu, 18 Jun 2020 07:26:08 +0000 (15:26 +0800)]
drm/amd/powerplay: optimize the mclk dpm policy settings

Different mclk dpm policy will be applied based on the VRAM
width.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/gmc9: simplify the return expression of gmc_v9_0_suspend
Liu Shixin [Mon, 21 Sep 2020 08:24:29 +0000 (16:24 +0800)]
drm/amdgpu/gmc9: simplify the return expression of gmc_v9_0_suspend

Simplify the return expression.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: simplify the return expression of smu_hw_fini
Liu Shixin [Mon, 21 Sep 2020 08:24:30 +0000 (16:24 +0800)]
drm/amd/pm: simplify the return expression of smu_hw_fini

Simplify the return expression.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: simplify the return expression
Qinglang Miao [Mon, 21 Sep 2020 13:10:13 +0000 (21:10 +0800)]
drm/amdgpu: simplify the return expression

Simplify the return expression.

Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/mes: simplify the return expression of mes_v10_1_ring_init
Qinglang Miao [Mon, 21 Sep 2020 13:10:11 +0000 (21:10 +0800)]
drm/amdgpu/mes: simplify the return expression of mes_v10_1_ring_init

Simplify the return expression.

Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: [FIX] update clock under two conditions
Lewis Huang [Wed, 16 Sep 2020 21:13:11 +0000 (17:13 -0400)]
drm/amd/display: [FIX] update clock under two conditions

[Why]
Update clock only when non-seamless boot stream exists
creates regression on multiple scenerios.

[How]
Update clock in two conditions
1. Non-seamless boot stream exist.
2. Stream_count = 0

Fixes: 598c13b21e25 ("drm/amd/display: update clock when non-seamless boot stream exist")
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Qingqing Zhuo <Qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
4 years agodrm/amd/display: 3.2.104
Aric Cyr [Mon, 14 Sep 2020 15:40:19 +0000 (11:40 -0400)]
drm/amd/display: 3.2.104

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: [FW Promotion] Release 0.0.34
Anthony Koo [Sun, 13 Sep 2020 20:41:57 +0000 (16:41 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.34

[Header Changes]
       - Add new SCRATCH0 status bits for detecting restore state

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: TMDS Fallback transition
Chris Park [Sat, 12 Sep 2020 17:06:59 +0000 (13:06 -0400)]
drm/amd/display: TMDS Fallback transition

[Why]
HDMI requires fallback to TMDS by redetection
in order to switch PHY settings.
This avoids black out when link training fail
during mode setting, link quality update,
disable driver sequence.

[How]
Allow driver to redetect HDMI displays
based on retraining or fallback mechanism.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Check for flip pending before locking pipes.
Taimur Hassan [Thu, 10 Sep 2020 14:13:42 +0000 (10:13 -0400)]
drm/amd/display: Check for flip pending before locking pipes.

[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.

[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.

Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Implement PSR wait for enable/disable
Wyatt Wood [Fri, 11 Sep 2020 01:50:52 +0000 (21:50 -0400)]
drm/amd/display: Implement PSR wait for enable/disable

[Why]
For DMUB implementation of PSR, the 'wait' parameter,
used to determine if driver should wait for PSR enable/disable,
is not implemented correctly.

[How]
Implement wait for PSR enable/disable.

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: allow DP RX to use more cr aux rd interval delay
Wenjing Liu [Thu, 10 Sep 2020 18:11:37 +0000 (14:11 -0400)]
drm/amd/display: allow DP RX to use more cr aux rd interval delay

[why]
Regression is caused by previous change with attempt to correct the
extended cr aux rd interval delay due to mis interpretation of the DP specs.
The change turns out not working well with certain RXs.
So we decided to keep the cr aux rd interval logic as before.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Enable DP YCbCr420 mode support for DCN10
Gary Li [Thu, 10 Sep 2020 18:32:13 +0000 (14:32 -0400)]
drm/amd/display: Enable DP YCbCr420 mode support for DCN10

[WHY]
In DCN10 when a panel with YCbCr420 capability is connected via
USB-C to HDMI active dongle, no YCbCr420 option is listed in
Radeon settings.

[HOW]
Enable DP YCbCr420 mode support for DCN10

Signed-off-by: Gary Li <gary.li@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Increase timeout for DP Disable
Wesley Chalmers [Wed, 9 Sep 2020 21:41:53 +0000 (17:41 -0400)]
drm/amd/display: Increase timeout for DP Disable

[WHY]
When disabling DP video, the current REG_WAIT timeout
of 50ms is too low for certain cases with very high
VSYNC intervals.

[HOW]
Increase the timeout to 102ms, so that
refresh rates as low as 10Hz can be handled properly.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
4 years agodrm/amd/display: Fix ODM policy implementation
Wesley Chalmers [Tue, 8 Sep 2020 20:22:25 +0000 (16:22 -0400)]
drm/amd/display: Fix ODM policy implementation

[WHY]
Only the leftmost ODM pipe should be offset when scaling. A previous
code change was intended to implement this policy, but a section of code
was overlooked.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
4 years agodrm/amd/display: eDP intermittent black screen during PnP
Peikang Zhang [Tue, 8 Sep 2020 15:27:25 +0000 (11:27 -0400)]
drm/amd/display: eDP intermittent black screen during PnP

[Why]
We dont's turn off backlight before power off eDP (VDD),
which is a violation of eDP specs.

[How]
Power off eDP backlight before power off eDP

Signed-off-by: Peikang Zhang <peikang.zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Bug in dce_is_panel_backlight_on()
Peikang Zhang [Thu, 3 Sep 2020 17:45:07 +0000 (13:45 -0400)]
drm/amd/display: Bug in dce_is_panel_backlight_on()

[Why]
dce_is_panel_backlight_on() will return wrong value if
LVTMA_BLON_OVRD is 0

[How]
When LVTMA_BLON_OVRD is 0, read
LVTMA_PWRSEQ_TARGET_STATE instead

Signed-off-by: Peikang Zhang <peikang.zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: 3.2.103
Aric Cyr [Tue, 8 Sep 2020 14:35:37 +0000 (10:35 -0400)]
drm/amd/display: 3.2.103

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: [FW Promotion] Release 0.0.33
Anthony Koo [Mon, 7 Sep 2020 17:01:02 +0000 (13:01 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.33

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix incorrect backlight register offset for DCN
David Galiffi [Thu, 3 Sep 2020 23:20:36 +0000 (19:20 -0400)]
drm/amd/display: Fix incorrect backlight register offset for DCN

[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
4 years agodrm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT
Kent Russell [Fri, 18 Sep 2020 18:47:47 +0000 (14:47 -0400)]
drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT

Since we're dynamically allocating the CPU VCRAT, use kvmalloc in case
the allocation size is huge.

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: Fix kfd init stack dump
Philip Cox [Mon, 21 Sep 2020 10:45:45 +0000 (06:45 -0400)]
drm/amdkfd: Fix kfd init stack dump

amdkfd is dumping a stack during initialization.
kfd_procfs_add_sysfs_stats is being called twice.  This removes one of
them.

Fixes: 4327bed2ff8e3d ("drm/amdkfd: Add process eviction counters to sysfs")
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Fix dead lock issue for vblank
Emily.Deng [Mon, 14 Sep 2020 09:57:01 +0000 (17:57 +0800)]
drm/amdgpu: Fix dead lock issue for vblank

Always start vblank timer, but only calls vblank function
when vblank is enabled.

This is used to fix the dead lock issue.
When drm_crtc_vblank_off want to disable vblank,
it first get event_lock, and then call hrtimer_cancel,
but hrtimer_cancel want to wait timer handler function finished.
Timer handler also want to aquire event_lock in drm_handle_vblank.

Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: fix crash/reboot while accessing sysfs files
Shirish S [Thu, 17 Sep 2020 08:37:32 +0000 (14:07 +0530)]
drm/amd/display: fix crash/reboot while accessing sysfs files

read/writes to aux_dpcd_* sysfs entries leads to system
reboot or hang.
Hence fix the handling of input data and reporting of errors
appropriately to the user space.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: Move process doorbell allocation into kfd device
Mukul Joshi [Fri, 18 Sep 2020 20:45:45 +0000 (16:45 -0400)]
drm/amdkfd: Move process doorbell allocation into kfd device

Move doorbell allocation for a process into kfd device and
allocate doorbell space in each PDD during process creation.
Currently, KFD manages its own doorbell space but for some
devices, amdgpu would allocate the complete doorbell
space instead of leaving a chunk of doorbell space for KFD to
manage. In a system with mix of such devices, KFD would need
to request process doorbell space based on the type of device,
either from amdgpu or from its own doorbell space.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: Calculate CPU VCRAT size dynamically (v2)
Kent Russell [Fri, 18 Sep 2020 11:42:57 +0000 (07:42 -0400)]
drm/amdkfd: Calculate CPU VCRAT size dynamically (v2)

Instead of guessing at a sufficient size for the CPU VCRAT, base the
size on the number of online NUMA nodes.

v2: fix warning

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Fix handling of KFD initialization failures
Felix Kuehling [Thu, 17 Sep 2020 01:19:34 +0000 (21:19 -0400)]
drm/amdgpu: Fix handling of KFD initialization failures

Remember KFD module initializaton status in a global variable. Skip KFD
device probing when the module was not initialized. Other amdgpu_amdkfd
calls are then protected by the adev->kfd.dev check.

Also print a clear error message when KFD disables itself. Amdgpu
continues its initialization even when KFD failed.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: Skip smu_post_init in SRIOV
Jingwen Chen [Thu, 17 Sep 2020 07:58:40 +0000 (15:58 +0800)]
drm/amd/pm: Skip smu_post_init in SRIOV

smu_post_init needs to enable SMU feature, while this require
virtualization off. Skip it since this feature is not used in SRIOV.

v2: move the check to the early stage of smu_post_init.

v3: fix typo

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: apply dummy reads workaround for CDR enabled only
Evan Quan [Fri, 18 Sep 2020 02:31:14 +0000 (10:31 +0800)]
drm/amd/pm: apply dummy reads workaround for CDR enabled only

For CDR disabled case, the dummy reads workaround is not needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: remove experimental flag from navi12
Alex Deucher [Tue, 15 Sep 2020 17:36:20 +0000 (13:36 -0400)]
drm/amdgpu: remove experimental flag from navi12

Navi12 has worked fine for a while now.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: Reduce eviction/restore message levels
Philip Cox [Wed, 9 Sep 2020 19:44:14 +0000 (15:44 -0400)]
drm/amdkfd: Reduce eviction/restore message levels

Reduce the eviction and restore messages from INFO level to DEBUG level.

Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: Add process eviction counters to sysfs
Philip Cox [Tue, 30 Jun 2020 19:51:05 +0000 (15:51 -0400)]
drm/amdkfd: Add process eviction counters to sysfs

Add per-process eviction counters to sysfs to keep track of
how many eviction events have happened for each process.

v2: rename the stats dir, and track all evictions per process, per device.
v3: Simplify the stats kobject handling and cleanup.
v4: more code cleanup

Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: Add some eveiction debugging code
Philip Cox [Mon, 29 Jun 2020 13:49:59 +0000 (09:49 -0400)]
drm/amdkfd: Add some eveiction debugging code

Extending the module parameter debug_evictions to also print a stack
trace when the eviction code path is called.

Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/powerplay: hwmgr - modify the return value
Xiaoliang Pang [Thu, 17 Sep 2020 03:46:10 +0000 (11:46 +0800)]
drm/amdgpu/powerplay: hwmgr - modify the return value

Return value should be -EINVAL rather than EINVAL

Fixes: f83a9991648bb("drm/amd/powerplay: add Vega10 powerplay support (v5)")
Fixes: 2cac05dee6e30("drm/amd/powerplay: add the hw manager for vega12 (v4)")
Cc: Eric Huang <JinHuiEric.Huang@amd.com>
Cc: Evan Quan <evan.quan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Xiaoliang Pang <dawning.pang@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Delete duplicated argument to '&&' or '||'
Ye Bin [Thu, 17 Sep 2020 10:57:59 +0000 (18:57 +0800)]
drm/amd/display: Delete duplicated argument to '&&' or '||'

Fixes coccicheck warnig:
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c:282:12-42:
duplicated argument to && or ||
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:3240:12-42:
duplicated argument to && or ||
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5520:7-91:
duplicated argument to && or ||
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5309:86-122:
duplicated argument to && or ||

Fixes: 6725a88f88a7 ("drm/amd/display: Add DCN3 DML")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: dc/clk_mgr: make function static
Mauro Rossi [Thu, 17 Sep 2020 07:33:31 +0000 (09:33 +0200)]
drm/amd/display: dc/clk_mgr: make function static

[Why]
linux-next kernel test robot reported the following problem:
warning: no previous prototype for 'dce60_get_dp_ref_freq_khz' [-Wmissing-prototypes]

[How]
mark dce60_get_dp_ref_freq_khz() as static

Fixes: 3ecb3b794e2c "drm/amd/display: dc/clk_mgr: add support for SI parts (v2)"
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add device ID for sienna_cichlid (v2)
Likun Gao [Thu, 16 Jan 2020 02:45:38 +0000 (10:45 +0800)]
drm/amdgpu: add device ID for sienna_cichlid (v2)

Add device ID for sienna_cichlid.

v2: squash in additional device ids.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: use the AV1 defines for VCN 3.0
Alex Deucher [Fri, 1 May 2020 20:46:11 +0000 (16:46 -0400)]
drm/amdgpu: use the AV1 defines for VCN 3.0

Switch from magic numbers to defines for AV1 clockgating.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add VCN 3.0 AV1 registers
Alex Deucher [Fri, 1 May 2020 20:45:09 +0000 (16:45 -0400)]
drm/amdgpu: add VCN 3.0 AV1 registers

This adds the AV1 registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add the GC 10.3 VRS registers
Alex Deucher [Fri, 1 May 2020 20:42:56 +0000 (16:42 -0400)]
drm/amdgpu: add the GC 10.3 VRS registers

Add the VRS registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Remove set but used 'temp'
Ye Bin [Wed, 16 Sep 2020 01:08:58 +0000 (09:08 +0800)]
drm/amd/display: Remove set but used 'temp'

Addresses the following gcc warning with "make W=1":

In file included from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../dmub_srv.h:67:0,
from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn21.c:26:
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h: In function ‘dmub_rb_flush_pending’:
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h:795:12: warning: variable ‘temp’ set but not used
 [-Wunused-but-set-variable]
    uint64_t temp;
                ^
In file included from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../dmub_srv.h:67:0,
                 from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn30.c:26:
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h: In function ‘dmub_rb_flush_pending’:
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h:795:12: warning: variable ‘temp’ set but not used
[-Wunused-but-set-variable]
   uint64_t temp;

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: unmap register bar on device init failure
Alex Deucher [Wed, 16 Sep 2020 14:28:55 +0000 (10:28 -0400)]
drm/amdgpu: unmap register bar on device init failure

We never unmapped the regiser BAR on failure.

Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700
Tom St Denis [Wed, 16 Sep 2020 16:17:04 +0000 (12:17 -0400)]
drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700

This register was requested for umr debugging support.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add missing "Copy GSL groups when committing a new context"
Bhawanpreet Lakha [Wed, 16 Sep 2020 16:44:46 +0000 (12:44 -0400)]
drm/amd/display: Add missing "Copy GSL groups when committing a new context"

[Why]
"Copy GSL groups when committing a new context" patch was accidentally
removed during a refactor

Patch: 21ffcc94d5b ("drm/amd/display: Copy GSL groups when committing a new context")

[How]
Re add it

Fixes: b6e881c9474 ("drm/amd/display: update navi to use new surface programming behaviour")
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Don't log hdcp module warnings in dmesg
Bhawanpreet Lakha [Tue, 15 Sep 2020 21:26:29 +0000 (17:26 -0400)]
drm/amd/display: Don't log hdcp module warnings in dmesg

[Why]
DTM topology updates happens by default now. This results in DTM
warnings when hdcp is not even being enabled. This spams the dmesg
and doesn't effect normal display functionality so it is better to log it
using DRM_DEBUG_KMS()

[How]
Change the DRM_WARN() to DRM_DEBUG_KMS()

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: prevent double kfree ttm->sg
Philip Yang [Tue, 15 Sep 2020 21:07:35 +0000 (17:07 -0400)]
drm/amdgpu: prevent double kfree ttm->sg

Set ttm->sg to NULL after kfree, to avoid memory corruption backtrace:

[  420.932812] kernel BUG at
/build/linux-do9eLF/linux-4.15.0/mm/slub.c:295!
[  420.934182] invalid opcode: 0000 [#1] SMP NOPTI
[  420.935445] Modules linked in: xt_conntrack ipt_MASQUERADE
[  420.951332] Hardware name: Dell Inc. PowerEdge R7525/0PYVT1, BIOS
1.5.4 07/09/2020
[  420.952887] RIP: 0010:__slab_free+0x180/0x2d0
[  420.954419] RSP: 0018:ffffbe426291fa60 EFLAGS: 00010246
[  420.955963] RAX: ffff9e29263e9c30 RBX: ffff9e29263e9c30 RCX:
000000018100004b
[  420.957512] RDX: ffff9e29263e9c30 RSI: fffff3d33e98fa40 RDI:
ffff9e297e407a80
[  420.959055] RBP: ffffbe426291fb00 R08: 0000000000000001 R09:
ffffffffc0d39ade
[  420.960587] R10: ffffbe426291fb20 R11: ffff9e49ffdd4000 R12:
ffff9e297e407a80
[  420.962105] R13: fffff3d33e98fa40 R14: ffff9e29263e9c30 R15:
ffff9e2954464fd8
[  420.963611] FS:  00007fa2ea097780(0000) GS:ffff9e297e840000(0000)
knlGS:0000000000000000
[  420.965144] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  420.966663] CR2: 00007f16bfffefb8 CR3: 0000001ff0c62000 CR4:
0000000000340ee0
[  420.968193] Call Trace:
[  420.969703]  ? __page_cache_release+0x3c/0x220
[  420.971294]  ? amdgpu_ttm_tt_unpopulate+0x5e/0x80 [amdgpu]
[  420.972789]  kfree+0x168/0x180
[  420.974353]  ? amdgpu_ttm_tt_set_user_pages+0x64/0xc0 [amdgpu]
[  420.975850]  ? kfree+0x168/0x180
[  420.977403]  amdgpu_ttm_tt_unpopulate+0x5e/0x80 [amdgpu]
[  420.978888]  ttm_tt_unpopulate.part.10+0x53/0x60 [amdttm]
[  420.980357]  ttm_tt_destroy.part.11+0x4f/0x60 [amdttm]
[  420.981814]  ttm_tt_destroy+0x13/0x20 [amdttm]
[  420.983273]  ttm_bo_cleanup_memtype_use+0x36/0x80 [amdttm]
[  420.984725]  ttm_bo_release+0x1c9/0x360 [amdttm]
[  420.986167]  amdttm_bo_put+0x24/0x30 [amdttm]
[  420.987663]  amdgpu_bo_unref+0x1e/0x30 [amdgpu]
[  420.989165]  amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x9ca/0xb10
[amdgpu]
[  420.990666]  kfd_ioctl_alloc_memory_of_gpu+0xef/0x2c0 [amdgpu]

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: No sysfs, not an error condition
Luben Tuikov [Wed, 16 Sep 2020 17:03:50 +0000 (13:03 -0400)]
drm/amdgpu: No sysfs, not an error condition

Not being able to create amdgpu sysfs attributes
is not a fatal error warranting not to continue
to try to bring up the display. Thus, if we get
an error trying to create amdgpu sysfs attrs,
report it and continue on to try to bring up
a display.

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Slava Abramov <slava.abramov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: declare ta firmware for navy_flounder
Jiansong Chen [Wed, 16 Sep 2020 11:17:20 +0000 (19:17 +0800)]
drm/amdgpu: declare ta firmware for navy_flounder

The firmware provided via MODULE_FIRMWARE appears in the
module information. External tools(eg. dracut) may use the
list of fw files to include them as appropriate in an initramfs,
thus missing declaration will lead to request firmware failure
in boot time.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agoamdgpu/gmc_v9: Warn if SDPIF_MMIO_CNTRL_0 is not set
Shirish S [Mon, 14 Sep 2020 04:41:23 +0000 (10:11 +0530)]
amdgpu/gmc_v9: Warn if SDPIF_MMIO_CNTRL_0 is not set

With IOMMU enabled, if SDPIF_MMIO_CNTRL_0 is not set
appropriately the system hangs without any trace
during S3.

To ease debug and to ensure that the failure, if any,
was caused by a race conditions that disabled write access to
SDPIF_MMIO_CNTRL_0 register, warn the user about it.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: correct Renoir UMD Stable Pstate settings
Evan Quan [Fri, 4 Sep 2020 08:08:15 +0000 (16:08 +0800)]
drm/amd/pm: correct Renoir UMD Stable Pstate settings

Update the UMD stable Pstate settings with correct clocks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: lower Raven UMD Stable Pstate VCN values
Evan Quan [Fri, 4 Sep 2020 07:49:08 +0000 (15:49 +0800)]
drm/amd/pm: lower Raven UMD Stable Pstate VCN values

SMU FCLK,SOCCLK have dependency on VCN CLKs. Lower VCN values so that
FCLK, SOCCLK reflect values set by UMD Stable Pstate.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: move NAVI1X power mode switching workaround to post_init
Evan Quan [Fri, 4 Sep 2020 07:05:55 +0000 (15:05 +0800)]
drm/amd/pm: move NAVI1X power mode switching workaround to post_init

Since that should be the correct place to put ASIC specific
workarounds.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: apply no power source workaround if dc reported by gpio
Evan Quan [Fri, 4 Sep 2020 06:55:43 +0000 (14:55 +0800)]
drm/amd/pm: apply no power source workaround if dc reported by gpio

If dc reported by gpio is supported, the power source switching will
be performed by pmfw automatically. Thus the power source setting
workaround for Navi1x will be not needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: process pending AC/DC switch interrupt
Evan Quan [Fri, 4 Sep 2020 06:41:07 +0000 (14:41 +0800)]
drm/amd/pm: process pending AC/DC switch interrupt

Process any pending interrupt that occured before driver register
for interrupt from GPIO/SMU.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: add Raven2 watermark WmType setting
Evan Quan [Thu, 3 Sep 2020 07:42:59 +0000 (15:42 +0800)]
drm/amd/pm: add Raven2 watermark WmType setting

Which tells it's a normal pstate change or memory retraining.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: add Renoir watermark WmType setting
Evan Quan [Thu, 3 Sep 2020 07:13:09 +0000 (15:13 +0800)]
drm/amd/pm: add Renoir watermark WmType setting

Which tells it's a normal pstate change or memory retraining.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: drop unnecessary wrappers around watermark setting
Evan Quan [Thu, 3 Sep 2020 07:02:37 +0000 (15:02 +0800)]
drm/amd/pm: drop unnecessary wrappers around watermark setting

The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15"
is totally unnecessary and can be dropped.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: drop dead code
Evan Quan [Thu, 3 Sep 2020 06:41:47 +0000 (14:41 +0800)]
drm/amd/pm: drop dead code

Raven never goes to swsmu path. So "adev->smu.ppt_funcs" will be
always false.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: minor cleanups
Evan Quan [Mon, 24 Aug 2020 07:25:28 +0000 (15:25 +0800)]
drm/amd/pm: minor cleanups

Drop unneeded "ret".

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: drop unnecessary table existence and dpm enablement check
Evan Quan [Mon, 24 Aug 2020 07:21:30 +0000 (15:21 +0800)]
drm/amd/pm: drop unnecessary table existence and dpm enablement check

Either this was already performed in parent API. Or the table is
confirmed to exist.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: drop unnecessary smu_baco->mutex lock protections(V2)
Evan Quan [Mon, 24 Aug 2020 07:18:00 +0000 (15:18 +0800)]
drm/amd/pm: drop unnecessary smu_baco->mutex lock protections(V2)

As these operations are performed in hardware setup and there
is actually no race conditions during this period considering:
1. the hardware setup is serial and cannot be in parallel
2. all other operations can be performed only after hardware
   setup complete.

V2: rich the commit log description

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: drop unnecessary feature->mutex lock protections(V2)
Evan Quan [Mon, 24 Aug 2020 07:11:47 +0000 (15:11 +0800)]
drm/amd/pm: drop unnecessary feature->mutex lock protections(V2)

As these operations are performed in hardware setup and there
is actually no race conditions during this period considering:
1. the hardware setup is serial and cannot be in parallel
2. all other operations can be performed only after hardware
   setup complete.

V2: rich the commit log description

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: make namings and comments more readable
Evan Quan [Wed, 26 Aug 2020 10:37:00 +0000 (18:37 +0800)]
drm/amd/pm: make namings and comments more readable

And to fit more accurately what the cod does.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: correct the requirement for umc cdr workaround
Evan Quan [Wed, 26 Aug 2020 10:27:09 +0000 (18:27 +0800)]
drm/amd/pm: correct the requirement for umc cdr workaround

The workaround can be applied only with UCLK DPM enabled.
And expand the workaround to more Navi10 SKUs and also
Navi14.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares(V2)
Evan Quan [Wed, 26 Aug 2020 10:19:28 +0000 (18:19 +0800)]
drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares(V2)

And different workaround will be applied based on hybrid cdr bit.

V2: add pmfw version guard to make sure the new workaround applied only
    with pmfw >= 42.53.0

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: implement a new umc cdr workaround
Evan Quan [Wed, 26 Aug 2020 09:58:29 +0000 (17:58 +0800)]
drm/amd/pm: implement a new umc cdr workaround

By uploading dummy pstate tables.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: allocate a new buffer for pstate dummy reading
Evan Quan [Wed, 26 Aug 2020 08:10:29 +0000 (16:10 +0800)]
drm/amd/pm: allocate a new buffer for pstate dummy reading

This dummy reading buffer will be used for the new Navi1x
UMC CDR workaround.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: revise the umc hybrid cdr workaround
Evan Quan [Wed, 26 Aug 2020 08:50:30 +0000 (16:50 +0800)]
drm/amd/pm: revise the umc hybrid cdr workaround

Drop the unused message(SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE).
And do not apply this workaround when the max uclk frequency
is greater than 750Mhz.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: put Navi1X umc cdr workaround in post_smu_init
Evan Quan [Tue, 1 Sep 2020 03:33:53 +0000 (11:33 +0800)]
drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init

That's where the uclk dpm get enabled and then the
uclk cdr workaround can be applied.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2)
Evan Quan [Tue, 1 Sep 2020 03:02:31 +0000 (11:02 +0800)]
drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2)

This is needed for Navi1X only. And it may help for display missing
or hang issue seen on some high resolution monitors.

V2: no UCLK DPM enablement for Navi10 A0 secure SKU

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2)
Evan Quan [Tue, 1 Sep 2020 02:23:34 +0000 (10:23 +0800)]
drm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2)

So that ASIC specific actions can be added.

V2: better namings

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is
Michel Dänzer [Fri, 4 Sep 2020 10:43:04 +0000 (12:43 +0200)]
drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is

Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:

 * Hence drivers must not consult @active in their various
 * &drm_mode_config_funcs.atomic_check callback to reject an atomic
 * commit.

atomic_remove_fb disables the CRTC as needed for disabling the primary
plane.

This prevents at least the following problems if the primary plane gets
disabled (e.g. due to destroying the FB assigned to the primary plane,
as happens e.g. with mutter in Wayland mode):

* The legacy cursor ioctl returned EINVAL for a non-0 cursor FB ID
  (which enables the cursor plane).
* If the cursor plane was enabled, changing the legacy DPMS property
  value from off to on returned EINVAL.

v2:
* Minor changes to code comment and commit log, per review feedback.

GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1108
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1165
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1344
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/gmc9: remove mmhub client duplicated case
Alex Deucher [Mon, 14 Sep 2020 15:36:21 +0000 (11:36 -0400)]
drm/amdgpu/gmc9: remove mmhub client duplicated case

Copy paste typo.

Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Fail to load on RAVEN if SME is active
Alex Deucher [Sun, 6 Sep 2020 16:05:12 +0000 (12:05 -0400)]
drm/amdgpu: Fail to load on RAVEN if SME is active

Due to hardware bugs, scatter/gather display on raven requires
a 1:1 IOMMU mapping, however, SME (System Memory Encryption)
requires an indirect IOMMU mapping because the encryption bit
is beyond the DMA mask of the chip.  As such, the two are
incompatible.

Acked-by: Joerg Roedel <jroedel@suse.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Create trigger_hotplug entry
YueHaibing [Thu, 10 Sep 2020 03:13:52 +0000 (11:13 +0800)]
drm/amd/display: Create trigger_hotplug entry

Add trigger_hotplug debugfs entry.

Fixes: 6f77b2ac6280 ("drm/amd/display: Add connector HPD trigger debugfs entry")
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix possible memleak in dp_trigger_hotplug()
YueHaibing [Thu, 10 Sep 2020 03:26:36 +0000 (11:26 +0800)]
drm/amd/display: Fix possible memleak in dp_trigger_hotplug()

If parse_write_buffer_into_params() fails, we should free
wr_buf before return.

Fixes: 6f77b2ac6280 ("drm/amd/display: Add connector HPD trigger debugfs entry")
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: optimize code runtime a bit
Bernard Zhao [Thu, 10 Sep 2020 02:05:04 +0000 (19:05 -0700)]
drm/amd/display: optimize code runtime a bit

In fnction is_cr_done & is_ch_eq_done, when done = false
happened once, no need to circle left ln_count.
This change is to make the code run a bit fast.

Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v4_0.c
Zheng Bin [Wed, 9 Sep 2020 13:07:20 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v4_0.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1003:4-9: WARNING: Comparison to bool
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1083:5-11: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in amdgpu_atpx_handler.c
Zheng Bin [Wed, 9 Sep 2020 13:07:19 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in amdgpu_atpx_handler.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c:619:15-49: WARNING: Comparison to bool
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c:629:15-49: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in uvd_v6_0.c
Zheng Bin [Wed, 9 Sep 2020 13:07:18 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in uvd_v6_0.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c:1243:14-25: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in si.c
Zheng Bin [Wed, 9 Sep 2020 13:07:17 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in si.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/si.c:1342:5-10: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_2.c
Zheng Bin [Wed, 9 Sep 2020 13:07:16 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_2.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:562:5-11: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_0.c
Zheng Bin [Wed, 9 Sep 2020 13:07:15 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_0.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:619:5-11: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v10_0.c
Zheng Bin [Wed, 9 Sep 2020 13:07:14 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v10_0.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3563:5-31: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v9_0.c
Zheng Bin [Wed, 9 Sep 2020 13:07:13 +0000 (21:07 +0800)]
drm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v9_0.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2805:5-11: WARNING: Comparison to bool

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: Add sclk frequency as hwmon sensor
Sandeep Raghuraman [Wed, 9 Sep 2020 11:04:33 +0000 (16:34 +0530)]
drm/radeon: Add sclk frequency as hwmon sensor

This patch adds support for reporting sclk values for Radeon GPUs, where supported.

Signed-off-by: Sandeep Raghuraman <sandy.8925@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/scheduler: fix sched_fence.c kernel-doc warnings
Tian Tao [Wed, 9 Sep 2020 07:57:05 +0000 (15:57 +0800)]
drm/scheduler: fix sched_fence.c kernel-doc warnings

Fix kernel-doc warnings.
drivers/gpu/drm/scheduler/sched_fence.c:110: warning: Function parameter or
member 'f' not described in 'drm_sched_fence_release_scheduled'
drivers/gpu/drm/scheduler/sched_fence.c:110: warning: Excess function
parameter 'fence' description in 'drm_sched_fence_release_scheduled'

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm: amd/display: fix spelling of "function"
Randy Dunlap [Tue, 8 Sep 2020 23:56:09 +0000 (16:56 -0700)]
drm: amd/display: fix spelling of "function"

Fix spellos of "function" in drivers/gpu/drm/amd/display/.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Remove duplicate include
Chen Zhou [Tue, 8 Sep 2020 13:35:52 +0000 (21:35 +0800)]
drm/amd/display: Remove duplicate include

Remove duplicate header which is included twice.

Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: stop resetting xgmi perfmons on disable
Jonathan Kim [Tue, 4 Aug 2020 20:26:20 +0000 (16:26 -0400)]
drm/amdgpu: stop resetting xgmi perfmons on disable

Disabling perf events does not specify reset in ABI so stop doing it in
hardware.

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: revert "Prefer lower feedback dividers"
Christian König [Wed, 9 Sep 2020 11:12:46 +0000 (13:12 +0200)]
drm/radeon: revert "Prefer lower feedback dividers"

Turns out this breaks a lot of different hardware.

This reverts commit fc8c70526bd30733ea8667adb8b8ffebea30a8ed.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: More accurate description of a function param
Oak Zeng [Wed, 9 Sep 2020 17:51:45 +0000 (12:51 -0500)]
drm/amdgpu: More accurate description of a function param

Add more accurate description of the pe parameter of function
amdgpu_vm_sdma_udpate and amdgpu_vm_cpu_update

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add comment to function amdgpu_ttm_alloc_gart
Oak Zeng [Wed, 5 Aug 2020 15:53:09 +0000 (10:53 -0500)]
drm/amdgpu: Add comment to function amdgpu_ttm_alloc_gart

Add comments to refect what function does

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Include sienna_cichlid in USBC PD FW support.
Andrey Grodzovsky [Thu, 10 Sep 2020 17:59:33 +0000 (13:59 -0400)]
drm/amdgpu: Include sienna_cichlid in USBC PD FW support.

Create sysfs interface also for sienna_cichlid.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>