Fortran/OpenMP: align/allocator modifiers to the allocate clause

gcc/fortran/ChangeLog:

* dump-parse-tree.cc (show_omp_namelist): Improve OMP_LIST_ALLOCATE
output.
* gfortran.h (struct gfc_omp_namelist): Add 'align' to 'u'.
(gfc_free_omp_namelist): Add bool arg.
* match.cc (gfc_free_omp_namelist): Likewise; free 'u.align'.
* openmp.cc (gfc_free_omp_clauses, gfc_match_omp_clause_reduction,
gfc_match_omp_flush): Update call.
(gfc_match_omp_clauses): Match 'align/allocate modifers in
'allocate' clause.
(resolve_omp_clauses): Resolve align.
* st.cc (gfc_free_statement): Update call
* trans-openmp.cc (gfc_trans_omp_clauses): Handle 'align'.

libgomp/ChangeLog:

* libgomp.texi (5.1 Impl. Status): Split allocate clause/directive
item about 'align'; mark clause as 'Y' and directive as 'N'.
* testsuite/libgomp.fortran/allocate-2.f90: New test.
* testsuite/libgomp.fortran/allocate-3.f90: New test.

rs6000: Remove useless copy_rtx in rs6000_emit_set_{,long}_const

Function rs6000_emit_set_const/rs6000_emit_set_long_const are only invoked from
two "define_split"s where the target operand is limited to gpc_reg_operand or
int_reg_operand, then the operand must be REG_P.
And in rs6000_emit_set_const/rs6000_emit_set_long_const, to create temp rtx,
it is using code like "gen_reg_rtx({S|D}Imode)", it must also be REG_P.
So, copy_rtx is not needed for temp and dest.

This patch removes those "copy_rtx" for rs6000_emit_set_const and
rs6000_emit_set_long_const.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_set_const): Remove copy_rtx.
(rs6000_emit_set_long_const): Likewise.

MAINTAINERS: fix spacing

ChangeLog:

* MAINTAINERS: Fix spacing.

i386: fix assert (__builtin_cpu_supports ("x86-64") >= 0)

Similar story as PR103661, we again return a negative number
for __builtin_cpu_supports:

Documentation says:

int __builtin_cpu_supports(const char *feature)
This function returns a positive integer if the run-time CPU supports feature and returns 0 otherwise.
while we return -2147483648.

Moreover, I noticed "x86-64" is not a valid option for __builtin_cpu_is,
but for __builtin_cpu_supports.

PR target/107551

gcc/ChangeLog:

* config/i386/i386-builtins.cc (fold_builtin_cpu): Use same path
as for PR103661.
* doc/extend.texi: Fix "x86-64" use.

gcc/testsuite/ChangeLog:

* gcc.target/i386/builtin_target.c: Add more checks.

Rename SUBTARGET_CC1_SPEC to OS_CC1_SPEC

This change resolves a naming conflict introduced by the recently added
SUBTARGET_CC1_SPEC to gcc.cc.  Some targets (mips and loongarch) aready used
a SUBTARGET_CC1_SPEC define.  Rename the define used by gcc.cc to OS_CC1_SPEC.

gcc/ChangeLog:

* config/rtems.h (SUBTARGET_CC1_SPEC): Rename to...
(OS_CC1_SPEC): ...this.
* gcc.cc (SUBTARGET_CC1_SPEC): Rename to...
(OS_CC1_SPEC): ...this.

analyzer: rename region-model-impl-calls.cc to kf.cc

gcc/ChangeLog:
* Makefile.in (ANALYZER_OBJS): Update for renaming of
analyzer/region-model-impl-calls.cc to analyzer/kf.cc.

gcc/analyzer/ChangeLog:
* analyzer.h (class known_function): Expand comment.
* region-model-impl-calls.cc: Rename to...
* kf.cc: ...this.
* known-function-manager.h (class known_function_manager): Add
leading comment.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

analyzer: fix ICE on region creation during get_referenced_base_regions [PR108003]

gcc/analyzer/ChangeLog:
PR analyzer/108003
* call-summary.cc
(call_summary_replay::convert_region_from_summary_1): Convert
heap_regs_in_use from auto_sbitmap to auto_bitmap.
* region-model-manager.cc
(region_model_manager::get_or_create_region_for_heap_alloc):
Convert from sbitmap to bitmap.
* region-model-manager.h: Likewise.
* region-model.cc
(region_model::get_or_create_region_for_heap_alloc): Convert from
auto_sbitmap to auto_bitmap.
(region_model::get_referenced_base_regions): Likewise.
* region-model.h: Include "bitmap.h" rather than "sbitmap.h".
(region_model::get_referenced_base_regions): Convert from
auto_sbitmap to auto_bitmap.

gcc/testsuite/ChangeLog:
PR analyzer/108003
* g++.dg/analyzer/pr108003.C: New test.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

analyzer: handle memmove like memcpy

gcc/analyzer/ChangeLog:
* region-model-impl-calls.cc (class kf_memcpy): Rename to...
(class kf_memcpy_memmove): ...this.
(kf_memcpy::impl_call_pre): Rename to...
(kf_memcpy_memmove::impl_call_pre): ...this, and check the src for
poison.
(register_known_functions): Update for above renaming, and
register BUILT_IN_MEMMOVE and BUILT_IN_MEMMOVE_CHK.

gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/memcpy-1.c (test_8a, test_8b): New tests.
* gcc.dg/analyzer/memmove-1.c: New test, based on memcpy-1.c
* gcc.dg/analyzer/out-of-bounds-1.c (test7): Update expected
result for uninit srcBuf.
* gcc.dg/analyzer/out-of-bounds-5.c (test8, test9): Add
dg-warnings for memcpy from uninit src vla.
* gcc.dg/analyzer/pr104308.c (test_memmove_within_uninit):
Expect creation point note to be missing on riscv*-*-*.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

Enable hwasan for x86-64.

libsanitizer
* configure.tgt: Enable hwasan for x86-64.

Implement hwasan target_hook.

gcc/ChangeLog:

* doc/invoke.texi (x86 options): Document
-mlam={none,u48,u57}.
* config/i386/i386-opts.h (enum lam_type): New enum.
* config/i386/i386.cc (ix86_memtag_can_tag_addresses): New.
(ix86_memtag_set_tag): Ditto.
(ix86_memtag_extract_tag): Ditto.
(ix86_memtag_add_tag): Ditto.
(ix86_memtag_tag_size): Ditto.
(ix86_memtag_untagged_pointer): Ditto.
(TARGET_MEMTAG_CAN_TAG_ADDRESSES): New.
(TARGET_MEMTAG_ADD_TAG): Ditto.
(TARGET_MEMTAG_SET_TAG): Ditto.
(TARGET_MEMTAG_EXTRACT_TAG): Ditto.
(TARGET_MEMTAG_UNTAGGED_POINTER): Ditto.
(TARGET_MEMTAG_TAG_SIZE): Ditto.
(IX86_HWASAN_SHIFT): Ditto.
(IX86_HWASAN_TAG_SIZE): Ditto.
* config/i386/i386-expand.cc (ix86_expand_call): Untag code
pointer.
* config/i386/i386-options.cc (ix86_option_override_internal):
Error when enable -mlam=[u48|u57] for 32-bit code.
* config/i386/i386.opt: Add -mlam=[none|u48|u57].
* config/i386/i386-protos.h (ix86_memtag_untagged_pointer):
Declare.
(ix86_memtag_can_tag_addresses): Ditto.

libstdc++: Remove digit separators [PR108015]

These are not valid in C++11 and cause a warning when preprocessing,
even though they're inside a skipped group.

chrono:2436: warning: missing terminating ' character

libstdc++-v3/ChangeLog:

PR libstdc++/108015
* include/std/chrono (hh_mm_ss): Remove digit separators.

libstdc++: Fix some -Wunused warnings in tests

libstdc++-v3/ChangeLog:

* include/ext/pb_ds/detail/type_utils.hpp (PB_DS_STATIC_ASSERT):
Add unused attribute to avoid -Wunused-local-typedef warnings.
* testsuite/17_intro/tag_type_explicit_ctor.cc: Add pragma to
ignore -Wunused-variable warnings

libstdc++: Add [[nodiscard]] to chrono conversion functions

Also add doxygen comments.

libstdc++-v3/ChangeLog:

* include/bits/chrono.h (duration_cast, floor, round, abs, ceil)
(time_point_cast): Add [[nodiscard]] attribute and doxygen
comments.
(treat_as_floating_point): Add doxygen commen.

libstdc++: Change class-key for duration and time_point to class

We define these with the 'struct' keyword, but the standard uses
'class'. This results in warnings if users try to refer to them using
elaborated type specifiers.

libstdc++-v3/ChangeLog:

* include/bits/chrono.h (duration, time_point): Change 'struct'
to 'class'.

Daily bump.

docs: Suggest options to improve ASAN stack traces

I got a complaint that while Clang docs suggest options that improve
the quality of the backtraces ASAN prints (cf.
<https://clang.llvm.org/docs/AddressSanitizer.html#usage>), our docs
don't say anything to that effect.  This patch amends that with a new
paragraph.  (It deliberately doesn't mention -fno-omit-frame-pointer.)

gcc/ChangeLog:

* doc/invoke.texi (-fsanitize=address): Suggest options to improve
stack traces.

Fortran: diagnose and reject duplicate CONTIGUOUS attribute [PR108025]

gcc/fortran/ChangeLog:

PR fortran/108025
* symbol.cc (gfc_add_contiguous): Diagnose and reject duplicate
CONTIGUOUS attribute.

gcc/testsuite/ChangeLog:

PR fortran/108025
* gfortran.dg/contiguous_12.f90: New test.

Fix count comparison in ipa-cp

The existing comparison was incorrect for non-PRECISE counts
(e.g., AFDO): we could end up with a 0 base_count, which could
lead to asserts, e.g., in good_cloning_opportunity_p.

Tested on x86_64-pc-linux-gnu.

gcc/ChangeLog:
PR ipa/108000
* ipa-cp.cc (ipcp_propagate_stage): Fix profile count comparison

gcc/testsuite
* gcc.dg/tree-prof/pr108000.c: Regression test

bpf: add define_insn for bswap

The eBPF architecture provides 'end[be,le]' instructions for endianness
swapping. Add a define_insn for bswap<mode>2 to use them instaed of
falling back on a libcall.

gcc/

* config/bpf/bpf.md (bswap<mode>2): New define_insn.

gcc/testsuite/

* gcc.target/bpf/bswap-1.c: New test.

c++: build initializer_list<string> in a loop [PR105838]

The previous patch avoided building an initializer_list<string> at all when
building a vector<string>, but in situations where that isn't possible, we
could still build the initializer_list with a loop over a constant array.

This is represented using a VEC_INIT_EXPR, which required adjusting a couple
of places that expected the initializer array to have the same type as the
target array and fixing build_vec_init not to undo our efforts.

PR c++/105838

gcc/cp/ChangeLog:

* call.cc (convert_like_internal) [ck_list]: Use
maybe_init_list_as_array.
* constexpr.cc (cxx_eval_vec_init_1): Init might have
a different type.
* tree.cc (build_vec_init_elt): Likewise.
* init.cc (build_vec_init): Handle from_array from a
TARGET_EXPR.  Retain TARGET_EXPR of a different type.

gcc/testsuite/ChangeLog:

* g++.dg/tree-ssa/initlist-opt2.C: New test.

c++: avoid initializer_list<string> [PR105838]

When constructing a vector<string> from { "strings" }, first is built an
initializer_list<string>, which is then copied into the strings in the
vector.  But this is inefficient: better would be treat the { "strings" }
as a range and construct the strings in the vector directly from the
string-literals.  We can do this transformation for standard library
classes because we know the design patterns they follow.

PR c++/105838

gcc/cp/ChangeLog:

* call.cc (list_ctor_element_type): New.
(braced_init_element_type): New.
(has_non_trivial_temporaries): New.
(maybe_init_list_as_array): New.
(maybe_init_list_as_range): New.
(build_user_type_conversion_1): Use maybe_init_list_as_range.
* parser.cc (cp_parser_braced_list): Call
recompute_constructor_flags.
* cp-tree.h (find_temps_r): Declare.

gcc/testsuite/ChangeLog:

* g++.dg/tree-ssa/initlist-opt1.C: New test.

c++: fewer allocator temps [PR105838]

In this PR, initializing the array of std::string to pass to the vector
initializer_list constructor gets very confusing to the optimizers as the
number of elements increases, primarily because of all the std::allocator
temporaries passed to all the string constructors.  Instead of creating one
for each string, let's share an allocator between all the strings; we can do
this safely because we know that std::allocator is stateless and that string
doesn't care about the object identity of its allocator parameter.

PR c++/105838

gcc/cp/ChangeLog:

* cp-tree.h (is_std_allocator): Declare.
* constexpr.cc (is_std_allocator): Split out  from...
(is_std_allocator_allocate): ...here.
* init.cc (find_temps_r): New.
(find_allocator_temp): New.
(build_vec_init): Use it.

gcc/testsuite/ChangeLog:

* g++.dg/tree-ssa/allocator-opt1.C: New test.

c++: comment

gcc/cp/ChangeLog:

* constexpr.cc (maybe_constant_value): Add default arg comments.

AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776]

Currently patchable area is at the wrong place on AArch64.  It is placed
immediately after function label, before .cfi_startproc.  This patch
adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and
modifies aarch64_print_patchable_function_entry to avoid placing
patchable area before .cfi_startproc.

gcc/
PR target/98776
* config/aarch64/aarch64-protos.h (aarch64_output_patchable_area):
Declared.
* config/aarch64/aarch64.cc (aarch64_print_patchable_function_entry):
Emit an UNSPECV_PATCHABLE_AREA pseudo instruction.
(aarch64_output_patchable_area): New.
* config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New.
(patchable_area): Define.

gcc/testsuite/
PR target/98776
* gcc.target/aarch64/pr98776.c: New.
* gcc.target/aarch64/pr92424-2.c: Adjust pattern.
* gcc.target/aarch64/pr92424-3.c: Adjust pattern.

testsuite: Fix leaks in tree-dynamic-object-size-0.c

In commit e5cfb9cac1d7aba9a8ea73bfe7922cfaff9d61f3 I introduced tests
for strdup and strndup with leaks.  Fix those leaks.

gcc/testsuite/ChangeLog:

* gcc.dg/builtin-dynamic-object-size-0.c (test_strdup,
test_strndup, test_strdup_min, test_strndup_min): Free RES
before returning from function.

Signed-off-by: Siddhesh Poyarekar <siddhesh@gotplt.org>

cfgbuild: Fix DEBUG_INSN handling in find_bb_boundaries [PR106719]

The following testcase FAILs on aarch64-linux.  We have some atomic
instruction followed by 2 DEBUG_INSNs (if -g only of course) followed
by NOTE_INSN_EPILOGUE_BEG followed by some USE insn.
Now, split3 pass replaces the atomic instruction with a code sequence
which ends with a conditional jump and the split3 pass calls
find_many_sub_basic_blocks.
For -g0, find_bb_boundaries sees the flow_transfer_insn (the new conditional
jump), then NOTE_INSN_EPILOGUE_BEG which can live in between basic blocks
and then the USE insn, so splits block after the NOTE_INSN_EPILOGUE_BEG
and puts the NOTE in between the blocks.
For -g, if sees a DEBUG_INSN after the flow_transfer_insn, so sets
debug_insn to it, then walks over another DEBUG_INSN, NOTE_INSN_EPILOGUE_BEG
until it finally sees the USE insn, and triggers the:
          rtx_insn *prev = PREV_INSN (insn);

          /* If the first non-debug inside_basic_block_p insn after a control
             flow transfer is not a label, split the block before the debug
             insn instead of before the non-debug insn, so that the debug
             insns are not lost.  */
          if (debug_insn && code != CODE_LABEL && code != BARRIER)
            prev = PREV_INSN (debug_insn);
code I've added for PR81325.  If there are only DEBUG_INSNs, that is
the right thing to do, but if in between debug_insn and insn there are
notes which can stay in between basic blocks or simnilarly JUMP_TABLE_DATA
or their associated CODE_LABELs, it causes -fcompare-debug differences.

The following patch fixes it by clearing debug_insn if JUMP_TABLE_DATA
or associated CODE_LABEL is seen (I'm afraid there is no good answer
what to do with DEBUG_INSNs before those; the code then removes them:
              /* Clean up the bb field for the insns between the blocks.  */
              for (x = NEXT_INSN (flow_transfer_insn);
                   x != BB_HEAD (fallthru->dest);
                   x = next)
                {
                  next = NEXT_INSN (x);
                  /* Debug insns should not be in between basic blocks,
                     drop them on the floor.  */
                  if (DEBUG_INSN_P (x))
                    delete_insn (x);
                  else if (!BARRIER_P (x))
                    set_block_for_insn (x, NULL);
                }
but if there are NOTEs, the patch just reorders the NOTEs and DEBUG_INSNs,
such that the NOTEs come first (so that they stay in between basic blocks
like with -g0) and DEBUG_INSNs after those (so that bb is split before
them, so they will be in the basic block after NOTE_INSN_BASIC_BLOCK).

2022-12-08  Jakub Jelinek  <jakub@redhat.com>

PR debug/106719
* cfgbuild.cc (find_bb_boundaries): If there are NOTEs in between
debug_insn (seen after flow_transfer_insn) and insn, move NOTEs
before all the DEBUG_INSNs and split after NOTEs.  If there are
other insns like jump table data, clear debug_insn.

* gcc.dg/pr106719.c: New test.

i386: Add *concat<mode><dwi>3_{5,6,7} patterns [PR107627]

On Thu, Dec 01, 2022 at 09:09:51AM +0100, Jakub Jelinek via Gcc-patches wrote:
> BTW, I wonder if we couldn't add additional patterns which would catch
> the case where one of the operands is constant.

The following patch does add those.
The difference with the patch on the 2 testcases is:
 baz:
-       movq    8(%rsi), %rax
+       movq    8(%rsi), %rsi
+       movq    %rdi, %r8
        movl    %edx, %ecx
-       xorl    %r8d, %r8d
-       xorl    %edx, %edx
-       movabsq $-2401053089206453570, %r9
-       orq     %r8, %rax
-       orq     %r9, %rdx
-       shrdq   %rdx, %rax
-       movq    %rax, (%rdi)
+       movabsq $-2401053089206453570, %rdi
+       movq    %rsi, %rax
+       shrdq   %rdi, %rax
+       movq    %rax, (%r8)
 qux:
-       movq    (%rsi), %rax
+       movq    %rdi, %r8
+       movq    (%rsi), %rdi
        movl    %edx, %ecx
-       xorl    %r9d, %r9d
-       movabsq $-2401053089206453570, %r8
-       movq    %rax, %rdx
-       xorl    %eax, %eax
-       orq     %r8, %rax
-       orq     %r9, %rdx
-       shrdq   %rdx, %rax
-       movq    %rax, (%rdi)
+       movabsq $-2401053089206453570, %rsi
+       movq    %rsi, %rax
+       shrdq   %rdi, %rax
+       movq    %rax, (%r8)
and
 garply:
        pushl   %esi
-       xorl    %edx, %edx
+       movl    $-559038737, %esi
        pushl   %ebx
        movl    16(%esp), %eax
-       orl     $-559038737, %edx
        movl    20(%esp), %ecx
-       movl    4(%eax), %eax
-       shrdl   %edx, %eax
        movl    12(%esp), %edx
+       movl    4(%eax), %ebx
+       movl    %ebx, %eax
+       shrdl   %esi, %eax
 fred:
...
        movl    16(%esp), %eax
+       movl    $-889275714, %ebx
        movl    20(%esp), %ecx
-       movl    (%eax), %eax
-       movl    %eax, %edx
-       movl    $0, %eax
-       orl     $-889275714, %eax
-       shrdl   %edx, %eax
        movl    12(%esp), %edx
+       movl    (%eax), %esi
+       movl    %ebx, %eax
+       shrdl   %esi, %eax

2022-12-08  Jakub Jelinek  <jakub@redhat.com>

PR target/107627
* config/i386/i386.md (HALF, half): New mode attributes.
(*concat<half><mode>3_5, *concat<mode><dwi>3_6,
*concat<mode><dwi>3_7): New define_insn_and_split patterns.

* gcc.target/i386/pr107627-3.c: New test.
* gcc.target/i386/pr107627-4.c: New test.

Ensure arguments to range-op handler are supported.

PR tree-optimization/107985
gcc/
* gimple-range-op.cc
(gimple_range_op_handler::gimple_range_op_handler): Check if type
of the operands is supported.
* gimple-range.cc (gimple_ranger::prefill_stmt_dependencies): Do
not assert if here is no range-op handler.

gcc/testsuite/
* g++.dg/pr107985.C: New.

rs6000: Update sign extension computation with sext_hwi

This patch just replaces the expression like:
((value & 0xf..f) ^ 0x80..0) - 0x80..0 to better code(e.g. sext_hwi) for
rs6000.cc, rs6000.md and predicates.md (files under rs6000/).

gcc/ChangeLog:

* config/rs6000/predicates.md: Use sext_hwi.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Likewise.
(darwin_rs6000_legitimate_lo_sum_const_p): Likewise.
(mem_operand_gpr): Likewise.
(mem_operand_ds_form): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_emit_set_const): Likewise.
(rs6000_emit_set_long_const): Likewise.
(print_operand): Likewise.
(constant_generates_xxspltiw): Remove unnecessary expressions.
* config/rs6000/rs6000.md: Use sext_hwi.

tree-optimization/107699 - missed &data._M_elems + _1 != &data._M_elems folding

The following addresses a missed folding noticed in PR107699 that can
be fixed amending the existing &x + a != &x + b pattern to also handle
the case of only one side having a pointer plus.  I'm moving the
patterns next to related simpifications showing there'd be an existing
pattern matching this if it were not gated with an explicit single_use
constraint.  Note the new pattern also handles &x.a + a != &x.b, but
this hints at some unification / generalization opportunities here.

PR tree-optimization/107699
* match.pd (&a !=/== &a.b + c -> (&a - &a.b) !=/== c): New
pattern variant.

* gcc.dg/tree-ssa/pr107699.c: New testcase.

[PR102706] [testsuite] -Wno-stringop-overflow vs Warray-bounds

The bogus Wstringop-overflow warnings conditionally issued for
Warray-bounds-48.c and -Wzero-length-array-bounds-2.c are expected
under conditions that depend on the availability of certain vector
patterns, but that don't seem to model the conditions under which the
warnings are expected.

On riscv64-elf and arm-eabi/-mcpu=cortex-r5, for example, though the
Warray-bounds-48.c condition passes, we don't issue warnings.  On
riscv64-elf, we decide not to vectorize the assignments; on cortex-r5,
we do vectorize pairs of assignments, but that doesn't yield the
expected warning, even though assignments that should trigger the
bogus warning are vectorized and associated with the earlier line
where the bogus warning would be expected.

On riscv64, for Wzero-length-array-bounds-2.c, we issue the expected
warning in test_C_global_buf, but we also issue a warning for
test_C_local_buf under the same conditions, that would be expected on
other platforms but that is not issued on them.  On
arm-eabi/-mcpu=cortex-r5, the condition passes so we'd expect the
warning in both functions, but we don't warn on either.

Instead of further extending the effective target tests, introduced to
temporarily tolerate these expected bogus warnings, so as to capture
the vectorizer analyses that lead to the mismatched decisions, I'm
disabling the undesired warnings for these two tests.

for  gcc/testsuite/ChangeLog

PR tree-optimization/102706
* gcc.dg/Warray-bounds-48.c: Disable -Wstringop-overflow.
* gcc.dg/Wzero-length-array-bounds-2.c: Likewise.

[arm] xfail fp-uint64-convert-double tests

The FP emulation on ARM doesn't take rounding modes into account.  The
tests require hard_float, but that only tests for calls when adding
doubles.  There are arm targets that support hardware adds, but that
emulate conversions.

for  gcc/testsuite/ChangeLog

* gcc.dg/torture/fp-uint64-convert-double-1.c: Expect fail on
arm-*-eabi*.
* gcc.dg/torture/fp-uint64-convert-double-2.c: Likewise.

[testsuite] [arm/aarch64] -fno-short-enums for auto-init-[12].c

On arm-eabi, and possibly on other platforms, -fshort-enums is enabled
by default, which breaks some tests' expectations as to enum sizes
with DEFERRED_INIT.  Disable short enums so that the expectations are
met.

for  gcc/testsuite/ChangeLog

* c-c++-common/auto-init-1.c: Add -fno-short-enums.
* c-c++-common/auto-init-2.c: Likewise.
* gcc.dg/debug/btf/btf-enum-1.c: Likewise.

range-op-float: frange_arithmetic tweaks for MODE_COMPOSITE_P

As mentioned in PR107967, ibm-ldouble-format documents that
+- has 1ulp accuracy, * 2ulps and / 3ulps.
So, even if the result is exact, we need to widen the range a little bit.

The following patch does that.  I just wonder what it means for reverse
division (the op1_range case), which we implement through multiplication,
when division has 3ulps error and multiplication just 2ulps.  In any case,
this format is a mess and for non-default rounding modes can't be trusted
at all, instead of +inf or something close to it it happily computes -inf.

2022-12-08  Jakub Jelinek  <jakub@redhat.com>

* range-op-float.cc (frange_nextafter): For MODE_COMPOSITE_P from
denormal or zero, use real_nextafter on DFmode with conversions
around it.
(frange_arithmetic): For mode_composite, on top of rounding in the
right direction accept extra 1ulp error for PLUS/MINUS_EXPR, extra
2ulps error for MULT_EXPR and extra 3ulps error for RDIV_EXPR.

arm: fix mve intrinsics scan body tests for C++

Hi all,

this patch is to export the functions defined in these MVE tests as C
so the body scan assembler works as expected also for our C++ tests.

Best Regards and sorry for the regression!

  Andrea

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Extern functions
as "C".
* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.

range-op-float: Fix up frange_arithmetic [PR107967]

The addition of PLUS/MINUS/MULT/RDIV_EXPR frange handlers causes
miscompilation of some of the libm routines, resulting in lots of
glibc test failures.  A part of them is purely PR107608 fold-overflow-1.c
etc. issues, say when the code does
  return -0.5 / 0.0;
and expects division by zero to be emitted, but we propagate -Inf
and avoid the operation.
But there are also various tests where we end up with different computed
value from the expected ones.  All those cases are like:
 is:          inf   inf
 should be:   1.18973149535723176502e+4932   0xf.fffffffffffffff0p+16380
 is:          inf   inf
 should be:   1.18973149535723176508575932662800701e+4932   0x1.ffffffffffffffffffffffffffffp+16383
 is:          inf   inf
 should be:   1.7976931348623157e+308   0x1.fffffffffffffp+1023
 is:          inf   inf
 should be:   3.40282346e+38   0x1.fffffep+127
and the corresponding source looks like:
static const double huge = 1.0e+300;
double whatever (...) {
...
  return huge * huge;
...
}
which for rounding to nearest or +inf should and does return +inf, but
for rounding to -inf or 0 should instead return nextafter (inf, -inf);
The rules IEEE754 has are that operations on +-Inf operands are exact
and produce +-Inf (except for the invalid ones that produce NaN) regardless
of rounding mode, while overflows:
"a) roundTiesToEven and roundTiesToAway carry all overflows to ∞ with the
sign of the intermediate result.
b) roundTowardZero carries all overflows to the format’s largest finite
number with the sign of the intermediate result.
c) roundTowardNegative carries positive overflows to the format’s largest
finite number, and carries negative overflows to −∞.
d) roundTowardPositive carries negative overflows to the format’s most
negative finite number, and carries positive overflows to +∞."

The behavior around overflows to -Inf or nextafter (-inf, inf) was actually
handled correctly, we'd construct [-INF, -MAX] ranges in those cases
because !real_less (&value, &result) in that case - value is finite
but larger in magnitude than what the format can represent (but GCC
internal's format can), while result is -INF in that case.
But for the overflows to +Inf or nextafter (inf, -inf) was handled
incorrectly, it tested real_less (&result, &value) rather than
!real_less (&result, &value), the former test is true when already the
rounding value -> result rounded down and in that case we shouldn't
round again, we should round down when it didn't.

So, in theory this could be fixed just by adding one ! character,
-  if ((mode_composite || (real_isneg (&inf) ? real_less (&result, &value)
+  if ((mode_composite || (real_isneg (&inf) ? !real_less (&result, &value)
                          : !real_less (&value, &result)))
but the following patch goes further.  The distance between
nextafter (inf, -inf) and inf is large (infinite) and expressions like
1.0e+300 * 1.0e+300 always produce +inf in round to nearest mode by far,
so I think having low bound of nextafter (inf, -inf) in that case is
unnecessary.  But if it isn't multiplication but say addition and we are
inexact and very close to the boundary between rounding to nearest
maximum representable vs. rounding to nearest +inf, still using [MAX, +INF]
etc. ranges seems safer because we don't know exactly what we lost in the
inexact computation.

The following patch implements that.

2022-12-08  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/107967
* range-op-float.cc (frange_arithmetic): Fix a thinko - if
inf is negative, use nextafter if !real_less (&result, &value)
rather than if real_less (&result, &value).  If result is +-INF
while value is finite and -fno-rounding-math, don't do rounding
if !inexact or if result is significantly above max representable
value or below min representable value.

* gcc.dg/pr107967-1.c: New test.
* gcc.dg/pr107967-2.c: New test.
* gcc.dg/pr107967-3.c: New test.

libgcc: xtensa: remove stray symbols from X*HAL macro definitions

libgcc/
* config/xtensa/xtensa-config-builtin.h (XCHAL_NUM_AREGS)
(XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE, XCHAL_ICACHE_LINESIZE)
(XCHAL_DCACHE_LINESIZE, XCHAL_MMU_MIN_PTE_PAGE_SIZE)
(XSHAL_ABI): Remove stray symbols from macro definitions.

libbacktrace: support zstd decompression

Support decompressing --compress-debug-sections=zstd.
* configure.ac: Check for zstd library and
--compress-debug-sections=zstd linker option.
* Makefile.am (zstdtest_*): New targets.
(zstdtest_alloc_*, ctestzstd_*): New targets.
(BUILDTESTS): Add zstdtest, zstdtest_alloc, ctestzstd as
appropriate.
* elf.c (ELFCOMPRESS_ZSTD): Define.
(elf_fetch_bits): Rename from elf_zlib_fetch.  Update uses.
(elf_fetch_bits_backward): New static function.
(ZLIB_HUFFMAN_*): Rename from HUFFMAN_*.  Update uses.
(ZLIB_TABLE_*): Rename from ZDEBUG_TABLE_*.  Update uses.
(ZSTD_TABLE_*): Define.
(struct elf_zstd_fse_entry): Define.
(elf_zstd_read_fse): New static function.
(elf_zstd_build_fse): Likewise.
(lit): Define if BACKTRACE_GENERATE_ZSTD_FSE_TABLES.
(match, offset, next, print_table, main): Likewise.
(elf_zstd_lit_table): New static const array.
(elf_zstd_match_table, elf_zstd_offset_table): Likewise.
(elf_zstd_read_huff): New static function.
(struct elf_zstd_seq_decode): Define.
(elf_zstd_unpack_seq_decode): New static function.
(ZSTD_LIT_*): Define.
(struct elf_zstd_literals): Define.
(elf_zstd_literal_output): New static function.
(ZSTD_LITERAL_LENGTH_BASELINE_OFFSET): Define.
(elf_zstd_literal_length_baseline): New static const array.
(elf_zstd_literal_length_bits): Likewise.
(ZSTD_MATCH_LENGTH_BASELINE_OFFSET): Define.
(elf_zstd_match_length_baseline): New static const array.
(elf_zstd_match_length_bits): Likewise.
(elf_zstd_decompress): New static function.
(ZDEBUG_TABLE_SIZE): New definition.
(elf_uncompress_chdr): Support ELF_COMPRESS_ZSTD.
(backtrace_uncompress_zstd): New function.
(elf_add): Use ZLIB_TABLE_SIZE for zlib-gnu sections.
* internal.h (backtrace_uncompress_zstd): Declare.
* zstdtest.c: New file.
* configure, config.h.in, Makefile.in: Regenerate.

Daily bump.

Fortran: handle zero-sized arrays in ctors with typespec [PR108010]

gcc/fortran/ChangeLog:

PR fortran/108010
* arith.cc (reduce_unary): Handle zero-sized arrays.
(reduce_binary_aa): Likewise.

gcc/testsuite/ChangeLog:

PR fortran/108010
* gfortran.dg/pr108010.f90: New test.

c: Diagnose auto constexpr used with a type

The constraints on auto in C2x disallow use with other storage-class
specifiers unless the type is inferred from an initializer.  That
includes constexpr; add the missing checks for this case (the
combination of auto, constexpr and a type specifier).

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

gcc/c/
* c-decl.cc (declspecs_add_type, declspecs_add_scspec): Check for
auto, constexpr and a type used together.

gcc/testsuite/
* gcc.dg/c2x-constexpr-1.c: Do not use auto, constexpr and a type
together.
* gcc.dg/c2x-constexpr-3.c: Add tests of auto, constexpr and type
used together.

libstdc++: Pass error handler to libbacktrace functions

Also pass threaded=1 to __glibcxx_backtrace_create_state and remove some
of the namespace scope declarations in the header.

Co-authored-by: François Dumont <frs.dumont@gmail.com>
libstdc++-v3/ChangeLog:

* include/debug/formatter.h [_GLIBCXX_DEBUG_BACKTRACE]
(_Error_formatter::_Error_formatter): Pass error handler to
__glibcxx_backtrace_create_state. Pass 1 for threaded argument.
(_Error_formatter::_S_err): Define empty function.
* src/c++11/debug.cc (_Error_formatter::_M_error): Pass error
handler to __glibcxx_backtrace_full.

testsuite: Add test for C90 auto with implicit int

Add a test for the case of auto with implicit int in C90 mode, which
is incompatible with C2x semantics (I missed adding such a test when
implementing C2x auto).

Tested for x86_64-pc-linux-gnu.

* gcc.dg/c90-auto-1.c: New test.

preprocessor: Enable __VA_OPT__ for C2x

C2x supports __VA_OPT__, so adjust libcpp not to pedwarn for uses of
it (or of not passing any variable arguments to a variable-arguments
macro) in standard C2x mode.

I didn't try to duplicate existing tests for the details of the
feature, just verified -pedantic-errors handling is as expected.  And
there's a reasonable argument (bug 98859) that __VA_OPT__ shouldn't be
diagnosed in older standard modes at all (as opposed to not passing
any variable arguments to a variable-arguments macro, for which older
versions of the C standard require a diagnostic as a constraint
violation); that argument applies to C as much as to C++, but I
haven't made any changes in that regard.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

libcpp/
* init.cc (lang_defaults): Enable va_opt for STDC2X.
* lex.cc (maybe_va_opt_error): Adjust diagnostic message for C.
* macro.cc (_cpp_arguments_ok): Update comment.

gcc/testsuite/
* gcc.dg/cpp/c11-vararg-1.c, gcc.dg/cpp/c2x-va-opt-1.c: New tests.

libgcc: xtensa: use built-in configuration

Now that gcc provides __XCHAL_* definitions use them instead of XCHAL_*
definitions from the include/xtensa-config.h. That makes libgcc
dynamically configurable for the target xtensa core.

libgcc/
* config/xtensa/crti.S (xtensa-config.h): Replace #inlcude with
xtensa-config-builtin.h.
* config/xtensa/crtn.S: Likewise.
* config/xtensa/lib1funcs.S: Likewise.
* config/xtensa/lib2funcs.S: Likewise.
* config/xtensa/xtensa-config-builtin.h: New File.

gcc: xtensa: allow dynamic configuration

Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields
of a structure returned from the xtensa_get_config_v<x> function call.
Define that structure and fill it with default parameter values
specified in the include/xtensa-config.h.
Define reusable function xtensa_load_config that tries to load
configuration and return an address of an exported object from it.
Define the function xtensa_get_config_v1 that uses xtensa_load_config
to get structure xtensa_config_v1, either dynamically configured or the
default.

Provide essential XCHAL_* configuration parameters as __XCHAL_* built-in
macros. This way it will be possible to use them in libgcc and libc
without need to patch libgcc or libc source for the specific xtensa core
configuration.

gcc/
* config.gcc (xtensa*-*-*): Add xtensa-dynconfig.o to extra_objs.
* config/xtensa/t-xtensa (TM_H): Add xtensa-dynconfig.h.
(xtensa-dynconfig.o): New rule.
* config/xtensa/xtensa-dynconfig.c: New file.
* config/xtensa/xtensa-protos.h (xtensa_get_config_strings): New
declaration.
* config/xtensa/xtensa.h (xtensa-config.h): Replace #include
with xtensa-dynconfig.h
(XCHAL_HAVE_MUL32_HIGH, XCHAL_HAVE_RELEASE_SYNC)
(XCHAL_HAVE_S32C1I, XCHAL_HAVE_THREADPTR)
(XCHAL_HAVE_FP_POSTINC): Drop definitions.
(TARGET_DIV32): Replace with __XCHAL_HAVE_DIV32.
(TARGET_CPU_CPP_BUILTINS): Add new 'builtin' variable and loop
through string array returned by the xtensa_get_config_strings
function call.

include/
* xtensa-dynconfig.h: New file.

AArch64: Fix assert in aarch64_move_imm [PR108006]

Ensure we only pass SI/DImode which fixes the assert.

gcc/
PR target/108006
* config/aarch64/aarch64.cc (aarch64_expand_sve_const_vector):
Fix call to aarch64_move_imm to use SI/DI.

MAINTAINERS: Add myself as Rust front-end maintainer

Changelog:
* MAINTAINERS: Add Arthur Cohen as Rust front-end maintainer.

configure: When host-shared, pass --with-pic to in-tree lib configs.

If we are building PIC/PIE host executables, and we are building dependent
libs (e.g. GMP) in-tree those libs need to be configured to generate PIC code.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
ChangeLog:

* Makefile.def: Pass host_libs_picflag to host dependent library
configures.
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.ac (host_libs_picflag): New configure variable set to
'--with-pic' when building 'host_shared'.

ipa/105676 - pure attribute suggestion for const function

When a function is declared const (even though it technically
accesses memory), ipa-modref discovering pureness shouldn't end
up suggesting that attribute.  The following thus exempts
'const' functions from ipa_make_function_pure handling.

PR ipa/105676
* ipa-pure-const.cc (ipa_make_function_pure): Skip also
for functions already being const.

* gcc.dg/pr105676.c: New testcase.

i386: Avoid fma_chain for -march=alderlake and sapphirerapids.

For Alderlake there is similar issue like PR 81616, enable
avoid_fma256_chain will also benefit on Intel latest platforms
Alderlake and Sapphire Rapids.

gcc/ChangeLog:

* config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS): Add
m_SAPPHIRERAPIDS, m_ALDERLAKE and m_CORE_ATOM.

PR107920: Fix handling of virtual operands and disable folding for -fnon-call-exceptions.

gcc/ChangeLog:
PR target/107920
* config/aarch64/aarch64-sve-builtins-base.cc: Use
gsi_replace_with_seq_vops to handle virtual operands, and gate
the transform on !flag_non_call_exceptions.
* gimple-fold.cc (gsi_replace_with_seq_vops): Make function non static.
* gimple-fold.h (gsi_replace_with_seq_vops): Declare.

gcc/testsuite/ChangeLog:
PR target/107920
* gcc.target/aarch64/sve/acle/general/pr107920.c: New test.
* g++.target/aarch64/sve/pr107920.C: Likewise.

Fix ICE due to condition mismatch between expander and define_insn.

ice.i:7:1: error: unrecognizable insn:
    7 | }
      | ^
(insn 7 6 8 2 (set (reg:V2SF 84 [ vect__3.8 ])
        (unspec:V2SF [
                (reg:V2SF 86 [ vect__1.7 ])
                (const_int 11 [0xb])
            ] UNSPEC_ROUND)) "ice.i":5:14 -1
     (nil))
during RTL pass: vregs

gcc/ChangeLog:

PR target/107970
* config/i386/mmx.md (btruncv2sf2): Add TARGET_MMX_WITH_SSE to
the condition.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr107970.c: New test.

libgccjit: Fix float vector comparison

Fix float vector comparison and add comparison tests to include float and
vectors.

gcc/testsuite:
PR jit/107770
* jit.dg/harness.h: Add new macro to to perform vector
comparisons
* jit.dg/test-expressions.c: Extend comparison tests to add float
types and vectors

gcc/jit:
PR jit/107770
* jit-playback.cc: Fix vector float comparison
* jit-playback.h: Update comparison function signature
* jit-recording.cc: Update call for "new_comparison" function
* jit-recording.h: Fix vector float comparison

Co-authored-by: Guillaume Gomez <guillaume1.gomez@gmail.com>
Signed-off-by: Guillaume Gomez <guillaume1.gomez@gmail.com>

Daily bump.

analyzer: don't create bindings or binding keys for empty regions [PR107882]

PR analyzer/107882 reports an ICE, due to trying to get a compound svalue
for this binding:

  cluster for: a:
    key:   {bytes 0-3}
    value:  {UNKNOWN()}
    key:   {empty}
    value:  {UNKNOWN()}
    key:   {bytes 4-7}
    value:  {UNKNOWN()}

where there's an binding to the unknown value of zero bits in size
"somewhere" within "a" (perhaps between bits 3 and 4?)

This makes no sense, so this patch adds an assertion that we never
attempt to create a binding key for an empty region, and adds early
rejection of attempts to get or set the values of such regions, fixing
the ICE.

gcc/analyzer/ChangeLog:
PR analyzer/107882
* region-model.cc (region_model::get_store_value): Return an
unknown value for empty regions.
(region_model::set_value): Bail on empty regions.
* region.cc (region::empty_p): New.
* region.h (region::empty_p): New decl.
* state-purge.cc (same_binding_p): Bail if either region is empty.
* store.cc (binding_key::make): Assert that a concrete binding's
bit_size must be > 0.
(binding_cluster::mark_region_as_unknown): Bail on empty regions.
(binding_cluster::get_binding): Likewise.
(binding_cluster::remove_overlapping_bindings): Likewise.
(binding_cluster::on_unknown_fncall): Don't conjure values for
empty regions.
(store::fill_region): Bail on empty regions.
* store.h (class concrete_binding): Update comment to reflect that
the range of bits must be non-empty.
(concrete_binding::concrete_binding): Assert that bit range is
non-empty.

gcc/testsuite/ChangeLog:
PR analyzer/107882
* gcc.dg/analyzer/memcpy-pr107882.c: New test.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

libstdc++: Fix test that fails due to name clash with old glibc [PR107979]

This test was recently modified to check that the library doesn't use
__unused anywhere, because that's a macro in newlib. But it's also a
macro in old versions of glibc, so the test now fails for those targets.
Disable that check for those targets as well as for newlib.

libstdc++-v3/ChangeLog:

PR libstdc++/107979
* testsuite/17_intro/names.cc: Do not check __unused on old
Glibc versions.

libstdc++: Add casts for integer-like difference type [PR107871]

libstdc++-v3/ChangeLog:

PR libstdc++/107871
* include/std/format (_Iter_sink::_M_overflow): Add cast to
size_t.
(_Iter_sink<CharT, contiguous_iterator auto>::_M_make_span): Use
typedef instead of decltype.
* testsuite/std/format/functions/107871.cc: New test.

libstdc++: Make chrono::hh_mm_ss more compact

This uses a single byte for the minutes and seconds members, and places
the bool member next to those single bytes. This means we do not need 40
bytes to store a time that can fit in a single 8-byte integer.

When there is no subsecond precision we can do away with the _M_ss
member altogether. If the subsecond precision is coarse enough, we can
use a smaller representation for _M_ss, e.g. hh_mm_ss<milliseconds> only
needs uint_least32_t for _M_ss, and hh_mm_ss<duration<long, ratio<1,10>>
and hh_mm_ss<duration<int8_t, nano>> only need a single byte. In the
latter case the type can only ever represent up to 255ns anyway, so we
don't need a larger representation type (in such cases, we could even
remove the _M_h, _M_m and _M_s members, but it's a very unlikely
scenario that isn't worth optimizing for).

Except for specializations with a floating-point rep or using higher
precision than nanoseconds, hh_mm_ss should now fit in 16 bytes, or even
12 bytes for x86-32 where alignof(long long) == 4.

libstdc++-v3/ChangeLog:

* include/std/chrono (chrono::hh_mm_ss): Do not use 64-bit
representations for all four duration members. Reorder members.
(hh_mm_ss::hh_mm_ss()): Define as defaulted.
(hh_mm_ss::hh_mm_ss(Duration)): Delegate to a new private
constructor, instead of calling chrono::abs repeatedly.
* testsuite/std/time/hh_mm_ss/1.cc: Check floating-point
representations. Check default constructor. Check sizes.

libstdc++: Add hint to compiler about vector invariants [PR106434]

The PR shows a bogus warning where jump threading generates code for the
undefined case that the insertion point is a value-initialized iterator
but _M_finish and _M_end_of_storage are unequal (so at least one must be
non-null). Using __builtin_unreachable() removes the bogus warning. Also
add an assertion to diagnose undefined misuses of a null iterator here,
so we don't just silently optimize that undefined code to something
unsafe.

libstdc++-v3/ChangeLog:

PR c++/106434
* include/bits/vector.tcc (insert(const_iterator, const T&)):
Add assertion and optimization hint that the iterator for the
insertion point must be non-null.

libstdc++: Add nodiscard attribute to mutex try_lock functions

libstdc++-v3/ChangeLog:

* include/bits/std_mutex.h (mutex): Add nodiscard attribute to
try_lock member function.
* include/bits/unique_lock.h (unique_lock): Likewise for
try_lock, try_lock_until, try_lock_for member functions, and
owns_lock and mutex member functions.
* include/std/mutex (recursive_mutex): Likewise for try_lock
member function.
(timed_mutex, recursive_timed_mutex, try_lock): Likewise for
try_lock, try_lock_until, try_lock_for member functions.
(try_lock): Likewise for non-member function.
* include/std/shared_mutex (shared_mutex): Likewise for try_lock
and try_lock_shared member functions.
(shared_timed_mutex): Likewise for try_lock, try_lock_for,
try_lock_shared, try_lock_shared_for, try_lock_until, and
try_lock_shared_until member functions.
(shared_lock): Likewise for try_lock, try_lock, try_lock_for,
try_lock_until, owns_lock, and mutex member functions.
* testsuite/30_threads/recursive_timed_mutex/try_lock_until/clock_neg.cc:
Cast discarded value expression to void.
* testsuite/30_threads/shared_lock/locking/3.cc: Likewise.
* testsuite/30_threads/shared_lock/locking/4.cc: Likewise.
* testsuite/30_threads/shared_lock/locking/clock_neg.cc:
Likewise.
* testsuite/30_threads/shared_timed_mutex/try_lock_until/clock_neg.cc:
Likewise.
* testsuite/30_threads/timed_mutex/try_lock_until/clock_neg.cc:
Likewise.
* testsuite/30_threads/try_lock/4.cc: Likewise.
* testsuite/30_threads/unique_lock/cons/60497.cc: Likewise.
* testsuite/30_threads/unique_lock/locking/3.cc: Likewise.
* testsuite/30_threads/unique_lock/locking/clock_neg.cc:
Likewise.

libstdc++: The Trouble with Tribbles

Fix digit grouping for integers formatted with "{:#Lx}" which were
including the "0x" prefix in the grouped digits. This resulted in output
like "0,xff,fff" instead of "0xff,fff".

Also change std:::basic_format_parse_context to not throw for an arg-id
that is larger than the actual number of format arguments. I clarified
with Victor Zverovich that this is the intended behaviour for the
run-time format-string checks. An out-of-range arg-id should be
diagnosed at compile-time (as clarified by LWG 3825) but not run-time.
The formatting function will still throw at run-time when args.arg(id)
returns an empty basic_format_arg.

libstdc++-v3/ChangeLog:

* include/std/format (basic_format_parse_context::next_arg_id):
Only check arg-id is in range during constant evaluation.
* testsuite/std/format/functions/format.cc: Check "{:#Lx}".
* testsuite/std/format/parse_ctx.cc: Adjust expected results for
format-strings using an out-of-range arg-id.

AArch64: Cleanup move immediate code

Simplify, refactor and improve various move immediate functions.
Allow 32-bit MOVN/I as a valid 64-bit immediate which removes special
cases in aarch64_internal_mov_immediate.  Add new constraint so the movdi
pattern only needs a single alternative for move immediate.

gcc/
* config/aarch64/aarch64.cc (aarch64_bitmask_imm): Use unsigned type.
(aarch64_is_mov_xn_imm): New function.
(aarch64_move_imm): Refactor, assert mode is SImode or DImode.
(aarch64_internal_mov_immediate): Assert mode is SImode or DImode.
Simplify special cases.
(aarch64_uimm12_shift): Simplify code.
(aarch64_clamp_to_uimm12_shift): Likewise.
(aarch64_movw_imm): Rename to aarch64_is_movz.
(aarch64_float_const_rtx_p): Pass either SImode or DImode to
aarch64_internal_mov_immediate.
(aarch64_rtx_costs): Likewise.
* config/aarch64/aarch64.md (movdi_aarch64): Merge 'N' and 'M'
constraints into single 'O'.
(mov<mode>_aarch64): Likewise.
* config/aarch64/aarch64-protos.h (aarch64_move_imm): Use unsigned.
(aarch64_bitmask_imm): Likewise.
(aarch64_uimm12_shift): Likewise.
(aarch64_is_mov_xn_imm): New prototype.
* config/aarch64/constraints.md: Add 'O' for 32/64-bit immediates,
limit 'N' to 64-bit only moves.

Update -Warray-bounds with -fstrict-flex-arrays.

     A. add the following to clarify the relationship between -Warray-bounds
        and the LEVEL of -fstrict-flex-array:

     By default, the trailing array of a structure will be treated as a
     flexible array member by '-Warray-bounds' or '-Warray-bounds=N' if
     it is declared as either a flexible array member per C99 standard
     onwards ('[]'), a GCC zero-length array extension ('[0]'), or an
     one-element array ('[1]').  As a result, out of bounds subscripts
     or offsets into zero-length arrays or one-element arrays are not
     warned by default.

     You can add the option '-fstrict-flex-arrays' or
     '-fstrict-flex-arrays=LEVEL' to control how this option treat
     trailing array of a structure as a flexible array member.

     when LEVEL<=1, no change to the default behavior.

     when LEVEL=2, additional warnings will be issued for out of bounds
     subscripts or offsets into one-element arrays;

     when LEVEL=3, in addition to LEVEL=2, additional warnings will be
     issued for out of bounds subscripts or offsets into zero-length
     arrays.

     B. change -Warray-bounds=2 to exclude its control on how to treat
        trailing arrays as flexible array members:

     '-Warray-bounds=2'
          This warning level also warns about the intermediate results
          of pointer arithmetic that may yield out of bounds values.
          This warning level may give a larger number of false positives
          and is deactivated by default.

gcc/ChangeLog:

* attribs.cc (strict_flex_array_level_of): New function.
* attribs.h (strict_flex_array_level_of): Prototype for new function.
* doc/invoke.texi: Update -Warray-bounds by specifying the impact from
-fstrict-flex-arrays. Also update -Warray-bounds=2 by eliminating its
impact on treating trailing arrays as flexible array members.
* gimple-array-bounds.cc (get_up_bounds_for_array_ref): New function.
(check_out_of_bounds_and_warn): New function.
(array_bounds_checker::check_array_ref): Update with call to the above
new functions.
* tree.cc (array_ref_flexible_size_p): Add one new argument.
(component_ref_sam_type): New function.
(component_ref_size): Control with level of strict-flex-array.
* tree.h (array_ref_flexible_size_p): Update prototype.
(enum struct special_array_member): Add two new enum values.
(component_ref_sam_type): New prototype.

gcc/c/ChangeLog:

* c-decl.cc (is_flexible_array_member_p): Call new function
strict_flex_array_level_of.

gcc/testsuite/ChangeLog:

* gcc.dg/Warray-bounds-11.c: Update warnings for -Warray-bounds=2.
* gcc.dg/Warray-bounds-flex-arrays-1.c: New test.
* gcc.dg/Warray-bounds-flex-arrays-2.c: New test.
* gcc.dg/Warray-bounds-flex-arrays-3.c: New test.
* gcc.dg/Warray-bounds-flex-arrays-4.c: New test.
* gcc.dg/Warray-bounds-flex-arrays-5.c: New test.
* gcc.dg/Warray-bounds-flex-arrays-6.c: New test.

analyzer: use __attribute__((nonnull)) at top level of analysis [PR106325]

PR analyzer/106325 reports false postives from
-Wanalyzer-null-dereference on code like this:

__attribute__((nonnull))
void foo_a (Foo *p)
{
  foo_b (p);

  switch (p->type)
    {
      /* ... */
    }
}

where foo_b (p) has a:

  g_return_if_fail (p);

that expands to:

  if (!p)
    {
      return;
    }

The analyzer "sees" the comparison against NULL in foo_b, and splits the
analysis into the NULL and not-NULL cases; later, back in foo_a,  at
  switch (p->type)
it complains that p is NULL.

Previously we were only using __attribute__((nonnull)) as something to
complain about when it was violated; we weren't using it as a source of
knowledge.

This patch fixes things by making the analyzer respect
__attribute__((nonnull)) at the top-level of the analysis: any such
params are now assumed to be non-NULL, so that the analyzer assumes the
g_return_if_fail inside foo_b doesn't fail when called from foo_a

Doing so fixes the false positives.

gcc/analyzer/ChangeLog:
PR analyzer/106325
* region-model-manager.cc
(region_model_manager::get_or_create_null_ptr): New.
* region-model-manager.h
(region_model_manager::get_or_create_null_ptr): New decl.
* region-model.cc (region_model::on_top_level_param): Add
"nonnull" param and make use of it.
(region_model::push_frame): When handling a top-level entrypoint
to the analysis, determine which params __attribute__((nonnull))
applies to, and pass to on_top_level_param.
* region-model.h (region_model::on_top_level_param): Add "nonnull"
param.

gcc/testsuite/ChangeLog:
PR analyzer/106325
* gcc.dg/analyzer/attr-nonnull-pr106325.c: New test.
* gcc.dg/analyzer/attribute-nonnull.c (test_6): New.
(test_7): New.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

contrib: doxygen: add gcc/analyzer subdirectory to INPUT

contrib/ChangeLog:
* gcc.doxy (INPUT): Add gcc/analyzer subdirectory.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

analyzer: update internal docs

gcc/ChangeLog:
* doc/analyzer.texi: Drop out-of-date ideas for other checkers.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

analyzer: split out more stuff from region-model-impl-calls.cc

gcc/ChangeLog:
* Makefile.in (ANALYZER_OBJS): Add analyzer/call-details.o,
analyzer/kf-analyzer.o, and kf-lang-cp.o.

gcc/analyzer/ChangeLog:
* analyzer.h (register_known_analyzer_functions): New decl.
(register_known_functions_lang_cp): New decl.
* call-details.cc: New file, split out from
region-model-impl-calls.cc.
* call-details.h: New file, split out from region-model.h.
* call-info.cc: Include "analyzer/call-details.h".
* call-summary.h: Likewise.
* kf-analyzer.cc: New file, split out from
region-model-impl-calls.cc.
* kf-lang-cp.cc: Likewise.
* known-function-manager.cc: Include "analyzer/call-details.h".
* region-model-impl-calls.cc: Move definitions of call_details's
member functions to call-details.cc.  Move class kf_analyzer_* to
kf-analyzer.cc.  Move kf_operator_new and kf_operator_delete to
kf-lang-cp.cc.  Refresh #includes accordingly.
(register_known_functions): Replace registration of __analyzer_*
functions with a call to register_known_analyzer_functions.
Replace registration of C++ support functions with a call to
register_known_functions_lang_cp.
* region-model.h (class call_details): Move to new call-details.h.
* sm-fd.cc: Include "analyzer/call-details.h".
* sm-file.cc: Likewise.
* sm-malloc.cc: Likewise.
* varargs.cc: Likewise.

gcc/testsuite/ChangeLog:
* gcc.dg/plugin/analyzer_kernel_plugin.c: Include
"analyzer/call-details.h".
* gcc.dg/plugin/analyzer_known_fns_plugin.c: Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

OpenMP: omp_get_max_teams, omp_set_num_teams, and omp_{gs}et_teams_thread_limit on offload devices

This patch adds support for omp_get_max_teams, omp_set_num_teams, and
omp_{gs}et_teams_thread_limit on offload devices. That includes the usage of
device-specific ICV values (specified as environment variables or changed on a
device). In order to reuse device-specific ICV values, a copy back mechanism is
implemented that copies ICV values back from device to the host.

Additionally, a limitation of the number of teams on gcn offload devices is
implemented.  The number of teams is limited by twice the number of compute
units (one team is executed on one compute unit).  This avoids queueing
unnessecary many teams and a corresponding allocation of large amounts of
memory.  Without that limitation the memory allocation for a large number of
user-specified teams can result in an "memory access fault".
A limitation of the number of teams is already also implemented for nvptx
devices (see nvptx_adjust_launch_bounds in libgomp/plugin/plugin-nvptx.c).

gcc/ChangeLog:

* gimplify.cc (optimize_target_teams): Set initial num_teams_upper
to "-2" instead of "1" for non-existing num_teams clause in order to
disambiguate from the case of an existing num_teams clause with value 1.

libgomp/ChangeLog:

* config/gcn/icv-device.c (omp_get_teams_thread_limit): Added to
allow processing of device-specific values.
(omp_set_teams_thread_limit): Likewise.
(ialias): Likewise.
* config/nvptx/icv-device.c (omp_get_teams_thread_limit): Likewise.
(omp_set_teams_thread_limit): Likewise.
(ialias): Likewise.
* icv-device.c (omp_get_teams_thread_limit): Likewise.
(ialias): Likewise.
(omp_set_teams_thread_limit): Likewise.
* icv.c (omp_set_teams_thread_limit): Removed.
(omp_get_teams_thread_limit): Likewise.
(ialias): Likewise.
* libgomp.texi: Updated documentation for nvptx and gcn corresponding
to the limitation of the number of teams.
* plugin/plugin-gcn.c (limit_teams): New helper function that limits
the number of teams by twice the number of compute units.
(parse_target_attributes): Limit the number of teams on gcn offload
devices.
* target.c (get_gomp_offload_icvs): Added teams_thread_limit_var
handling.
(gomp_load_image_to_device): Added a size check for the ICVs struct
variable.
(gomp_copy_back_icvs): New function that is used in GOMP_target_ext to
copy back the ICV values from device to host.
(GOMP_target_ext): Update the number of teams and threads in the kernel
args also considering device-specific values.
* testsuite/libgomp.c-c++-common/icv-4.c: Fixed an error in the reading
of OMP_TEAMS_THREAD_LIMIT from the environment.
* testsuite/libgomp.c-c++-common/icv-5.c: Extended.
* testsuite/libgomp.c-c++-common/icv-6.c: Extended.
* testsuite/libgomp.c-c++-common/icv-7.c: Extended.
* testsuite/libgomp.c-c++-common/icv-9.c: New test.
* testsuite/libgomp.fortran/icv-5.f90: New test.
* testsuite/libgomp.fortran/icv-6.f90: New test.

gcc/testsuite/ChangeLog:

* c-c++-common/gomp/target-teams-1.c: Adapt expected values for
num_teams from "1" to "-2" in cases without num_teams clause.
* g++.dg/gomp/target-teams-1.C: Likewise.
* gfortran.dg/gomp/defaultmap-4.f90: Likewise.
* gfortran.dg/gomp/defaultmap-5.f90: Likewise.
* gfortran.dg/gomp/defaultmap-6.f90: Likewise.

ada: Allow No_Caching on volatile types

SPARK RM now allow the property No_Caching on volatile types, to
indicate that they should be considered volatile for compilation, but
not by GNATprove's analysis.

gcc/ada/

* contracts.adb (Add_Contract_Item): Allow No_Caching on types.
(Check_Type_Or_Object_External_Properties): Check No_Caching.
Check that non-effectively volatile types does not contain an
effectively volatile component (instead of just a volatile
component).
(Analyze_Object_Contract): Remove shared checking of No_Caching.
* sem_prag.adb (Analyze_External_Property_In_Decl_Part): Adapt checking
of No_Caching for types.
(Analyze_Pragma): Allow No_Caching on types.
* sem_util.adb (Has_Effectively_Volatile_Component): New query function.
(Is_Effectively_Volatile): Type with Volatile and No_Caching is not
effectively volatile.
(No_Caching_Enabled): Remove assertion to apply to all entities.
* sem_util.ads: Same.

ada: Spurious error on nested call using the prefix notation

gcc/ada/

* exp_ch6.adb
(Build_Static_Check_Helper_Call): Perform implicit type conversion
to ensure matching types and avoid reporting spurious errors.

ada: Suppress warning for specific constant valid condition

Like in Exp_Ch4, we do not want to give warnings in Sem_Warn on a membership
test with a mark for a subtype that is predicated.

gcc/ada/

* sem_warn.adb (Warn_On_Constant_Valid_Condition): Bail out for a
membership test with a mark for a subtype that is predicated.

ada: Fix spurious error in checking of SPARK elaboration

The problem is that the computation of early call regions skips freeze nodes
but scenarios involving procedures declared as actions of these freeze nodes
are taken into account.  As a consequence if a subprogram body, typically of
an expression function, is placed just after a freeze node, its early call
region depends on whether the construct just before the freeze node can be
preelaborated or not; in other words, the legality of calls made from the
actions of this freeze node to the subprogram depends on what happens ahead
of the freeze node, which may be totally unrelated to the situation.

This change disables the ABE diagnostics in this case, as is done in a few
other similar cases leading to bogus errors too.

gcc/ada/

* sem_elab.adb (Processing_In_State): Add Within_Freezing_Actions
component.
(Process_Conditional_ABE_Call): Compute its value.
(Process_Conditional_ABE_Call_SPARK): For a call and a target in
the main unit, do not emit any ABE diagnostics if the call occurs
in a freezing actions context.

ada: Elide the copy in extended returns for nonlimited by-reference types

This implements elision of the copy operation for extended return statements
in the case of nonlimited by-reference types (the copy operation is already
elided for limited types by the front-end and nonlimited non-by-reference
types by the code generator), which comprise controlled and tagged types.

The implementation partly reuses the machinery implemented for limited types
(the build-in-place machinery) to allocate the return object directly on the
primary or the secondary stack, depending on whether the result type of the
function is constrained or not.

This requires further special-casing for the allocators generated by this
machinery as well as an adjustment to the implementation of a specific case
of string concatenation.

gcc/ada/

* einfo.ads (Actual_Subtype): Document additional usage.
* exp_aggr.adb (Expand_Array_Aggregate): Replace test on
Is_Build_In_Place_Return_Object with Is_Special_Return_Object.
* exp_ch3.adb (Expand_N_Object_Declaration): Factor out parts of the
processing done for build-in-place return objects and reuse them to
implement a similar processing for specific return objects.
* exp_ch4.adb (Expand_Allocator_Expression): Do not generate a tag
assignment or an adjustment if the allocator was made for a special
return object.
(Expand_Concatenate): If the result is allocated on the secondary
stack, use an unconstrained allocation.
* exp_ch6.ads (Apply_CW_Accessibility_Check): New declaration.
(Is_By_Reference_Return_Object): Likewise.
(Is_Secondary_Stack_Return_Object): Likewise.
(Is_Special_Return_Object): Likewise.
* exp_ch6.adb (Expand_Ctrl_Function_Call): Do not bail out for the
expression in the declaration of a special return object.
(Expand_N_Extended_Return_Statement): Add missing guard and move
the class-wide accessibility check to Expand_N_Object_Declaration.
(Expand_Simple_Function_Return): Delete obsolete commentary.
Skip the special processing for types that require finalization or
are returned on the secondary stack if the return originally comes
from an extended return statement.  Add missing Constant_Present.
(Is_By_Reference_Return_Object): New predicate.
(Is_Secondary_Stack_Return_Object): Likewise.
(Is_Special_Return_Object): Likewise.
* exp_util.adb (Is_Related_To_Func_Return): Also return true if the
parent of the expression is the renaming declaration generated for
the expansion of a return object.
* gen_il-fields.ads (Opt_Field_Enum): Replace Alloc_For_BIP_Return
with For_Special_Return_Object.
* gen_il-gen-gen_nodes.adb (N_Allocator): Likewise.
* gen_il-internals.adb (Image): Remove Alloc_For_BIP_Return.
* sem_ch3.adb (Check_Return_Subtype_Indication): New procedure
moved from sem_ch6.adb.
(Analyze_Object_Declaration): Call it on a return object.
* sem_ch4.adb: Add with and use clauses for Rtsfind.
(Analyze_Allocator): Test For_Special_Return_Object to skip checks
for allocators made for special return objects.
Do not report restriction violations for the return stack pool.
* sem_ch5.adb (Analyze_Assignment.Set_Assignment_Type): Return the
Actual_Subtype for return objects that live on the secondary stack.
* sem_ch6.adb (Check_Return_Subtype_Indication): Move procedure to
sem_ch3.adb.
(Analyze_Function_Return): Do not call above procedure.
* sem_res.adb (Resolve_Allocator): Replace Alloc_For_BIP_Return
with For_Special_Return_Object.
* sinfo.ads: Likewise.
* treepr.adb (Image): Remove Alloc_For_BIP_Return.
* gcc-interface/trans.cc (gnat_to_gnu): Do not convert to the result
type in the unconstrained array type case if the parent is a simple
return statement.

ada: Small adjustment to special resolution of membership test

It's needed because, in GNAT, universal_integer does not cover all the
values of all the supported integer types.

gcc/ada/

* sem_res.adb (Resolve_Membership_Op): Adjust latest change.

ada: Use larger type for membership test of universal value

When a membership test is applied to a nonstatic expression of a universal
type, for example an attribute whose type is universal_integer and whose
prefix is not static, the operation is performed using the tested type that
is determined by the choice list.  In particular, a check that the value of
the expression lies in the range of the tested type may be generated before
the test is actually performed.

This goes against the spirit of membership tests, which are typically used
to guard a specific operation and ought not to fail a check in doing so.

Therefore the resolution of the operands of membership tests is changed in
this case to use the universal type instead of the tested type. The final
computation of the type used to actually perform the test is left to the
expander, which already has the appropriate circuitry.

This nevertheless requires fixing an irregularity in the expansion of the
subtype_mark form of membership tests, which was dependent on the presence
of predicates for the subtype; the confusing name of a routine used by this
expansion is also changed in the process.

gcc/ada/

* exp_ch4.adb (Expand_N_In) <Substitute_Valid_Check>: Rename to...
<Substitute_Valid_Test>: ...this.
Use Is_Entity_Name to test for the presence of entity references.
Do not warn or substitute a valid test for a test with a mark for
a subtype that is predicated.
Apply the same transformation for a test with a mark for a subtype
that is predicated as for a subtype that is not.
Remove useless return statement.
* sem_res.adb (Resolve_Membership_Op): Perform a special resolution
if the left operand is of a universal numeric type.

ada: Accessibility code reorganization and bug fixes

This patch performs a large reorganization of accessibility related sources,
and also corrects some latent issues with accessibility checks - namely the
calculation of accessibility levels for expanded iterators and type
conversions.

gcc/ada/
* accessibility.adb, accessibility.ads
(Accessibility_Message): Moved from sem_attr.
(Apply_Accessibility_Check): Moved from checks.
(Apply_Accessibility_Check_For_Allocator): Moved from exp_ch4 and
renamed
(Check_Return_Construct_Accessibility): Moved from sem_ch6.
(Innermost_Master_Scope_Depth): Moved from sem_util. Add condition
to detect expanded iterators.
(Prefix_With_Safe_Accessibility_Level): Moved from sem_attr.
(Static_Accessibility_Level): Moved from sem_util.
(Has_Unconstrained_Access_Discriminants): Likewise.
(Has_Anonymous_Access_Discriminant): Likewise.
(Is_Anonymous_Access_Actual): Likewise.
(Is_Special_Aliased_Formal_Access): Likewise.
(Needs_Result_Accessibility_Level): Likewise.
(Subprogram_Access_Level): Likewise.
(Type_Access_Level): Likewise.
(Deepest_Type_Access_Level): Likewise.
(Effective_Extra_Accessibility): Likewise.
(Get_Dynamic_Accessibility): Likewise.
(Has_Access_Values): Likewise.
(Accessibility_Level): Likewise.
* exp_attr.adb (Access_Cases): Obtain the proper enclosing object
which applies to a given 'Access by looking through type
conversions.
* exp_ch4.adb (Apply_Accessibility_Check): Moved to accessibility.
* exp_ch5.adb: Likewise.
* exp_ch6.adb: Likewise.
* exp_ch9.adb: Likewise.
* exp_disp.adb: Likewise.
* gen_il-fields.ads: Add new flag Comes_From_Iterator.
* gen_il-gen-gen_nodes.adb: Add new flag Comes_From_Iterator for
N_Object_Renaming_Declaration.
* sem_ch5.adb (Analyze_Iterator_Specification): Mark object
renamings resulting from iterator expansion with the new flag
Comes_From_Iterator.
* sem_aggr.adb (Resolve_Container_Aggregate): Refine test.
* sem_ch13.adb: Add dependence on the accessibility package.
* sem_ch3.adb: Likewise.
* sem_ch4.adb: Likewise.
* sem_ch9.adb: Likewise.
* sem_res.adb: Likewise.
* sem_warn.adb: Likewise.
* exp_ch3.adb: Likewise.
* sem_attr.adb (Accessibility_Message): Moved to accessibility.
(Prefix_With_Safe_Accessibility_Level): Likewise.
* checks.adb, checks.ads (Apply_Accessibility_Check): Likewise.
* sem_ch6.adb (Check_Return_Construct_Accessibility): Likewise.
* sem_util.adb, sem_util.ads
(Accessibility_Level): Likewise.
(Deepest_Type_Access_Level): Likewise.
(Effective_Extra_Accessibility): Likewise.
(Get_Dynamic_Accessibility): Likewise.
(Has_Access_Values): Likewise.
(Has_Anonymous_Access_Discriminant): Likewise.
(Static_Accessibility_Level): Likewise.
(Has_Unconstrained_Access_Discriminants): Likewise.
(Is_Anonymous_Access_Actual): Likewise.
(Is_Special_Aliased_Formal_Access): Likewise.
(Needs_Result_Accessibility_Level): Likewise.
(Subprogram_Access_Level): Likewise.
(Type_Access_Level): Likewise.
* sinfo.ads: Document new flag Comes_From_Iterator.
* gcc-interface/Make-lang.in: Add entry for new Accessibility package.

ada: Add Codepeer Exemption + simplify TO_C code.

This patch simplify the TO_C code to have a single branch for
raising exception. Furthermore, adding pragma annotate for codepeer
to ignore uninitialized value since this is caused because we have
input check before the initialization.

gcc/ada/

* libgnat/i-c.adb (To_C): Simplify code for having a single
exception raise. Add pragma annotate about uninitialized value
which happen only on exception raising.

arm: Fix MVE's vcmp vector-scalar patterns [PR107987]

This patch surrounds the scalar operand of the MVE vcmp patterns with a
vec_duplicate to ensure both operands of the comparision operator have the same
(vector) mode.

gcc/ChangeLog:

PR target/107987
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>,
@mve_vcmp<mve_cmp_op>q_n_f<mode>): Apply vec_duplicate to scalar
operand.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/pr107987.c: New test.

i386: Fix up expander conditions on cbranchbf4 and cstorebf4 [PR107969]

With -msoft-float we ICE on __bf16 comparisons, because the
insns we want to use under the hood (cbranchsf4 and cstoresf4)
after performing the fast extensions aren't available.

The following patch copies the conditions from the c*sf4 expanders
to the corresponding c*bf4 expanders.

2022-12-06  Jakub Jelinek  <jakub@redhat.com>

PR target/107969
* config/i386/i386.md (cbranchbf4, cstorebf4): Guard expanders
with the same condition as cbranchsf4 or cstoresf4 expanders.

* gcc.target/i386/pr107969.c: New test.

testsuite: Use -mnofpu for rx-*-* in ieee testsuite [PR107046]

add_options_for_ieee has:
    if { [istarget alpha*-*-*]
         || [istarget sh*-*-*] } {
       return "$flags -mieee"
    }
    if { [istarget rx-*-*] } {
       return "$flags -mnofpu"
    }
but ieee.exp doesn't use add_options_for_ieee, instead it has:
if { [istarget "alpha*-*-*"]
     || [istarget "sh*-*-*"] } then {
  lappend additional_flags "-mieee"
}
among other things (plus -ffloat-store on some arches etc.).

The following patch adds the rx -mnofpu similarly in the hope
of fixing ieee.exp FAILs on rx.

Preapproved in the PR by Jeff, committed to trunk.

2022-12-06  Jakub Jelinek  <jakub@redhat.com>

PR testsuite/107046
* gcc.c-torture/execute/ieee/ieee.exp: For rx-*-* append
-mnofpu.

tree-optimization/104475 - improve access diagnostics

When we end up isolating a nullptr path it happens we diagnose
accesses to offsetted nullptr objects.  The current diagnostics
have no good indication that this happens so the following records
the fact that our heuristic detected a nullptr based access in
the access_ref structure and sets up diagnostics to inform
of that detail.  The diagnostic itself could probably be
improved here but its API is twisted and the necessary object
isn't passed around.

Instead of just

...bits/atomic_base.h:655:34: warning: 'unsigned int __atomic_fetch_and_4(volatile void*, unsigned int, int)' writing 4 bytes into a region of size 0 overflows the destination [-Wstringop-overflow=]

we now add

In member function 'void QFutureInterfaceBase::setThrottled(bool)':
cc1plus: note: destination object is likely at address zero

PR tree-optimization/104475
* pointer-query.h (access_ref::ref_nullptr_p): New flag.
* pointer-query.cc (access_ref::access_ref): Initialize
ref_nullptr_p.
(compute_objsize_r): Set ref_nullptr_p if we treat it that way.
(access_ref::inform_access): If ref was treated as nullptr
based, indicate that.

range-op-float: Improve binary reverse operations

On Mon, Dec 05, 2022 at 02:29:36PM +0100, Aldy Hernandez wrote:
> > So like this for multiplication op1/2_range if it passes bootstrap/regtest?
> > For division I'll need to go to a drawing board...
>
> Sure, looks good to me.

Ulrich just filed PR107972, so in the light of that PR the following patch
attempts to do that differently.

As for testcase, I've tried both attached testcases, but unfortunately it
seems that in neither of the cases we actually figure out that res range
is finite (or for last function non-zero ordered).  So there is further
work needed on that.

2022-12-06  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/107972
* range-op-float.cc (frange_drop_infs): New function.
(float_binary_op_range_finish): Add DIV_OP2 argument.  If DIV_OP2 is
false and lhs is finite or if DIV_OP2 is true and lhs is non-zero and
not NAN, r must be finite too.
(foperator_div::op2_range): Pass true to DIV_OP2 of
float_binary_op_range_finish.

range-op-float: Fix up ICE in lower_bound [PR107975]

According to https://gcc.gnu.org/pipermail/gcc-regression/2022-December/077258.html
my patch caused some ICEs, e.g. the following testcase ICEs.
The problem is that lower_bound and upper_bound methods on a france assert
that the range isn't VR_NAN or VR_UNDEFINED.
All the op1_range/op2_range methods already return early if lhs.undefined_p,
but the other cases (when lhs is VR_NAN or the other opN is VR_NAN or
VR_UNDEFINED) aren't.  float_binary_op_range_finish will DTRT for those
cases already.

2022-12-06  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/107975
* range-op-float.cc (foperator_mult::op1_range,
foperator_div::op1_range, foperator_div::op2_range): Just
return float_binary_op_range_finish result if lhs is known
NAN, or the other operand is known NAN or UNDEFINED.

* gcc.dg/pr107975.c: New test.

libgomp.texi: Fix a OpenMP 5.2 and a TR11 impl-status item

libgomp/
* libgomp.texi (OpenMP 5.2): Add missing 'the'.
(TR11): Add missing '@tab N @tab'.

tree-optimization/104165 - bougs -Warray-bounds, add testcase

The following adds the testcase from the description which was
fixed by r13-2894-gbe4a6551ed37c1.

PR tree-optimization/104165
* g++.dg/warn/Warray-bounds-pr104165-1.C: New testcase.

testsuite, X86, Darwin: Fix bf16 ABI tests for Mach-O/MacOS ABI.

These tests have failed since introduction since they assume that the
assembler output is ELF and that the ABI targeted supports the addressing.

For Darwin, Mach-O and ABI we need to make several changes:
1. Use the __USER_LABEL__PREFIX__
2. Remove the use of ELF-specific constructs (.size, .type etc.)
3. We cannot make direct access to common variables in the ABI, so that we
   must move these to BSS.

These changes are made in darwin-specific asm files.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
gcc/testsuite/ChangeLog:

* gcc.target/x86_64/abi/bf16/abi-bf16.exp: Use separate asm for Darwin.
* gcc.target/x86_64/abi/bf16/m256bf16/abi-bf16-ymm.exp: Likewise.
* gcc.target/x86_64/abi/bf16/m512bf16/abi-bf16-zmm.exp: Likewise.
* gcc.target/x86_64/abi/bf16/args.h: Make xmm_regs, x87_regs extern.
* gcc.target/x86_64/abi/bf16/m256bf16/args.h: Likewise.
* gcc.target/x86_64/abi/bf16/m512bf16/args.h: Likewise.
* gcc.target/x86_64/abi/bf16/asm-support-darwin.S: New file.
* gcc.target/x86_64/abi/bf16/m256bf16/asm-support-darwin.S: New file.
* gcc.target/x86_64/abi/bf16/m512bf16/asm-support-darwin.S: New file.

aarch64: Use dup and zip1 for interleaving elements in vector initializer.

gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_expand_vector_init): Use dup
and zip1 for interleaving elements in vector initializer.

gcc/testsuite/ChangeLog:
* gcc.target/aarch64/interleave-init-1.c: New test.

Daily bump.

middle-end/40635 - SSA update losing PHI arg loations

The following fixes an issue where SSA update loses PHI argument
locations when updating PHI nodes it didn't create as part of the
SSA update.  For the case where the reaching def is the same as
the current argument opt to do nothing and for the case where the
PHI argument already has a location keep that (that's an indication
the PHI node wasn't created as part of the update SSA process).

PR middle-end/40635
* tree-into-ssa.cc (rewrite_update_phi_arguments): Only
update the argument when the reaching definition is different
from the current argument.  Keep an existing argument
location.

* gcc.dg/uninit-pr40635.c: New testcase.

tree-optimization/106868 - bogus -Wdangling-pointer diagnostic

The testcase shows we mishandle the case where there's a pass-through
of a pointer through a function like memcpy.  The following adjusts
handling of this copy case to require a taken address and adjust
the PHI case similarly.

PR tree-optimization/106868
* gimple-ssa-warn-access.cc (pass_waccess::gimple_call_return_arg_ref):
Inline into single user ...
(pass_waccess::check_dangling_uses): ... here and adjust the
call and the PHI case to require that ref.aref is the address
of the decl.

* gcc.dg/Wdangling-pointer-pr106868.c: New testcase.

match.pd: Don't fold nan < x etc. for -ftrapping-math [PR106805]

As reported in the PR, the following pr106805.c testcase is miscompiled
with the default -ftrapping-math, because we fold all the comparisons into
constants and don't raise any exceptions.

The match.pd pattern handles just simple comparisons, from those
EQ/NE are quiet and don't raise exceptions on anything but sNaN, while
GT/GE/LT/LE are signaling and do raise exceptions even on qNaN.

fold_relational_const handles this IMHO correctly:
      /* Handle the cases where either operand is a NaN.  */
      if (real_isnan (c0) || real_isnan (c1))
        {
          switch (code)
            {
            case EQ_EXPR:
            case ORDERED_EXPR:
              result = 0;
              break;

            case NE_EXPR:
            case UNORDERED_EXPR:
            case UNLT_EXPR:
            case UNLE_EXPR:
            case UNGT_EXPR:
            case UNGE_EXPR:
            case UNEQ_EXPR:
              result = 1;
              break;

            case LT_EXPR:
            case LE_EXPR:
            case GT_EXPR:
            case GE_EXPR:
            case LTGT_EXPR:
              if (flag_trapping_math)
                return NULL_TREE;
              result = 0;
              break;

            default:
              gcc_unreachable ();
            }

          return constant_boolean_node (result, type);
        }
by folding the signaling comparisons only if -fno-trapping-math.
The following patch does the same in match.pd.

Unfortunately the pr106805.c testcase still fails, but no longer because of
match.pd, but on the trunk because of the still unresolved ranger problems
(same issue as for fold-overflow-1.c etc.) and on 12 branch (and presumably
trunk too) somewhere during expansion the comparisons are also expanded
into constants (which is ok for -fno-trapping-math, but not ok with that).

Though, I think the patch is a small step in the direction, so I'd like
to commit this patch without the gcc.dg/pr106805.c testcase for now.

2022-12-05  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/106805
* match.pd (cmp @0 REAL_CST@1): Don't optimize x cmp NaN
or NaN cmp x to false/true for cmp >/>=/</<= if -ftrapping-math.

* c-c++-common/pr57371-4.c: Revert 2021-09-19 changes.
* c-c++-common/pr57371-5.c: New test.
* gcc.c-torture/execute/ieee/fp-cmp-6.x: Add -fno-trapping-math.
* gcc.c-torture/execute/ieee/fp-cmp-9.c: New test.
* gcc.c-torture/execute/ieee/fp-cmp-9.x: New file.

range-op-float: Fix up multiplication and division reverse operation [PR107879]

While for the normal cases it seems to be correct to implement
reverse multiplication (op1_range/op2_range) through division
with float_binary_op_range_finish, reverse division (op1_range)
through multiplication with float_binary_op_range_finish or
(op2_range) through division with float_binary_op_range_finish,
as e.g. following testcase shows for the corner cases it is
incorrect.
Say on the testcase we are doing reverse multiplication, we
have [-0., 0.] range (no NAN) on lhs and VARYING on op1 (or op2).
We implement that through division, because x from
lhs = x * op2
is
x = lhs / op2
For the division, [-0., 0.] / VARYING is computed (IMHO correctly)
as [-0., 0.] +-NAN, because 0 / anything but 0 or NAN is still
0 and 0 / 0 is NAN and ditto 0 / NAN.  And then we just
float_binary_op_range_finish, which figures out that because lhs
can't be NAN, neither operand can be NAN.  So, the end range is
[-0., 0.].  But that is not correct for the reverse multiplication.
When the result is 0, if op2 can be zero, then x can be anything
(VARYING), to be precise anything but INF (unless result can be NAN),
because anything * 0 is 0 (or NAN for INF).  While if op2 must be
non-zero, then x must be 0.  Of course the sign logic
(signbit(x) = signbit(lhs) ^ signbit(op2)) still holds, so it actually
isn't full VARYING if both lhs and op2 have known sign bits.
And going through other corner cases one by one shows other differences
between what we compute for the corresponding forward operation and
what we should compute for the reverse operations.
The following patch is slightly conservative and includes INF
(in case of result including 0 and not NAN) in the ranges or
0 in the ranges (in case of result including INF and not NAN).
The latter is what happens anyway because we flush denormals to 0,
and the former just not to deal with all the corner cases.
So, the end test is that for reverse multiplication and division
op2_range the cases we need to adjust to VARYING or VARYING positive
or VARYING negative are if lhs and op? ranges both contain 0,
or both contain some infinity, while for division op1_range the
corner case is if lhs range contains 0 and op2 range contains INF or vice
versa.  Otherwise I believe ranges from the corresponding operation
are ok, or could be slightly more conservative (e.g. for
reverse multiplication, if op? range is singleton INF and lhs
range doesn't include any INF, then x's range should be UNDEFINED or
known NAN (depending on if lhs can be NAN), while the division computes
[-0., 0.] +-NAN; or similarly if op? range is only 0 and lhs range
doesn't include 0, division would compute +INF +-NAN, or -INF +-NAN,
or (for lack of multipart franges -INF +INF +-NAN just VARYING +-NAN),
while again it is UNDEFINED or known NAN.

Oh, and I found by code inspection wrong condition for the division's
known NAN result, due to thinko it would trigger not just when
both operands are known to be 0 or both are known to be INF, but
when either both are known to be 0, or at least one is known to be INF.

2022-12-05  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/107879
* range-op-float.cc (foperator_mult::op1_range): If both
lhs and op2 ranges contain zero or both ranges contain
some infinity, set r range to zero_to_inf_range depending on
signbit_known_p.
(foperator_div::op2_range): Similarly for lhs and op1 ranges.
(foperator_div::op1_range): If lhs range contains zero and op2
range contains some infinity or vice versa, set r range to
zero_to_inf_range depending on signbit_known_p.
(foperator_div::rv_fold): Fix up condition for returning known NAN.

tree-optimization/107833 - invariant motion of uninit uses

The following fixes a wrong-code bug caused by loop invariant motion
hoisting an expression using an uninitialized value outside of its
controlling condition causing IVOPTs to use that to rewrite a defined
value.  PR107839 is a similar case involving a bogus uninit diagnostic.

PR tree-optimization/107833
PR tree-optimization/107839
* cfghooks.cc: Include tree.h.
* tree-ssa-loop-im.cc (movement_possibility): Wrap and
make stmts using any ssa_name_maybe_undef_p operand
to preserve execution.
(loop_invariant_motion_in_fun): Call mark_ssa_maybe_undefs
to init maybe-undefined status.
* tree-ssa-loop-ivopts.cc (ssa_name_maybe_undef_p,
ssa_name_set_maybe_undef, ssa_name_any_use_dominates_bb_p,
mark_ssa_maybe_undefs): Move ...
* tree-ssa.cc: ... here.
* tree-ssa.h (ssa_name_any_use_dominates_bb_p,
mark_ssa_maybe_undefs): Declare.
(ssa_name_maybe_undef_p, ssa_name_set_maybe_undef): Define.

* gcc.dg/torture/pr107833.c: New testcase.
* gcc.dg/uninit-pr107839.c: Likewise.

plugins/107964 - install contracts.h

contracts.h is included by cp-tree.h so needs to be installed for
plugins.

PR plugins/107964
gcc/cp/
* Make-lang.in (CP_PLUGIN_HEADERS): Install contracts.h

tree-optimization/107956 - ICE with NULL call LHS

The following adds a missing check for a NULL call LHS in the
vector pattern recognizer.

PR tree-optimization/107956
* tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
Check for NULL LHS on masked loads.

gimple-fold: Refine gimple_fold_partial_load_store_mem_ref [PR107412]

Following Richard's review comments, this patch is to use
untruncated type for the length used for IFN_LEN_{LOAD,STORE}
instead of "unsigned int" for better robustness.  It also
avoid to use to_constant and tree arithmetic for subtraction.

Co-authored-by: Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/107412

gcc/ChangeLog:

* gimple-fold.cc (gimple_fold_partial_load_store_mem_ref): Use
untruncated type for the length, and avoid to_constant and tree
arithmetic for subtraction.

Daily bump.

Fortran: error recovery simplifying UNPACK for insufficient FIELD [PR107922]

gcc/fortran/ChangeLog:

PR fortran/107922
* simplify.cc (gfc_simplify_unpack): Terminate simplification when
array-valued argument FIELD does not provide enough elements.

gcc/testsuite/ChangeLog:

PR fortran/107922
* gfortran.dg/unpack_field_1.f90: New test.

Fortran: fix typo in documentation of intrinsic FLOOR [PR107870]

gcc/fortran/ChangeLog:

PR fortran/107870
* intrinsic.texi: Fix typo in documentation of intrinsic FLOOR.
Describe the optional KIND argument to intrinsics as a scalar
constant expression, in accordance with the current standard.