Fedor Ross [Thu, 14 Apr 2022 16:36:23 +0000 (18:36 +0200)]
ARM: imx: Fix parsing of ROM log event IDs on iMX8M
It seems like the ROM log events for the iMX8M are not fully covered by
AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
ID 0x82 seems to use parameter0 which stops the parsing because the end
of list is detected too early.
This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
parsed.
Fixes:
a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log")
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Tue, 16 May 2023 15:23:30 +0000 (11:23 -0400)]
Merge tag 'efi-2023-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2023-07-rc3
Documentation:
* update the description of signature algorithms
UEFI:
* fix unaligned access to GUID in HII database protocol
* fix launching EFI binaries loaded via semihosting
* fix filling of file path in loaded image protocol for non-block devices
Tom Rini [Tue, 16 May 2023 15:16:42 +0000 (11:16 -0400)]
Merge branch '2023-05-15-assorted-bugfixes'
- Merge in a long-standing fix for some exynos platforms, correct a
Kconfig description, fix some env issues, fix an issue in
devfdt_get_addr_size_index_ptr and look for "panel-timings" not
"panel-timing" per upstream binding.
Tom Rini [Tue, 16 May 2023 13:10:57 +0000 (09:10 -0400)]
Merge tag 'xilinx-for-v2023.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.07-rc3
.mailmap
- Fix Xilinx IDs
ZynqMP:
- Fix R5 split boot mode
- DT fixes - sync with Linux
Xilinx:
- Enable virtio and RNG support
- Enable ADI ethernet phy
SPI/Zynq:
- Fix dummy byte calculation
Manorit Chawdhry [Mon, 15 May 2023 06:52:42 +0000 (12:22 +0530)]
environment: ti: rproc: fix remoteproc environment variables
During refactor this seemed to have been missed.
Fixes:
65dbb128fb45 ("include: environment: ti: Use .env for environment variables")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Johan Jonker [Wed, 10 May 2023 21:48:44 +0000 (23:48 +0200)]
core: fdtaddr: use map_sysmem() as cast for the return (part 2)
For the devfdt_get_addr_size_index_ptr() function use
map_sysmem() function as cast for the return for use in
sandbox.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Raphael Gallais-Pou [Thu, 11 May 2023 14:36:52 +0000 (16:36 +0200)]
drivers: core: ofnode: fix typo in panel timing decode
In case where a single timing resolution is implemented in the
device-tree, the property is named "panel-timing", as specify
in Linux kernel binding file:
Documentation/devicetree/bindings/display/panel/panel-common.yaml
# Display Timings
panel-timing:
description:
Most display panels are restricted to a single resolution and
require specific display timings. The panel-timing subnode expresses those
timings.
$ref: panel-timing.yaml#
display-timings:
description:
Some display panels support several resolutions with different timings.
The display-timings bindings supports specifying several timings and
optionally specifying which is the native mode.
$ref: display-timings.yaml#
Fixes:
0347cc773270 ("drivers: core: ofnode: Add panel timing decode.")
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Christophe Leroy [Thu, 11 May 2023 06:16:49 +0000 (08:16 +0200)]
envtools lack extra settings since commit
86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in
After converting my targets from CFG_EXTRA_ENV_SETTINGS to
CONFIG_EXTRA_ENV_TEXT as suggested by Tom, I discovered that
fw_setenv doesn't set the entire defaut environment anymore.
I tried to fix it with the below patch, but it fails qemu-x86 CI test,
see https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/16326
That's the only CI test that fails AFAICS.
Could you help with a solution ? This needs to be fixed.
Thanks
Christophe
---- >8 ----
From: Christophe Leroy <christophe.leroy@csgroup.eu>
Subject: [RFC PATCH] envtools: Fix default environment
After converting some targets from CFG_EXTRA_ENV_SETTINGS to
CONFIG_EXTRA_ENV_TEXT, default environment embedded in
fw_env tool missed all extra settings.
Commit
86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in
a .env file") restricted the inclusion of the content of that
file to builds without USE_HOSTCC.
But as mentionned in commit
79fc0c5f49 ("tools/env: cross-compile
fw_printenv without setting HOSTCC"), HOSTCC and USE_HOSTCC are
kept for code re-use.
Remove the restricting so that settings included in a .env
file are also added to fw_env tool.
Fixes:
86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in a .env file")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Henrik Grimler [Tue, 9 May 2023 19:05:47 +0000 (21:05 +0200)]
samsung: common: do not reset if cros-ec uclass is missing
Otherwise non-ChromeOS samsung devices, like the odroid boards, are
stuck in a bootloop if CONFIG_CROS_EC is not enabled:
<...>
MMC: SAMSUNG SDHCI: 2, EXYNOS DWMMC: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment
cros-ec communications failure -96
Please reset with Power+Refresh
Cannot init cros-ec device
resetting ...
Issue started after commit
e44d7e73fe0d ("dm: core: Switch
uclass_*_device_err to use uclass_*_device_check").
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Henrik Grimler [Tue, 9 May 2023 19:05:46 +0000 (21:05 +0200)]
Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"
This reverts commit
a034ec06ff1d558bbe11d5ee05edbb4de3ee2215.
Commit
4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when
there are data"") reverted the alternative fix that was added for
Exynos 4 devices, causing an error when trying to boot from an sdcard:
<...>
Loading Environment from MMC... sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
<...>
Re-add the quirk to allow booting from sdcards again.
Signed-off-by: Henrik Grimler <henrik@grimler.se>
John Keeping [Tue, 9 May 2023 11:02:50 +0000 (12:02 +0100)]
video: tweak CONFIG_SPL_VIDEO description
Make it clear that this is the SPL option to avoid potential confusion
when the description for CONFIG_SPL_VIDEO is the same as that for
CONFIG_VIDEO.
Signed-off-by: John Keeping <john@metanate.com>
Tom Rini [Mon, 15 May 2023 12:33:16 +0000 (08:33 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash
- cfi: respect reg address length (Nuno)
Nuno Sá [Thu, 11 May 2023 11:19:50 +0000 (13:19 +0200)]
mtd: cfi: respect reg address length
flash_get_size() will get the flash size from the device itself and go
through all erase regions to read protection status. However, the device
mappable region (eg: devicetree reg property) might be lower than the
device full size which means that the above cycle will result in a data
bus exception. This change fixes it by reading the 'addr_size' during
probe() and also use that as one possible upper limit.
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Algapally Santosh Sagar [Wed, 26 Apr 2023 06:01:04 +0000 (00:01 -0600)]
.mailmap: Map all Xilinx users mail ids to AMD
The mail ids of all the current Xilinx users are to be mapped to AMD
following the merger with AMD. The mailmap file is updated accordingly.
The ids of Marek Behún and Michal Simek are taken as reference.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230426060104.10412-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Algapally Santosh Sagar [Wed, 26 Apr 2023 06:01:03 +0000 (00:01 -0600)]
.mailmap: Sort the mailmap ids in dictionary order
The mailmap ids are not arranged in the dictionary order. So, sort the
mailmap ids in the dictionary order.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230426060104.10412-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Stefan Herbrechtsmeier [Thu, 27 Apr 2023 06:53:54 +0000 (08:53 +0200)]
Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"
This reverts commit
e09784728689de7949d4cdd559a9590e0bfcc702. The
commit wrongly divides the dummy bytes by dummy bus width to calculate
the dummy bytes. The framework already converts the dummy cycles to the
number of bytes and the controller use the SPI flash command to
determine the dummy cycles via the address width.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 20 Apr 2023 08:56:45 +0000 (02:56 -0600)]
arm64: versal: Enable ADIN ethernet phy
Versal VEK280 board has Analog Devices ethernet phy. So, enable
CONFIG_PHY_ADIN config in Versal defconfig.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230420085645.21260-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 20 Apr 2023 08:56:44 +0000 (02:56 -0600)]
arm64: zynqmp: Enable ADIN ethernet phy
Some of the Kria SOM and ZynqMP boards are using Analog Devices ethernet
phy. So, enable CONFIG_PHY_ADIN for all ZynqMP platforms.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230420085645.21260-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Michal Simek [Wed, 12 Apr 2023 14:30:27 +0000 (16:30 +0200)]
arm64: zynqmp: Fix User MTD partition size
The commit
c8630167e0dc ("arm64: zynqmp: Add mtd partition for secure OS
storage area") didn't update User partition size that's why size was beyond
actual device size.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
Ashok Reddy Soma [Wed, 5 Apr 2023 13:06:45 +0000 (15:06 +0200)]
arm64: zynqmp: Fix issue of apps executing from R5 core 1
In current implementation, applications can execute only on R5 core 0.
The boot address for R5 core 1 is not supplied. Pass TCM address for
R5 core 1 based on the argument to fix the issue.
Remove incomplete comment.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
Michal Simek [Tue, 28 Mar 2023 07:21:33 +0000 (09:21 +0200)]
ARM: zynq: Sync Microzed board with Linux kernel
Fix model name, node locations and also add pinctrl description for usb.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
Michal Simek [Tue, 28 Mar 2023 07:17:31 +0000 (09:17 +0200)]
ARM: zynq: Switch from earlyprintk to earlycon
Switch to earlycon which is preffered over earlyprintk.
It is also sync with Linux kernel (zynq-microzed).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
Michal Simek [Thu, 23 Mar 2023 14:52:11 +0000 (15:52 +0100)]
xilinx: Enable virtio mmio transport and devices
Qemu can create virtio mmio transports and passing devices through it
that's why enable virtio by default on all arm64 based SoCs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a2ee18e7e8c1881ce72c5cd13127794a02410696.1679583129.git.michal.simek@amd.com
Neal Frager [Thu, 23 Mar 2023 08:25:06 +0000 (08:25 +0000)]
arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode
The "zynqmp tcminit split" command should halt both cores and not just RPU1
when configuring the TCM memory for split mode.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tom Rini [Sun, 14 May 2023 15:29:45 +0000 (11:29 -0400)]
Merge branch 'master_rzn1/rzn1' of https://source.denx.de/u-boot/custodians/u-boot-sh
- R-Car RZN1 support
Tom Rini [Sun, 14 May 2023 15:27:18 +0000 (11:27 -0400)]
Merge branch '2023-05-13-bootstd-updates-and-improvements'
- Assorted bootstd fixes and cleanups. This should fix problems with
Debian, and make script-based distributions work when BOOTMETH_DISTRO
is enabled now (as BOOTMETH_DISTRO was renamed and then reintroduced).
Simon Glass [Wed, 10 May 2023 22:34:47 +0000 (16:34 -0600)]
bootstd: Create a new BOOTMETH_DISTRO
We cannot be sure what bootmeth a distro will need to use. Add a new
BOOTMETH_DISTRO option which collects these together. Select this from
BOOTSTD_DEFAULTS so that it is clear what is needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make BOOTMETH_EFILOADER depend on EFI_LOADER, select if EFI_LOADER]
Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 10 May 2023 22:34:46 +0000 (16:34 -0600)]
bootstd: Rename distro and syslinux to extlinux
We use the terms 'distro' to mean extlinux but they are not really the
same. 'Distro' could refer to any method of booting a distribution,
whereas extlinux is a particular method.
Also we sometimes use syslinux, but it is better to use the same term in
all cases.
Rename distro to syslinux and also update bootstd uses of syslinux to use
extlinux instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 10 May 2023 22:34:26 +0000 (16:34 -0600)]
bootstd: Tidy up reporting of errors
In a few cases the error handling is not quite right. Make sure we
return the actual error in distro_efi_read_bootflow_file() rather than
-EINVAL. Return -IO when a file cannot be read. Also show the error name
if available.
This does not change operation, but does make it easier to diagnose
problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 May 2023 14:27:09 +0000 (08:27 -0600)]
bootstd: Correct default boot command
The patch to relax flag requirements was not accepted[1], so we still have
to have separate bootcommands depending on CMD_BOOTFLOW_FULL.
The previous attempt at this did not work, since it used the wrong name
for the options.
Fix this and change the message to mention BOOTSTD_FULL since this affects
not just the flags, but all functionality, so is more likely what the user
wants.
Drop the useless condition on CMD_BOOTFLOW_FULL while we are here.
[1] https://patchwork.ozlabs.org/project/uboot/patch/
20230329071655.1959513-2-sjg@chromium.org/
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes:
a91492b6e9c ("bootstd: Provide a default command")
Simon Glass [Sat, 6 May 2023 02:03:05 +0000 (20:03 -0600)]
bootstd: Require HUSH_PARSER for script booting
Armbian uses a script which needs the HUSH parser. It is likely that
other distros will do the same. Enable it by default, just in case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Simon Glass [Sat, 6 May 2023 02:03:04 +0000 (20:03 -0600)]
bootstd: usb: Avoid initing USB twice
This causes crashes on some boards, e.g. rockpro64. In any case, we
should not do it.
Check the usb_started flag to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sat, 6 May 2023 02:03:03 +0000 (20:03 -0600)]
usb: Tidy up the usb_start flag
This should be declared in a header file so that type-checking works
correctly.
Add a single declaration to usb.h and remove the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Simon Glass [Fri, 28 Apr 2023 19:18:09 +0000 (13:18 -0600)]
bootstd: Work around missing partition 1
If there is no partition numbered 1, we decide that there are no
partitions at all. That may not be correct, since at least one Debian
installed has just a single partition numbered 2.
Continue searching up to partition 3, just in case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 13 May 2023 08:36:21 +0000 (10:36 +0200)]
efi_loader: fix efi_dp_from_file()
* When called from efi_dp_from_name() we miss to append the filename
for non-block devices.
* expand_media_path() could be simplified by using efi_dp_from_file to
prepend the device path of the boot device.
This can be avoided by passing a device path to efi_dp_from_file() instead
of a block device descriptor and a partition number.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 13 May 2023 08:30:43 +0000 (10:30 +0200)]
efi_loader: simplify efi_dp_from_name()
Don't do the same check and assignment in multiple places.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 13 May 2023 08:22:21 +0000 (10:22 +0200)]
efi_loader: error code efi_dp_from_name()
Use EFI_OUT_OF_RESOURCES if the device path cannot be constructed.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 13 May 2023 08:18:24 +0000 (10:18 +0200)]
efi_loader: clean up efi_dp_from_file
* Improve variable name usage: Use pos instead of buf to indicate the
current position in a buffer.
* Avoid double assignment in a single code line.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 13 May 2023 08:00:55 +0000 (10:00 +0200)]
efi_loader: duplicate code in efi_dp_from_name
efi_dp_from_name() has duplicate code to replace slash by backslash.
path_to_uefi() called by efi_dp_from_file() already does this.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 13 May 2023 07:55:26 +0000 (09:55 +0200)]
efi_loader: avoid #ifdef in efi_dp_from_name()
According to our coding style guide #ifdef should be avoided.
Use IS_ENABLED() instead.
Sort string comparisons alphabetically.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Fri, 12 May 2023 18:18:10 +0000 (20:18 +0200)]
efi_loader: support booting semihosting file
Executing an EFI binary fails for files loaded via semihosting.
Construct a dummy device path for EFI binaries loaded via semihosting.
A future complete solution may include the creation of a handle with a
simple file system protocol.
Reported-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Fri, 12 May 2023 19:23:15 +0000 (21:23 +0200)]
efi_loader: print file path w/o boot device
Helloworld.efi should print the file path even if the boot device is
not set.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Ilias Apalodimas [Thu, 11 May 2023 16:40:35 +0000 (19:40 +0300)]
efi_loader: Fix warnings for unaligned accesses
Tom reports that when building with clang we see this warning:
field guid within 'struct efi_hii_keyboard_layout' is less aligned than 'efi_guid_t' and is usually due to 'struct efi_hii_keyboard_layout' being packed, which can lead to unaligned accesses [-Wunaligned-access]
This happens because 'struct efi_hii_keyboard_layout' is defined as
packed and thus has 1-byte alignment but efi_guid_t is a type that
requires greater alignment than that.
However the EFI spec describes the EFI_GUID as
"128-bit buffer containing a unique identifier value.
Unless otherwise specified"
So convert the efi_guid_t -> u8 b[16] here and skip the alignment
requirements. Since the struct is packed to begin with, it makes no
difference on the final memory layout.
Suggested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 7 May 2023 06:39:34 +0000 (08:39 +0200)]
fwu: fix config FWU_MULTI_BANK_UPDATE
Symbol CONFIG_EFI_SETUP_EARLY does not exist anymore.
CONFIG_FWU_MULTI_BANK_UPDATE without CONFIG_FWU_MDATA results in
lib/fwu_updates/fwu.c:49: undefined reference to `fwu_get_mdata'
Fixes:
86794052418b ("FWU: Add support for the FWU Multi Bank Update feature")
Fixes:
023d9c93932c ("efi_loader: remove CONFIG_EFI_SETUP_EARLY")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Baruch Siach [Tue, 2 May 2023 10:21:46 +0000 (13:21 +0300)]
doc: devicetree: fix u-boot.bin filename typo
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Baruch Siach [Tue, 2 May 2023 04:47:31 +0000 (07:47 +0300)]
doc: signature: trim the future work list
Since U-Boot supports more RSA/SHA variants, as well as ECDSA, remove
these items from the TODO list.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Baruch Siach [Tue, 2 May 2023 04:47:30 +0000 (07:47 +0300)]
doc: signature: describe how to enable ECDSA
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Baruch Siach [Tue, 2 May 2023 04:47:29 +0000 (07:47 +0300)]
doc: signature: update algorithm addition description
U-Boot now uses the U_BOOT_CRYPTO_ALGO() macro.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Baruch Siach [Tue, 2 May 2023 04:47:28 +0000 (07:47 +0300)]
doc: signature: update algorithms support description
U-Boot supports more hash and verification algorithms these days.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:58 +0000 (21:36 -0400)]
doc: renesas: add Renesas board docs
As a starting point, list all currently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:57 +0000 (21:36 -0400)]
tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \
-T spkgimage -a 0x20040000 -e 0x20040000 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:56 +0000 (21:36 -0400)]
board: schneider: add RZN1 board support
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:55 +0000 (21:36 -0400)]
ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:54 +0000 (21:36 -0400)]
ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3
(commit
457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:53 +0000 (21:36 -0400)]
ram: cadence: add driver for Cadence EDAC
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:52 +0000 (21:36 -0400)]
pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:51 +0000 (21:36 -0400)]
clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit
02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/
20230301215520.828455-1-ralph.siemsen@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:50 +0000 (21:36 -0400)]
clk: renesas: prepare for non R-Car clock drivers
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car
clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3.
This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing
recursion into the drivers/clk/reneasas directory, without bringing in
the R-Car support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ralph Siemsen [Sat, 13 May 2023 01:36:49 +0000 (21:36 -0400)]
ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit
2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Thu, 11 May 2023 12:40:33 +0000 (08:40 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Various fixes for Google chromebooks
- Various minor enhancements for coreboot
Simon Glass [Thu, 4 May 2023 22:51:01 +0000 (16:51 -0600)]
x86: samus: Adjust TPL start and pre-reloc memory size
Move the TPL up a little to make room for the refcode binary blob. Also
increase the pre-relocation memory to make space for recent additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:51:00 +0000 (16:51 -0600)]
x86: samus: Don't include audio and SATA in TPL
These are not used in TPL so disable the drivers to save space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:59 +0000 (16:50 -0600)]
x86: Simplify cpu_jump_to_64bit_uboot()
This copies the cpu_call64() function to memory address and then jumps to
it. This seems to work correctly even when called from SPL, which is
running from SPI flash.
Drop the copy as it is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:58 +0000 (16:50 -0600)]
spl: Commit MTRRs only in board_init_f_r()
We don't need to commit the SPI-flash MTRR change immediately, since it is
now done in the board_init_f_r(). Also this causes chromebook_link64 to
hang, presumably since we are still running from CAR (Cache-as-RAM) in
SPL. Coral handles this OK, perhaps since it is running from a different
memory area, but it has no effect on Coral anyway.
Drop the extra mtrr_commit() in the SPL implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:57 +0000 (16:50 -0600)]
x86: spl: Avoid using init_cache_f_r() from SPL
This function is used by U-Boot proper. It does not set up MTRRs when SPL
is enabled, but we do want this done when it is called from SPL. In fact
it is confusing to use the same function from SPL, since there are quite
a few conditions there.
All init_cache_f_r() really does is commit the MTRRs and set up the cache.
Do this in the SPL's version of this function instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:55 +0000 (16:50 -0600)]
x86: Tidy up address for loading U-Boot from SPL
Use the binman symbols for this, to avoid hard-coding the value. We could
use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to
obtain the offset and size through the same mechanism.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 9 May 2023 10:13:47 +0000 (18:13 +0800)]
x86: sysreset: Set up LPC only after relocation
Probing LPC can cause PCI enumeration to take place, which significantly
increases pre-relocation memory usage. Also, LPC is somtimes enabled
directly by SPL.
Adjust the logic to probe the LPC only after relocation. This allows
chromebook_link64 to start up without a much larger
CONFIG_SYS_MALLOC_F_LEN value.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:54 +0000 (16:50 -0600)]
x86: spl: Show debugging for BSS
Show the area of memory cleared for BSS, when debugging is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:53 +0000 (16:50 -0600)]
x86: mrc: Correct SPL debug message
SPL printf() does not normally support %#x so just use %x instead. Hex is
expected in U-Boot anyway.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:52 +0000 (16:50 -0600)]
x86: Tidy up availability of string functions
For now, just enable the fast-but-large string functions in 32-boot
U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit
builds since we only have 32-bit assembly.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 4 May 2023 22:50:51 +0000 (16:50 -0600)]
x86: Support debug UART in 64-bit mode
The debug UART is already set up in SPL, so there is no need to do
anything here. We must provide the (empty) function though.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:50 +0000 (16:50 -0600)]
x86: samus: Drop EFI_LOADER
This adds a lot of code so that it cannot be built with the binary
blobs. It is not used on this board. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:49 +0000 (16:50 -0600)]
x86: ivybridge: Ensure LPC is available for GPIO base
The bd82x6x_get_gpio_base() does not work if the LPC is not set up.
Probe it early to avoid this problem.
In chromebook_link64 this problem shows up as an inability to read
the GPIO straps for the memory type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:48 +0000 (16:50 -0600)]
sf: Rename spi-nor-tiny functions
The 'tiny' SPI nor functions have the same name as their big brothers,
which can be confusing. Use different names so it is clear which
version is in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:47 +0000 (16:50 -0600)]
sf: Guard against zero erasesize
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero
error. Check for this and return a proper error instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:46 +0000 (16:50 -0600)]
binman: Support writing symbols for ucode etypes
Allow symbol writing in these cases so that U-Boot can find the position
and size of U-Boot at runtime.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:50:45 +0000 (16:50 -0600)]
dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes:
7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:09 +0000 (16:55 -0600)]
coreboot: Enable ms command
This is useful when looking for tables in memory. Enable it for coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:08 +0000 (16:55 -0600)]
x86: nvme: coreboot: Enable NVMe
Enable support for NVMe storage devices. Update the driver to enable the
bus master bit, since coreboot does not do that automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:07 +0000 (16:55 -0600)]
nvme: Enable PCI bus mastering
U-Boot sets up devices ready for use, but coreboot does not. Enable this
so that NVMe works OK from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:06 +0000 (16:55 -0600)]
x86: coreboot: Show unimplemented sysinfo tags
Sometimes coreboot adds new tags that U-Boot does not know about. These
are silently ignored, but it is useful to at least know what we are
missing.
Add a way to collect this information. For Brya it shows:
Unimpl. 38 41 37 34 42 40
These are:
LB_TAG_PLATFORM_BLOB_VERSION
LB_TAG_ACPI_CNVS
LB_TAG_FMAP
LB_TAG_VBOOT_WORKBUF
LB_TAG_TYPE_C_INFO
LB_TAG_BOARD_CONFIG
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:05 +0000 (16:55 -0600)]
x86: coreboot: Log function names and line numbers
Turn these options on to make it easier to debug things.
Also enable dhrystone so we can get some measure of performance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:04 +0000 (16:55 -0600)]
x86: coreboot: Scan PCI after relocation
Enable this so that PCI devices can be used correctly without needing
to do a manual scan.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:03 +0000 (16:55 -0600)]
x86: coreboot: Document how to enable the debug UART
This is not obvious so add a little note about how it works.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:02 +0000 (16:55 -0600)]
x86: coreboot: Use a memory-mapped UART
This is much more common on modern hardware, so default to using it.
This does not affect the normal UART, but does allow the debug UART to
work, since it uses serial_out_shift(), etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:01 +0000 (16:55 -0600)]
pci: coreboot: Don't read regions when booting
When U-Boot is the second-stage bootloader, PCI is already set up. We
cannot read the regions from the device tree. There is no point anyway,
since PCI devices have already been allocated according to the regions
and it is not safe for U-Boot to make any changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes:
f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()")
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:55:00 +0000 (16:55 -0600)]
x86: Allow locating the UART from ACPI tables
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.
Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.
Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.
For now this only supports a memory-mapped 16550-style UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:59 +0000 (16:54 -0600)]
x86: coreboot: Collect the address of the ACPI tables
At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.
Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.
Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:58 +0000 (16:54 -0600)]
acpi: Move the table-finding functions into the libary
This is useful for other features. Move the function into library code
so it can be used outside just the 'acpi' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:57 +0000 (16:54 -0600)]
acpi: Create a new Kconfig for ACPI
We have several Kconfig options for ACPI, but all relate to specific
functions, such as generating tables and AML code.
Add a new option which controls including basic ACPI library code,
including the lib/acpi directory. This will allow us to add functions
which are available even if table generation is not supported.
Adjust the command to avoid a build error when ACPIGEN is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:56 +0000 (16:54 -0600)]
input: Flush the keyboard buffer before resetting it
If U-Boot is not the first-stage bootloader the keyboard may already be
set up. Make sure to flush any data before trying to reset it. This
avoids a long timeout / hang.
Add some comments and a log category while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:55 +0000 (16:54 -0600)]
x86: Adjust search range for sysinfo table
Avoid searching starting at 0 since this memory may not be available,
e.g. if protection against NULL-pointer access is enabled. The table
cannot be there anyway, since the first 1KB of memory was originally
used for the interrupt table and coreboot avoids it.
Start at 0x400 instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 4 May 2023 22:54:54 +0000 (16:54 -0600)]
mtrr: Don't show an invalid CPU number
When U-Boot did not do the MP init, we don't get an actual CPU number
here. Skip printing it in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 9 May 2023 16:45:49 +0000 (12:45 -0400)]
Merge tag 'u-boot-rockchip-
20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
Eugen Hristev [Thu, 13 Apr 2023 11:36:45 +0000 (14:36 +0300)]
clk: rockchip: rk3588: add hardcoded assigned clocks values
The CRU is being probed with a default set of assigned clocks, which
are not implemented in the driver at all.
Hence, when clk_set_defaults is called, it fails with ENOENT.
This would not be a problem, as the CRU still handles all the required
clocks, and the assigned clocks are default configs which are preprogrammed
or not required for Uboot operations.
However, the rockchip reset driver is being bound by the same DT node
as CRU, as the reset driver has no DT node.
But, when probing the reset node, it will call again the clk_set_defaults
for the CRU node, and failing because of missing those specific clocks
in the rk3588 clock driver.
To avoid this, simply implement a basic set/get that will just return
success and the default corresponding rate for the required assigned clocks.
As those clocks were not supported in Uboot, not required for Uboot
operations, there is no need to do any different kind of initialization.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Wed, 12 Apr 2023 11:52:53 +0000 (12:52 +0100)]
rockchip: handle peripheral as well as otg dr_mode
The OTG port is identified by inspecting the "dr_mode" property which is
expected to be "otg" for this port. But it will work just as well as a
device controller when dr_mode is set to "peripheral", which may be
required if the mode detection pin is not set up correctly and the
device controller needs to be programmed to override this.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Wed, 12 Apr 2023 11:52:52 +0000 (12:52 +0100)]
rockchip: use standard dr_mode parsing function
Instead of duplicating the string values here, use usb_get_dr_mode() to
handle the property lookup and converting the values to an enum.
This is implemented with a switch in preparation for the next patch
which adds extra handling for peripheral mode.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Thu, 20 Apr 2023 09:42:30 +0000 (09:42 +0000)]
arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-order
use common one defined in rk356x-u-boot.dtsi.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Sat, 8 Apr 2023 09:33:42 +0000 (09:33 +0000)]
arm: dts: rk356x: Makefile: sort
sort alphanumerically.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Wed, 26 Apr 2023 02:23:56 +0000 (02:23 +0000)]
doc: rockchip: update list of Radxa ROCK (Pi) 4 boards
add Radxa ROCK (Pi) 4 variants.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>