Nick Desaulniers [Fri, 17 Feb 2023 01:49:16 +0000 (17:49 -0800)]
[Clang] refactor CodeGenFunction::EmitAsmStmt NFC
Prerequisite to further modifications in D136497.
Basically, there is a large body of code in CodeGenFunction::EmitAsmStmt
for emitting stores of outputs. We want to be able to repeat this logic,
for each destination of a callbr (rather than just the default
destination which is what the code currently does).
Also does some smaller cleanups like whitespace cleanups, and removing
pointless casts.
Reviewed By: void, jyknight
Differential Revision: https://reviews.llvm.org/D137113
Nick Desaulniers [Fri, 17 Feb 2023 01:48:14 +0000 (17:48 -0800)]
[llvm] add CallBrPrepare pass to pipelines
Capstone of
https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8
Clang changes are still necessary to enable the use of outputs along
indirect edges of asm goto statements.
Link: https://github.com/llvm/llvm-project/issues/53562
Reviewed By: void
Differential Revision: https://reviews.llvm.org/D140180
Nick Desaulniers [Fri, 17 Feb 2023 01:47:37 +0000 (17:47 -0800)]
[llvm][SelectionDAGBuilder] codegen callbr.landingpad intrinsic
Given a CallBrInst, retain its first virtual register in SelectionDagBuilder's
FunctionLoweringInfo if there's corresponding landingpad. Walk the list
of COPY MachineInstr to find the original virtual and physical registers
defined by the INLINEASM_BR MachineInst.
Test cases from https://reviews.llvm.org/D139565.
Link: https://github.com/llvm/llvm-project/issues/59538
Part 3 from
https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8
Follow up patches still need to wire up CallBrPrepare into the pass
pipelines.
Reviewed By: efriedma, void
Differential Revision: https://reviews.llvm.org/D140160
Nick Desaulniers [Fri, 17 Feb 2023 01:47:13 +0000 (17:47 -0800)]
[llvm][CallBrPrepare] use SSAUpdater to use intrinsic value
Now that we've inserted a call to an intrinsic, we need to update
certain previous uses of CallBrInst values to use the value of this
intrinsic instead.
There are 3 cases to handle:
1. The @llvm.callbr.landingpad.<type>() intrinsic call is in the same
BasicBlock as the use of the callbr we're replacing.
2. The use is dominated by the direct destination.
3. The use is not dominated by the direct destination, and may or may
not be dominated by the indirect destination.
Part 2c of
https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8.
Reviewed By: efriedma, void, jyknight
Differential Revision: https://reviews.llvm.org/D139970
Nick Desaulniers [Fri, 17 Feb 2023 01:46:47 +0000 (17:46 -0800)]
[llvm][CallBrPrepare] add llvm.callbr.landingpad intrinsic
Insert a new intrinsic call after splitting critical edges, and verify
it. Later commits will update the SSA values to use this new value along
indirect branches rather than the callbr's value, and have SelectionDAG
consume this new value.
Part 2b of
https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8.
Reviewed By: efriedma, jyknight
Differential Revision: https://reviews.llvm.org/D139883
Nick Desaulniers [Fri, 17 Feb 2023 01:46:21 +0000 (17:46 -0800)]
[llvm][CallBrPrepare] split critical edges
If we have a CallBrInst with output that's used, we need to split
critical edges so that we have some place to insert COPYs for physregs
to virtregs.
Part 2a of
https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8.
Test cases and logic re-purposed from D138078.
Reviewed By: efriedma, void, jyknight
Differential Revision: https://reviews.llvm.org/D139872
Nick Desaulniers [Fri, 17 Feb 2023 01:45:50 +0000 (17:45 -0800)]
[llvm] boilerplate for new callbrprepare codegen IR pass
Because this pass is to be a codegen pass, it must use the legacy pass
manager.
Link: https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8
Reviewed By: aeubanks, void
Differential Revision: https://reviews.llvm.org/D139861
Nick Desaulniers [Fri, 17 Feb 2023 01:44:02 +0000 (17:44 -0800)]
[Dominators] check indirect branches of callbr
This will be necessary to support outputs from asm goto along indirect
edges.
Test via:
$ pushd llvm/build; ninja IRTests; popd
$ ./llvm/build/unittests/IR/IRTests \
--gtest_filter=DominatorTree.CallBrDomination
Also, return nullptr in Instruction::getInsertionPointAfterDef for
CallBrInst as was recommened in
https://reviews.llvm.org/D135997#3991427. The following phab review was
folded into this commit: https://reviews.llvm.org/D140166
Link: https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8
Reviewed By: void, efriedma, ChuanqiXu, MaskRay
Differential Revision: https://reviews.llvm.org/D135997
Shengchen Kan [Thu, 16 Feb 2023 13:17:17 +0000 (21:17 +0800)]
[X86][MC] Fix the bug of -output-asm-variant=1 for intel syntax
Before this patch
```
$ echo "leal (,%r15), %eax" | llvm-mc --show-encoding --output-asm-variant=1
lea eax, [r15] # encoding: [0x42,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00]
$ echo "lea eax, [r15]" | llvm-mc --show-encoding -x86-asm-syntax=intel --output-asm-variant=1
lea eax, [r15] # encoding: [0x41,0x8d,0x07]
```
MC printed the register r15 as a base in intel syntax even when it's an index.
Then we got a different encoding by using the assembly from the output of the
first command.
I believe the behavior is too weird to be called a feature.
After this patch, we get
```
$ echo "leal (,%r15), %eax" | llvm-mc --show-encoding --output-asm-variant=1
lea eax, [1*r15] # encoding: [0x42,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00]
```
Reviewed By: RKSimon, pengfei, MaskRay
Differential Revision: https://reviews.llvm.org/D144183
Johannes Doerfert [Fri, 17 Feb 2023 01:40:47 +0000 (17:40 -0800)]
[Attributor][FIX] Ensure we adjust types properly
When we simplify loads we need to adjust types (esp. null-values)
properly to avoid inconsinstencies down the line. Add a cast and an
error message.
Fixes: https://github.com/llvm/llvm-project/issues/60788
Jie Fu [Fri, 17 Feb 2023 01:31:05 +0000 (09:31 +0800)]
[LLDB] Remove unused variable 'lang_rt' in ClangExpressionParser.cpp (NFC)
/data/llvm-project/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp:398:34: error: variable 'lang_rt' set but not used [-Werror,-Wunused-but-set-variable]
lldb_private::LanguageRuntime *lang_rt = nullptr;
^
1 error generated.
chenglin.bi [Fri, 17 Feb 2023 01:34:04 +0000 (09:34 +0800)]
[ComplexLogicCombine] Precommit tests for complex logic combine init patch; NFC
Alexander Yermolovich [Fri, 17 Feb 2023 01:20:27 +0000 (17:20 -0800)]
Revert "[LLDB] Enable 64 bit debug/type offset"
This reverts commit
2062e90aa531e8445e5dc0e16222c0f246af1bf4.
Jun Ma [Thu, 16 Feb 2023 07:36:07 +0000 (15:36 +0800)]
[WebAssembly] Fix simd bit shift intrinsics codegen
According to github.com/WebAssembly/simd/blob/main/proposals/simd/SIMD.md,
the shift count of bit shift instructions is taken modulo lane width.
This patch adds such operation.
Fixes PR#60655
Differential Revision: https://reviews.llvm.org/D144169
Jun Ma [Thu, 16 Feb 2023 07:42:40 +0000 (15:42 +0800)]
[WebAssembly] Update wasm.c with update_cc_test_checks.py. NFC
Peiming Liu [Fri, 17 Feb 2023 01:08:00 +0000 (01:08 +0000)]
[mlir][sparse] comment out test cases in sparse_conversion with similiar behavior.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D144236
Peter Klausler [Thu, 16 Feb 2023 18:46:50 +0000 (10:46 -0800)]
[flang][runtime] Allow record advancement in child I/O via '/' control edit descriptor
My earlier misreading of the Fortran standards had convinced me that child I/O
-- meaning the use of user-defined subroutines via generic interfaces to implement
data transfer statements -- was not allowed to advance the current record in the
ultimate unit of the original (non-child parent) data transfer statement.
This turns out to be wrong, so forward AdvanceRecord() from ChildFormattedIoStatement<>
to its parent I/O statement rather than implementing it as a no-op.
Differential Revision: https://reviews.llvm.org/D144205
Ting Wang [Fri, 17 Feb 2023 00:21:35 +0000 (19:21 -0500)]
[PowerPC] remove XXSWAPD after load from CP which is a splat value
If the value from constant-pool is a splat value of vector type, do not
need swap after load from constant-pool.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D139491
Huihui Zhang [Thu, 16 Feb 2023 23:40:43 +0000 (15:40 -0800)]
[AArch64][ISel] Always use pre-inc/post-inc addressing mode for auto-indexed load/store with constant offset.
Unlike ARM target, current AArch64 target doesn't have facility to encode the
operation bit: whether to add an offset to base pointer for pre-inc/post-inc
addressing mode, or to subtract an offset from base pointer for
pre-dec/post-dec addressing mode.
A mis-compile (https://github.com/llvm/llvm-project/issues/60645) was noticed
due to this limitation.
Therefore, for AArch64 auto-indexed load/store with constant offset, always
use pre-inc/post-inc addressing mode. The constant offset is negated for
pre-dec/post-dec addressing mode.
An auto-indexed address with non-constant offset is currently not split into
base and offset parts. If we are to handle non-constant offset in the future,
offset node will need to take a negate.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D143796
Peiming Liu [Thu, 16 Feb 2023 23:58:02 +0000 (23:58 +0000)]
[mlir][sparse] split reshape.mlir into expand/collapse_shape.mlir.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D144231
Kiran Chandramohan [Thu, 16 Feb 2023 18:48:49 +0000 (18:48 +0000)]
[MLIR][OpenMP] Add Conversion for Atomic Update Op
Reviewed By: TIFitis
Differential Revision: https://reviews.llvm.org/D143964
Arthur Eubanks [Mon, 6 Feb 2023 19:04:32 +0000 (11:04 -0800)]
[Pipeline] Move ControlHeightReduction to module optimization pipeline
This pass isn't a simplification, it's a non-canonical optimization.
This makes it only run once in a (Thin)LTO pipeline during postlink, just like all the other optimization pipeline passes.
Reviewed By: xur
Differential Revision: https://reviews.llvm.org/D143424
Peiming Liu [Thu, 16 Feb 2023 20:24:01 +0000 (20:24 +0000)]
[mlir][sparse] allow foreach operation to generate out-of-order loop on non-annotated tensor.
No need for a temp COO and sort even when converting dense -> CSC, we can instead rotate the loop to yield a ordered coordinates at beginning.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D144213
Alexander Yermolovich [Thu, 16 Feb 2023 22:46:13 +0000 (14:46 -0800)]
[LLDB] Enable 64 bit debug/type offset
This came out of from https://discourse.llvm.org/t/dwarf-dwp-4gb-limit/63902
With big binaries we can have .dwp files where .debug_info.dwo section can grow
beyond 4GB. We would like to support this in LLVM and in LLDB.
The plan is to enable manual parsing of cu/tu index in DWARF library
(https://reviews.llvm.org/D137882), and then
switch internal index data structure to 64 bit.
For the second part is to enable 64bit offset support in LLDB with
this patch.
Depends on D139955
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D138618
Arthur Eubanks [Thu, 16 Feb 2023 21:41:05 +0000 (13:41 -0800)]
[gn build] Manually port D143983
Gregory Alfonso [Thu, 16 Feb 2023 21:20:41 +0000 (13:20 -0800)]
[Object][NFC] Remove unneeded llvm_unreachable
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D139452
Nemanja Ivanovic [Thu, 16 Feb 2023 21:15:25 +0000 (16:15 -0500)]
[PowerPC] Bail out of FISel when lowering long calls
We currently don't handle tail calls in fast-isel but
we continue with the lowering when -mlongcall is
specified and lower the calls normally. We should
defer to SDISel for this so that it is lowered correctly.
Differential revision: https://reviews.llvm.org/D123997
bixia1 [Thu, 16 Feb 2023 17:52:01 +0000 (09:52 -0800)]
[mlir][sparse] Remove the expansion of symmetric MTX in the sparse tensor storage.
We will support symmetric MTX without expanding the data in the sparse tensor
storage.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D144059
Joseph Huber [Thu, 16 Feb 2023 20:50:56 +0000 (14:50 -0600)]
[Libomptarget] Check errors when synchronizing the async queue
Summary:
Currently when we synchronize the asynchronous queue for the plugins, we
ignore the return value. This is problematic because we will continue on
like nothing happened if the kernel fails.
Fixes https://github.com/llvm/llvm-project/issues/60814
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D144191
Joseph Huber [Thu, 16 Feb 2023 20:50:31 +0000 (14:50 -0600)]
Revert "[Libomptarget] Check errors when synchronizing the async queue"
This reverts commit
861709107b43d40ad366e0efd225cb804be3b44d.
Reverting this to reland as it will make it easier to backport.
Sterling Augustine [Thu, 16 Feb 2023 20:19:26 +0000 (12:19 -0800)]
RenderScript still exists as a clang language, so handle as invalid
Pranav Kant [Thu, 16 Feb 2023 19:57:18 +0000 (19:57 +0000)]
[Bazel][mlir] Fix build errors
Fallback from https://reviews.llvm.org/D143925
Differential Revision: https://reviews.llvm.org/D144212
Valentin Clement [Thu, 16 Feb 2023 19:59:54 +0000 (20:59 +0100)]
[flang] Handle expression in SELECT TYPE selector
Expression in selector were raising an error. In some
cases expression can be found in selector. This patch
updates the code to accept expression and adds a lowering
test.
Reviewed By: PeteSteinfeld, vdonaldson
Differential Revision: https://reviews.llvm.org/D144185
Sterling Augustine [Thu, 16 Feb 2023 19:54:35 +0000 (11:54 -0800)]
Remove now unused enum.
Arthur Eubanks [Thu, 16 Feb 2023 19:35:18 +0000 (11:35 -0800)]
[Pipeline] Remove -enable-npm-O3-nontrivial-unswitch flag
This was added to help debugging performance issues, no longer needed.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D98675
Arthur Eubanks [Wed, 15 Feb 2023 19:19:48 +0000 (11:19 -0800)]
[Pipeline] Remove -enable-no-rerun-simplification-pipeline flag
This has been on without complaint for a while.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D144130
Michael Jones [Wed, 15 Feb 2023 22:26:30 +0000 (14:26 -0800)]
[libc][bazel] add string to float targets
This patch adds atof, strtof, strtod, and strtold to the bazel build, as
well as their tests.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D144140
Alex Langford [Fri, 27 Jan 2023 01:33:33 +0000 (17:33 -0800)]
[lldb] Replace SB swig interfaces with API headers
Instead of maintaining separate swig interface files, we can use the API
headers directly. They implement the exact same C++ APIs and we can
conditionally include the python extensions as needed. To remove the
swig extensions from the API headers when building the LLDB
framework, we can use the unifdef tool when it is available. Otherwise
we just copy them as-is.
Differential Revision: https://reviews.llvm.org/D142926
Louis Dionne [Wed, 15 Feb 2023 15:49:45 +0000 (10:49 -0500)]
[libc++] Add regression test for std::hash implementation in ABI v1
Differential Revision: https://reviews.llvm.org/D144107
Hanhan Wang [Thu, 16 Feb 2023 01:38:46 +0000 (17:38 -0800)]
[mlir][linalg][tensor] Delete duplicate tests and fix typo in filename
These two files contain the identical tests. The commit deletes one of
the files, and fix a typo in filename for the other one.
Reviewed By: chelini
Differential Revision: https://reviews.llvm.org/D144152
Yi Kong [Tue, 14 Feb 2023 06:55:57 +0000 (14:55 +0800)]
Remove Renderscript LLDB
Renderscript is deprecated from Android, we no longer support LLDB for
Renderscript.
Differential Revision: https://reviews.llvm.org/D143983
Philip Reames [Thu, 16 Feb 2023 18:27:52 +0000 (10:27 -0800)]
[RISCV] Accept zicsr and zifencei command line options
This change adds the definition of the two extensions, but does not either a) make any instruction conditional on them or b) enabled the extensions by default. (The *instructions* do remain enabled by default per ISA version 2.0 which is our current default.)
This is meant to be a building block towards something like https://reviews.llvm.org/D141666, and in the meantime, address one of the most surprising of the current user experience warts. The current behavior of rejecting the extensions at the command line despite emitting code which appears to use them is surprising to anyone not deeply versed in the details of this situation.
Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions (these), but were no longer required by the base ISA. This change is described in “Preface to Document Version
20190608-Base-Ratified” from the specification document.
As LLVM currently implements only version 2.0 of the base specification, accepting these extensions at the command line introduces a configuration which doesn't actually match any spec version. It's a pretty harmless variant since the 2.0 extension definitions, to my knowledge, exactly match the text from the 2.0 I text before they were moved into standalone extensions in 2.1 of I. (The version numbering in that sentence is a tad confusing to say the least. Hopefully I got it right.)
It is worth noting that we already have numerous examples of accepting extensions in the march string which didn't exist in version of the spec document corresponding to our current base I version, so this doesn't set any new precedent.
Differential Revision: https://reviews.llvm.org/D143953
Nemanja Ivanovic [Thu, 16 Feb 2023 18:37:31 +0000 (13:37 -0500)]
[libunwind][PowerPC] Fix saving/restoring VSX registers on LE systems
Currently, libunwind just uses stxvd2x/lxvd2x to save/restore
VSX registers respectively. This puts the registers in
doubleword-reversed order into memory on little endian systems.
If both the save and restore are done the same way, this
isn't a problem. However if the unwinder is just restoring
a callee-saved register, it will restore it in the wrong
order (since function prologues save them in the correct order).
This patch adds the necessary swaps before the saves and after
the restores.
Differential revision: https://reviews.llvm.org/D137599
Raman Tenneti [Thu, 16 Feb 2023 17:56:36 +0000 (09:56 -0800)]
[libc] Implement htonl and htons
Per spec:
* https://pubs.opengroup.org/onlinepubs/
9699919799/functions/htonl.html
* https://pubs.opengroup.org/onlinepubs/
9699919799/functions/htons.html
Also adds UInt16Type and UInt32Type to spec.td
Co-authored-by: Jeff Bailey <jbailey@google.com>
Reviewed By: sivachandra, jeffbailey, rtenneti
Differential Revision: https://reviews.llvm.org/D143795
Krzysztof Parzyszek [Wed, 15 Feb 2023 21:59:54 +0000 (13:59 -0800)]
[Hexagon] Fix number of arguments in call to DAG.getNode for VINSERTW0
HexagonISD::VINSERTW0 takes two inputs, but only one was provided.
Joshua Batista [Thu, 16 Feb 2023 17:28:33 +0000 (09:28 -0800)]
[HLSL] add log library functions
This change exposes the log library functions for HLSL,excluding long, int, and long long doubles. The log functions are supported for all scalar, vector, and matrix types.
Long and long long double support is missing in this patch because those types
don't exist in HLSL. Int is missing because the log functions only work on floating type arguments.
The full documentation of the HLSL log functions are available here:
https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-log
https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-log2
https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-log10
Reviewed By: python3kgae
Differential Revision: https://reviews.llvm.org/D144120
Philip Reames [Thu, 16 Feb 2023 17:30:14 +0000 (09:30 -0800)]
Revert "[RISCV][MC] Add support for experimental zfa extension (FLI instruction not included)"
This reverts commit
f6fa5a66d8a8190002d3eb542e4b5a99deb53004. Several buildbots are failing. An example:
https://lab.llvm.org/buildbot#builders/196/builds/26601
Jay Foad [Thu, 16 Feb 2023 17:09:26 +0000 (17:09 +0000)]
AMDGPU: Add a regression test case for D143963
Jay Foad [Thu, 16 Feb 2023 17:05:33 +0000 (17:05 +0000)]
Revert "AMDGPU: Override getNegatedExpression constant handling"
This reverts commit
11c3cead23783e65fb30e673d62771352078ff05.
It was causing infinite loops in the DAG combiner.
Simon Tatham [Thu, 16 Feb 2023 17:05:43 +0000 (17:05 +0000)]
Revert "[LowerTypeTests] Support generating Armv6-M jump tables."
This reverts commit
f6ddf7781471b71243fa3c3ae7c93073f95c7dff.
Eight buildbots reported that the two test files changed by that
commit had started failing. The buildbots in question all had in
common that they build with a very restricted `LLVM_TARGETS_TO_BUILD`,
such as only X86 or AArch64 or Hexagon. I didn't notice this before
commit because my own build has the full default set of targets, and
in that circumstance, the tests pass.
I assume the problem has something to do with the attempt to query
TargetTransformInfo: if you can't make a valid TTI for the target
triple then you can't ask it what kind of inline assembler you should
be emitting, and so `opt` without the Arm backend can't get the Arm
cases of these tests right.
I don't have time to fix this until next week, so I'll revert the
change for now to keep the buildbots happy.
Jay Foad [Thu, 16 Feb 2023 16:41:25 +0000 (16:41 +0000)]
[AMDGPU] Add another G_UNMERGE_VALUES legalization test case
Alex Brachet [Thu, 16 Feb 2023 16:38:19 +0000 (16:38 +0000)]
[libc] Support running tests for Pigweed
Differential Revision: https://reviews.llvm.org/D144146
Florian Hahn [Thu, 16 Feb 2023 16:38:15 +0000 (16:38 +0000)]
[AMDGPU] Regenerate check lines to enable updating for D144050.
Nigel Perks [Wed, 15 Feb 2023 14:44:57 +0000 (14:44 +0000)]
[XCore] Adapt Clang tests to opaque pointers.
Differential Revision: https://reviews.llvm.org/D144195
Peter Klausler [Thu, 16 Feb 2023 00:39:14 +0000 (16:39 -0800)]
[flang] Always incorporate parent types' special generic bindings
The runtime type information table generator was broken when dealing
with an extension derived type that didn't include a special generic
procedure binding for ASSIGNMENT(=) or user-defined I/O, but one of
whose ancestor types did. Ensure that the runtime derived type info
tables have complete subtables for all of these special bindings,
and respect any overrides that may have been defined.
Motivating example:
type parent
contains
procedure :: dtWrite => dtWrite1
generic :: write(formatted) => dtWrite
end type
type, extends(parent) :: extended
contains
procedure :: dtWrite => dtWrite2
end type
The runtime derived type information table for "extended" must include
a special generic procedure entry for "write(formatted)" that points
to "dtWrite2" even though "extend" has no generic procedure for
"write(formatted)".
Differential Revision: https://reviews.llvm.org/D144148
Florian Hahn [Thu, 16 Feb 2023 16:12:07 +0000 (16:12 +0000)]
[LSR] Add test case which shows additional LSR with D144050.
Joseph Huber [Thu, 16 Feb 2023 15:51:21 +0000 (09:51 -0600)]
[Libomptarget] Check errors when synchronizing the async queue
Currently when we synchronize the asynchronous queue for the plugins, we
ignore the return value. This is problematic because we will continue on
like nothing happened if the kernel fails.
Fixes https://github.com/llvm/llvm-project/issues/60814
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D144191
Jun Sha (Joshua) [Thu, 16 Feb 2023 15:51:34 +0000 (07:51 -0800)]
[RISCV][MC] Add support for experimental zfa extension (FLI instruction not included)
This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-
20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.
This change adds assembly support for all instructions except load-immediate instructions (fli.s/fli.d/fli.h). Assembly support for that instruction and codegen support will follow in separate patches.
Differential Revision: https://reviews.llvm.org/D141984
Nikita Popov [Thu, 16 Feb 2023 15:53:59 +0000 (16:53 +0100)]
[Clang] Convert some tests to opaque pointers (NFC)
Nikita Popov [Thu, 16 Feb 2023 15:49:30 +0000 (16:49 +0100)]
[Clang] Regenerate check lines (NFC)
Convert test to use update_cc_test_checks.
Philip Reames [Thu, 16 Feb 2023 15:22:51 +0000 (07:22 -0800)]
Revert "[RISCV][MC] Add support for experimental zfa extension(FLI instruction not included)"
This reverts commit
54c136e6c630966255293d42c882eab116437834. It was submitted without an appropriate patch description. Will reapply shortly.
Philip Reames [Thu, 16 Feb 2023 15:22:46 +0000 (07:22 -0800)]
Revert "Update: [RISCV][MC] Add support for experimental zfa extension(FLI instruction not included)"
This reverts commit
321cd52ba2647259f58b0d38cdb62528a9ded9a1. It was submitted without an appropriate patch description. Will reapply shortly.
Philip Reames [Thu, 16 Feb 2023 15:22:15 +0000 (07:22 -0800)]
Revert "[RISCV][CodeGen] Add codegen pattern for experimental zfa extension (FLI and FCVTMOD not included)"
This reverts commit
fc6d517e2f335c2ab2b14a34eb747a4703aca7e4. It was submitted without an appropriate patch description. Will reapply shortly.
David Green [Thu, 16 Feb 2023 15:48:12 +0000 (15:48 +0000)]
[LSR] Improve filtered uses in NarrowSearchSpaceByPickingWinnerRegs
NarrowSearchSpaceByPickingWinnerRegs has an aggressive filtering method to
reduce the complexity of the search space down by picking a best formula with
the highest number of reuses and assuming it will yield profitable reuse. In
certain cases we can find a best formula like {X+30,+,1} and later check a
formula like {X,+,1} with the same number of Uses. On some architectures it
can be better to pick {X,+,1}, especially if an offset of 30 can be used as a
legal addressing mode, but -30 cannot. That happens under Thumb1 code, which
has fairly limited addressing modes. This patch adds a check to see if it can
pick the simpler formula, if it looks more profitable.
Differential Revision: https://reviews.llvm.org/D144014
Nikita Popov [Thu, 16 Feb 2023 15:37:20 +0000 (16:37 +0100)]
[Clang] Convert some tests to opaque pointers (NFC)
Simon Tatham [Thu, 16 Feb 2023 15:34:33 +0000 (15:34 +0000)]
[LowerTypeTests] Support generating Armv6-M jump tables.
The LowerTypeTests pass emits a jump table in the form of an
`inlineasm` IR node containing a string representation of some
assembly. It tests the target triple to see what architecture it
should be generating assembly for. But that's not good enough for
`Triple::thumb`, because the 32-bit PC-relative `b.w` branch
instruction isn't available in all supported architecture versions. In
particular, Armv6-M doesn't support that instruction (although the
similar Armv8-M Baseline does).
Most of this patch is concerned with working out whether the
compilation target is Armv6-M or not, which I'm doing by going through
all the functions in the module, retrieving a TargetTransformInfo for
each one, and querying it via a new method I've added to check its
SubtargetInfo. If any function's TTI indicates that it's targeting an
architecture supporting B.W, then we assume we're also allowed to use
B.W in the jump table.
The Armv6-M compatible jump table format requires a temporary
register, and therefore also has to use the stack in order to restore
that register.
Another consequence of this change is that jump tables on Arm/Thumb
are no longer always the same size. In particular, on an architecture
that supports Arm and Thumb-1 but not Thumb-2, the Arm and Thumb
tables are different sizes from //each other//. As a consequence,
``getJumpTableEntrySize`` can no longer base its answer on the target
triple's architecture: it has to take into account the decision that
``selectJumpTableArmEncoding`` made, which meant I had to move that
function to an earlier point in the code and store its answer in the
``LowerTypeTestsModule`` class.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D143576
NAKAMURA Takumi [Thu, 16 Feb 2023 15:28:07 +0000 (00:28 +0900)]
llvm-tblgen: Apply IWYU partially
Tom Eccles [Tue, 14 Feb 2023 18:09:35 +0000 (18:09 +0000)]
[flang] lower hlfir.matmul into fir runtime call
We can't test lowering calls with hlfir.expr arguments yet because this
hits a not yet implemented: "get shape form HLFIR expr without producer
holding the shape".
Differential Revision: https://reviews.llvm.org/D144098
Tom Eccles [Tue, 14 Feb 2023 12:04:52 +0000 (12:04 +0000)]
[flang] lower matmul intrinsic to hlfir.matmul operation
Differential Revision: https://reviews.llvm.org/D144096
Tom Eccles [Mon, 13 Feb 2023 18:04:46 +0000 (18:04 +0000)]
[flang] add hlfir.matmul operation
Add a HLFIR operation for the MATMUL transformational intrinsic,
according to the design set out in flang/doc/HighLevelFIR.md
Differential Revision: https://reviews.llvm.org/D144094
Nicolas Vasilache [Thu, 16 Feb 2023 15:02:21 +0000 (07:02 -0800)]
[mlir][MemRef] NFC - Add debug information to MultiBuffer.cpp
Matthias Springer [Thu, 16 Feb 2023 15:05:58 +0000 (16:05 +0100)]
[mlir][bufferization] Fix bug in findValueInReverseUseDefChain
`alwaysIncludeLeaves` was not respected by all code paths.
Differential Revision: https://reviews.llvm.org/D144187
Nikita Popov [Wed, 2 Dec 2020 20:31:22 +0000 (21:31 +0100)]
[DataLayout] Use separate vectors to store alignment (NFC)
Instead of storing alignment for integers, floats, vectors and
structs in a single vector with a type tag, store them in
separate vectors instead. This makes the alignment lookup faster,
as we don't have to scan over irrelevant alignment entries.
Maya Amrami [Thu, 2 Feb 2023 15:21:51 +0000 (17:21 +0200)]
[mlir] PromoteBuffersToStackPass - Copy attributes of original AllocOp
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D143185
Christian Ulmann [Thu, 16 Feb 2023 14:44:05 +0000 (15:44 +0100)]
[mlir][llvm] Use before def debug intrinsic import
This commit adds special handling for the debug intrinsic value
handling. LLVM allows to relax the def before use property for debug
intrinsics, so this property cannot be assumed for metadata values.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D144177
Nikita Popov [Thu, 16 Feb 2023 14:30:35 +0000 (15:30 +0100)]
[Clang] Convert some tests to opaque pointers (NFC)
Florian Hahn [Thu, 16 Feb 2023 14:44:49 +0000 (14:44 +0000)]
[ConstraintSystem] Use sparse representation for constraints. (NFC)
Update ConstraintSystem to use a sparse representation for entries in a
row. Most rows only contain a small number of variables, so the sparse
representation can result in significant speedups.
For a large test case from D135915, it halves the time spent in
ConstraintElimination.
To ensure this returns the same results as the old implementation in all
cases, I built a large set of projects with an extra assertion that it
produces the same result as the old implementation.
David Green [Thu, 16 Feb 2023 14:24:51 +0000 (14:24 +0000)]
[ARM] Add Thumb LSR codegen tests. NFC
This is the same routine generated in two different ways that ends up with
different orders to loads. The first currently does better than the second
with ordered loads, but needn't if the filtering in LSR is improved.
Jean Perier [Thu, 16 Feb 2023 14:20:34 +0000 (15:20 +0100)]
[flang][hlfir] Array constructor lowering [part 2/4]
This patch adds the lowering strategy that lowers an array constructor
to an hlfir.elemental (without creating any temporary yet in lowering).
This will allow more high level array expression optimization to elide
the array constructor temporary when possible, but this is only doable
for a restricted although common form of array constructors:
"[(pure_scalar_expr(i),i=lower,upper,stride)]".
Differential Revision: https://reviews.llvm.org/D144111
Jean Perier [Thu, 16 Feb 2023 14:18:42 +0000 (15:18 +0100)]
[flang][hlfir] Array constructor lowering [part 1/4]
This is the first and biggest chunk that introduces support for
array constructor to HLFIR.
This patch:
- adds a new ConvertArrayConstructor.cpp that centralizes the
code dealing with array constructor lowering.
- introduces a framework to lower array constructor according to
different strategies: A common analysis of the array constructor is
done, and based on that, a lowering startegy is selected and driven
through the ac-values of the array constructor. See
ConvertArrayConstructor.cpp comments for more details.
- implements the first strategy that creates a temporary inlined and
updates it with inlined code. This strategy can only be used if the
temporary can be pre-allocated (i.e: the extents and length parameters
can be pre-computed without evaluating any ac-values), and if all the
ac-value expressions are scalars.
For the sake of simplicity, characters and derived type will be enabled
once all the strategies are added.
Reviewed By: clementval, PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D144102
Akash Banerjee [Thu, 16 Feb 2023 13:42:47 +0000 (13:42 +0000)]
[Flang][OpenMP] Added parser support for device_type clause
This patch adds parser suppert for the device_type clause used by the Declare Target directive.
Differential Revision: https://reviews.llvm.org/D143671
Valentin Clement [Thu, 16 Feb 2023 13:53:47 +0000 (14:53 +0100)]
[flang] Use derivedType from toAddedum to get updated components
When the rhs is polymorphic and allocated during assignment, the
derivedType might have change from the one set in `toDerived`.
Use the one set in the addendum so it is always up to date.
This can happen in cases like the one shown below:
```
type :: t1
end type t1
type, extends(t1) :: t2
integer, allocatable :: i(:)
end type
subroutine assign(t)
class(t2), intent(in) :: t
class(t1), allocatable :: cp
cp = t
end subroutine
```
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D144171
Nicolas Vasilache [Wed, 15 Feb 2023 17:23:52 +0000 (09:23 -0800)]
[mlir][Linalg] Add a transform dialect op to rewrite ops to destination passing style.
A new transform dialect op is introduced to perform the rewrite.
The test pass option is now obsolete and is removed in favor of the transform.
In the process I realized the tensor.pad nofold attribute was not taken into account
and added support to emit a bufferization.alloc_tensor + linalg.copy.
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D143943
Johannes Reifferscheid [Thu, 16 Feb 2023 13:17:28 +0000 (14:17 +0100)]
Add a lowering for memref.dealloc with unranked memrefs.
This is permitted by the op, but the current lowering generates invalid IR.
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D144090
Kerry McLaughlin [Thu, 16 Feb 2023 11:58:32 +0000 (11:58 +0000)]
[SME2][AArch64] Add multi-single multiply-add long long intrinsics
Adds intrinsics for the following SME2 instructions:
- smlall (1, 2 & 4 vectors)
- umlall (1, 2 & 4 vectors)
- smlsll (1, 2 & 4 vectors)
- umlsll (1, 2 & 4 vectors)
- sumlall (2 & 4 vectors)
- usmlall (1, 2 & 4 vectors)
NOTE: These intrinsics are still in development and are subject to future changes.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D143276
Valentin Clement [Thu, 16 Feb 2023 13:05:03 +0000 (14:05 +0100)]
[flang] Add TODO instead of crashing on assert
Current code are crashing on the assert `assert(seqTy && "must be an array");`.
Add a TODO instead until the support is in.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D144173
Joe Loser [Tue, 14 Feb 2023 03:16:50 +0000 (20:16 -0700)]
[libc++] LWG 3857: allow `string_view` conversion when only traits vary
The `basic_string_view` constructor accepting a contiguous range rejects
converting between `basic_string_view` even when only the trait types vary.
This prevents conversions for converting from `basic_string_view<C, T1>` and
`basic_string<C, T1, A>` to `basic_string_view<C, T2>`. Recently, this
constructor was made `explicit`, so there's no reason to really forbid this
conversion anymore.
Relax the restriction that the trait types need to match in this constructor.
Differential Revision: https://reviews.llvm.org/D143972
Sergei Barannikov [Wed, 15 Feb 2023 14:04:37 +0000 (17:04 +0300)]
[clang] Fix a bug that allowed some overflowing octal escape sequences
Reviewed By: cor3ntin
Differential Revision: https://reviews.llvm.org/D144100
Anton Sidorenko [Tue, 14 Feb 2023 10:30:59 +0000 (13:30 +0300)]
[MachineCombiner][NFC] Rename `MinInstr` to `TraceEnsemble`
We are about to allow different trace strategies for MachineCombiner. Make
the name of the ensemble strategy-neutral.
Depends on D140540
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D140541
Florian Hahn [Thu, 16 Feb 2023 11:28:18 +0000 (11:28 +0000)]
[LV] Move invalid cost remark code to separate function (NFC).
The code only needs access to INvalidCosts, ORE and TheLoop, so it can
easily be moved into a helper to make selectVectorizationFactor more
compact.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D143957
Christian Ulmann [Thu, 16 Feb 2023 10:36:34 +0000 (11:36 +0100)]
[mlir][llvm] Rename void debug type to null
This commit renames the "di_void_result_type" to "di_null_type" as LLVM
does use null not exclusively for void types. An added test demonstrates
this for variadic function declarations, whose DISubroutine indicates the
start of variadic types with `null`.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D144109
Jay Foad [Thu, 16 Feb 2023 09:01:48 +0000 (09:01 +0000)]
[UniformityAnalysis] Fix some file headers and pass names
Differential Revision: https://reviews.llvm.org/D144167
Kiran Chandramohan [Thu, 16 Feb 2023 09:23:16 +0000 (09:23 +0000)]
[Flang][OpenMP] Fix a corner case where target region is empty
Reviewed By: psoni2628, raghavendhra
Differential Revision: https://reviews.llvm.org/D144110
Quentin Colombet [Fri, 27 Jan 2023 15:10:54 +0000 (16:10 +0100)]
[mlir][MemRef|Tensor] Fix the handling of DimOp
Although specifying an index that is out of bounds for both `memref.dim`
and `tensor.dim` produces an undefined behavior, this is still valid IR.
In particular, we could expose an out of bound index because of some
optimizations, for instance as demonstrated with
https://github.com/llvm/llvm-project/issues/60295, and this shouldn't
cause the compiler to abort.
This patch removes the overzealous verifier checks and properly handles
out of bound indices (as in it doesn't crash the compiler, but still
produces UB).
This fixes https://github.com/llvm/llvm-project/issues/60295.
Note: That `shape.dim` has a similar problem but we're not supposed to
produce UB in this case. Instead we're supposed to propagate an error in
the resulting value and I don't know how to do that at the moment. Hence I
left this part out of the patch.
Differential Revision: https://reviews.llvm.org/D143999
Carlos Alberto Enciso [Thu, 16 Feb 2023 09:52:50 +0000 (09:52 +0000)]
[llvm-debuginfo-analyzer] (08a/09) - Memory Management
llvm-debuginfo-analyzer is a command line tool that processes debug
info contained in a binary file and produces a debug information
format agnostic “Logical View”, which is a high-level semantic
representation of the debug info, independent of the low-level
format.
The code has been divided into the following patches:
1) Interval tree
2) Driver and documentation
3) Logical elements
4) Locations and ranges
5) Select elements
6) Warning and internal options
7) Compare elements
8) ELF Reader
8a) Memory Management
9) CodeView Reader
Full details:
https://discourse.llvm.org/t/llvm-dev-rfc-llvm-dva-debug-information-visual-analyzer/62570
This patch:
This is a high level summary of the changes in this patch.
Memory Management
- Use Bump allocators for memory management.
As the logical elements are only allocated in one pass (debuginfo
parsing) and they are never manipulated/created/destroyed later,
use the SpecificBumpPtrAllocator for the memory management.
Reviewed By: dblaikie, Orlando
Differential Revision: https://reviews.llvm.org/D137933
Tim Northover [Fri, 27 Jan 2023 13:18:59 +0000 (13:18 +0000)]
AArch64: count callee stack we use when estimating scavenging requirements.
Diana Picus [Thu, 16 Feb 2023 09:07:50 +0000 (10:07 +0100)]
[AMDGPU] Autogenerate checks for several tests. NFCI
David Spickett [Thu, 16 Feb 2023 09:41:50 +0000 (09:41 +0000)]
[lld-macho] Use uint64_t instead of size_t to fix 32 bit test failures
Our bot has been failing https://lab.llvm.org/buildbot/#/builders/178/builds/3967:
Assertion `isecEnd - isecVA <= forwardBranchRange && "should only finalize sections in jump range"' failed.
I think this is due to the use of size_t, which is 32 bit on 32 bit,
for a value used in some 64 bit address calculations. Which was added in
https://reviews.llvm.org/D144029.
Switching to uint64_t fixes the issues.
Nikita Popov [Wed, 15 Feb 2023 13:39:52 +0000 (14:39 +0100)]
[InstSimplify] Slightly optimize simplifyLoad() (NFC)
Check upfront whether the load is based on a constant global
with definitive initializer. Don't bother computing offsets
otherwise.
Chuanqi Xu [Thu, 16 Feb 2023 09:13:31 +0000 (17:13 +0800)]
[NFC] Add a test for C++20 Modules
Add a test to check that the template instantiation during the template
specialization wouldn't be emitted again in the importer.