Anna Zaks [Tue, 26 Mar 2013 18:57:58 +0000 (18:57 +0000)]
[analyzer] Change inlining policy to inline small functions when reanalyzing ObjC methods as top level.
This allows us to better reason about(inline) small wrapper functions.
llvm-svn: 178063
Anna Zaks [Tue, 26 Mar 2013 18:57:51 +0000 (18:57 +0000)]
[analyzer] micro optimization as per Jordan’s feedback on r177905.
llvm-svn: 178062
NAKAMURA Takumi [Tue, 26 Mar 2013 18:57:40 +0000 (18:57 +0000)]
clang/test/CodeGenCXX/debug-info-namespace.cpp: Disable it on non-bash lit for now.
With dosish filename, it misgenerates an improper extra entry.
!1 = metadata !{metadata !"E:\5Cllvm\5Cllvm-project\5Cclang\5Ctest\5CCodeGenCXX/debug-info-namespace.cpp", metadata !"E:\5Cllvm\5Cbuild\5Cninja-win32-vs11\5Ctools\5Cclang\5Ctest\5CCodeGenCXX"}
!8 = metadata !{metadata !"E:\5Cllvm\5Cllvm-project\5Cclang\5Ctest\5CCodeGenCXX\5Cdebug-info-namespace.cpp", metadata !"E:\5Cllvm\5Cbuild\5Cninja-win32-vs11\5Ctools\5Cclang\5Ctest\5CCodeGenCXX"}
!8 is unexpected.
llvm-svn: 178061
Hal Finkel [Tue, 26 Mar 2013 18:57:22 +0000 (18:57 +0000)]
Use multiple virtual registers in PPC CR spilling
Now that the register scavenger can support multiple spill slots, and PEI can
use virtual-register-based scavenging for multiple simultaneous registers, we
can use a virtual register for the transfer register in the CR spilling code.
This should eliminate the last place (outside of the prologue/epilogue) where
we depend on the unconditional availability of the r0 register. We will soon be
able to allocate it (in a somewhat restricted sense) as a GPR.
llvm-svn: 178060
Hal Finkel [Tue, 26 Mar 2013 18:57:20 +0000 (18:57 +0000)]
Update PPCRegisterInfo's use of virtual registers to be SSA
PPC's use of PEI's virtual-register-based scavenging functionality had
redefined the virtual registers (it was non-SSA). Now that PEI supports
dealing with instructions with multiple virtual registers, this can be
cleanup up to use multiple virtual registers and keep SSA form.
No functionality change intended.
llvm-svn: 178059
Hal Finkel [Tue, 26 Mar 2013 18:56:54 +0000 (18:56 +0000)]
Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings
The previous algorithm could not deal properly with scavenging multiple virtual
registers because it kept only one live virtual -> physical mapping (and
iterated through operands in order). Now we don't maintain a current mapping,
but rather use replaceRegWith to completely remove the virtual register as
soon as the mapping is established.
In order to allow the register scavenger to return a physical register killed
by an instruction for definition by that same instruction, we now call
RS->forward(I) prior to eliminating virtual registers defined in I. This
requires a minor update to forward to ignore virtual registers.
These new features will be tested in forthcoming commits.
llvm-svn: 178058
Enrico Granata [Tue, 26 Mar 2013 18:55:08 +0000 (18:55 +0000)]
Data formatters cleanup:
- Making an error message more consistent
- Ensuring the element size is not zero before using it in a modulus
- Properly using target settings to cap the std::list element count
- Removing spurious element size calculations that were unused
- Removing spurious capping in std::map
llvm-svn: 178057
Greg Clayton [Tue, 26 Mar 2013 18:42:13 +0000 (18:42 +0000)]
Don't crash when we have an element size of zero.
llvm-svn: 178056
Rafael Espindola [Tue, 26 Mar 2013 18:41:47 +0000 (18:41 +0000)]
Remove useGlobalsForAutomaticVariables.
It is unused since pic support went away.
llvm-svn: 178055
Reid Kleckner [Tue, 26 Mar 2013 18:30:28 +0000 (18:30 +0000)]
[ms-cxxabi] Give the MS inheritance attributes a base class
Required making a handful of changes to the table generator. Also adds
an unspecified inheritance attribute. This opens the path for us to
apply these attributes to C++ records implicitly.
llvm-svn: 178054
Manman Ren [Tue, 26 Mar 2013 18:29:15 +0000 (18:29 +0000)]
Fix uninitialized read of CalleeWithThisReturn.
Initialize CalleeWithThisReturn to 0 in the constructor.
Also revert r170815 since checking CalleeWithThisReturn is faster.
PR15598
llvm-svn: 178053
Jim Ingham [Tue, 26 Mar 2013 18:29:03 +0000 (18:29 +0000)]
That wasn't a typo, if the short letter option is from a non-obvious source, I capitolize it in the help as an aid to memory.
llvm-svn: 178052
Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:22 +0000 (18:24 +0000)]
Annotate the remaining x86 instructions with SchedRW lists.
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.
There are still unannotated instructions remaining, but they don't have
itinerary classes either.
llvm-svn: 178051
Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:20 +0000 (18:24 +0000)]
Annotate x87 and mmx instructions with SchedRW lists.
This only covers the instructions that were given itinerary classes for
the Atom model.
llvm-svn: 178050
Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:17 +0000 (18:24 +0000)]
Annotate control instructions with SchedRW lists.
This could definitely be more granular. I am not sure if it makes a
difference.
llvm-svn: 178049
Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:15 +0000 (18:24 +0000)]
Annotate the rest of X86InstrInfo.td with SchedRW lists.
llvm-svn: 178048
John Thompson [Tue, 26 Mar 2013 18:17:28 +0000 (18:17 +0000)]
Revised per review comments to rename test files and rearrange input files.
llvm-svn: 178047
Michael Liao [Tue, 26 Mar 2013 18:15:45 +0000 (18:15 +0000)]
Fix PRFCHW test on non-x86 builds
- 'prefetch' intrinsics are only lowered when SSE is available. On non-X86
builds, 'generic' CPU is used and stops lowering any prefetch intrinsics.
llvm-svn: 178046
Arnold Schwaighofer [Tue, 26 Mar 2013 18:07:53 +0000 (18:07 +0000)]
BasicAA: Only query twice if the result of the more general query was MayAlias
This is a compile time optimization. Before the patch we would do two traversals
on each call to aliasGEP - one with a set size parameter one with UnknownSize.
We can do better by first checking the result of the alias query with
UnknownSize.
Only if this one returns MayAlias do we query a second time using size and type.
This recovers an about 7% compile time regression on spec/ammp.
radar://
12349960
llvm-svn: 178045
Enrico Granata [Tue, 26 Mar 2013 18:04:53 +0000 (18:04 +0000)]
Our commands that end up displaying a ValueObject as part of their workflow use OptionGroupValueObjectDisplay as their currency for deciding the final representation
ValueObjects themselves use DumpValueObjectOptions as the currency for the same purpose
The code to convert between these two units was replicated (to varying degrees of correctness) in several spots in the code
This checkin provides one and only one (and hopefully correct :-) entry point for this conversion
llvm-svn: 178044
Jim Ingham [Tue, 26 Mar 2013 18:04:40 +0000 (18:04 +0000)]
Change the stepping test to output "total time" for the step as well.
llvm-svn: 178043
Chad Rosier [Tue, 26 Mar 2013 18:01:48 +0000 (18:01 +0000)]
Fix a crasher by reporting a fatal error if we're unable to create the target
machine and one is required.
Part of rdar://
13295753
llvm-svn: 178042
Michael Liao [Tue, 26 Mar 2013 17:52:08 +0000 (17:52 +0000)]
Add PRFCHW intrinsic support
- Add head 'prfchwintrin.h' to define '_m_prefetchw' which is mapped to
LLVM/clang prefetch builtin
- Add option '-mprfchw' to enable PRFCHW feature and pre-define '__PRFCHW__'
macro
llvm-svn: 178041
Michael Liao [Tue, 26 Mar 2013 17:47:11 +0000 (17:47 +0000)]
Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension
llvm-svn: 178040
Sean Callanan [Tue, 26 Mar 2013 17:45:02 +0000 (17:45 +0000)]
Fixed a typo.
llvm-svn: 178039
Ulrich Weigand [Tue, 26 Mar 2013 17:30:02 +0000 (17:30 +0000)]
Add test case for commit r178031.
llvm-svn: 178038
Argyrios Kyrtzidis [Tue, 26 Mar 2013 17:17:01 +0000 (17:17 +0000)]
[Preprocessor/Modules] Separate the macro directives kinds into their own MacroDirective's subclasses.
For each macro directive (define, undefine, visibility) have a separate object that gets chained
to the macro directive history. This has several benefits:
-No need to mutate a MacroDirective when there is a undefine/visibility directive. Stuff like
PPMutationListener become unnecessary.
-No need to keep extra source locations for the undef/visibility locations for the define directive object
(which is the majority of the directives)
-Much easier to hide/unhide a section in the macro directive history.
-Easier to track the effects of the directives across different submodules.
llvm-svn: 178037
Reid Kleckner [Tue, 26 Mar 2013 16:56:59 +0000 (16:56 +0000)]
[ms-cxxabi] Mangle vector types
Summary:
The only vector types a user can pass from MSVC code to clang code are
the ones from *mmintrin.h, so we only have to match the MSVC mangling
for these types. MSVC mangles the __m128 family of types as tag types,
which we match. For other vector types, we emit a unique tag type
mangling that won't match anything produced by MSVC.
Reviewers: rjmccall
CC: chandlerc, timurrrr, cfe-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D576
llvm-svn: 178036
Greg Clayton [Tue, 26 Mar 2013 16:47:22 +0000 (16:47 +0000)]
Remove FunctionProfiler and ProfileObjectiveC action classes as they are not used.
llvm-svn: 178035
Edwin Vane [Tue, 26 Mar 2013 16:44:29 +0000 (16:44 +0000)]
Docs describing limitations of the cpp11-migrate Loop Convert Transform
Sam Panzer, author of loop convert, provided a list of limitations of the tool
to be documented. (Thanks Sam!)
The transform's limitations are now documented in the existing user doc.
Included are examples of the cases where the tool may change semantics.
Author: Jack Yang <jack.yang@intel.com>
llvm-svn: 178034
Howard Hinnant [Tue, 26 Mar 2013 15:45:56 +0000 (15:45 +0000)]
More vector debug tests.
llvm-svn: 178033
Jyotsna Verma [Tue, 26 Mar 2013 15:43:57 +0000 (15:43 +0000)]
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
llvm-svn: 178032
Ulrich Weigand [Tue, 26 Mar 2013 15:36:14 +0000 (15:36 +0000)]
Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.
The OptimizeIntToFloatBitCast converts shift-truncate sequences
into extractelement operations. The computation of the element
index to be used in the resulting operation is currently only
correct for little-endian targets.
This commit fixes the element index computation to be correct
for big-endian targets as well. If the target byte order is
unknown, the optimization cannot be performed at all.
llvm-svn: 178031
Jyotsna Verma [Tue, 26 Mar 2013 15:34:22 +0000 (15:34 +0000)]
Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h.
llvm-svn: 178030
Marshall Clow [Tue, 26 Mar 2013 15:28:33 +0000 (15:28 +0000)]
Fixed race conditions in thread tests; exposed by UBSan
llvm-svn: 178029
Arnold Schwaighofer [Tue, 26 Mar 2013 15:14:04 +0000 (15:14 +0000)]
Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.
"fatal error: error in backend: Expected a variant SchedClass"
Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
llvm-svn: 178028
Shankar Easwaran [Tue, 26 Mar 2013 15:06:52 +0000 (15:06 +0000)]
[ELF][Hexagon] remove duplicated code
llvm-svn: 178027
Howard Hinnant [Tue, 26 Mar 2013 14:28:25 +0000 (14:28 +0000)]
Simply debug mode tests per Dmitri Gribenko's suggestion.
llvm-svn: 178026
Benjamin Kramer [Tue, 26 Mar 2013 14:17:42 +0000 (14:17 +0000)]
Remove default case from fully covered switch.
llvm-svn: 178025
Christian Konig [Tue, 26 Mar 2013 14:04:17 +0000 (14:04 +0000)]
R600/SI: improve post ISel folding
Not only fold immediates, but avoid unnecessary copies as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178024
Christian Konig [Tue, 26 Mar 2013 14:04:12 +0000 (14:04 +0000)]
R600/SI: improve vector interpolation
Prevent loading M0 multiple times.
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178023
Christian Konig [Tue, 26 Mar 2013 14:04:07 +0000 (14:04 +0000)]
R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLE
Just define the address as unknown instead of VReg_32.
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178022
Christian Konig [Tue, 26 Mar 2013 14:04:02 +0000 (14:04 +0000)]
R600/SI: switch back to RegPressure scheduling
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178021
Christian Konig [Tue, 26 Mar 2013 14:03:57 +0000 (14:03 +0000)]
R600/SI: mark most intrinsics as readnone v2
They read from constant register space anyway.
v2: fix lit tests
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178020
Christian Konig [Tue, 26 Mar 2013 14:03:50 +0000 (14:03 +0000)]
R600/SI: replace WQM intrinsic
Just enable WQM when we see an LDS interpolation instruction.
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178019
Christian Konig [Tue, 26 Mar 2013 14:03:44 +0000 (14:03 +0000)]
R600/SI: fix ELSE pseudo op handling
Restore the EXEC mask early, otherwise a copy might end up not beeing executed.
Candidate for the mesa stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178018
Joe Abbey [Tue, 26 Mar 2013 13:58:53 +0000 (13:58 +0000)]
Patch by Gordon Keiser!
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
llvm-svn: 178017
Howard Hinnant [Tue, 26 Mar 2013 13:48:57 +0000 (13:48 +0000)]
Need one more swap overload for swapping two lvalue vector<bool>::reference's.
llvm-svn: 178016
Evgeniy Stepanov [Tue, 26 Mar 2013 13:44:29 +0000 (13:44 +0000)]
Fix uninitialized read of CalleeWithThisReturn.
CalleeWithThisReturn can be left initialized if HasThisReturn() is false.
This change reverses the order of checks in EmitFunctionEpilog such that
CalleeWithThisReturn is only examined when it has a meaningful value.
Found with MemorySanitizer.
llvm-svn: 178015
Alexey Samsonov [Tue, 26 Mar 2013 13:06:12 +0000 (13:06 +0000)]
[ASan] Change the ABI of __asan_before_dynamic_init function: now it takes pointer to private string with module name. This string serves as a unique module ID in ASan runtime. compiler-rt part
llvm-svn: 178014
Alexey Samsonov [Tue, 26 Mar 2013 13:05:41 +0000 (13:05 +0000)]
[ASan] Change the ABI of __asan_before_dynamic_init function: now it takes pointer to private string with module name. This string serves as a unique module ID in ASan runtime. LLVM part
llvm-svn: 178013
Alexander Potapenko [Tue, 26 Mar 2013 13:02:11 +0000 (13:02 +0000)]
[libsanitizer] Fix the Win build.
llvm-svn: 178012
Kostya Serebryany [Tue, 26 Mar 2013 12:42:18 +0000 (12:42 +0000)]
[tsan] make memcpy_race.cc test immune to memcpy inlining
llvm-svn: 178011
Dmitry Vyukov [Tue, 26 Mar 2013 12:40:23 +0000 (12:40 +0000)]
asan/tsan: move strcasecmp() interceptor to sanitizer_common
llvm-svn: 178010
Dmitry Vyukov [Tue, 26 Mar 2013 12:07:04 +0000 (12:07 +0000)]
asan/tsan: change SANITIZER_GO to more general SANITIZER_SUPPORTS_WEAK_HOOKS
llvm-svn: 178009
Ulrich Weigand [Tue, 26 Mar 2013 10:57:16 +0000 (10:57 +0000)]
PowerPC: Mark patterns as isCodeGenOnly.
There remain a number of patterns that cannot (and should not)
be handled by the asm parser, in particular all the Pseudo patterns.
This commit marks those patterns as isCodeGenOnly.
No change in generated code.
llvm-svn: 178008
Ulrich Weigand [Tue, 26 Mar 2013 10:56:47 +0000 (10:56 +0000)]
PowerPC: Simplify handling of fixups.
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like:
if (isSVR4ABI() && is64BitMode())
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_toc16));
else
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
This is a problem for the asm parser, since it requires knowledge of
the ABI / 64-bit mode to be set up. However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.
Fortunately, this is actually completely unnecessary; that code was added
to decide whether to generate TOC relocations, but that information is in
fact already encoded in the VariantKind of the underlying symbol.
This commit therefore merges those fixup types into one, and then decides
which relocation to use based on the VariantKind.
No changes in generated code.
llvm-svn: 178007
Ulrich Weigand [Tue, 26 Mar 2013 10:56:22 +0000 (10:56 +0000)]
PowerPC: Simplify FADD in round-to-zero mode.
As part of the the sequence generated to implement long double -> int
conversions, we need to perform an FADD in round-to-zero mode. This is
problematical since the FPSCR is not at all modeled at the SelectionDAG
level, and thus there is a risk of getting floating point instructions
generated out of sequence with the instructions to modify FPSCR.
The current code handles this by somewhat "special" patterns that in part
have dummy operands, and/or duplicate existing instructions, making them
awkward to handle in the asm parser.
This commit changes this by leaving the "FADD in round-to-zero mode"
as an atomic operation on the SelectionDAG level, and only split it up into
real instructions at the MI level (via custom inserter). Since at *this*
level the FPSCR *is* modeled (via the "RM" hard register), much of the
"special" stuff can just go away, and the resulting patterns can be used by
the asm parser.
No significant change in generated code expected.
llvm-svn: 178006
Ulrich Weigand [Tue, 26 Mar 2013 10:55:45 +0000 (10:55 +0000)]
PowerPC: Remove LDrs pattern.
The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64. An operand type
"memrs" is defined for just that purpose.
However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.
To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32. This will also make address parsing easier to
implment in the asm parser.
No change in generated code.
llvm-svn: 178005
Ulrich Weigand [Tue, 26 Mar 2013 10:55:20 +0000 (10:55 +0000)]
PowerPC: Remove ADDIL patterns.
The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L,
which describe the same instruction, except that they accept a
symbolLo[64] operand instead of a s16imm[64] operand.
This duplication confuses the asm parser, and it actually not really
needed, since symbolLo[64] already accepts immediate operands anyway.
So this commit removes the duplicate patterns.
No change in generated code.
llvm-svn: 178004
Ulrich Weigand [Tue, 26 Mar 2013 10:54:54 +0000 (10:54 +0000)]
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
llvm-svn: 178003
Ulrich Weigand [Tue, 26 Mar 2013 10:53:27 +0000 (10:53 +0000)]
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
llvm-svn: 178002
Ulrich Weigand [Tue, 26 Mar 2013 10:53:03 +0000 (10:53 +0000)]
PowerPC: Move some 64-bit branch patterns.
In PPCInstr64Bit.td, some branch patterns appear in a different sequence
than the corresponding 32-bit patterns in PPCInstrInfo.td.
To simplify future changes that affect both files, this commit moves
those patterns to rearrange them into a similar sequence.
No effect on generated code.
llvm-svn: 178001
Alexander Potapenko [Tue, 26 Mar 2013 10:34:37 +0000 (10:34 +0000)]
[libsanitizer] Unmapping the old cache partially invalidates the memory layout, so add
a flag to skip cache update for cases when that's unacceptable (e.g. lsan).
Patch by Sergey Matveev (earthdok@google.com)
llvm-svn: 178000
Christian Konig [Tue, 26 Mar 2013 10:24:20 +0000 (10:24 +0000)]
R600: fix DenseMap with pointer key iteration in the structurizer
Use a MapVector on types where the iteration order matters.
Otherwise we doesn't always produce a deterministic output.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 177999
Alexey Samsonov [Tue, 26 Mar 2013 08:55:38 +0000 (08:55 +0000)]
[Sanitizer] Disable atomic_test on Android, where it crashes Clang.
llvm-svn: 177998
Alexey Samsonov [Tue, 26 Mar 2013 08:45:29 +0000 (08:45 +0000)]
Actually mark ASan-unfriendly test as XFAIL
llvm-svn: 177997
Kostya Serebryany [Tue, 26 Mar 2013 08:31:02 +0000 (08:31 +0000)]
[tsan] add a test for aligned-vs-unaligned race (tsan's false negative)
llvm-svn: 177996
Alexey Samsonov [Tue, 26 Mar 2013 08:28:18 +0000 (08:28 +0000)]
Add asan/msan to the list of available features in LIT test runner. Mark ASan-unfriendly test as XFAIL.
llvm-svn: 177995
Alexey Samsonov [Tue, 26 Mar 2013 08:27:39 +0000 (08:27 +0000)]
Add asan/msan to the list of available features in LIT test runner
llvm-svn: 177994
Kostya Serebryany [Tue, 26 Mar 2013 08:01:37 +0000 (08:01 +0000)]
[asan] print thread number while reporting invalid-free and double-free; add tests; also add a test for use-after-poison
llvm-svn: 177993
Alexey Samsonov [Tue, 26 Mar 2013 07:49:46 +0000 (07:49 +0000)]
Add CMake option LLVM_USE_SANITIZER={Address,Memory,MemoryWithOrigins} to simplify bootstrap of LLVM/Clang under ASan/MSan
llvm-svn: 177992
Shankar Easwaran [Tue, 26 Mar 2013 04:01:26 +0000 (04:01 +0000)]
[ELF][Hexagon] Fixing failing test on Bots, few symbol names are available only in debug builds, dont check the symbol names
llvm-svn: 177991
Shankar Easwaran [Tue, 26 Mar 2013 03:53:33 +0000 (03:53 +0000)]
[ELF] no change in functionality, add functions to symbol table so that they can be overridden by derived classes
llvm-svn: 177990
Chandler Carruth [Tue, 26 Mar 2013 03:45:48 +0000 (03:45 +0000)]
Manually specify the link dependencies. Turns out that all the work on
LLVMBuild stuff didn't actually provide a single place for dependencies,
it just added a third place.
llvm-svn: 177989
Chandler Carruth [Tue, 26 Mar 2013 03:45:47 +0000 (03:45 +0000)]
Manually update the dependencies in the Makefiles. It turns out that all
that work on the LLVMBuild based dependency specification didn't
actually work, we just now maintain dependencies in *3* places instead
of 2. Yay.
There may still be some missing dependencies, I'm still sifting through
the bots and my builds, but this is a step in the right direction.
llvm-svn: 177988
Richard Trieu [Tue, 26 Mar 2013 03:41:40 +0000 (03:41 +0000)]
Handle CXXOperatorCallExpr when checking self referrnce during initialization of
class types.
llvm-svn: 177987
Andrew Trick [Tue, 26 Mar 2013 03:14:53 +0000 (03:14 +0000)]
Fix SCEV forgetMemoizedResults should search and destroy backedge exprs.
Fixes PR15570: SEGV: SCEV back-edge info invalid after dead code removal.
Indvars creates a SCEV expression for the loop's back edge taken
count, then determines that the comparison is always true and
removes it.
When loop-unroll asks for the expression, it contains a NULL
SCEVUnknkown (as a CallbackVH).
forgetMemoizedResults should invalidate the loop back edges expression.
llvm-svn: 177986
Chandler Carruth [Tue, 26 Mar 2013 02:25:54 +0000 (02:25 +0000)]
The IRReader header is now part of its own library. Update the include
line and the library dependencies to reflect this.
llvm-svn: 177972
Chandler Carruth [Tue, 26 Mar 2013 02:25:37 +0000 (02:25 +0000)]
Split out the IRReader header and the utility functions it provides into
its own library. These functions are bridging between the bitcode reader
and the ll parser which are in different libraries. Previously we didn't
have any good library to do this, and instead played fast and loose with
a "header only" set of interfaces in the Support library. This really
doesn't work well as evidenced by the recent attempt to add timing logic
to the these routines.
As part of this, make them normal functions rather than weird inline
functions, and sink the implementation into the library. Also clean up
the header to be nice and minimal.
This requires updating lots of build system dependencies to specify that
the IRReader library is needed, and several source files to not
implicitly rely upon the header file to transitively include all manner
of other headers.
If you are using IRReader.h, this commit will break you (the header
moved) and you'll need to also update your library usage to include
'irreader'. I will commit the corresponding change to Clang momentarily.
llvm-svn: 177971
Shankar Easwaran [Tue, 26 Mar 2013 02:20:56 +0000 (02:20 +0000)]
[ELF][Hexagon] add GOTREL/GOT relocations
llvm-svn: 177970
Shankar Easwaran [Tue, 26 Mar 2013 02:20:08 +0000 (02:20 +0000)]
[ELF] order rela.dyn/rela.plt properly
llvm-svn: 177969
Arnold Schwaighofer [Tue, 26 Mar 2013 02:01:42 +0000 (02:01 +0000)]
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
llvm-svn: 177968
Arnold Schwaighofer [Tue, 26 Mar 2013 02:01:39 +0000 (02:01 +0000)]
ARM Scheduler Model: Partial implementation of the new machine scheduler model
This is very much work in progress. Please send me a note if you start to depend
on the added abstract read/write resources. They are subject to change until
further notice.
The old itinerary is still the default.
llvm-svn: 177967
Greg Clayton [Tue, 26 Mar 2013 01:51:59 +0000 (01:51 +0000)]
<rdar://problem/
13502196>
We have the tag when figuring out the fully qualified name, append a suitable name for other types of tags when no name is available.
llvm-svn: 177966
Greg Clayton [Tue, 26 Mar 2013 01:45:43 +0000 (01:45 +0000)]
<rdar://problem/
13502196>
Functions in "(anonymous namespace)" was causing LLDB to crash when trying to complete a type and it would also cause functions arguments to appear in wrong place in frame display when showing function arguments.
llvm-svn: 177965
Jim Ingham [Tue, 26 Mar 2013 01:43:36 +0000 (01:43 +0000)]
Make the stepping perf test case actually work.
llvm-svn: 177964
Nick Lewycky [Tue, 26 Mar 2013 01:29:15 +0000 (01:29 +0000)]
Add missing file to cmake build.
llvm-svn: 177963
Nick Lewycky [Tue, 26 Mar 2013 01:27:52 +0000 (01:27 +0000)]
Add a new watchdog timer interface. The interface does not permit handling timeouts, so
it's only really useful if you're going to crash anyways. Use it in the pretty stack trace
printer to kill the compiler if we hang while printing the stack trace.
llvm-svn: 177962
Enrico Granata [Tue, 26 Mar 2013 01:27:04 +0000 (01:27 +0000)]
<rdar://problem/
13221060>
Make register read and write accept $<regname> as valid.
This allows:
(lldb) reg read rbx
rbx = 0x0000000000000000
(lldb) reg read $rbx
rbx = 0x0000000000000000
(lldb) reg write $rbx 1
(lldb) reg read $rbx
rbx = 0x0000000000000001
to function correctly
It is not done at the RegisterContext level because we should keep the internal API clean of this user-friendly behavior and name registers appropriately.
If this ends up being needed in more places we can reconsider.
llvm-svn: 177961
John Thompson [Tue, 26 Mar 2013 01:18:28 +0000 (01:18 +0000)]
Added simple regression test for modularize.
llvm-svn: 177960
John Thompson [Tue, 26 Mar 2013 01:17:48 +0000 (01:17 +0000)]
Revised to use file list path as reference path, or path provide by new -prefix option. Revised to use LLVM option parser.
llvm-svn: 177959
Richard Smith [Tue, 26 Mar 2013 01:17:18 +0000 (01:17 +0000)]
Remove FIXMEs: these are covered by a core issue which we don't yet implement
(but we happen to get this part right).
llvm-svn: 177958
Richard Smith [Tue, 26 Mar 2013 01:15:19 +0000 (01:15 +0000)]
Implement special-case name lookup for inheriting constructors: member
using-declarations with names which look constructor-like are interpreted as
constructor names.
llvm-svn: 177957
Bill Wendling [Tue, 26 Mar 2013 01:10:03 +0000 (01:10 +0000)]
Remove testcase. It's failing on some platforms but not others.
llvm-svn: 177956
Bill Wendling [Tue, 26 Mar 2013 01:08:02 +0000 (01:08 +0000)]
Hmm...not failing...odd
llvm-svn: 177955
Richard Smith [Tue, 26 Mar 2013 00:54:11 +0000 (00:54 +0000)]
Remove some no-op static_casts.
llvm-svn: 177954
Bill Wendling [Tue, 26 Mar 2013 00:46:31 +0000 (00:46 +0000)]
Temporarily XFAIL this test until Michael can look at it.
llvm-svn: 177953
Michael Gottesman [Tue, 26 Mar 2013 00:42:09 +0000 (00:42 +0000)]
[ObjCARC Annotations] Added support for displaying the state of pointers at the bottom/top of BBs of the ARC dataflow analysis for both bottomup and topdown analyses.
This will allow for verification and analysis of the merge function of
the data flow analyses in the ARC optimizer.
The actual implementation of this feature is by introducing calls to
the functions llvm.arc.annotation.{bottomup,topdown}.{bbstart,bbend}
which are only declared. Each such call takes in a pointer to a global
with the same name as the pointer whose provenance is being tracked and
a pointer whose name is one of our Sequence states and points to a
string that contains the same name.
To ensure that the optimizer does not consider these annotations in any
way, I made it so that the annotations are considered to be of IC_None
type.
A test case is included for this commit and the previous
ObjCARCAnnotation commit.
llvm-svn: 177952
Michael Gottesman [Tue, 26 Mar 2013 00:42:04 +0000 (00:42 +0000)]
[ObjCARC Annotations] Implemented ARC annotation metadata to expose the ARC data flow analysis state in the IR via metadata.
Previously the inner works of the data flow analysis in ObjCARCOpts was hard to
get out of the optimizer for analysis of bugs or testing. All of the current ARC
unit tests are based off of testing the effect of the data flow
analysis (i.e. what statements are removed or moved, etc.). This creates
weakness in the current unit testing regimem since we are not actually testing
what effects various instructions have on the modeled pointer state.
Additionally in order to analyze a bug in the optimizer, one would need to track
by hand what the optimizer was actually doing either through use of DEBUG
statements or through the usage of a debugger, both yielding large loses in
developer productivity.
This patch deals with these two issues by providing ARC annotation
metadata that annotates instructions with the state changes that they cause in
various pointers as well as provides metadata to annotate provenance sources.
Specifically, we introduce the following metadata types:
1. llvm.arc.annotation.bottomup.
2. llvm.arc.annotation.topdown.
3. llvm.arc.annotation.provenancesource.
llvm.arc.annotation.{bottomup,topdown}: These annotations describes a state
change in a pointer when we are visiting instructions bottomup/topdown
respectively. The output format for both is the same:
!1 = metadata !{metadata !"(test,%x)", metadata !"S_Release", metadata !"S_Use"}
The first element is a string tuple with the following format:
(function,variable name)
The second two elements of the metadata show the previous state of the
pointer (in this case S_Release) and the new state of the pointer (S_Use). We
write the metadata in such a manner to ensure that it is easy for outside tools
to parse. This is important since I am currently working on a tool for taking
this information and pretty printing it besides the IR and that can be used for
LIT style testing via the generation of an index.
llvm.arc.annotation.provenancesource: This metadata is used to annotate
instructions which act as provenance sources, i.e. ones that introduce a
new (from the optimizer's perspective) non-argument pointer to track. This
enables cross-referencing in between provenance sources and the state changes
that occur to them.
This is still a work in progress. Additionally I plan on committing
later today additions to the annotations that annotate at the top/bottom
of basic blocks the state of the various pointers being tracked.
*NOTE* The metadata support is conditionally compiled into libObjCARCOpts only
when we are producing a debug build of llvm/clang and even so are
disabled by default. To enable the annotation metadata, pass in
-enable-objc-arc-annotations to opt.
llvm-svn: 177951