platform/upstream/mesa.git
8 years agogallium/radeon: simplify if/else/endif blocks
Nicolai Hähnle [Wed, 28 Sep 2016 16:59:42 +0000 (18:59 +0200)]
gallium/radeon: simplify if/else/endif blocks

In particular, we no longer emit an else block when there is no ELSE
instruction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: label basic blocks by the corresponding TGSI pc
Nicolai Hähnle [Wed, 28 Sep 2016 16:30:09 +0000 (18:30 +0200)]
gallium/radeon: label basic blocks by the corresponding TGSI pc

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: cleanup and fix branch emits
Nicolai Hähnle [Wed, 28 Sep 2016 16:20:32 +0000 (18:20 +0200)]
gallium/radeon: cleanup and fix branch emits

Some of the existing code is needlessly complicated. The basic principle
should be: control-flow opcodes emit branches to properly terminate the
current block, _unless_ the current block already has a terminator (which
happens if and only if there was a BRK or CONT).

This also fixes a bug where multiple terminators were created in a block.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97887
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agowinsys/radeon: add buffer_get_reloc_offset
Nicolai Hähnle [Tue, 4 Oct 2016 08:50:55 +0000 (10:50 +0200)]
winsys/radeon: add buffer_get_reloc_offset

Really fix the bug that was supposed to be fixed by commits 3e7cced4b and
a48bf02d: even when virtual addresses are used, the legacy relocation-based
method with offsets relative to the kernel's buffer object are used for
video submissions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: don't declare LDS in PS when ds_bpermute is used
Marek Olšák [Sun, 2 Oct 2016 20:01:38 +0000 (22:01 +0200)]
radeonsi: don't declare LDS in PS when ds_bpermute is used

I guess this is not needed because dead code elimination removes
the declaration.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: use DDX/DDY directly in si_llvm_emit_ddxy_interp
Marek Olšák [Sun, 2 Oct 2016 19:56:00 +0000 (21:56 +0200)]
radeonsi: use DDX/DDY directly in si_llvm_emit_ddxy_interp

We can finally do this, because the opcodes are scalar now.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: simplify si_llvm_emit_ddxy
Marek Olšák [Sun, 2 Oct 2016 19:37:13 +0000 (21:37 +0200)]
radeonsi: simplify si_llvm_emit_ddxy

si_llvm_emit_ddxy is called once per element, so we don't have to generate
code for 4 elements at once.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: don't call build_gep0 in si_llvm_emit_ddxy on VI
Marek Olšák [Sun, 2 Oct 2016 19:23:26 +0000 (21:23 +0200)]
radeonsi: don't call build_gep0 in si_llvm_emit_ddxy on VI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: use a helper function for BuildGEP(0, x)
Marek Olšák [Sun, 2 Oct 2016 18:54:30 +0000 (20:54 +0200)]
radeonsi: use a helper function for BuildGEP(0, x)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: remove obsolete shader definitions
Marek Olšák [Sun, 2 Oct 2016 18:21:19 +0000 (20:21 +0200)]
radeonsi: remove obsolete shader definitions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: remove unnecessary #includes
Marek Olšák [Sun, 2 Oct 2016 15:52:46 +0000 (17:52 +0200)]
radeonsi: remove unnecessary #includes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: clean up lucky #include dependencies
Marek Olšák [Sun, 2 Oct 2016 15:40:49 +0000 (17:40 +0200)]
radeonsi: clean up lucky #include dependencies

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: don't re-create shader PM4 states after scratch buffer update
Marek Olšák [Sat, 11 Jun 2016 19:07:14 +0000 (21:07 +0200)]
radeonsi: don't re-create shader PM4 states after scratch buffer update

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agogallium/radeon: move r600_common_context::texture_buffers to r600g
Marek Olšák [Sun, 2 Oct 2016 14:12:47 +0000 (16:12 +0200)]
gallium/radeon: move r600_common_context::texture_buffers to r600g

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: don't set sampler buffer offsets in create_sampler_view
Marek Olšák [Sun, 2 Oct 2016 14:05:51 +0000 (16:05 +0200)]
radeonsi: don't set sampler buffer offsets in create_sampler_view

do it at bind time, so that pipe_sampler_view is immutable with regard to
buffer reallocations and we don't have to remember all existing buffer
views.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: optimize si_invalidate_buffer based on bind_history
Marek Olšák [Sun, 2 Oct 2016 13:50:15 +0000 (15:50 +0200)]
radeonsi: optimize si_invalidate_buffer based on bind_history

Just enclose each section with: if (rbuffer->bind_history & PIPE_BIND_...)

Bioshock Infinite: +1% performance

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: track buffer bind history
Marek Olšák [Sun, 2 Oct 2016 13:45:15 +0000 (15:45 +0200)]
radeonsi: track buffer bind history

similar to gl_buffer_object::UsageHistory

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: drop support for NULL sampler views
Marek Olšák [Sun, 2 Oct 2016 13:40:10 +0000 (15:40 +0200)]
radeonsi: drop support for NULL sampler views

not used anymore. It was used when the polygon stipple texture was constant.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: separate IA_MULTI_VGT_PARAM and VGT_PRIMITIVE_TYPE emission
Marek Olšák [Fri, 30 Sep 2016 20:47:20 +0000 (22:47 +0200)]
radeonsi: separate IA_MULTI_VGT_PARAM and VGT_PRIMITIVE_TYPE emission

We want to emit IA_MULTI_VGT_PARAM less often because it's a context reg.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: move VGT_LS_HS_CONFIG to derived tess_state
Marek Olšák [Fri, 30 Sep 2016 20:37:14 +0000 (22:37 +0200)]
radeonsi: move VGT_LS_HS_CONFIG to derived tess_state

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER
Marek Olšák [Fri, 30 Sep 2016 22:46:39 +0000 (00:46 +0200)]
radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER

Caches are always flushed at IB boundary.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: parse SURFACE_SYNC correctly on CIK-VI
Marek Olšák [Fri, 30 Sep 2016 18:20:32 +0000 (20:20 +0200)]
radeonsi: parse SURFACE_SYNC correctly on CIK-VI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agogallium/radeon: inline r600_context_add_resource_size
Marek Olšák [Sun, 2 Oct 2016 13:36:19 +0000 (15:36 +0200)]
gallium/radeon: inline r600_context_add_resource_size

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
8 years agoradeonsi: Fix primitive restart when index changes
James Legg [Tue, 4 Oct 2016 13:30:11 +0000 (14:30 +0100)]
radeonsi: Fix primitive restart when index changes

If primitive restart is enabled for two consecutive draws which use
different primitive restart indices, then the first draw's primitive
restart index was incorrectly used for the second draw.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98025

Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agospirv: replace assert() with unreachable()
Timothy Arceri [Tue, 4 Oct 2016 00:25:25 +0000 (11:25 +1100)]
spirv: replace assert() with unreachable()

This fixes an uninitialized warning for is_vertex_input.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agointel: use the correct format specifier for printing uint64_t
Timothy Arceri [Tue, 4 Oct 2016 01:03:14 +0000 (12:03 +1100)]
intel: use the correct format specifier for printing uint64_t

Fixes a bunch of warnings in 32-bit builds.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agogallium/winsys: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Matt Whitlock [Sun, 2 Oct 2016 03:49:45 +0000 (23:49 -0400)]
gallium/winsys: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agost/xa: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Matt Whitlock [Sun, 2 Oct 2016 03:49:44 +0000 (23:49 -0400)]
st/xa: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agost/dri: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Matt Whitlock [Sun, 2 Oct 2016 03:49:43 +0000 (23:49 -0400)]
st/dri: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agogallium/auxiliary: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Matt Whitlock [Sun, 2 Oct 2016 03:49:42 +0000 (23:49 -0400)]
gallium/auxiliary: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoegl/android: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Matt Whitlock [Sun, 2 Oct 2016 03:49:41 +0000 (23:49 -0400)]
egl/android: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agointel: fix compilation warning on gen_get_device_info
Tapani Pälli [Mon, 3 Oct 2016 06:32:54 +0000 (09:32 +0300)]
intel: fix compilation warning on gen_get_device_info

(warning: 'const' type qualifier on return type has no effect)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
8 years agoi965: Only emit 1 viewport when possible.
Kenneth Graunke [Mon, 26 Sep 2016 17:30:30 +0000 (10:30 -0700)]
i965: Only emit 1 viewport when possible.

In core profile, we support up to 16 viewports.  However, in the
majority of cases, only 1 of them is actually used - we only need
the others if the last shader stage prior to the rasterizer writes
gl_ViewportIndex.

Processing all 16 viewports adds additional CPU overhead, which hurts
CPU-intensive workloads such as Glamor.  This meant that switching to
core profile actually penalized Glamor to an extent, which is
unfortunate.

This patch tracks the number of relevant viewports, switching between
1 and ctx->Const.MaxViewports if gl_ViewportIndex is written.  A new
BRW_NEW_VIEWPORT_COUNT flag tracks this.  This could mean re-emitting
viewport state when switching, but hopefully this is offset by doing
1/16th of the work in the common case.  The new flag is also lighter
weight than BRW_NEW_VUE_MAP_GEOM_OUT, which we were using in one case.

According to Eric Anholt, x11perf -copypixwin10 performance improves by
11.5094% +/- 3.10841% (n=10) on his Skylake.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
8 years agospirv: translate cull distance semantic.
Dave Airlie [Mon, 29 Aug 2016 00:18:15 +0000 (10:18 +1000)]
spirv: translate cull distance semantic.

This just translates to the correct cull distance slot.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agocompiler: add printable values for cull distance varyings.
Dave Airlie [Mon, 29 Aug 2016 00:17:16 +0000 (10:17 +1000)]
compiler: add printable values for cull distance varyings.

We need these for spir-v/nir shaders.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agonir/spirv/cfg: Use a nop intrinsic for tagging the ends of blocks
Jason Ekstrand [Fri, 16 Sep 2016 04:12:34 +0000 (21:12 -0700)]
nir/spirv/cfg: Use a nop intrinsic for tagging the ends of blocks

Previously, we were saving off the last nir_block in a vtn_block before
moving on so that we could find the nir_block again when it came time to
handle phi sources.  Unfortunately, NIR's control flow modification code is
inconsistent when it comes to how it splits blocks so the block pointer we
saved off may point to a block somewhere else in the shader by the time we
get around to handling phi sources.  In order to get around this, we insert
a nop instruction and use that as the logical end of our block.  Since the
control flow manipulation code respects instructions, the nop will keeps
its place like any other instruction and we can easily find the end of our
block when we need it.

This fixes a bug triggered by a couple of vkQuake shaders.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97233
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agonir: Add a nop intrinsic
Jason Ekstrand [Fri, 16 Sep 2016 04:02:37 +0000 (21:02 -0700)]
nir: Add a nop intrinsic

This intrinsic has no destination, no sources, no variables, and can be
eliminated.  In other words, it does nothing and will always get deleted by
dead code elimination.  However, it does provide a quick-and-easy way to
temporarily tag a particular location in a NIR shader.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
8 years agointel/isl: Allow non-2D HiZ surfaces
Jason Ekstrand [Tue, 13 Sep 2016 00:56:38 +0000 (17:56 -0700)]
intel/isl: Allow non-2D HiZ surfaces

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Add a detailed comment about multisampling with HiZ
Jason Ekstrand [Fri, 2 Sep 2016 22:45:18 +0000 (15:45 -0700)]
intel/isl: Add a detailed comment about multisampling with HiZ

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Remove tiling checks from choose_msaa_layout
Jason Ekstrand [Fri, 2 Sep 2016 05:25:50 +0000 (22:25 -0700)]
intel/isl: Remove tiling checks from choose_msaa_layout

We already do those checks in filter_tiling.  There's no good reason to
repeat them in choose_msaa_layout.  If anything they should have been
asserts and not "return false" checks.  Also, this check was causing us to
outright reject multisampled HiZ surfaces which wasn't intended.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Handle HiZ and CCS tiling more directly
Jason Ekstrand [Fri, 2 Sep 2016 05:01:47 +0000 (22:01 -0700)]
intel/isl: Handle HiZ and CCS tiling more directly

The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces
respectively.  There's no reason why we should go through filter_tiling and
it's much easier to always get HiZ and CCS right if we just handle them
directly.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Allow multisampling with ISL_FORMAT_HiZ
Jason Ekstrand [Fri, 2 Sep 2016 01:57:18 +0000 (18:57 -0700)]
intel/isl: Allow multisampling with ISL_FORMAT_HiZ

HiZ buffers can be multisampled and, on Broadwell and earlier, simply using
interleaved multisampling with a compression block size of 8x4 samples
yields the correct HiZ surface size calculations.  Unfortunately,
choose_msaa_layout was rejecting multisampled HiZ buffers because of format
checks.  Now that we have a simple helper for determining if a format
supports multisampling, that's an easy enough issue to fix.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Allow creation of 1-D compressed textures
Jason Ekstrand [Tue, 13 Sep 2016 00:43:28 +0000 (17:43 -0700)]
intel/isl: Allow creation of 1-D compressed textures

Compressed 1-D textures are not well-defined thing in either GL or Vulkan.
However, auxiliary surfaces are treated as compressed textures in ISL and
we can do HiZ and CCS with 1-D so we need to be able to create them.  In
order to prevent actually using them (the docs say no), we assert in the
state setup code.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Fix up asserts in calc_phys_level0_extent_sa
Jason Ekstrand [Fri, 2 Sep 2016 02:52:38 +0000 (19:52 -0700)]
intel/isl: Fix up asserts in calc_phys_level0_extent_sa

The assertion that a format is uncompressed in the multisample layouts
isn't quite right.  What we really want to assert is that the format
supports multisampling which is a bit more complicated query.  We also want
to assert that it has a block size of 1x1 since we do nothing with the
block size in the phys_level0_sa assignment.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agointel/isl: Add a format_supports_multisampling helper
Jason Ekstrand [Fri, 2 Sep 2016 01:57:01 +0000 (18:57 -0700)]
intel/isl: Add a format_supports_multisampling helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
8 years agovl/dri3: fix warning about incompatible pointer type
Nayan Deshmukh [Sat, 1 Oct 2016 05:22:52 +0000 (10:52 +0530)]
vl/dri3: fix warning about incompatible pointer type

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
8 years agoswr: Removed stalling SwrWaitForIdle from queries.
Bruce Cherniak [Tue, 27 Sep 2016 18:27:08 +0000 (13:27 -0500)]
swr: Removed stalling SwrWaitForIdle from queries.

Previous fundamental change in stats gathering added a temporary
SwrWaitForIdle to begin_query and end_query.  Code has been reworked to
remove stall.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
8 years agoswr: [rasterizer core] refactor thread creation
Tim Rowley [Fri, 30 Sep 2016 21:05:19 +0000 (16:05 -0500)]
swr: [rasterizer core] refactor thread creation

Create worker pool now computes number of worker threads based on
things like topologies, etc. and creates the pool but doesn't actually
launch the threads. Instead there is a separate start thread pool
function. This allows thread resources to be constructed first before
threads start.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agoswr: [rasterizer jitter] canonicalize blend compile state
Tim Rowley [Fri, 30 Sep 2016 20:18:13 +0000 (15:18 -0500)]
swr: [rasterizer jitter] canonicalize blend compile state

Canonicalize to prevent unnecessary JIT compiles.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agoswr: [rasterizer core] archrast fixes
Tim Rowley [Thu, 22 Sep 2016 23:00:47 +0000 (18:00 -0500)]
swr: [rasterizer core] archrast fixes

- Immediately sleep threads until thread data is initialized
- Fix some compile bugs with AR enabled

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agoswr: [rasterizer jitter] fixes for icc in vs2015 compat mode
Tim Rowley [Tue, 20 Sep 2016 22:14:54 +0000 (17:14 -0500)]
swr: [rasterizer jitter] fixes for icc in vs2015 compat mode

- Move most jitter functionality into SwrJit namespace
- Avoid global "using namespace llvm" in headers

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agoswr: [rasterizer core] generalize compute dispatch mechanism
Tim Rowley [Wed, 21 Sep 2016 18:39:44 +0000 (13:39 -0500)]
swr: [rasterizer core] generalize compute dispatch mechanism

Generalize compute dispatch mechanism to support other types of dispatches.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agoswr: [rasterizer common] os.h portability header changes
Tim Rowley [Wed, 21 Sep 2016 04:55:24 +0000 (23:55 -0500)]
swr: [rasterizer common] os.h portability header changes

- Fix conflict between windows MemoryFence and llvm::sys::MemoryFence
- Declare gettid()

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agoanv/formats: Fix build on gcc-4 and earlier
Ville Syrjälä [Fri, 30 Sep 2016 20:00:22 +0000 (23:00 +0300)]
anv/formats: Fix build on gcc-4 and earlier

gcc-4 and earlier don't allow compound literals where a constant
is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
when populating the anv_formats[] array. There are a few ways around
it: First one would be -std=c89/gnu89, but the rest of the code
depends on c99 so it's not really an option. The second option
would be to upgrade to gcc-5+ where the compiler behaviour was relaxed
a bit [1]. And the third option is just to avoid using compound
literals. I chose the last option since it keeps gcc-4 and earlier
working.

[1] https://gcc.gnu.org/gcc-5/porting_to.html

Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes: 7ddb21708c80 ("intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoegl: stop claiming support for pbuffer + msaa
Tapani Pälli [Mon, 26 Sep 2016 07:03:32 +0000 (10:03 +0300)]
egl: stop claiming support for pbuffer + msaa

This fixes a crash in egl-create-msaa-pbuffer-surface Piglit test
and same crash in many dEQP EGL tests.

I also found that some Qt example did a workaround because of this
crash: https://bugreports.qt.io/browse/QTBUG-47509

v2: Ian pointed out that v1 removed support for all multisample
    configs, including window ones. This one removes pbuffer bit
    when adding configs, now only pbuffer+msaa gets rejected and
    window+msaa continues to work. Fixed also comment (Emil)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
8 years agoi965: rename max_ds_* variable to max_tes_*
Timothy Arceri [Sun, 2 Oct 2016 23:39:29 +0000 (10:39 +1100)]
i965: rename max_ds_* variable to max_tes_*

Using consistent naming allows us to create macros more easily.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: rename max_hs_* variables to max_tcs_*
Timothy Arceri [Sun, 2 Oct 2016 23:39:28 +0000 (10:39 +1100)]
i965: rename max_hs_* variables to max_tcs_*

Using consistent naming allows us to create macros more easily.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: Drop pointless stage == MESA_SHADER_FRAGMENT checks.
Kenneth Graunke [Fri, 9 Sep 2016 07:12:58 +0000 (00:12 -0700)]
i965: Drop pointless stage == MESA_SHADER_FRAGMENT checks.

There's an assert right above this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoglsl: add missing headers to blob.h
Timothy Arceri [Sat, 1 Oct 2016 01:45:22 +0000 (11:45 +1000)]
glsl: add missing headers to blob.h

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agonir/spirv/cfg: Detect switch_break after loop_break/continue
Jason Ekstrand [Sat, 17 Sep 2016 05:04:57 +0000 (22:04 -0700)]
nir/spirv/cfg: Detect switch_break after loop_break/continue

While the current CFG code is valid in the case where a switch break also
happens to be a loop continue, it's a bit suboptimal.  Since hardware is
capable of handling the continue as a direct jump, it's better to use a
continue instruction when we can than to bother with all of the nasty
switch break lowering.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
8 years agonir/spirv/cfg: Handle switches whose break block is a loop continue
Jason Ekstrand [Sat, 17 Sep 2016 04:55:08 +0000 (21:55 -0700)]
nir/spirv/cfg: Handle switches whose break block is a loop continue

It is possible that the break block of a switch is actually the continue of
the loop containing the switch.  In this case, we need to identify the
break block as a continue and break out of current level of CFG handling.
If we don't, the continue portion of the loop will get handled twice, once
by following after the break and a second time by the loop handling code
handling it explicitly.

This fixes 6 of the new Vulkan CTS tests:
 - dEQP-VK.spirv_assembly.instruction.graphics.opphi.out_of_order*
 - dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order*

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
8 years agonir/spirv: add spirv2nir binary to .gitignore
Eric Engestrom [Sun, 25 Sep 2016 15:49:53 +0000 (16:49 +0100)]
nir/spirv: add spirv2nir binary to .gitignore

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agonir/spirv: improve mmap() error handling
Eric Engestrom [Sun, 25 Sep 2016 15:49:52 +0000 (16:49 +0100)]
nir/spirv: improve mmap() error handling

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agonir/spirv: improve lseek() error handling
Eric Engestrom [Sun, 25 Sep 2016 15:49:51 +0000 (16:49 +0100)]
nir/spirv: improve lseek() error handling

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agonir/spirv: add some error checking to open()
Eric Engestrom [Sun, 25 Sep 2016 15:49:50 +0000 (16:49 +0100)]
nir/spirv: add some error checking to open()

CovID: 1373369
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agomesa: use uint32_t rather than unsigned for xfb struct members
Timothy Arceri [Fri, 30 Sep 2016 23:20:26 +0000 (09:20 +1000)]
mesa: use uint32_t rather than unsigned for xfb struct members

These structs will be written to disk as part of the shader cache
so use uint32_t just to be safe.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi915/i965: remove commented out warning
Timothy Arceri [Fri, 30 Sep 2016 06:37:03 +0000 (16:37 +1000)]
i915/i965: remove commented out warning

The warning was also the wrong location, it should have been
in the else.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
8 years agomesa: move _mesa_valid_to_render() to api_validate.c
Brian Paul [Fri, 30 Sep 2016 16:25:05 +0000 (10:25 -0600)]
mesa: move _mesa_valid_to_render() to api_validate.c

Almost all of the other drawing validation code is in api_validate.c
so put this function there as well.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
8 years agogallium/hud: Add support for CPU frequency monitoring
Steven Toth [Fri, 30 Sep 2016 11:58:00 +0000 (05:58 -0600)]
gallium/hud: Add support for CPU frequency monitoring

Detect all of the CPUs in the system. Expose metrics
for min, max and current frequency in Hz.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agoRevert "gallium/hud: automatically print % if max_value == 100"
Marek Olšák [Fri, 30 Sep 2016 10:55:08 +0000 (12:55 +0200)]
Revert "gallium/hud: automatically print % if max_value == 100"

This reverts commit dbfeb0ec12d6550e68de1bcd164e422e79bccf2d.

With max_value being rounded to 100, it's often wrong.

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agodocs: update the list of Mesa major versions and API support
Brian Paul [Fri, 30 Sep 2016 13:18:13 +0000 (07:18 -0600)]
docs: update the list of Mesa major versions and API support

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
8 years agogallium/radeon: fix crash/regression in performance counters
Nicolai Hähnle [Fri, 30 Sep 2016 10:00:44 +0000 (12:00 +0200)]
gallium/radeon: fix crash/regression in performance counters

Regression introduced by "gallium/radeon: zero all query buffers".

Cc: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: update documentation of buffer_get_virtual_address
Nicolai Hähnle [Thu, 29 Sep 2016 14:47:27 +0000 (16:47 +0200)]
gallium/radeon: update documentation of buffer_get_virtual_address

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: emit relocations for query fences
Nicolai Hähnle [Fri, 30 Sep 2016 09:46:47 +0000 (11:46 +0200)]
gallium/radeon: emit relocations for query fences

This is only needed for r600 which doesn't have ARB_query_buffer_object and
therefore wouldn't really need the fences, but let's be optimistic about
filling in this feature gap eventually.

Cc: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeon/uvd: adjust the buffer offset when relocation is used
Nicolai Hähnle [Thu, 29 Sep 2016 14:50:10 +0000 (16:50 +0200)]
radeon/uvd: adjust the buffer offset when relocation is used

We don't plan to use sub-allocated buffers with UVD, but just in case one
slips through, this increases the chances of things working out anyway.

Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agoradeon/vce: adjust the buffer offset when relocation is used
Nicolai Hähnle [Thu, 29 Sep 2016 14:47:53 +0000 (16:47 +0200)]
radeon/vce: adjust the buffer offset when relocation is used

We don't plan to use sub-allocated buffers with VCE, but just in case one
slips through, this increases the chances of things working out anyway.

Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agoradeon/video: don't use sub-allocated buffers
Nicolai Hähnle [Fri, 30 Sep 2016 09:26:13 +0000 (11:26 +0200)]
radeon/video: don't use sub-allocated buffers

Cc: Christian König <christian.koenig@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agogallium/hud: Add power sensor support
Steven Toth [Thu, 29 Sep 2016 14:11:00 +0000 (08:11 -0600)]
gallium/hud: Add power sensor support

Implement support for power based sensors, reporting units in
milli-watts and watts.

Also, minor cleanup - change the related if block to a switch.

Tested with two different power sensors, including the nouveau
'power1' sensors on a GTX950 card.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agonv50/ir: teach insnCanLoad() about SHLADD
Samuel Pitoiset [Wed, 14 Sep 2016 21:02:38 +0000 (23:02 +0200)]
nv50/ir: teach insnCanLoad() about SHLADD

Commutativity is not allowed with SHLADD, but src2 can accept
loads. To allow the load propagation pass to do its job, add a
special case like for SUCLAMP because src1 is always an immediate.

This IMAD to SHLADD optimization helps a bunch of shaders from Tomb
Raider, Victor Vran, UE4 demos (+15% perf with Elemental) and Shadow
Warrior.

GF100/GK104:

total instructions in shared programs :2838045 -> 2834712 (-0.12%)
total gprs used in shared programs    :396684 -> 396386 (-0.08%)
total local used in shared programs   :34416 -> 34416 (0.00%)

                local        gpr       inst      bytes
    helped           0         326        1105        1105
      hurt           0          55           3           3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: optimize SHLADD(a, b, c) to MOV((a << b) + c)
Samuel Pitoiset [Wed, 14 Sep 2016 20:15:14 +0000 (22:15 +0200)]
nv50/ir: optimize SHLADD(a, b, c) to MOV((a << b) + c)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: optimize SHLADD(a, b, 0x0) to SHL(a, b)
Samuel Pitoiset [Wed, 14 Sep 2016 16:57:02 +0000 (18:57 +0200)]
nv50/ir: optimize SHLADD(a, b, 0x0) to SHL(a, b)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: optimize IMAD to SHLADD in presence of power of 2
Samuel Pitoiset [Wed, 14 Sep 2016 16:49:36 +0000 (18:49 +0200)]
nv50/ir: optimize IMAD to SHLADD in presence of power of 2

Only and only if src1 is a power of 2 we can replace IMAD by SHLADD.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonvc0/ir: add emission for SHLADD
Samuel Pitoiset [Wed, 14 Sep 2016 22:18:25 +0000 (00:18 +0200)]
nvc0/ir: add emission for SHLADD

Unfortunately, we can't use the emit helpers for GF100/GK110
because src1 and src2 are swapped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: add preliminary support for SHLADD
Samuel Pitoiset [Wed, 14 Sep 2016 14:42:45 +0000 (16:42 +0200)]
nv50/ir: add preliminary support for SHLADD

This instruction is available since SM20 (Fermi) and allow to do
(a << b) + c in one shot. In some situations, IMAD should be
replaced by SHLADD when b is a power of 2, and ADD+SHL should be
replaced by SHLADD as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonvc0: update GM107 sched control codes format
Samuel Pitoiset [Tue, 27 Sep 2016 20:08:11 +0000 (22:08 +0200)]
nvc0: update GM107 sched control codes format

envyas now uses a much better representation for those control
codes and it displays the different flags instead of an
unreadable hex number.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agogallium/radeon: use smaller buffers for query results
Nicolai Hähnle [Tue, 27 Sep 2016 14:52:42 +0000 (16:52 +0200)]
gallium/radeon: use smaller buffers for query results

Most of the time, even the 512 bytes that we now get is more than sufficient
(pipeline stats queries are the largest at 184 bytes per shot).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon/winsyses: add radeon_winsys::min_alloc_size
Nicolai Hähnle [Tue, 27 Sep 2016 14:51:46 +0000 (16:51 +0200)]
gallium/radeon/winsyses: add radeon_winsys::min_alloc_size

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: enable ARB_query_buffer_object (v2)
Nicolai Hähnle [Wed, 14 Sep 2016 07:43:42 +0000 (09:43 +0200)]
radeonsi: enable ARB_query_buffer_object (v2)

v2: enable only when compute is available

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: implement get_query_result_resource (v2)
Nicolai Hähnle [Wed, 14 Sep 2016 10:00:50 +0000 (12:00 +0200)]
gallium/radeon: implement get_query_result_resource (v2)

v2: fix a comment (Gustaw Smolarczyk)

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: zero all query buffers
Nicolai Hähnle [Thu, 15 Sep 2016 13:58:36 +0000 (15:58 +0200)]
gallium/radeon: zero all query buffers

To ensure that fences are properly initialized.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: cleanup getting PIPE_QUERY_TIMESTAMP result
Nicolai Hähnle [Thu, 15 Sep 2016 10:18:24 +0000 (12:18 +0200)]
gallium/radeon: cleanup getting PIPE_QUERY_TIMESTAMP result

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: add query fences and r600_get_hw_query_params
Nicolai Hähnle [Wed, 14 Sep 2016 08:38:33 +0000 (10:38 +0200)]
gallium/radeon: add query fences and r600_get_hw_query_params

We will support the waiting option in ARB_query_buffer_object using
WAIT_REG_MEM on an appropriate fence-like dword. Some queries conveniently
write their results with the highest bit set, and we can just use that;
for others, we have to write a fence explicitly.

ZPASS_DONE for occlusion queries writes its results with the high bit
set, but it writes up to 8 pairs of results (one for each DB). We have
to wait for all of these results, so let's just add an explicit fence.

The new function provides summary information to be used by subsequent
patches.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: add save_qbo_state
Nicolai Hähnle [Wed, 14 Sep 2016 07:46:36 +0000 (09:46 +0200)]
radeonsi: add save_qbo_state

Save compute shader state that will be used for the ARB_query_buffer_object
implementation.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: add si_get_shader_buffers/get_pipe_constant_buffers (v2)
Nicolai Hähnle [Wed, 14 Sep 2016 07:45:37 +0000 (09:45 +0200)]
radeonsi: add si_get_shader_buffers/get_pipe_constant_buffers (v2)

These functions extract the pipe state structure from the current
descriptors, for state saving.

v2: correctly dereference *buf (Bas)

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: add r600_gfx_{write,wait}_fence
Nicolai Hähnle [Wed, 14 Sep 2016 13:43:18 +0000 (15:43 +0200)]
gallium/radeon: add r600_gfx_{write,wait}_fence

For bottom-of-pipe fences inside the gfx command stream.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: add barrier_flags to r600_common_screen
Nicolai Hähnle [Thu, 15 Sep 2016 14:24:17 +0000 (16:24 +0200)]
gallium/radeon: add barrier_flags to r600_common_screen

There are driver-specific context flags for barriers that are not covered
by the Gallium barrier interfaces.

The R600 settings of these flags may not be optimal, but we're not going
to use them yet anyway.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoglsl: remove remaining tabs from ast_type.cpp
Timothy Arceri [Wed, 28 Sep 2016 06:04:09 +0000 (16:04 +1000)]
glsl: remove remaining tabs from ast_type.cpp

Acked-by: Dave Airlie <airlied@redhat.com>
8 years agoglsl: remove remaining tabs from ast_to_hir.cpp
Timothy Arceri [Wed, 28 Sep 2016 06:04:08 +0000 (16:04 +1000)]
glsl: remove remaining tabs from ast_to_hir.cpp

Acked-by: Dave Airlie <airlied@redhat.com>
8 years agoglsl: remove remaining tabs from ast_array_index.cpp
Timothy Arceri [Wed, 28 Sep 2016 06:04:07 +0000 (16:04 +1000)]
glsl: remove remaining tabs from ast_array_index.cpp

Acked-by: Dave Airlie <airlied@redhat.com>
8 years agoglsl: remove tabs from ast_expr.cpp
Timothy Arceri [Wed, 28 Sep 2016 06:04:06 +0000 (16:04 +1000)]
glsl: remove tabs from ast_expr.cpp

Acked-by: Dave Airlie <airlied@redhat.com>