platform/upstream/mesa.git
2 years agor300: remove some dead logic in tex pair scheduling
Pavel Ondračka [Thu, 3 Mar 2022 11:24:37 +0000 (12:24 +0100)]
r300: remove some dead logic in tex pair scheduling

The max_score == -1 condition is already before so this
will never trigger. Its unclear what was the intention anyway. Now we
emit either:
- if we have accumulated enough tex intructions for a full block
- if we have nothing else to emit
- or if we can emit all remaining tex instructions already.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15165>

2 years agoVenus: Add `vn_physical_device_{features, properties}` for better organization
Igor Torrente [Mon, 28 Feb 2022 11:59:41 +0000 (08:59 -0300)]
Venus: Add `vn_physical_device_{features, properties}` for better organization

New extensions properties/feature are being put in the `vn_physical_device`
which is not ideal from an organization point of view.

Here the `vn_physical_device_{features,properties}` are two new struct to
help the `vn_physical_device` organzation.

Signed-off-by: Igor Torrente <igor.torrente@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15170>

2 years agofreedreno/a4xx: fix integer tg4
Ilia Mirkin [Mon, 29 Nov 2021 06:44:32 +0000 (01:44 -0500)]
freedreno/a4xx: fix integer tg4

Something is slightly off in the integer values returned. It passes many
tests without the fixup, but the dEQP-GLES31 tests complain. The blob
ends up doing 3x gathers, and selects between them based on getinfo
results. Since we already have a per-sampler key with some spare bits,
just stick the bit-size info in there. And we can derive signedness from
the associated type info.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14670>

2 years agofreedreno/a4xx: add swizzles to shader keys for tg4 workaround
Ilia Mirkin [Sun, 14 Nov 2021 09:38:04 +0000 (04:38 -0500)]
freedreno/a4xx: add swizzles to shader keys for tg4 workaround

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14670>

2 years agofreedreno/a4xx: move tex_type to header
Ilia Mirkin [Sun, 23 Jan 2022 17:14:43 +0000 (12:14 -0500)]
freedreno/a4xx: move tex_type to header

This will be used in several places. Factor it out for common use.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14670>

2 years agonir: remove bogus logic to allow cube + offset to work
Ilia Mirkin [Sun, 14 Nov 2021 06:01:47 +0000 (01:01 -0500)]
nir: remove bogus logic to allow cube + offset to work

This was done for an a4xx hack which is now removed. No API allows cube
texturing to have offsets.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14670>

2 years agofreedreno/ir3: remove bogus tg4 -> tex lowering pass
Ilia Mirkin [Sun, 14 Nov 2021 05:58:30 +0000 (00:58 -0500)]
freedreno/ir3: remove bogus tg4 -> tex lowering pass

It can't be done. This just provides bad results. The blob had a
comparable approach where they fixed up coordinates, but that also can't
work with a separate texture definition with nearest filtering. By then,
might as well provide a unswizzled variant instead, and using native
functionality.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14670>

2 years agor300/compiler/tests: print regoff_t as size_t
Alex Xu (Hello71) [Wed, 24 Nov 2021 23:01:29 +0000 (18:01 -0500)]
r300/compiler/tests: print regoff_t as size_t

fixes compilation on musl

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13949>

2 years agoradv,aco: do not lower nir_op_pack_{unorm,snorm}_2x16
Samuel Pitoiset [Wed, 2 Mar 2022 14:47:03 +0000 (15:47 +0100)]
radv,aco: do not lower nir_op_pack_{unorm,snorm}_2x16

v_cvt_pknorm_{u16,i16}_f32 can be emitted instead, it's supported on
all generations.

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15215>

2 years agovulkan/wsi: drop unused wsi_create_win32_image
Michel Zou [Fri, 18 Feb 2022 20:03:33 +0000 (21:03 +0100)]
vulkan/wsi: drop unused wsi_create_win32_image

fixes: ed391d2a

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15088>

2 years agoglsl: add member's location layout qualifier rules for `arrayed` in/out blocks
Andrii Simiklit [Fri, 31 Jul 2020 11:53:25 +0000 (14:53 +0300)]
glsl: add member's location layout qualifier rules for `arrayed` in/out blocks

From Section 4.4.1 (Input Layout Qualifiers) of the GLSL 4.50 spec:

     "For some blocks declared as arrays, the location can only be applied
     at the block level: When a block is declared as an array where
     additional locations are needed for each member for each block array
     element, it is a compile-time error to specify locations on the block
     members. That is, when locations would be under specified by applying
     them on block members, they are not allowed on block members. For
     arrayed interfaces (those generally having an extra level of
     arrayness due to interface expansion), the outer array is stripped
     before applying this rule"

From Section 1.2.1 (Changes from Revision 6 of GLSL Version) of the GLSL 4.50 spec:

     "Private Bug 15678: Don’t allow location = on block members where
      the block needs an array of locations"

From Section 4.4.1 (Input Layout Qualifiers) of the GLSL ES 3.20 spec

     "If an input is declared as an array of blocks, excluding per-vertex-arrays
      as required for tessellation, it is an error to declare a member of
      the block with a location qualifier"

From Section 1.1.3 (Changes from GLSL ES 3.2 revision 3) of the GLSL ES 3.20 spec:

     "Arrayed blocks cannot have layout location qualifiers on members"

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11522>

2 years agozink: ci updates
Mike Blumenkrantz [Thu, 3 Mar 2022 05:07:45 +0000 (00:07 -0500)]
zink: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>

2 years agozink: split primitives generated queries if xfb/gs states change
Mike Blumenkrantz [Wed, 2 Mar 2022 21:20:49 +0000 (16:20 -0500)]
zink: split primitives generated queries if xfb/gs states change

if one of these states change then it affects which result needs to be
used for that query, so split it up over multiple query ids to make sure
the correct result is obtained

fixes (lavapipe):
GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_pause_resume
GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_states

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>

2 years agozink: split out query suspending into util function
Mike Blumenkrantz [Wed, 2 Mar 2022 21:20:30 +0000 (16:20 -0500)]
zink: split out query suspending into util function

no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>

2 years agozink: update query states before starting renderpass during draw
Mike Blumenkrantz [Wed, 2 Mar 2022 21:19:46 +0000 (16:19 -0500)]
zink: update query states before starting renderpass during draw

this gives some leeway for doing transfer ops without crashing the renderpass

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>

2 years agonvc0: disable EXT_texture_sRGB_RG8
Ilia Mirkin [Wed, 2 Mar 2022 04:38:31 +0000 (23:38 -0500)]
nvc0: disable EXT_texture_sRGB_RG8

Looks like the green component doesn't get srgb-decoding, and no obvious
way to force it. It works fine on nv50 though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15211>

2 years agomesa: enable GL_EXT_texture_sRGB_RG8 on desktop
Ilia Mirkin [Wed, 2 Mar 2022 04:26:55 +0000 (23:26 -0500)]
mesa: enable GL_EXT_texture_sRGB_RG8 on desktop

Looks like an extension number was assigned in late 2020. This makes it
possible to hook up this format to teximage-colors without teaching it
about ES.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15211>

2 years agozink: remove loop from generated tcs
Mike Blumenkrantz [Wed, 9 Feb 2022 12:59:46 +0000 (07:59 -0500)]
zink: remove loop from generated tcs

this is already using per-vertex io, no need to add conditionals to verify

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15225>

2 years agofreedreno/registers: Add a couple regs we need for kernel
Rob Clark [Thu, 3 Mar 2022 01:11:10 +0000 (17:11 -0800)]
freedreno/registers: Add a couple regs we need for kernel

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221>

2 years agogallivm/llvmpipe: add support for NIR to the linear/aos paths.
Dave Airlie [Fri, 25 Feb 2022 00:00:25 +0000 (10:00 +1000)]
gallivm/llvmpipe: add support for NIR to the linear/aos paths.

When the AOS/linear code was added it only worked with TGSI which
meant nothing in mesa upstream was really using it.

This adds support to analyse NIR shaders, and adds aos support
to the backend.

AOS support is limited to mov,vec,fmul,tex sampling in order to
accelerate mostly compositing operations. I've tested weston uses
the fast path. gnome-shell can't use it yet as we can't optimise
the depth test paths.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15140>

2 years agogallivm/nir: split load_const out into backend helper.
Dave Airlie [Thu, 24 Feb 2022 23:05:11 +0000 (09:05 +1000)]
gallivm/nir: split load_const out into backend helper.

This just makes adding aos support easier.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15140>

2 years agollvmpipe/linear: fix disk caching.
Dave Airlie [Tue, 22 Feb 2022 23:26:05 +0000 (09:26 +1000)]
llvmpipe/linear: fix disk caching.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15140>

2 years agozink: switch to u_foreach_bit for ntv image access decorations
Mike Blumenkrantz [Wed, 2 Mar 2022 18:36:00 +0000 (13:36 -0500)]
zink: switch to u_foreach_bit for ntv image access decorations

no functional changes

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15217>

2 years agozink: emit Aliased decorations for any image that isn't explicitly marked restrict
Mike Blumenkrantz [Wed, 2 Mar 2022 18:36:21 +0000 (13:36 -0500)]
zink: emit Aliased decorations for any image that isn't explicitly marked restrict

these might be aliased

fixes:
arb_shader_image_load_store-restrict

fixes #6090

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15217>

2 years agozink: remove a bunch of flakes
Mike Blumenkrantz [Thu, 3 Mar 2022 00:55:07 +0000 (19:55 -0500)]
zink: remove a bunch of flakes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15219>

2 years agolavapipe: always set read/write on ssbo/images.
Dave Airlie [Thu, 3 Mar 2022 00:14:48 +0000 (10:14 +1000)]
lavapipe: always set read/write on ssbo/images.

This fixes a regressions with overlap in llvmpipe, this is pessimistic
we should write code to make it work properly.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15219>

2 years agopan/bi: Add arithmetic flag to RSHIFT ops
Alyssa Rosenzweig [Fri, 25 Feb 2022 19:53:39 +0000 (14:53 -0500)]
pan/bi: Add arithmetic flag to RSHIFT ops

Models ops like ARSHIFT_OR.i32 on Valhall without adding piles of new
instructions to the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Extend LD_TILE with a register format
Alyssa Rosenzweig [Fri, 28 Jan 2022 23:15:47 +0000 (18:15 -0500)]
pan/bi: Extend LD_TILE with a register format

Required for Valhall. NIR has the information anyway, pass it along.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Add BRANCHZI instruction
Alyssa Rosenzweig [Tue, 1 Mar 2022 20:14:13 +0000 (15:14 -0500)]
pan/bi: Add BRANCHZI instruction

Technically this is just JUMP on Valhall, but the semantic is an indirect branch
based on comparing with zero. It can also be used as a conservative branch (like
BRANCHC), but this isn't modeled.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Model LD_BUFFER instructions
Alyssa Rosenzweig [Fri, 21 Jan 2022 19:03:35 +0000 (14:03 -0500)]
pan/bi: Model LD_BUFFER instructions

We'll use these to read from UBOs on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Model offset for LOAD/STORE
Alyssa Rosenzweig [Sun, 12 Dec 2021 21:17:14 +0000 (16:17 -0500)]
pan/bi: Model offset for LOAD/STORE

Needed to model the immediate offset on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Model pos/vary segments in STORE instructions
Alyssa Rosenzweig [Wed, 8 Dec 2021 00:07:43 +0000 (19:07 -0500)]
pan/bi: Model pos/vary segments in STORE instructions

For Bifrost, we model load/store segments, for example for thread local storage.
We need something similar on Valhall -- access modifiers. There are four access
modifiers on Valhall, controlling memory subsystem optimizations for the access:

none: Nothing may be assumed. Corresponds to "global".

istream: Internally streaming within the GPU. Corresponds to "pos", as it's
used for position stores.

estream: Externally streaming outside the GPU. Corresponds to "vary", as it's
used for varying stores.

force: Force access in discarded threads. Corresponds to "tl", as it's required
for correct behaviour of helper invocations that use the stack.

If these access modifiers end up being useful outside these fixed purposes, we
may need to rework this part of the IR. For now, this should suffice.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Model LEA_BUF_IMM in the IR
Alyssa Rosenzweig [Wed, 8 Dec 2021 00:04:25 +0000 (19:04 -0500)]
pan/bi: Model LEA_BUF_IMM in the IR

Required for varying stores in malloced IDVS jobs on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions
Alyssa Rosenzweig [Tue, 7 Dec 2021 23:55:57 +0000 (18:55 -0500)]
pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions

For use on Valhall with memory-allocated IDVS jobs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Generalize I->table for Valhall
Alyssa Rosenzweig [Mon, 6 Dec 2021 22:55:10 +0000 (17:55 -0500)]
pan/bi: Generalize I->table for Valhall

Can be reused for resource tables in a natural way.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Extend BLEND to take a register format
Alyssa Rosenzweig [Thu, 29 Jul 2021 20:58:13 +0000 (16:58 -0400)]
pan/bi: Extend BLEND to take a register format

Needed on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/bi: Model Valhall texture instructions
Alyssa Rosenzweig [Wed, 2 Mar 2022 15:03:54 +0000 (10:03 -0500)]
pan/bi: Model Valhall texture instructions

These act like a TEXC+immediate.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Add memory access modifier to LOADs
Alyssa Rosenzweig [Thu, 3 Mar 2022 00:00:43 +0000 (19:00 -0500)]
pan/va: Add memory access modifier to LOADs

Might be required for correct spilling in some circumstances.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Remap "store segment" to "memory access"
Alyssa Rosenzweig [Wed, 2 Mar 2022 23:58:39 +0000 (18:58 -0500)]
pan/va: Remap "store segment" to "memory access"

For now, the difference does not matter. However it's better to model the actual
hardware behaviour, rather than isomorphic driver behaviour, when we can do so.
So fix the names.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Fix LEA_BUF_IMM definition
Alyssa Rosenzweig [Wed, 2 Mar 2022 16:19:41 +0000 (11:19 -0500)]
pan/va: Fix LEA_BUF_IMM definition

Technically the table is folded, too; the 0xD refers to table 61. But this
instruction is more general than previously thought.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Fix definitions of LD_VAR_BUF_IMM
Alyssa Rosenzweig [Wed, 2 Mar 2022 16:06:55 +0000 (11:06 -0500)]
pan/va: Fix definitions of LD_VAR_BUF_IMM

So close! However, LD_VAR_IMM is something else -- Bifrost-style varying
interpolation, without a hardware buffer. For ES3, we'll need to support both.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Add TEX_GATHER instruction
Alyssa Rosenzweig [Wed, 2 Mar 2022 15:36:57 +0000 (10:36 -0500)]
pan/va: Add TEX_GATHER instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Add TEX_DUAL instruction
Alyssa Rosenzweig [Wed, 2 Mar 2022 15:29:28 +0000 (10:29 -0500)]
pan/va: Add TEX_DUAL instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Add modifiers required for gathers
Alyssa Rosenzweig [Wed, 2 Mar 2022 15:36:43 +0000 (10:36 -0500)]
pan/va: Add modifiers required for gathers

Mostly isomorphic to Bifrost-style gathers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agopan/va: Handle force_enum differing from name
Alyssa Rosenzweig [Wed, 2 Mar 2022 15:42:47 +0000 (10:42 -0500)]
pan/va: Handle force_enum differing from name

Needed for secondary register width, for dual texturing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>

2 years agoi915g: Emit better code for SEQ(x, 0) and SNE(x, 0)
Ian Romanick [Wed, 2 Mar 2022 00:30:31 +0000 (16:30 -0800)]
i915g: Emit better code for SEQ(x, 0) and SNE(x, 0)

total instructions in shared programs: 789000 -> 788481 (-0.07%)
instructions in affected programs: 16179 -> 15660 (-3.21%)
helped: 157
HURT: 0
helped stats (abs) min: 3 max: 12 x̄: 3.31 x̃: 3
helped stats (rel) min: 1.56% max: 14.29% x̄: 4.24% x̃: 2.56%
95% mean confidence interval for instructions value: -3.51 -3.10
95% mean confidence interval for instructions %-change: -4.70% -3.78%
Instructions are helped.

LOST:   0
GAINED: 3

v2: Drop setting src1 to zero.  Suggested by Emma.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>

2 years agoi915g: Handle constants composed exclusively of 0 or ±1 specially
Ian Romanick [Tue, 1 Mar 2022 23:48:51 +0000 (15:48 -0800)]
i915g: Handle constants composed exclusively of 0 or ±1 specially

This can avoid some cases where a constant has to be loaded into a
temporary register.

v2: Update i915-g33-fails.txt.

total instructions in shared programs: 788625 -> 782376 (-0.79%)
instructions in affected programs: 166269 -> 160020 (-3.76%)
helped: 1578
HURT: 0
helped stats (abs) min: 3 max: 21 x̄: 3.96 x̃: 3
helped stats (rel) min: 1.56% max: 33.33% x̄: 4.82% x̃: 3.45%
95% mean confidence interval for instructions value: -4.06 -3.86
95% mean confidence interval for instructions %-change: -5.00% -4.64%
Instructions are helped.

LOST:   0
GAINED: 35

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>

2 years agonir/algebraic: Optimize some cases of (sXX(a, b) != 0.0)
Ian Romanick [Tue, 1 Mar 2022 23:21:02 +0000 (15:21 -0800)]
nir/algebraic: Optimize some cases of (sXX(a, b) != 0.0)

I noticed the SGE case while looking at the output of
shaders/closed/steam/trine-2/fp-3.shader_test on i915g.  These are
especially bad on i915 that needs two instructions to implement SNE.

An alternative would be to duplicate the sne(sXX(a, b), 0.0) rules in an
algebraic pass that occurs after bool_to_float.  Doing the work earlier
seems preferable.

i915
total instructions in shared programs: 788274 -> 788223 (<.01%)
instructions in affected programs: 666 -> 615 (-7.66%)
helped: 5
HURT: 0
helped stats (abs) min: 9 max: 12 x̄: 10.20 x̃: 9
helped stats (rel) min: 5.00% max: 11.11% x̄: 8.12% x̃: 8.16%
95% mean confidence interval for instructions value: -12.24 -8.16
95% mean confidence interval for instructions %-change: -10.81% -5.43%
Instructions are helped.

LOST:   0
GAINED: 2

The two gained shaders are assembly fragment programs in Euro Truck
Simulator 2.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>

2 years agoi915g/ci: update piglit fails
Ian Romanick [Wed, 2 Mar 2022 01:23:36 +0000 (17:23 -0800)]
i915g/ci: update piglit fails

I believe these were fixed by !14573.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>

2 years agonir: Switch to using nir_vec_scalars() for things that used nir_channel().
Emma Anholt [Thu, 3 Feb 2022 20:23:34 +0000 (12:23 -0800)]
nir: Switch to using nir_vec_scalars() for things that used nir_channel().

This should reduce follow-on optimization work to copy-propagate and
dead-code away the movs generated in construction of vectors.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14865>

2 years agonir: Add a helper for setting up a nir_ssa_scalar struct.
Emma Anholt [Thu, 3 Feb 2022 19:15:59 +0000 (11:15 -0800)]
nir: Add a helper for setting up a nir_ssa_scalar struct.

Trivial, but will help users avoid some struct constructions that can be
awkward in C.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14865>

2 years agonir: Introduce a nir_vec_scalars() helper using nir_ssa_scalar.
Emma Anholt [Thu, 3 Feb 2022 19:11:00 +0000 (11:11 -0800)]
nir: Introduce a nir_vec_scalars() helper using nir_ssa_scalar.

Many users of nir_vec() do so by nir_channel()-ing a new ssa defs as movs
from other vectors to put the new vector together, which then just have to
get copy-propagated into the ALU srcs and DCEed away the temporary movs.
If they instead take nir_ssa_scalar, we can avoid that extra work.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14865>

2 years agovulkan/wsi: handle queue families properly for non-concurrent sharing mode.
Dave Airlie [Mon, 21 Feb 2022 05:43:39 +0000 (15:43 +1000)]
vulkan/wsi: handle queue families properly for non-concurrent sharing mode.

"queueFamilyIndexCount is the number of queue families having access to the image(s) of the
swapchain when imageSharingMode is VK_SHARING_MODE_CONCURRENT.
pQueueFamilyIndices is a pointer to an array of queue family indices having access to the
images(s) of the swapchain when imageSharingMode is VK_SHARING_MODE_CONCURRENT."

If the type isn't concurrent, don't attempt to access the arrays.

dEQP-VK.wsi.xlib.swapchain.create.exclusive_nonzero_queues on lavapipe.

Fixes: 5b13d74583513 ("vulkan/wsi/drm: Break create_native_image in pieces")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15101>

2 years agoci/freedreno: Consolidate some information about an a630 flake.
Emma Anholt [Mon, 28 Feb 2022 22:04:45 +0000 (14:04 -0800)]
ci/freedreno: Consolidate some information about an a630 flake.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15197>

2 years agoir3: Don't assert on not finding the VS output for an FS input.
Emma Anholt [Mon, 28 Feb 2022 21:21:16 +0000 (13:21 -0800)]
ir3: Don't assert on not finding the VS output for an FS input.

It should return undefined data, not terminate the program.  Fixes some
piglit tests poking at the UB handling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15197>

2 years agoradv: include disable_aniso_single_level and adjust_frag_coord_z in key
Rhys Perry [Fri, 25 Feb 2022 14:54:22 +0000 (14:54 +0000)]
radv: include disable_aniso_single_level and adjust_frag_coord_z in key

Fixes potential pipeline caching bug.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15175>

2 years agofreedreno: Improve robustness behavior for VBs with offset > size.
Emma Anholt [Mon, 28 Feb 2022 22:45:19 +0000 (14:45 -0800)]
freedreno: Improve robustness behavior for VBs with offset > size.

We were just emitting the bad reloc (either an assert fail on a debug
build or for a release build likely a GPU hang from the resulting fault).
Given that the GLES 3.2 spec's robust context requirement says we should
return undefined data but not terminate for element indices outside of the
VB, ignoring the offset in this case seems like a better behavior to have
in all cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15198>

2 years agofreedreno: Fix start_slot handling in set_vertex_buffers.
Emma Anholt [Tue, 1 Mar 2022 22:57:29 +0000 (14:57 -0800)]
freedreno: Fix start_slot handling in set_vertex_buffers.

mesa/st only ever provides a 0 for this value, but let's be ready if it
ever does something else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15198>

2 years agofreedreno: Use the resource size rather than BO size for VFD_FETCH[].SIZE.
Emma Anholt [Mon, 28 Feb 2022 22:39:59 +0000 (14:39 -0800)]
freedreno: Use the resource size rather than BO size for VFD_FETCH[].SIZE.

We should be using the API size to clamp, rather than what we allocated
the BO into.

Fixes: #13
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15198>

2 years agodocs: match build-flags markup with meson docs
Erik Faye-Lund [Wed, 2 Mar 2022 12:04:40 +0000 (13:04 +0100)]
docs: match build-flags markup with meson docs

In meson.rst, we document build-flags with double backticks, which puts
it inside a code-tag in the rendered HTML instead of a cite-tag like we
currently do.

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15213>

2 years agodocs: fix a broken link
Erik Faye-Lund [Wed, 2 Mar 2022 09:53:54 +0000 (10:53 +0100)]
docs: fix a broken link

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15213>

2 years agointel/fs: fix total_scratch computation
Lionel Landwerlin [Mon, 28 Feb 2022 13:13:07 +0000 (15:13 +0200)]
intel/fs: fix total_scratch computation

We only have a single prog_data::total_scratch for all shader variants
(SIMD 8, 16, 32). Therefore we should always max the total_scratch on
top of existing variant.

We probably haven't run into that issue before because we compile by
increasing SIMD size and higher SIMD size is more likely to spill. But
for bindless shaders with return shaders, if the last return part
doesn't spill, we completely ignore the previous parts' scratch
computation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15193>

2 years agov3d: enable texture filtering anisotropic
Juan A. Suarez Romero [Fri, 25 Feb 2022 16:47:44 +0000 (17:47 +0100)]
v3d: enable texture filtering anisotropic

Seems we already had implemented this feature (see commit 521e1d0275e
"broadcom/vc5: Add support for anisotropic filtering"), but we didn't
enable the proper capability.

Also update the maximum level of anistropy supported.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4201
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15180>

2 years agointel/compiler: Use pass helper in brw_nir_adjust_offset_for_arrayed_indices
Caio Oliveira [Tue, 1 Mar 2022 19:29:41 +0000 (11:29 -0800)]
intel/compiler: Use pass helper in brw_nir_adjust_offset_for_arrayed_indices

Also change the code to preserve certain metadata: control flow is not changed
so both block indices and dominance information is preserved.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15206>

2 years agobroadcom/compiler: simplify node/temp translation during register allocation
Iago Toral Quiroga [Fri, 25 Feb 2022 11:07:05 +0000 (12:07 +0100)]
broadcom/compiler: simplify node/temp translation during register allocation

Now that we don't sort our nodes we can arrange them so we can
easily translate between nodes and temps without a mapping table,
just applying an offset.

To do this we have a single array of nodes where twe put first the nodes
for accumulators and then the nodes for temps. With this setup we can
ensure that for any given temp T, its node is always T + ACC_COUNT.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>

2 years agobroadcom/compiler: don't sort nodes for register allocation
Iago Toral Quiroga [Fri, 25 Feb 2022 08:18:34 +0000 (09:18 +0100)]
broadcom/compiler: don't sort nodes for register allocation

Nodes are allocated in order to registers so initially sorting
was used to ensure that nodes with smaller life ranges would
be assigned first and therefore be more likely to get
accumulators.

However, since d81a6e5f1d now we don't rely on order to make
decisions about accumulators and instead we make policy decisions
based on actual liveness, so sorting is no longer strictly
relevant to this decision.

Furthermore, we are not re-sorting nodes after each spill either,
since that would probably require that we rebuild the interference
graph after each spill (the graph identifies nodes by their index).

Shader-db results show a significant improvement in instruction
counts, due to more optimal accumulator assignments. The reason for
this is that we use a round-robin policy for choosing the next
accumulator to assign. The idea behind this is preventing nearby
temps to be assigned to the same accumulator so that QPU scheduling
is more flexible, but if we  sort our nodes, we are basically not
assigning temps in program order any more and the round-robin policy
becomes less effective:

total instructions in shared programs: 13000420 -> 12663189 (-2.59%)
instructions in affected programs: 11791267 -> 11454036 (-2.86%)
helped: 62890
HURT: 19987

total threads in shared programs: 415874 -> 415870 (<.01%)
threads in affected programs: 20 -> 16 (-20.00%)
helped: 2
HURT: 4

total uniforms in shared programs: 3711652 -> 3711624 (<.01%)
uniforms in affected programs: 43430 -> 43402 (-0.06%)
helped: 134
HURT: 173

total max-temps in shared programs: 2144876 -> 2138822 (-0.28%)
max-temps in affected programs: 123334 -> 117280 (-4.91%)
helped: 4112
HURT: 1195

total spills in shared programs: 3870 -> 3860 (-0.26%)
spills in affected programs: 1013 -> 1003 (-0.99%)
helped: 14
HURT: 12

total fills in shared programs: 5560 -> 5573 (0.23%)
fills in affected programs: 1765 -> 1778 (0.74%)
helped: 14
HURT: 17

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>

2 years agobroadcom/compiler: sink uniform loads
Iago Toral Quiroga [Wed, 23 Feb 2022 08:58:33 +0000 (09:58 +0100)]
broadcom/compiler: sink uniform loads

total instructions in shared programs: 13014428 -> 13000420 (-0.11%)
instructions in affected programs: 743624 -> 729616 (-1.88%)
helped: 1392
HURT: 611

total threads in shared programs: 415858 -> 415874 (<.01%)
threads in affected programs: 16 -> 32 (100.00%)
helped: 8
HURT: 0

total uniforms in shared programs: 3720410 -> 3711652 (-0.24%)
uniforms in affected programs: 113442 -> 104684 (-7.72%)
helped: 635
HURT: 29

total max-temps in shared programs: 2154268 -> 2144876 (-0.44%)
max-temps in affected programs: 61279 -> 51887 (-15.33%)
helped: 1124
HURT: 187

total spills in shared programs: 4002 -> 3870 (-3.30%)
spills in affected programs: 265 -> 133 (-49.81%)
helped: 6
HURT: 0

total fills in shared programs: 5788 -> 5560 (-3.94%)
fills in affected programs: 603 -> 375 (-37.81%)
helped: 6
HURT: 0

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>

2 years agobroadcom/compiler: move constants before their first user
Iago Toral Quiroga [Mon, 21 Feb 2022 12:03:54 +0000 (13:03 +0100)]
broadcom/compiler: move constants before their first user

For us they are basically uniforms too so we want to make their
lifespans short to facilitate allocating them to accumulators.

total instructions in shared programs: 13043585 -> 13015385 (-0.22%)
instructions in affected programs: 8326040 -> 8297840 (-0.34%)
helped: 24939
HURT: 19894

total threads in shared programs: 415860 -> 415858 (<.01%)
threads in affected programs: 4 -> 2 (-50.00%)
helped: 0
HURT: 1

total uniforms in shared programs: 3721953 -> 3720451 (-0.04%)
uniforms in affected programs: 96134 -> 94632 (-1.56%)
helped: 744
HURT: 435

total max-temps in shared programs: 2173431 -> 2154260 (-0.88%)
max-temps in affected programs: 264598 -> 245427 (-7.25%)
helped: 10858
HURT: 841

total spills in shared programs: 4005 -> 4010 (0.12%)
spills in affected programs: 700 -> 705 (0.71%)
helped: 5
HURT: 10

total fills in shared programs: 5801 -> 5817 (0.28%)
fills in affected programs: 1346 -> 1362 (1.19%)
helped: 6
HURT: 11

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>

2 years agobroadcom/compiler: disallow TMU spills if max tmu spills is 0
Iago Toral Quiroga [Mon, 21 Feb 2022 10:43:48 +0000 (11:43 +0100)]
broadcom/compiler: disallow TMU spills if max tmu spills is 0

If we are compiling with a strategy that does not allow TMU spills
we should not allow spilling anything that is not a uniform.
Otherwise the RA cost/benefit algorithm may choose to spill a
temp that is not uniform and that will cause us to immediately
fail the strategy and fallback to the next one, even if we
could've instead chosen to spill more uniforms to compile the
program successfully with that strategy.

Some relevant shader-db stats:

total instructions in shared programs: 13040711 -> 13043585 (0.02%)
instructions in affected programs: 234238 -> 237112 (1.23%)
helped: 73
HURT: 172

total threads in shared programs: 415664 -> 415860 (0.05%)
threads in affected programs: 196 -> 392 (100.00%)
helped: 98
HURT: 0

total uniforms in shared programs: 3717266 -> 3721953 (0.13%)
uniforms in affected programs: 12831 -> 17518 (36.53%)
helped: 6
HURT: 100

total max-temps in shared programs: 2174177 -> 2173431 (-0.03%)
max-temps in affected programs: 4597 -> 3851 (-16.23%)
helped: 79
HURT: 21

total spills in shared programs: 4010 -> 4005 (-0.12%)
spills in affected programs: 55 -> 50 (-9.09%)
helped: 5
HURT: 0

total fills in shared programs: 5820 -> 5801 (-0.33%)
fills in affected programs: 186 -> 167 (-10.22%)
helped: 5
HURT: 0

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>

2 years agobroadcom/compiler: increase cost of TMU spills to 10
Iago Toral Quiroga [Mon, 21 Feb 2022 09:42:12 +0000 (10:42 +0100)]
broadcom/compiler: increase cost of TMU spills to 10

Our cost was 5 which matches the number of instructions we have to
add for a TMU spill (a fill is 4 instructions).

Uniform spills on the other hand add an extra instruction for each
fill and remove one instruction for the spill itself. These have
a cost of 1.

Therefore, if we have a single spill+fill, we end up with +9
instructions if it is a TMU spill and +0 instructions with a uniform
spill, so making the former only 5 times more costly is probably
not a good idea, and this is without even considering the added
latency of the TMU accesses.

Relevant shader-db changes show this causes as a marginal instruction
count increase in a few shaders but better thread counts and lower
TMU spilling overall:

total instructions in shared programs: 13037315 -> 13040711 (0.03%)
instructions in affected programs: 370106 -> 373502 (0.92%)
helped: 187
HURT: 321

total threads in shared programs: 415090 -> 415664 (0.14%)
threads in affected programs: 574 -> 1148 (100.00%)
helped: 287
HURT: 0

total uniforms in shared programs: 3706674 -> 3717266 (0.29%)
uniforms in affected programs: 63075 -> 73667 (16.79%)
helped: 40
HURT: 395

total max-temps in shared programs: 2176080 -> 2174177 (-0.09%)
max-temps in affected programs: 15838 -> 13935 (-12.02%)
helped: 316
HURT: 34

total spills in shared programs: 4247 -> 4010 (-5.58%)
spills in affected programs: 2599 -> 2362 (-9.12%)
helped: 107
HURT: 14

total fills in shared programs: 6121 -> 5820 (-4.92%)
fills in affected programs: 3622 -> 3321 (-8.31%)
helped: 108
HURT: 13

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>

2 years agoradeonsi: fix an assertion failure with register shadowing
Marek Olšák [Mon, 28 Feb 2022 20:37:48 +0000 (15:37 -0500)]
radeonsi: fix an assertion failure with register shadowing

The problem is that dirty_states must be 0 for any state that is NULL
in "queued". This code was flagging dirty_states for such states because
it was only looking at "emitted". It should have been looking at "queued".

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>

2 years agoradeonsi: fix register shadowing after the pm4 state size was decreased
Marek Olšák [Sun, 27 Feb 2022 03:37:14 +0000 (22:37 -0500)]
radeonsi: fix register shadowing after the pm4 state size was decreased

Fixes: 946bd90a097e8 "radeonsi: decrease the size of si_pm4_state::pm4 except for cs_preamble_state"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>

2 years agoac: add an environment variable that parses IBs in files
Marek Olšák [Tue, 1 Mar 2022 15:36:37 +0000 (10:36 -0500)]
ac: add an environment variable that parses IBs in files

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>

2 years agoac: define PKT3_ATOMIC_MEM
Marek Olšák [Tue, 1 Mar 2022 15:38:08 +0000 (10:38 -0500)]
ac: define PKT3_ATOMIC_MEM

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>

2 years agoac: parse SET_SH_REG_INDEX packet
Marek Olšák [Wed, 23 Feb 2022 02:40:59 +0000 (21:40 -0500)]
ac: parse SET_SH_REG_INDEX packet

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>

2 years agoac/llvm: update LLVM processor names for gfx10.3
Marek Olšák [Wed, 28 Jul 2021 15:18:59 +0000 (11:18 -0400)]
ac/llvm: update LLVM processor names for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>

2 years agoci: add point coord failures to d3d12
Marek Olšák [Tue, 1 Mar 2022 21:08:42 +0000 (16:08 -0500)]
ci: add point coord failures to d3d12

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agost/mesa: do nir_lower_io() for inputs & outputs with transform feedback info
Marek Olšák [Sat, 1 Jan 2022 10:50:05 +0000 (05:50 -0500)]
st/mesa: do nir_lower_io() for inputs & outputs with transform feedback info

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agogallium/aux: add helper nir_gather_stream_output_info
Marek Olšák [Mon, 3 Jan 2022 04:37:15 +0000 (23:37 -0500)]
gallium/aux: add helper nir_gather_stream_output_info

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agogallium/util: add util_dump_stream_output_info
Marek Olšák [Mon, 3 Jan 2022 10:42:08 +0000 (05:42 -0500)]
gallium/util: add util_dump_stream_output_info

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: pass nir_shader into nir_recompute_io_bases instead of func_impl
Marek Olšák [Tue, 4 Jan 2022 17:34:23 +0000 (12:34 -0500)]
nir: pass nir_shader into nir_recompute_io_bases instead of func_impl

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: add nir_print_xfb_info
Marek Olšák [Mon, 3 Jan 2022 10:41:53 +0000 (05:41 -0500)]
nir: add nir_print_xfb_info

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: add nir_gather_xfb_info_from_intrinsics for lowered IO
Marek Olšák [Mon, 3 Jan 2022 04:38:00 +0000 (23:38 -0500)]
nir: add nir_gather_xfb_info_from_intrinsics for lowered IO

Drivers will use this.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: add nir_lower_io_passes() with new transform feedback
Marek Olšák [Sat, 1 Jan 2022 10:32:14 +0000 (05:32 -0500)]
nir: add nir_lower_io_passes() with new transform feedback

moved from radeonsi without the vectorization, which won't be needed for
now. We will lower IO in st/mesa instead of radeonsi to get the transform
feedback info into store instructions.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: add nir_io_semantics::no_varying, no_sysval_output, and helpers
Marek Olšák [Mon, 3 Jan 2022 00:46:45 +0000 (19:46 -0500)]
nir: add nir_io_semantics::no_varying, no_sysval_output, and helpers

This is for drivers that have separate store instructions for varyings,
system value outputs (such as clip distances), and transform feedback.
The flags tell the driver not to store the output to those locations.

This will be used by radeonsi initially, and then maybe by a new linker.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: scalarize transform feedback info in nir_lower_io_to_scalar
Marek Olšák [Sun, 19 Dec 2021 21:23:42 +0000 (16:23 -0500)]
nir: scalarize transform feedback info in nir_lower_io_to_scalar

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: add shader_info::xfb_strides
Marek Olšák [Sat, 1 Jan 2022 11:18:56 +0000 (06:18 -0500)]
nir: add shader_info::xfb_strides

NIR now fully contains pipe_stream_output_info in shader_info and IO
intrinsics if lower_io_variables is true. radeonsi will not use
pipe_stream_output_info after this, and other drivers are free to follow
that.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: add transform feedback info into nir_intrinsic_store_output
Marek Olšák [Sun, 19 Dec 2021 19:20:52 +0000 (14:20 -0500)]
nir: add transform feedback info into nir_intrinsic_store_output

This will allow compaction of transform feedback varyings because they
are no longer tied to varying slots with this information.
It will also make transform feedback info available to all NIR passes
after IO is lowered. It's meant to replace pipe_stream_output_info.

Other intrinsics are not used with transform feedback.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: fix nir_io_semantics::gs_streams in nir_lower_io_to_scalar
Marek Olšák [Sun, 2 Jan 2022 04:11:00 +0000 (23:11 -0500)]
nir: fix nir_io_semantics::gs_streams in nir_lower_io_to_scalar

gs_streams is relative to the component. Also clear the high bits.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agonir: validate write_mask for all intrinsics that have it
Marek Olšák [Sun, 19 Dec 2021 20:32:08 +0000 (15:32 -0500)]
nir: validate write_mask for all intrinsics that have it

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>

2 years agoradeonsi: fix broken VK-GL buffer interop
Marek Olšák [Tue, 22 Feb 2022 21:46:28 +0000 (16:46 -0500)]
radeonsi: fix broken VK-GL buffer interop

Fixes: ad9b5ac0a18 - radeonsi: more fixes for si_buffer_from_winsys_buffer for GL-VK interop
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6063

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15124>

2 years agoanv: Disable aux if the explicit modifier lacks it
Nanley Chery [Fri, 25 Feb 2022 01:16:37 +0000 (17:16 -0800)]
anv: Disable aux if the explicit modifier lacks it

For dmabuf imports, configure the primary surface without support for
compression if the modifier doesn't specify it. This helps to create VkImages
with memory requirements that are compatible with the buffers apps provide.

Suggested-by: Philip Langdale <philipl@overt.org>
Cc: 22.0 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5940
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>

2 years agoanv: Refactor anv_image_init_from_create_info
Nanley Chery [Fri, 25 Feb 2022 17:50:13 +0000 (09:50 -0800)]
anv: Refactor anv_image_init_from_create_info

Use a variable to store the anv_image_create_info struct. We'll modify it for a
bug fix in the next patch.

Cc: 22.0 <mesa-stable>
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>

2 years agoanv: Change a parameter of the implicit layout fn
Nanley Chery [Fri, 25 Feb 2022 01:17:49 +0000 (17:17 -0800)]
anv: Change a parameter of the implicit layout fn

Replace the create_info parameter with isl_extra_usage_flags to more closely
match the parameters of explicit layout function.

Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>

2 years agopan/va: Add missing copyright notice
Alyssa Rosenzweig [Tue, 1 Mar 2022 19:14:12 +0000 (14:14 -0500)]
pan/va: Add missing copyright notice

Minor.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

2 years agopan/bi: Extract INSTRUCTION_CASE macro
Alyssa Rosenzweig [Fri, 19 Nov 2021 20:51:13 +0000 (15:51 -0500)]
pan/bi: Extract INSTRUCTION_CASE macro

Useful across multiple optimization tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

2 years agopan/bi: Adapt bi_lower_branch for Valhall
Alyssa Rosenzweig [Tue, 27 Jul 2021 00:19:48 +0000 (20:19 -0400)]
pan/bi: Adapt bi_lower_branch for Valhall

Disable the Bifrost optimization; it's not portable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

2 years agopan/bi: Trade off registers/threads on Valhall
Alyssa Rosenzweig [Mon, 2 Aug 2021 16:30:03 +0000 (12:30 -0400)]
pan/bi: Trade off registers/threads on Valhall

It's only v6 that's missing this feature.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

2 years agopan/bi: Add BI_SUBGROUP_SUBGROUP16 option
Alyssa Rosenzweig [Wed, 11 Aug 2021 20:34:46 +0000 (16:34 -0400)]
pan/bi: Add BI_SUBGROUP_SUBGROUP16 option

Valhall uses 16-wide warps.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

2 years agopan/bi: Wire Valhall disassembler into compiler
Alyssa Rosenzweig [Tue, 1 Mar 2022 19:13:53 +0000 (14:13 -0500)]
pan/bi: Wire Valhall disassembler into compiler

Useful when we grow Valhall support (soon!)

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>