Clivia.Cai [Wed, 20 Apr 2022 05:18:30 +0000 (22:18 -0700)]
dt-bingings:sd:update jh7110 sd dt-bingings
Add clock and reset for sdio1 nodes in device tree
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
andy.hu [Tue, 19 Apr 2022 15:56:43 +0000 (15:56 +0000)]
Merge branch 'CR_847_watchdog_xingyu.wu' into 'jh7110_fpga_dev_5.15'
Cr 847 watchdog xingyu.wu
See merge request sdk/sft-riscvpi-linux-5.10!9
xingyu.wu [Tue, 19 Apr 2022 13:27:13 +0000 (21:27 +0800)]
driver:watchdog:Add config definition to different uses of board level
1. The watchdog driver can get different rate from clock by different board.
2. arch:riscv:Kconfig: Adjust the format.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
xingyu.wu [Fri, 15 Apr 2022 08:48:50 +0000 (16:48 +0800)]
driver:watchdog: Add clock & reset
Add clock and reset in watchdog's driver and device tree.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
xingyu.wu [Fri, 15 Apr 2022 07:59:12 +0000 (15:59 +0800)]
clk:starfive: Adjust the format
Adjust and modify the clock driver's format
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
andy.hu [Tue, 19 Apr 2022 12:39:27 +0000 (12:39 +0000)]
Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15'
Cr 786 can clivia.cai
See merge request sdk/sft-riscvpi-linux-5.10!8
Clivia.Cai [Thu, 14 Apr 2022 11:10:51 +0000 (04:10 -0700)]
dt-bingings:can:update jh7110 can dt-bingings.
Update jh7110 can/canfd dt-bindings configuration
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Thu, 14 Apr 2022 03:36:20 +0000 (20:36 -0700)]
riscv:defconfig: enable CAN,IPMS_CAN
Enable can/canfd config in defconfig.
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Thu, 14 Apr 2022 02:18:41 +0000 (19:18 -0700)]
dt-bindings:net:can:ipms-can: add ipms-can.yaml references
Add CAN/CANFD binding documentation for jh7110 SoC.
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Sat, 2 Apr 2022 08:58:16 +0000 (01:58 -0700)]
can:ipms_can: fix code style
Optimize the can driver code to conform to the upstream specification
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Fri, 15 Apr 2022 02:49:35 +0000 (19:49 -0700)]
dt-bindings: Add vendor prefix
Add vendor prefix for can device
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
andy.hu [Tue, 19 Apr 2022 10:10:05 +0000 (10:10 +0000)]
Merge branch 'CR_864_update_pinctrl_jianlong' into 'jh7110_fpga_dev_5.15'
update pinctrl marco to more lines
See merge request sdk/sft-riscvpi-linux-5.10!12
jianlong.huang [Tue, 19 Apr 2022 09:23:01 +0000 (17:23 +0800)]
update pinctrl marco to more lines
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
andy.hu [Tue, 19 Apr 2022 09:29:59 +0000 (09:29 +0000)]
Merge branch 'CR_870_Reset_samin.guo' into 'jh7110_fpga_dev_5.15'
Cr 870 reset samin.guo
See merge request sdk/sft-riscvpi-linux-5.10!11
andy.hu [Tue, 19 Apr 2022 09:23:19 +0000 (09:23 +0000)]
Merge branch 'CR_833_VDEC_samin.guo' into 'jh7110_fpga_dev_5.15'
CR 833 vdec samin.guo
See merge request sdk/sft-riscvpi-linux-5.10!10
samin [Tue, 19 Apr 2022 07:42:35 +0000 (15:42 +0800)]
reset:starfive:jh7110: Fix wrong macro definition.
Fix wrong macro definition.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Tue, 19 Apr 2022 08:01:47 +0000 (16:01 +0800)]
reset:starfive:jh7110: Macro definitions are rearranged in order.
Macro definitions are rearranged in order, for better coding style.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Thu, 13 Jan 2022 03:48:56 +0000 (11:48 +0800)]
reset:starfive:jh7110: change how to obtain an assert address
Get assert addresses dynamically to reduce static array memory usage
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Fri, 15 Apr 2022 02:15:59 +0000 (10:15 +0800)]
dt-bingings:clk: remove dec_rootclk fixed clk define.
The clktree is ready. The VDEC uses the clock signal defined by the
clock tree, fixed-clk is not required.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Fri, 15 Apr 2022 01:56:09 +0000 (09:56 +0800)]
dt-bingings:vdec:jh7110: Add CLK signals to Vdec
Vdec uses the Clock framework API.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Fri, 15 Apr 2022 01:37:06 +0000 (09:37 +0800)]
drivers:soc:starfive: support driver for starfive soc.
Add Kconfig/Makefile support for starfive soc.
Signed-off-by: samin <samin.guo@starfivetech.com>
andy.hu [Thu, 14 Apr 2022 08:18:46 +0000 (08:18 +0000)]
Merge branch 'CR_783_dts_hal.feng' into 'jh7110_fpga_dev_5.15'
riscv: dts: starfive: Improve the structure of device tree
See merge request sdk/sft-riscvpi-linux-5.10!5
Hal Feng [Sat, 2 Apr 2022 09:11:50 +0000 (17:11 +0800)]
riscv: dts: starfive: Improve the structure of device tree
Divide the old device tree into several files according to different layers.
Make the device tree clearer and more readable.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
andy.hu [Thu, 14 Apr 2022 03:16:39 +0000 (03:16 +0000)]
Merge branch 'CR_792_PINCTRL_jianlong' into 'jh7110_fpga_dev_5.15'
modify pinctrl about vin_dvp function sel
See merge request sdk/sft-riscvpi-linux-5.10!7
jianlong.huang [Thu, 14 Apr 2022 02:29:04 +0000 (10:29 +0800)]
modify vin pinctrl dts
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
jianlong.huang [Wed, 13 Apr 2022 11:07:58 +0000 (19:07 +0800)]
add dvp pinctrl dts
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
jianlong.huang [Wed, 13 Apr 2022 10:27:52 +0000 (18:27 +0800)]
modify pinctrl about vin_dvp function sel
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
andy.hu [Wed, 13 Apr 2022 10:34:08 +0000 (10:34 +0000)]
Merge branch 'CR_737_CLOCK_TREE_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
Cr 737 clock tree xingyu.wu
See merge request sdk/sft-riscvpi-linux-5.10!6
xingyu.wu [Wed, 13 Apr 2022 08:45:38 +0000 (16:45 +0800)]
arch:riscv:Kconfig: Add choice with SOC board type
Add config about user can choose the board type about FPGA,
EVB or Visionfive
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
xingyu.wu [Wed, 13 Apr 2022 08:36:57 +0000 (16:36 +0800)]
clk:starfive: Add vout clock tree driver
Clock references refer to include/dt-bindings/clock/starfive-jh7110-vout.h
Change the value about 'status' of clkvout node in dts file when want to
use vout clock.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
xingyu.wu [Wed, 13 Apr 2022 08:10:47 +0000 (16:10 +0800)]
clk:starfive: Add JH7110 clock tree driver for kernel 5.15
Add clock driver about sys, stg and aon clock for JH7110.
Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
andy.hu [Wed, 13 Apr 2022 08:15:54 +0000 (08:15 +0000)]
Merge branch 'CR_792_PINCTRL_jianlong' into 'jh7110_fpga_dev_5.15'
add jh7110 pinctrl dts and driver
See merge request sdk/sft-riscvpi-linux-5.10!4
jianlong.huang [Tue, 12 Apr 2022 01:28:54 +0000 (09:28 +0800)]
enable sdio pinctrcl
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
jianlonghuang [Thu, 7 Apr 2022 03:53:37 +0000 (11:53 +0800)]
enable pinctrl and modify gpio irq init
Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com>
“jenny.zhang” [Thu, 3 Mar 2022 06:20:18 +0000 (22:20 -0800)]
[pinctrl]Synchronize vic7100&jh7110 pinctrl subsystem
“jenny.zhang” [Tue, 28 Dec 2021 06:42:59 +0000 (22:42 -0800)]
[pinctrl] Update parse gpio dts node
“jenny.zhang” [Tue, 28 Dec 2021 03:39:48 +0000 (19:39 -0800)]
[pinctrl]Update gpio control code
“jenny.zhang” [Wed, 22 Dec 2021 08:34:09 +0000 (00:34 -0800)]
[pinctrl] disable jh7110 pinctrl
“jenny.zhang” [Wed, 22 Dec 2021 03:34:45 +0000 (19:34 -0800)]
[pinctrl] 1.Update jh7110 pinctrl dts; 2.Adjust pinctrl coding style;
“jenny.zhang” [Tue, 30 Nov 2021 06:45:05 +0000 (22:45 -0800)]
[pinctrl] add jh7110 pinctrl dts and driver
andy.hu [Wed, 23 Mar 2022 13:33:51 +0000 (13:33 +0000)]
Merge branch 'CR_730_RTC_samin.guo' into 'jh7110_dev_5.15'
rtc: starfive: Get the interrupt status using Completion.
See merge request sdk/sft-riscvpi-linux-5.10!3
samin [Mon, 24 Jan 2022 01:40:33 +0000 (09:40 +0800)]
rtc: starfive: Get the interrupt status using Completion.
starfiv rtc needs to get interrupt status when setting rtc clock and
configuring hardware calibration. Use completion to identify states in
interrupt handlers.
In addition, when clearing the interrupt, you need to pull to determine
whether to clear the state, otherwise the clearing will be unsuccessful.
Signed-off-by: samin <samin.guo@starfivetech.com>
andy.hu [Tue, 15 Mar 2022 01:28:14 +0000 (01:28 +0000)]
Merge branch 'CR_722_DRM_keith.zhao' into 'jh7110_dev_5.15'
riscv:driver:drm:DC8200
See merge request sdk/sft-riscvpi-linux-5.10!2
keith.zhao [Mon, 14 Mar 2022 03:09:02 +0000 (11:09 +0800)]
riscv:driver:drm:DC8200
fix build error caused by vs-drm.h
modify SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note
Signed-off-by:keith.zhao <keith.zhao@statfivetech.com>
keith.zhao [Fri, 14 Jan 2022 12:58:47 +0000 (20:58 +0800)]
riscv::starfive:driver:dc8200
add head file vs-drm.h
Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
keith.zhao [Fri, 14 Jan 2022 12:46:25 +0000 (20:46 +0800)]
riscv:uboot:starfive:dc8200
update drdc8200iver kenerl version from 5.10 to 5.13
Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
samin [Fri, 14 Jan 2022 07:10:00 +0000 (15:10 +0800)]
soc:starfive: add jh7110 pmu driver.
The JH7110 PMU can dynamically switch on or off power domians and set
the power-on and power-off sequence.
API Instructions refer to include/soc/starfive/jh7110_pmu.h
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Fri, 14 Jan 2022 07:35:43 +0000 (15:35 +0800)]
dt-bingings:pmu:add jh7110 pmu dt-bingings.
Add jh7110 pmu support.
Signed-off-by: samin <samin.guo@starfivetech.com>
shanlong.li [Thu, 13 Jan 2022 10:32:53 +0000 (18:32 +0800)]
1.add mailbox driver; 2.add mailbox test driver.
Huan.Feng [Thu, 13 Jan 2022 10:11:09 +0000 (18:11 +0800)]
add patches for libkcapi tool
changhuang.liang [Wed, 12 Jan 2022 06:27:34 +0000 (14:27 +0800)]
v4l2: add mipi pipeline suppport and ov13850 sensor
david.li [Thu, 6 Jan 2022 05:04:28 +0000 (13:04 +0800)]
[v4l2][update kernel5.15]
samin [Wed, 5 Jan 2022 07:12:44 +0000 (15:12 +0800)]
reset: starfive-jh7110: Add isp/vout reset support.
Add isp/vout reset support for jh7110.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Wed, 5 Jan 2022 06:57:25 +0000 (14:57 +0800)]
reset: starfive-jh7110: use platform_ioremap_iomem_byname.
The reset module is scattered in several domains, and each address
segment may be located in the module device management.
Using devm_platform_get_and_ioremap_resource->devm_ioremap_resource will
cause the address of this segment to be occupied by the reset driver,
and other modules cannot be used, so use ioremap that can be mapped
multiple times instead.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Wed, 5 Jan 2022 06:43:19 +0000 (14:43 +0800)]
dt-bingings:reset:jh7110: Add isp/vout reg reset node.
Add isp/vout reg reset node for jh7110.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Wed, 5 Jan 2022 06:27:50 +0000 (14:27 +0800)]
dt-bingings:reset:jh7110: Add isp/vout domain reset define.
isp/vout domain are independent of other CRGS.
Signed-off-by: samin <samin.guo@starfivetech.com>
david.li [Wed, 5 Jan 2022 03:07:47 +0000 (11:07 +0800)]
[v4l2] [add vin path]
david.li [Thu, 23 Dec 2021 07:08:34 +0000 (15:08 +0800)]
open pcie
samin [Wed, 22 Dec 2021 07:34:41 +0000 (15:34 +0800)]
dt-bingings:reset: Add reset node for vdec&&jpeg.
Add reset bindings for the vdec&jpeg.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 20 Dec 2021 02:04:36 +0000 (10:04 +0800)]
dt-bingings:reset: Add Starfive JH7110 reset bindings
Add bindings for the reset controller on the JH7110 RISC-V SoC by
StarFive Ltd.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Thu, 16 Dec 2021 10:25:49 +0000 (18:25 +0800)]
reset: starfive-jh7110: Add StarFive JH7110 reset driver
Add a driver for the StarFive JH7110 reset controller.
Signed-off-by: samin <samin.guo@starfivetech.com>
“jenny.zhang” [Mon, 20 Dec 2021 08:05:23 +0000 (00:05 -0800)]
[pwm] Add jh7110 pwm driver code
“jenny.zhang” [Thu, 16 Dec 2021 07:40:17 +0000 (23:40 -0800)]
[can] Add jh7110 can driver code
“jenny.zhang” [Thu, 16 Dec 2021 06:55:08 +0000 (22:55 -0800)]
[trng] Add jh7110 trng driver code
“jenny.zhang” [Thu, 16 Dec 2021 06:14:04 +0000 (22:14 -0800)]
[alsa] Add jh7110 audio module driver code
david.li [Wed, 15 Dec 2021 07:02:38 +0000 (15:02 +0800)]
v4l2 add dvp modify
david.li [Tue, 14 Dec 2021 06:21:27 +0000 (14:21 +0800)]
[add v4l2 driver && close pcie]
Huan.Feng [Mon, 13 Dec 2021 05:45:00 +0000 (13:45 +0800)]
modified dts file for jh7110 i2c
Huan.Feng [Fri, 10 Dec 2021 09:51:30 +0000 (17:51 +0800)]
modified gpio driver for jh7110
Huan.Feng [Fri, 10 Dec 2021 09:50:41 +0000 (17:50 +0800)]
modified i2c driver for jh7110
vincent.zhang [Fri, 10 Dec 2021 06:30:37 +0000 (14:30 +0800)]
remove IMG-rogue and null-disp and drm_legacy
Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com>
vincent.zhang [Fri, 10 Dec 2021 06:19:47 +0000 (14:19 +0800)]
add IMG-rogue, DRM, GEM & KMS, enable DRM legacy for default config
vincent.zhang [Fri, 10 Dec 2021 05:54:59 +0000 (13:54 +0800)]
change the IRQ number of GPU
Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com>
Huan.Feng [Fri, 3 Dec 2021 03:12:49 +0000 (11:12 +0800)]
Merge branch 'jh7110_dev_5.15' of 192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15
Huan.Feng [Fri, 3 Dec 2021 03:12:02 +0000 (11:12 +0800)]
modify jh7110 gpio driver irq register function
ke.zhu [Fri, 3 Dec 2021 02:55:51 +0000 (10:55 +0800)]
Merge branch 'jh7110_dev_5.15' of 192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15
Huan.Feng [Fri, 3 Dec 2021 02:54:10 +0000 (10:54 +0800)]
modify jh7110 gpio driver
ke.zhu [Fri, 3 Dec 2021 02:54:10 +0000 (10:54 +0800)]
PLIC cannot EOI masked interrupts，so Re-enable the interrupt before completion if it has been masked during the handling and remask it afterwards.
samin [Wed, 1 Dec 2021 06:36:18 +0000 (14:36 +0800)]
Kconfig/dw-axi-dmac-starfive: selected by SOC_STARFIVE
Signed-off-by: samin <samin.guo@starfivetech.com>
Samin Guo [Wed, 1 Sep 2021 09:42:14 +0000 (17:42 +0800)]
clocksource: add starfive hw-timer driver
This driver applies to JH7100|JH7110
Signed-off-by: samin <samin.guo@starfivetech.com>
Samin Guo [Wed, 8 Sep 2021 03:27:49 +0000 (11:27 +0800)]
watchdog: add starfive watchdog driver
This driver applies to JH7100|JH7110
Signed-off-by: samin <samin.guo@starfivetech.com>
SaminGuo [Fri, 19 Nov 2021 04:05:19 +0000 (12:05 +0800)]
dt-bingings: Add dt-bingings support for StarFive JH7110 Timers.
Signed-off-by: samin <samin.guo@starfivetech.com>
SaminGuo [Fri, 19 Nov 2021 04:02:34 +0000 (12:02 +0800)]
dt-bingings: Add dt-bingings support for StarFive JH71xx WatchDog
Signed-off-by: samin <samin.guo@starfivetech.com>
ke.zhu [Thu, 25 Nov 2021 09:15:51 +0000 (17:15 +0800)]
1.Add plda pcie host controller driver.
2.Add PCIe host controller DT bingdings of starfive JH7110.
ke.zhu [Thu, 25 Nov 2021 06:02:50 +0000 (14:02 +0800)]
spi: support spi-pl022.
ke.zhu [Thu, 25 Nov 2021 03:24:50 +0000 (11:24 +0800)]
Merge branch 'jh7110_dev_5.15' of 192.168.110.45/sdk/sft-riscvpi-linux-5.10 into jh7110_dev_5.15
samin [Tue, 23 Nov 2021 06:32:44 +0000 (14:32 +0800)]
dt-bingings: Update dt-bingings for jh7110 jpu/vdec.
1) rename jpu/vdec match strings.
2) add axi/apb clock-names define for jpu/vdec.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 10:08:40 +0000 (18:08 +0800)]
dma: Added DMA misc driver interface for data transfer
1)add async_memcpy api kernel space.
2)add dma-misc driver for user space.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 10:08:40 +0000 (18:08 +0800)]
dma: Added DMA misc driver interface for data transfer
1)add async_memcpy api kernel space.
2)add dma-misc driver for user space.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 09:52:04 +0000 (17:52 +0800)]
dmaengine: dw-axi-dmac: Add support for StarFive ALSA device.
Solve the problem of audio DMA transmission and playback
failure.
Signed-off-by: jenny.zhang <jenny.zhang@starfivetech.com>
Signed-off-by: michael.yan <michael.yan@starfivetech.com>
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 09:21:34 +0000 (17:21 +0800)]
dmaengine: dw-axi-dmac: add burst_trans_len support.
Different peripherals may require different burst_trans_len.
Some ALSA devices may require BURST_TRANS_LEN_16, but this
parameter may not work properly on some peripherals (spi, etc.).
This patch will allow BURST_TRANS_LEN to be passed in from DTS.
dmas = <&dma hs_nu burst_trans_len>
burst_trans_len:
<-1> defalut
<0> BURST_TRANS_LEN_1
<1> BURST_TRANS_LEN_4 /*defalut value*/
<2> BURST_TRANS_LEN_8
<3> BURST_TRANS_LEN_16
<4> BURST_TRANS_LEN_32
<5> BURST_TRANS_LEN_64
<6> BURST_TRANS_LEN_128
<7> BURST_TRANS_LEN_256
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 08:52:21 +0000 (16:52 +0800)]
dmaengine: dw-axi-dmac: Add StarFive JHxxx AxiDMA support
Add support for StarFive AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible
string matches the "starfive,axi-dma".
Add "starfive_flush_dcache" due to VIC7100 Cache
Coherency issues.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 06:14:37 +0000 (14:14 +0800)]
dmaengine: dw-axi-dmac: Supports channels > 8 or hardware handshakes > 16.
1)Different num of chan/hw-handshakes have different register offsets.
When the channel > 8, DMA uses DMAC_CHENREG2 instead of DMAC_CHENREG.
When the channel > 8 or hw-handshake > 16, DMA uses CHx_CFG2 instead of CHx_CFG.
2)add OSR(Outstanding Request Limit) configuration
OSR can greatly improve performance in dma-memcpy.
Signed-off-by: samin <samin.guo@starfivetech.com>
samin [Mon, 22 Nov 2021 06:34:59 +0000 (14:34 +0800)]
dt-bingings: Add dt-bingings support for StarFive JH7110 DMA.
Signed-off-by: samin <samin.guo@starfivetech.com>
SaminGuo [Fri, 19 Nov 2021 05:33:34 +0000 (13:33 +0800)]
dt-bingings: Adjust the line feed to be more intuitive
Signed-off-by: SaminGuo <samin.guo@starfivetech.com>
SaminGuo [Wed, 17 Nov 2021 07:55:45 +0000 (15:55 +0800)]
rtc: starfive-rtc: Add RTC support for StarFive JH7110.
1)32.768k-RTC device.
2)sw/hw calibration support;
3)alarm support;
4)5.15 Use "devm_rtc_register_device" instead of "rtc_register_device"
Signed-off-by: SaminGuo <samin.guo@starfivetech.com>
SaminGuo [Fri, 19 Nov 2021 02:11:33 +0000 (10:11 +0800)]
dt-bingings: Add dt-bingings support for StarFive JH7110 RTC.
RTC fixed operating frequency is 32.768KHz, refclk for hardware
calibration
Signed-off-by: SaminGuo <samin.guo@starfivetech.com>
yanhong.wang [Fri, 19 Nov 2021 00:57:22 +0000 (08:57 +0800)]
[config]:Update default config
yanhong.wang [Thu, 18 Nov 2021 06:06:27 +0000 (14:06 +0800)]
[board]:Init board config for JH7110
yanhong.wang [Wed, 17 Nov 2021 09:34:12 +0000 (17:34 +0800)]
Merge branch 'worklym' into jh7110_dev_5.15
projects / platform / kernel / linux-starfive.git / log