Mikita Lipski [Wed, 14 Jul 2021 10:41:13 +0000 (06:41 -0400)]
drm/amd/display: Fix PSR command version
[why]
For dual eDP when setting the new settings we need to set
command version to DMUB_CMD_PSR_CONTROL_VERSION_1, otherwise
DMUB will not read panel_inst parameter.
[how]
Instead of PSR_VERSION_1 pass DMUB_CMD_PSR_CONTROL_VERSION_1
Reviewed-by: Wood Wyatt <Wyatt.Wood@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Tue, 6 Jul 2021 19:45:11 +0000 (15:45 -0400)]
drm/amd/display: Add missing DCN21 IP parameter
[why]
IP parameter min_meta_chunk_size_bytes is read for bandwidth
calculations but it was never defined.
[how]
Define min_meta_chunk_size_bytes and initialize value to 256.
Reviewed-by: Laktyushkin Dmytro <dmytro.laktyushkin@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pratik Vishwakarma [Mon, 26 Jul 2021 08:24:25 +0000 (13:54 +0530)]
drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supported
Rename amdgpu_acpi_is_s0ix_supported to better explain
functionality by renaming to amdgpu_acpi_is_s0ix_active
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Thu, 8 Jul 2021 18:50:48 +0000 (14:50 -0400)]
drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21
[why]
DST_Y_PREFETCH can overflow when DestinationLinesForPrefetch values are
too large due to the former being limited to 8 bits.
[how]
Set the maximum value of DestinationLinesForPrefetch to be 255 * refclk
period.
Reviewed-by: Laktyushkin Dmytro <dmytro.laktyushkin@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pratik Vishwakarma [Fri, 23 Jul 2021 12:38:40 +0000 (18:08 +0530)]
drm/amdgpu: Check pmops for desired suspend state
[Why]
User might change the suspend behaviour from OS.
[How]
Check with pm for target suspend state and set s0ix
flag only for s2idle state.
v2: User might change default suspend state, use target state
v3: squash in build fix
Suggested-by: Lijo Lazar <Lijo.Lazar@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 22 Jul 2021 05:46:47 +0000 (13:46 +0800)]
drm/amdgpu: retire sdma v5_2 golden settings from driver
They are initalized by hardware during power up phase,
starting from sdma v5_2 generation
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengzhe Liu [Thu, 22 Jul 2021 03:31:10 +0000 (11:31 +0800)]
drm/amdgpu: Add msix restore for pass-through mode
In pass-through mode, after mode 1 reset, msix enablement status would
lost and never receives interrupt again. So, we should restore msix
status after mode 1 reset.
Signed-off-by: Chengzhe Liu <ChengZhe.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roy Sun [Thu, 22 Jul 2021 05:55:42 +0000 (13:55 +0800)]
drm/amdgpu: Change the imprecise output
The fail reason is that the vfgate is disabled
Signed-off-by: Roy Sun <Roy.Sun@amd.com>
Reviewed-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Tue, 20 Jul 2021 02:58:19 +0000 (10:58 +0800)]
drm/amd/display: Fix ASSR regression on embedded panels
[Why]
Regression found in some embedded panels traces back to the earliest
upstreamed ASSR patch. The changed code flow are causing problems
with some panels.
[How]
- Change ASSR enabling code while preserving original code flow
as much as possible
- Simplify the code on guarding with internal display flag
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213779
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1620
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengzhe Liu [Tue, 20 Jul 2021 07:18:12 +0000 (15:18 +0800)]
drm/amdgpu: Clear doorbell interrupt status for Sienna Cichlid
On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO
mode(RTPM), then the kernel would receive thousands of interrupts.
That's because there is doorbell monitor interrupt on BIF, so KVM keeps
injecting interrupts to the guest VM. So we should clear the doorbell
interrupt status after BACO exit.
v2: Modify coding style and commit message
Signed-off-by: Chengzhe Liu <ChengZhe.Liu@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Sat, 10 Jul 2021 03:33:11 +0000 (23:33 -0400)]
drm/amd/pm: Fix a bug communicating with the SMU (v5)
This fixes a bug which if we probe a non-existing
I2C device, and the SMU returns 0xFF, from then on
we can never communicate with the SMU, because the
code before this patch reads and interprets 0xFF
as a terminal error, and thus we never write 0
into register 90 to clear the status (and
subsequently send a new command to the SMU.)
It is not an error that the SMU returns status
0xFF. This means that the SMU executed the last
command successfully (execution status), but the
command result is an error of some sort (execution
result), depending on what the command was.
When doing a status check of the SMU, before we
send a new command, the only status which
precludes us from sending a new command is 0--the
SMU hasn't finished executing a previous command,
and 0xFC--the SMU is busy.
This bug was seen as the following line in the
kernel log,
amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state!
when subsequent SMU commands, not necessarily
related to I2C, were sent to the SMU.
This patch fixes this bug.
v2: Add a comment to the description of
__smu_cmn_poll_stat() to explain why we're NOT
defining the SMU FW return codes as macros, but
are instead hard-coding them. Such a change, can
be followed up by a subsequent patch.
v3: The changes are,
a) Add comments to break labels in
__smu_cmn_reg2errno().
b) When an unknown/unspecified/undefined result is
returned back from the SMU, map that to
-EREMOTEIO, to distinguish failure at the SMU
FW.
c) Add kernel-doc to
smu_cmn_send_msg_without_waiting(),
smu_cmn_wait_for_response(),
smu_cmn_send_smc_msg_with_param().
d) In smu_cmn_send_smc_msg_with_param(), since we
wait for completion of the command, if the
result of the completion is
undefined/unknown/unspecified, we print that to
the kernel log.
v4: a) Add macros as requested, though redundant, to
be removed when SMU consolidates for all
ASICs--see comment in code.
b) Get out if the SMU code is unknown.
v5: Rename the macro names.
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Evan Quan <evan.quan@amd.com>
Cc: Lijo Lazar <Lijo.Lazar@amd.com>
Fixes:
fcb1fe9c9e0031 ("drm/amd/powerplay: pre-check the SMU state before issuing message")
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:57:06 +0000 (17:57 -0400)]
drm/amdgpu: add pci device id for cyan_skillfish
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Mon, 12 Jul 2021 02:51:15 +0000 (10:51 +0800)]
drm/amdgpu: add autoload_supported check for RLC autoload
Asic cyan_skilfish2 won't support RLC autoload when using
front door loading. We just use PSP to load firmware like
gfx9 here.
So add autoload_supported flag check instead of just
checking firmware load type for RLC autoload.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Tue, 13 Jul 2021 21:55:52 +0000 (17:55 -0400)]
drm/amdgpu: enable SMU for cyan_skilfish
Enable SMU support for cyan_skilfish.
v2: Squash in fix (Alex)
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Wed, 21 Jul 2021 15:05:07 +0000 (11:05 -0400)]
drm/amdgpu: add check_fw_version support for cyan_skillfish
Add check_fw_version function support for cyan_skillfish.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 1 Jul 2021 07:39:55 +0000 (15:39 +0800)]
drm/amdgpu: add basic ppt functions for cyan_skilfish
Add basic ppt funcs support or cyan_skilfish.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 1 Jul 2021 07:21:59 +0000 (15:21 +0800)]
drm/amdgpu: add smu interface header for cyan_skilfish
Add smu11_driver_if_cyan_skillfish.h for cyan_skilfish.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 1 Jul 2021 07:20:19 +0000 (15:20 +0800)]
drm/amdgpu: add smu_v11_8_ppsmc header for cyan_skilfish
Add smu_v11_8_ppsmc.h for cyan_skilfish.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 1 Jul 2021 07:18:34 +0000 (15:18 +0800)]
drm/amdgpu: add smu_v11_8_pmfw header for cyan_skilfish
Add smu_v11_8_pmfw.h for cyan_skilfish.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 17 Jun 2021 04:55:10 +0000 (12:55 +0800)]
drm/amdgpu: use direct loading by default for cyan_skillfish2
Will switch to front door loading by default after this function is
stable.
v2: use APU flags (Alex)
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 17 Jun 2021 04:48:45 +0000 (12:48 +0800)]
drm/amdgpu: enable psp v11.0.8 for cyan_skillfish
Add psp v11.0.8 to ip block initialization.
v2: use APU flags (Alex)
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Tue, 13 Jul 2021 21:50:23 +0000 (17:50 -0400)]
drm/amdgpu: init psp v11.0.8 function for cyan_skillfish
Add psp v11.0.8 function into psp driver.
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 17 Jun 2021 04:05:41 +0000 (12:05 +0800)]
drm/amdgpu: add psp v11.0.8 driver for cyan_skillfish
Introduce the psp v11.0.8 driver for cyan_skillfish.
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Thu, 17 Jun 2021 03:37:29 +0000 (11:37 +0800)]
drm/amdgpu: add mp 11.0.8 header for cyan_skillfish
The cyan_skillfish will use the mp 11.0.8.
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 1 Jun 2021 09:06:44 +0000 (17:06 +0800)]
drm/amdgpu: add nbio support for cyan_skillfish
nbio version is 2.3.
v2: Make it more explicit (Alex)
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:45:40 +0000 (17:45 -0400)]
drm/amdgpu: add chip early init for cyan_skillfish
Set cg/pg flags and rev id for cyan_skillfish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:34:53 +0000 (17:34 -0400)]
drm/amdkfd: enable cyan_skillfish KFD
Add KFD support for cyan_skillfish.
v2: whitespace fixes (Alex)
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:29:36 +0000 (17:29 -0400)]
drm/amdgpu: add gc v10 golden settings for cyan_skillfish
v2: squash in updates from Ray
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 19 Dec 2018 03:53:08 +0000 (11:53 +0800)]
drm/amdgpu: add sdma v5 golden settings for cyan_skillfish
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:27:35 +0000 (17:27 -0400)]
drm/amdgpu: add cyan_skillfish support in gfx v10
Add gfx support for cyan_skillfish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:25:33 +0000 (17:25 -0400)]
drm/amdgpu: add cyan_skillfish support in gmc v10
Add gmc support for cyan_skillfish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 18 Dec 2018 11:10:03 +0000 (19:10 +0800)]
drm/amdgpu: load fw direclty for cyan_skillfish
Use backdoor loading.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 18 Dec 2018 11:08:16 +0000 (19:08 +0800)]
drm/amdgpu: add sdma fw loading support for cyan_skillfish
Same as Navi10.
v2: squash in updates (Alex)
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:21:27 +0000 (17:21 -0400)]
drm/amdgpu: add cp/rlc fw loading support for cyan_skillfish
Add cp/rlc fw loading support and gfx golden setting.
v2: squash in updates (Alex)
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:19:25 +0000 (17:19 -0400)]
drm/amdgpu: set ip blocks for cyan_skillfish
Add ip blocks for cyan_skillfish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:18:03 +0000 (17:18 -0400)]
drm/amdgpu: init family name for cyan_skillfish
Use FAMILY_NV for cyan_skillfish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:16:43 +0000 (17:16 -0400)]
drm/amdgpu: dynamic initialize ip offset for cyan_skillfish
Add ip offset definition for cyan_skillfish and initialize it.
v2: squash in ip_offset updates (Alex)
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Jul 2021 21:13:48 +0000 (17:13 -0400)]
drm/amdgpu: add cyan_skillfish asic type
Add cyan_skillfish asic family.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Wed, 23 Jun 2021 06:48:34 +0000 (14:48 +0800)]
drm/amdgpu: adjust fw_name string length for toc
Adjust toc fw_name string length to PSP_FW_NAME_LEN.
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 19 May 2021 09:57:35 +0000 (17:57 +0800)]
drm/amdgpu: increase size for sdma fw name string
Longer firmware name needs more space.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 4 Nov 2020 05:04:06 +0000 (13:04 +0800)]
drm/amdgpu: add yellow carp pci id (v2)
Add Yellow Carp PCI id support.
v2: add another DID
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 2 Jun 2021 02:32:41 +0000 (10:32 +0800)]
drm/amdgpu: update yellow carp external rev_id handling
0x1681 has a different external revision id.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kai-Heng Feng [Tue, 20 Jul 2021 17:22:15 +0000 (01:22 +0800)]
drm/amdgpu/acp: Make PM domain really work
Devices created by mfd_add_hotplug_devices() don't really increase the
index of its name, so get_mfd_cell_dev() cannot find any device, hence a
NULL dev is passed to pm_genpd_add_device():
[ 56.974926] (NULL device *): amdgpu: device acp_audio_dma.0.auto added to pm domain
[ 56.974933] (NULL device *): amdgpu: Failed to add dev to genpd
[ 56.974941] [drm:amdgpu_device_ip_init [amdgpu]] *ERROR* hw_init of IP block <acp_ip> failed -22
[ 56.975810] amdgpu 0000:00:01.0: amdgpu: amdgpu_device_ip_init failed
[ 56.975839] amdgpu 0000:00:01.0: amdgpu: Fatal error during GPU init
[ 56.977136] ------------[ cut here ]------------
[ 56.977143] kernel BUG at mm/slub.c:4206!
[ 56.977158] invalid opcode: 0000 [#1] SMP NOPTI
[ 56.977167] CPU: 1 PID: 1648 Comm: modprobe Not tainted 5.12.0-051200rc8-generic #
202104182230
[ 56.977175] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./FM2A68M-HD+, BIOS P5.20 02/13/2019
[ 56.977180] RIP: 0010:kfree+0x3bf/0x410
[ 56.977195] Code: 89 e7 48 d3 e2 f7 da e8 5f 0d 02 00 80 e7 02 75 3e 44 89 ee 4c 89 e7 e8 ef 5f fd ff e9 fa fe ff ff 49 8b 44 24 08 a8 01 75 b7 <0f> 0b 4c 8b 4d b0 48 8b 4d a8 48 89 da 4c 89 e6 41 b8 01 00 00 00
[ 56.977202] RSP: 0018:
ffffa48640ff79f0 EFLAGS:
00010246
[ 56.977210] RAX:
0000000000000000 RBX:
ffff9286127d5608 RCX:
0000000000000000
[ 56.977215] RDX:
0000000000000000 RSI:
ffffffffc099d0fb RDI:
ffff9286127d5608
[ 56.977220] RBP:
ffffa48640ff7a48 R08:
0000000000000001 R09:
0000000000000001
[ 56.977224] R10:
0000000000000000 R11:
ffff9286087d8458 R12:
fffff3ae0449f540
[ 56.977229] R13:
0000000000000000 R14:
dead000000000122 R15:
dead000000000100
[ 56.977234] FS:
00007f9de5929540(0000) GS:
ffff928612e80000(0000) knlGS:
0000000000000000
[ 56.977240] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 56.977245] CR2:
00007f697dd97160 CR3:
00000001110f0000 CR4:
00000000001506e0
[ 56.977251] Call Trace:
[ 56.977261] amdgpu_dm_encoder_destroy+0x1b/0x30 [amdgpu]
[ 56.978056] drm_mode_config_cleanup+0x4f/0x2e0 [drm]
[ 56.978147] ? kfree+0x3dd/0x410
[ 56.978157] ? drm_managed_release+0xc8/0x100 [drm]
[ 56.978232] drm_mode_config_init_release+0xe/0x10 [drm]
[ 56.978311] drm_managed_release+0x9d/0x100 [drm]
[ 56.978388] devm_drm_dev_init_release+0x4d/0x70 [drm]
[ 56.978450] devm_action_release+0x15/0x20
[ 56.978459] release_nodes+0x77/0xc0
[ 56.978469] devres_release_all+0x3f/0x50
[ 56.978477] really_probe+0x245/0x460
[ 56.978485] driver_probe_device+0xe9/0x160
[ 56.978492] device_driver_attach+0xab/0xb0
[ 56.978499] __driver_attach+0x8f/0x150
[ 56.978506] ? device_driver_attach+0xb0/0xb0
[ 56.978513] bus_for_each_dev+0x7e/0xc0
[ 56.978521] driver_attach+0x1e/0x20
[ 56.978528] bus_add_driver+0x135/0x1f0
[ 56.978534] driver_register+0x91/0xf0
[ 56.978540] __pci_register_driver+0x54/0x60
[ 56.978549] amdgpu_init+0x77/0x1000 [amdgpu]
[ 56.979246] ? 0xffffffffc0dbc000
[ 56.979254] do_one_initcall+0x48/0x1d0
[ 56.979265] ? kmem_cache_alloc_trace+0x120/0x230
[ 56.979274] ? do_init_module+0x28/0x280
[ 56.979282] do_init_module+0x62/0x280
[ 56.979288] load_module+0x71c/0x7a0
[ 56.979296] __do_sys_finit_module+0xc2/0x120
[ 56.979305] __x64_sys_finit_module+0x1a/0x20
[ 56.979311] do_syscall_64+0x38/0x90
[ 56.979319] entry_SYSCALL_64_after_hwframe+0x44/0xae
[ 56.979328] RIP: 0033:0x7f9de54f989d
[ 56.979335] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d c3 f5 0c 00 f7 d8 64 89 01 48
[ 56.979342] RSP: 002b:
00007ffe3c395a28 EFLAGS:
00000246 ORIG_RAX:
0000000000000139
[ 56.979350] RAX:
ffffffffffffffda RBX:
0000560df3ef4330 RCX:
00007f9de54f989d
[ 56.979355] RDX:
0000000000000000 RSI:
0000560df3a07358 RDI:
000000000000000f
[ 56.979360] RBP:
0000000000040000 R08:
0000000000000000 R09:
0000000000000000
[ 56.979365] R10:
000000000000000f R11:
0000000000000246 R12:
0000560df3a07358
[ 56.979369] R13:
0000000000000000 R14:
0000560df3ef4460 R15:
0000560df3ef4330
[ 56.979377] Modules linked in: amdgpu(+) iommu_v2 gpu_sched drm_ttm_helper ttm drm_kms_helper cec rc_core i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt nft_counter xt_tcpudp ipt_REJECT nf_reject_ipv4 xt_conntrack iptable_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 iptable_mangle iptable_raw iptable_security ip_set nf_tables libcrc32c nfnetlink ip6_tables iptable_filter bpfilter input_leds binfmt_misc edac_mce_amd kvm_amd ccp kvm snd_hda_codec_realtek snd_hda_codec_generic crct10dif_pclmul snd_hda_codec_hdmi ledtrig_audio ghash_clmulni_intel aesni_intel snd_hda_intel snd_intel_dspcfg snd_seq_midi crypto_simd snd_intel_sdw_acpi cryptd snd_hda_codec snd_seq_midi_event snd_rawmidi snd_hda_core snd_hwdep snd_seq fam15h_power k10temp snd_pcm snd_seq_device snd_timer snd mac_hid soundcore sch_fq_codel nct6775 hwmon_vid drm ip_tables x_tables autofs4 dm_mirror dm_region_hash dm_log hid_generic usbhid hid uas usb_storage r8169 crc32_pclmul realtek ahci xhci_pci i2c_piix4
[ 56.979521] xhci_pci_renesas libahci video
[ 56.979541] ---[ end trace
cb8f6a346f18da7b ]---
Instead of finding MFD hotplugged device by its name, simply iterate
over the child devices to avoid the issue.
Squash in unused variable removal (Alex)
BugLink: https://bugs.launchpad.net/bugs/1920674
Fixes:
25030321ba28 ("drm/amd: add pm domain for ACP IP sub blocks")
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Candice Li [Wed, 21 Jul 2021 17:55:59 +0000 (13:55 -0400)]
drm/amd/amdgpu: add consistent PSP FW loading size checking
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jingwen Chen [Tue, 20 Jul 2021 10:35:35 +0000 (18:35 +0800)]
drm/amd/amdgpu: consider kernel job always not guilty
[Why]
Currently all timedout job will be considered to be guilty. In SRIOV
multi-vf use case, the vf flr happens first and then job time out is
found. There can be several jobs timeout during a very small time slice.
And if the innocent sdma job time out is found before the real bad
job, then the innocent sdma job will be set to guilty. This will lead
to a page fault after resubmitting job.
[How]
If the job is a kernel job, we will always consider it not guilty
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Graham Sider [Tue, 6 Jul 2021 21:46:37 +0000 (17:46 -0400)]
drm/amdkfd: Update SMI throttle event bitmask
Update Arcturus/Aldebaran thermal throttle SMI event path to use
ASIC-independent throttler bits when logging.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anson Jacob [Mon, 19 Jul 2021 17:46:09 +0000 (13:46 -0400)]
drm/amdgpu: Fix documentaion for dm_dmub_outbox1_low_irq
Fix make htmldocs complaint:
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:628: warning: Excess function parameter 'interrupt_params' description in 'DMUB_TRACE_MAX_READ'
v2:
Moved DMUB_TRACE_MAX_READ macro above function documentation
Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
CC: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anson Jacob [Tue, 20 Jul 2021 15:43:20 +0000 (11:43 -0400)]
drm/amd/amdgpu: Add a new line to debugfs phy_settings output
Add new line to phy_settings output
Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anson Jacob [Tue, 20 Jul 2021 15:00:44 +0000 (11:00 -0400)]
drm/amd/amdgpu: Update debugfs link_settings output link_rate field in hex
link_rate is updated via debugfs using hex values, set it to output
in hex as well.
eg: Resolution: 1920x1080@144Hz
cat /sys/kernel/debug/dri/0/DP-1/link_settings
Current: 4 0x14 0 Verified: 4 0x1e 0 Reported: 4 0x1e 16 Preferred: 0 0x0 0
echo "4 0x1e" > /sys/kernel/debug/dri/0/DP-1/link_settings
cat /sys/kernel/debug/dri/0/DP-1/link_settings
Current: 4 0x1e 0 Verified: 4 0x1e 0 Reported: 4 0x1e 16 Preferred: 4 0x1e 0
Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Thu, 15 Jul 2021 23:34:25 +0000 (18:34 -0500)]
drm/amdkfd: Fix a concurrency issue during kfd recovery
start_cpsch and stop_cpsch can be called during kfd device
initialization or during gpu reset/recovery. So they can
run concurrently. Currently in start_cpsch and stop_cpsch,
pm_init and pm_uninit is not protected by the dpm lock.
Imagine such a case that user use packet manager's function
to submit a pm4 packet to hang hws (ie through command
cat /sys/class/kfd/kfd/topology/nodes/1/gpu_id | sudo tee
/sys/kernel/debug/kfd/hang_hws), while kfd device is under
device reset/recovery so packet manager can be not initialized.
There will be unpredictable protection fault in such case.
This patch moves pm_init/uninit inside the dpm lock and check
packet manager is initialized before using packet manager
function.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Thu, 15 Jul 2021 22:02:46 +0000 (17:02 -0500)]
drm/amdkfd: Set priv_queue to NULL after it is freed
This variable will be used to determine whether packet
manager is initialized or not, in a future patch.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Thu, 15 Jul 2021 19:57:16 +0000 (14:57 -0500)]
drm/amdkfd: Renaming dqm->packets to dqm->packet_mgr
Renaming packets to packet_mgr to reflect the real meaning
of this variable.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Wed, 14 Jul 2021 14:59:51 +0000 (09:59 -0500)]
drm/amdgpu: Change a few function names
Function name "psp_np_fw_load" is not proper as people don't
know _np_fw_ means "non psp firmware". Change the function
name to psp_load_non_psp_fw for better understanding. Same
thing for function psp_execute_np_fw_load.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Wed, 14 Jul 2021 14:50:37 +0000 (09:50 -0500)]
drm/amdgpu: Fix a printing message
The printing message "PSP loading VCN firmware" is mis-leading because
people might think driver is loading VCN firmware. Actually when this
message is printed, driver is just preparing some VCN ucode, not loading
VCN firmware yet. The actual VCN firmware loading will be in the PSP block
hw_init. Fix the printing message
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roy Sun [Thu, 8 Jul 2021 08:18:30 +0000 (16:18 +0800)]
drm/amdgpu: Add error message when programing registers fails
Squash in warning fix (Alex)
Signed-off-by: Roy Sun <Roy.Sun@amd.com>
Reviewed-by: Zhou pengju <pengju.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roy Sun [Mon, 5 Jul 2021 09:47:57 +0000 (17:47 +0800)]
drm/amdgpu: Change the imprecise function name
The callback functions are used for SRIOV read/write instead
of just for rlcg read/write
Signed-off-by: Roy Sun <Roy.Sun@amd.com>
Reviewed-by: Zhou pengju <pengju.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Veerabadhran Gopalakrishnan [Mon, 19 Jul 2021 13:36:23 +0000 (19:06 +0530)]
drm/amdgpu - Corrected the video codecs array name for yellow carp
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Wed, 2 Jun 2021 13:46:16 +0000 (09:46 -0400)]
drm/amdkfd: report pcie bandwidth to the kfd
Similar to xGMI reporting the min/max bandwidth between direct peers, PCIe
will report the min/max bandwidth to the KFD.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Wed, 12 May 2021 16:30:41 +0000 (12:30 -0400)]
drm/amdkfd: report xgmi bandwidth between direct peers to the kfd
Report the min/max bandwidth in megabytes to the kfd for direct
xgmi connections only. Indirect peers will report 0 since
indirect route is unknown.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Wed, 12 May 2021 16:26:20 +0000 (12:26 -0400)]
drm/amdgpu: add psp command to get num xgmi links between direct peers
The TA can now be invoked to provide the number of xgmi links connecting
a direct source and destination peer.
Non-direct peers will report zero links.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anson Jacob [Mon, 19 Jul 2021 15:09:40 +0000 (11:09 -0400)]
drm/amdgpu: Fix documentaion for amdgpu_bo_add_to_shadow_list
make htmldocs complaints about parameter for amdgpu_bo_add_to_shadow_list
./drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:739: warning: Excess function parameter 'bo' description in 'amdgpu_bo_add_to_shadow_list'
./drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:739: warning: Function parameter or member 'vmbo' not described in 'amdgpu_bo_add_to_shadow_list'
./drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:739: warning: Excess function parameter 'bo' description in 'amdgpu_bo_add_to_shadow_list'
Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Thu, 15 Jul 2021 06:54:49 +0000 (14:54 +0800)]
drm/amd/pm: Support board calibration on aldebaran
Add support for board power calibration on Aldebaran.
Board calibration is done after DC offset calibration.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Wed, 30 Jun 2021 22:22:51 +0000 (18:22 -0400)]
drm/amd/display: change zstate allow msg condition
[Why]
PMFW message which previously thought to only control Z9 controls both
Z9 and Z10. Also HW design team requested that Z9 must only be supported
on eDP due to content protection interop.
[How]
Change zstate support condition to match updated policy
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sun, 11 Jul 2021 01:40:45 +0000 (21:40 -0400)]
drm/amd/display: 3.2.145
DC version 3.2.145 brings improvements in multiple areas. In summary, we
highlight:
- Code improvements for passive
- Cursor manipulation enhancements
- Expand debug in some areas
- Fix problems in DML
- Other minor code refactors
Reviewed-by: Anson Jacob <Anson.Jacob@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sun, 11 Jul 2021 02:03:07 +0000 (22:03 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.75
- Add reserved bits for future feature development
- Fix issue with mismatch with type const
- Replaced problematic code with old memcpy and casted problematic
pointers to unsigned char pointers
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krunoslav Kovac [Fri, 9 Jul 2021 14:25:44 +0000 (10:25 -0400)]
drm/amd/display: Refine condition for cursor visibility
[why]
There's a special case where upper plane is not the main plane. If it owns
the cursor, it will be invisible in the majority of the screen.
[How]
The condition for disabling cursor is changed:
- check if upper viewport completely covers current. This was the
previous change that doesn't handle all scenarios with pipe splitting.
- if not, show the cursor only if it's not scaled or no upper pipe.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bindu Ramamurthy [Fri, 9 Jul 2021 14:35:33 +0000 (10:35 -0400)]
drm/amd/display: Populate dtbclk entries for dcn3.02/3.03
[Why]
Populate dtbclk values from bwparams for dcn302, dcn303.
[How]
dtbclk values are fetched from bandwidthparams for all DPM levels and
for DPM levels where smu returns 0, previous level values are reported.
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Fri, 9 Jul 2021 16:57:50 +0000 (12:57 -0400)]
drm/amd/display: add workaround for riommu invalidation request hang
[Why]
When an riommu invalidation request come at the same time as a pipe is
disabled there can be a case where DCN cannot ACK the request if only
one VMID is setup in the inuse list.
[How]
Setup a second unused VMID will work around the issue.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nevenko Stupar [Fri, 9 Jul 2021 17:05:11 +0000 (13:05 -0400)]
drm/amd/display: Line Buffer changes
DCN 3x increased Line buffer size for DCHUB latency hiding, from 4 lines
of 4K resolution lines to 5 lines of 4K resolution lines. All Line
Buffer can be used as extended memory for P State change latency hiding.
The maximum number of lines is increased to 32 lines. Finally,
LB_MEMORY_CONFIG_1 (LB memory piece 1) and LB_MEMORY _CONFIG_2 (LB
memory piece 2) are not affected, no change in size, only 3 pieces is
affected, i.e., when all 3 pieces are used in both LB_MEMORY_CONFIG_0
and LB_MEMORY_CONFIG_3 (for 4:2:0) modes.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Tue, 15 Jun 2021 00:21:42 +0000 (20:21 -0400)]
drm/amd/display: Remove MALL function from DCN3.1
[why]
DCN31 doesn't have MALL in DMUB so to avoid sending unknown commands to
DMUB just remove the function pointer.
[how]
Remove apply_idle_power_optimizations from function pointers structure
for DCN31
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
sunglee [Fri, 9 Jul 2021 14:24:14 +0000 (10:24 -0400)]
drm/amd/display: DCN2X Prefer ODM over bottom pipe to find second pipe
[WHY]
When finding a second pipe for pipe split, currently will look for
bottom pipe in context first to decide the second pipe. This causes
issues in 2 plane to 1 plane transitions like fullscreen video where
bottom pipe no longer exists in the new configuration.
[HOW]
If previous context had an ODM pipe, use that to find the secondary pipe
first before looking at bottom pipe.
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: sunglee <sunglee@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Camille Cho [Thu, 8 Jul 2021 10:28:37 +0000 (18:28 +0800)]
drm/amd/display: Only set default brightness for OLED
[Why]
We used to unconditionally set backlight path as AUX for panels capable
of backlight adjustment via DPCD in set default brightness.
[How]
This should be limited to OLED panel only since we control backlight via
PWM path for SDR mode in LCD HDR panel.
Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Camille Cho <Camille.Cho@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 8 Jul 2021 16:59:59 +0000 (12:59 -0400)]
drm/amd/display: Update bounding box for DCN3.1
[Why & How]
We're missing a default value for dram_channel_width_bytes in the
DCN3.1 SOC bounding box and we don't currently have the interface in
place to query the actual value from VBIOS.
Put in a hardcoded default until we have the interface in place.
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 7 Jul 2021 20:38:57 +0000 (16:38 -0400)]
drm/amd/display: Query VCO frequency from register for DCN3.1
[Why]
Hardcoding the VCO frequency isn't correct since we don't own or control
the value.
In the case where the hardcode is also missing we can't lightup display.
[How]
Query from the CLK register instead. Update the DFS frequency to be able
to compute the VCO frequency.
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bindu Ramamurthy [Thu, 27 May 2021 14:11:32 +0000 (10:11 -0400)]
drm/amd/display: Populate socclk entries for dcn3.02/3.03
[Why]
Initialize socclk entries in bandwidth params for dcn302, dcn303.
[How]
Fetch the sockclk values from smu for the DPM levels and for the DPM
levels where smu returns 0, previous level values are reported.
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 7 Jul 2021 17:19:14 +0000 (13:19 -0400)]
drm/amd/display: Fix max vstartup calculation for modes with borders
[Why]
Vertical and horizontal borders in timings are treated as increasing the
active area - vblank and hblank actually shrink.
Our input into DML does not include these borders so it incorrectly
assumes it has more time than available for vstartup and tmdl
calculations for some modes with borders.
An example of such a timing would be 640x480@72Hz:
h_total: 832
h_border_left: 8
h_addressable: 640
h_border_right: 8
h_front_porch: 16
h_sync_width: 40
v_total: 520
v_border_top: 8
v_addressable: 480
v_border_bottom: 8
v_front_porch: 1
v_sync_width: 3
pix_clk_100hz: 315000
[How]
Include borders as part of destination vactive/hactive.
This change DCN20+ so it has wide impact, but the destination vactive
and hactive are only really used for vstartup calculation anyway.
Most modes do not have vertical or horizontal borders.
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Tue, 6 Jul 2021 18:52:12 +0000 (14:52 -0400)]
drm/amd/display: Enable eDP ILR on DCN2.1
[WHY]
Enable feature for 21.40
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Tue, 6 Jul 2021 00:53:23 +0000 (20:53 -0400)]
drm/amd/display: 3.2.144
Reviewed-by: Shahin Khayyer <Shahin.Khayyer@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Thu, 24 Jun 2021 15:05:42 +0000 (11:05 -0400)]
drm/amd/display: Fix comparison error in dcn21 DML
[why]
A comparison error made it possible to not iterate through all the
specified prefetch modes.
[how]
Correct "<" to "<="
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Yongqiang Sun <Yongqiang.Sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jake Wang [Wed, 30 Jun 2021 17:55:50 +0000 (13:55 -0400)]
drm/amd/display: Fixed hardware power down bypass during headless boot
[Why]
During headless boot, DIG may be on which causes HW/SW discrepancies.
To avoid this we power down hardware on boot if DIG is turned on. With
introduction of multiple eDP, hardware power down is being bypassed
under certain conditions.
[How]
Fixed hardware power down bypass, and ensured hardware will power down
if DIG is on and seamless boot is not enabled.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wesley Chalmers [Wed, 30 Jun 2021 14:42:23 +0000 (10:42 -0400)]
drm/amd/display: Add copyright notice to new files
Reviewed-by: Shahin Khayyer <Shahin.Khayyer@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan Liu [Tue, 29 Jun 2021 01:20:18 +0000 (21:20 -0400)]
drm/amd/display: Reduce delay when sink device not able to ACK 00340h write
[Why]
Theoretically, per DP 1.4a spec, sink device needs to AUX_ACK 00340h
write. However, due to hardware limitation, some sink devices have no
00340h dpcd address at all. This results in sink side fails to reply
ACK, and consequently cause source side keep retrying DPCD write on DPCD
00340h. This results in significant delay when DPCD 00340h write is
triggered (e.g. at S3 resume).
[How]
Check whether sink device could ACK on DPCD 00340h write on boot. If
sink device fails to ACK, then remember that, so we won't write to DPCD
00340h later on.
There will be a drm.debug KMS level message to inform user once a 00340h
DPCD write is skipped on purpose.
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Tue, 29 Jun 2021 01:41:08 +0000 (21:41 -0400)]
drm/amd/display: add debug print for DCC validation failure
[Why&How]
Print a debug message when dcc validation fails in the display driver.
Most DCC enablement related errors are from userspace. Adding a debug
print in case of a failure from display driver will aid quicker triage.
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 25 Jun 2021 20:36:01 +0000 (16:36 -0400)]
drm/amd/display: 3.2.143
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Fri, 25 Jun 2021 19:42:54 +0000 (15:42 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.73
- Add reserved bits for future feature development
- Fix issue with mismatch with type const
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 25 Jun 2021 13:09:09 +0000 (09:09 -0400)]
drm/amd/display: remove compbuf size wait
This tends to take miliseconds in certain scenarios and we'd rather not
wait that long. Due to how this interacts with det size update and
locking waiting should not be necessary as compbuf updates before
unlock.
Add a watch for config error instead as that is something we actually do
care about.
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Thu, 24 Jun 2021 02:48:43 +0000 (10:48 +0800)]
drm/amd/display: Extend dmub_cmd_psr_copy_settings_data struct
Reserve padding bytes for new feature implementation
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Wed, 23 Jun 2021 19:48:02 +0000 (15:48 -0400)]
drm/amd/display: implement workaround for riommu related hang
[Why]
During S4/S5/reboot, sometimes riommu invalidation request arrive too
early, DCN may be unable to respond to the invalidation request
resulting in pstate hang.
[How]
VBIOS will force allow pstate for riommu invalidation and driver will
clear it after powering down display pipes.
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Mon, 21 Jun 2021 16:17:24 +0000 (12:17 -0400)]
drm/amd/display: log additional register state for debug
[Why & How]
Extend existing state collection functions to add some additional
registers useful for debug, and add state collection function for DC
hubbub
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Thu, 17 Jun 2021 20:17:09 +0000 (16:17 -0400)]
drm/amd/display: Prevent Diags from entering S2
[why]
Lowering clocks when entering S2 Idle state causes DMUB to hang with
Diags.
[how]
Do not enter S2 optimization with Diags on dcn301 to prevent DMUB hang.
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oliver Logush [Wed, 23 Jun 2021 19:04:04 +0000 (15:04 -0400)]
drm/amd/display: Fix timer_per_pixel unit error
[why]
The units of the time_per_pixel variable were incorrect, this had to be
changed for the code to properly function.
[how]
The change was very straightforward, only required one line of code to
be changed where the calculation was done.
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Oliver Logush <oliver.logush@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krunoslav Kovac [Tue, 22 Jun 2021 22:42:28 +0000 (18:42 -0400)]
drm/amd/display: Assume active upper layer owns the HW cursor
[why]
The current logic checks if there's an upper pipe whose viewport
completely covers the current pipe viewport.
This fails in pipe splitting case as you can have layer 1 pipe that
crosses the two layer 0 pipes where it's contained in both, but neither
covers it completely, hence we allow the cursor on both layers.
[How]
Instead of trying to "sum up" rectangles from the higher level pipes
which could leave gaps and would not work generically, we will assume if
there's an upper layer that is active, it will control the HW cursor.
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 23 Jun 2021 01:32:53 +0000 (21:32 -0400)]
drm/amd/display: reset dpcd_cap.dpcd_rev for passive dongle.
[why]
currently dc has never reset this dpcd_cap.dpcd_rev.
[how]
ideally we should reset this before redo detection.
change the passive dongle only for now to reduce the impact.
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Liviu Dudau [Wed, 14 Jul 2021 08:06:52 +0000 (09:06 +0100)]
drm/amd/display: Fix 10bit 4K display on CIK GPUs
Commit
72a7cf0aec0c ("drm/amd/display: Keep linebuffer pixel depth at
30bpp for DCE-11.0.") doesn't seems to have fixed 10bit 4K rendering over
DisplayPort for CIK GPUs. On my machine with a HAWAII GPU I get a broken
image that looks like it has an effective resolution of 1920x1080 but
scaled up in an irregular way. Reverting the commit or applying this
patch fixes the problem on v5.14-rc1.
Fixes:
72a7cf0aec0c ("drm/amd/display: Keep linebuffer pixel depth at 30bpp for DCE-11.0.")
Acked-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Liviu Dudau <liviu@dudau.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 16 Jul 2021 18:03:08 +0000 (14:03 -0400)]
drm/amdgpu/ttm: optimize vram access in amdgpu_ttm_access_memory()
1. using vram aper to access vram if possible
2. avoid MM_INDEX/MM_DATA is not working when mmio protect feature is
enabled.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 15 Jul 2021 07:51:28 +0000 (15:51 +0800)]
drm/amdgpu/ttm: replace duplicate code with exiting function
using exiting function to replace duplicate code blocks in
amdgpu_ttm_vram_write().
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 16 Jul 2021 17:57:49 +0000 (13:57 -0400)]
drm/amdgpu: split amdgpu_device_access_vram() into two small parts
split amdgpu_device_access_vram()
1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram
2. amdgpu_device_aper_access(): using vram aperature to access vram (option)
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Thu, 15 Jul 2021 14:37:40 +0000 (15:37 +0100)]
drm/amdgpu/display: make a const array common_rates static, makes object smaller
Don't populate the const array common_rates on the stack but instead it
static. Makes the object code smaller by 80 bytes:
Before:
text data bss dec hex filename
268019 98322 256 366597 59805 ../display/amdgpu_dm/amdgpu_dm.o
After:
text data bss dec hex filename
267843 98418 256 366517 597b5 ../display/amdgpu_dm/amdgpu_dm.o
Reduction of 80 bytes
(gcc version 10.3.0)
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 15 Jul 2021 06:52:37 +0000 (14:52 +0800)]
drm/amd/pm: update DRIVER_IF_VERSION for beige_goby
Update the version to 0xD for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 15 Jul 2021 06:49:08 +0000 (14:49 +0800)]
drm/amdgpu: update gc golden setting for dimgrey_cavefish
Update gc_10_3_4 golden setting.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>