Aart Bik [Fri, 17 Jun 2022 00:01:42 +0000 (17:01 -0700)]
[mlir][sparse] move from by-value to by-reference for data types
This fixes all sorts of ABI issues due to passing by-value
(using by-reference with memref's exclusively).
Reviewed By: bkramer
Differential Revision: https://reviews.llvm.org/D128018
Christopher Bate [Tue, 7 Jun 2022 16:51:27 +0000 (10:51 -0600)]
[mlir][nvgpu] shared memory access optimization pass
This change adds a transformation and pass to the NvGPU dialect that
attempts to optimize reads/writes from a memref representing GPU shared
memory in order to avoid bank conflicts. Given a value representing a
shared memory memref, it traverses all reads/writes within the parent op
and, subject to suitable conditions, rewrites all last dimension index
values such that element locations in the final (col) dimension are
given by
`newColIdx = col % vecSize + perm[row](col/vecSize,row)`
where `perm` is a permutation function indexed by `row` and `vecSize`
is the vector access size in elements (currently assumes 128bit
vectorized accesses, but this can be made a parameter). This specific
transformation can help optimize typical distributed & vectorized accesses
common to loading matrix multiplication operands to/from shared memory.
Differential Revision: https://reviews.llvm.org/D127457
Guillaume Chatelet [Fri, 17 Jun 2022 15:13:10 +0000 (15:13 +0000)]
[NFC][Alignment] Remove assumeAligned from MachineFrameInfo ctor
Quinn Pham [Fri, 17 Jun 2022 14:33:32 +0000 (09:33 -0500)]
[PowerPC] Fix PPCVSXSwapRemoval pass to include MTVSCR and MFVSCR as not swappable.
This patch adds the instructions `MTVSCR` and `MFVSCR` as not swappable to the
PPCVSXSwapRemoval pass because they are not lane-insensitive. This will prevent
the compiler from optimizing out required swaps when using `lxvd2x` and
`stxvd2x`.
Reviewed By: #powerpc, nemanjai
Differential Revision: https://reviews.llvm.org/D128062
Philip Reames [Fri, 17 Jun 2022 15:01:49 +0000 (08:01 -0700)]
[RISCV] Avoid changing etype for splat of 0 or -1
A splat of the values 0 and -1 as sign extended 12 bit immediates are always the same bit pattern regardless of the etype used to perform the operation. As a result, we can sometimes avoid introducing a vsetvli just for the purposes of a splat.
Looking at the diffs, we don't get a huge amount of immediate value out of this. We mostly push the vsetvli one instruction down, usually in front of a vmerge. We also don't get the corresponding fixed length vector cases because VL typically is changed despite the actual bits written being the same. Both of these are areas I plan to explore in future patches.
Interestingly, this makes a great example of why we need the forward and backward implementation to be consistent. Before we merged the demanded field handling, if we implement only the forward direction, we lost the ability to mutate a prior vsetvli and eliminate a later one entirely. This resulted in practical regressions instead of improvements. It's always nice when practice matches theory. :)
Differential Revision: https://reviews.llvm.org/D128006
Ben Langmuir [Thu, 16 Jun 2022 21:00:35 +0000 (14:00 -0700)]
[clang][deps] Sort submodules when calculating dependencies
Dependency scanning does not care about the order of submodules for
correctness, so sort the submodules so that we get the same
command-lines to build the module across different TUs. The order of
inferred submodules can vary depending on the order of #includes in the
including TU.
Differential Revision: https://reviews.llvm.org/D128008
Sanjay Patel [Fri, 17 Jun 2022 14:41:00 +0000 (10:41 -0400)]
[InstCombine] convert mask and shift of power-of-2 to cmp+select
When the mask is a power-of-2 constant and op0 is a shifted-power-of-2
constant, test if the shift amount equals the offset bit index:
(ShiftC << X) & C --> X == (log2(C) - log2(ShiftC)) ? C : 0
(ShiftC >> X) & C --> X == (log2(ShiftC) - log2(C)) ? C : 0
This is an alternate to D127610 with a more general pattern.
We match only shift+and instead of the trailing xor, so we see a few
more tests diffs. I think we discussed this initially in D126617.
Here are proofs for shifts in both directions:
https://alive2.llvm.org/ce/z/CFrLs4
The test diffs look equal or better for IR, and this makes the
patterns more uniform in IR. The backend can partially invert this
in both cases if that is profitable. It is not trivially reversible,
however, so if we find perf regressions that are not easy to undo,
then we may want to revert this.
Differential Revision: https://reviews.llvm.org/D127801
Kadir Cetinkaya [Fri, 17 Jun 2022 14:47:29 +0000 (16:47 +0200)]
Revert "Revert "[clang] Dont print implicit forrange initializer""
This reverts commit
7aac15d5df6cfa03b802e055b63227a95fa1734e.
Only updates the tests, as these statements are still part of the CFG
and its just the pretty printer policy that changes. Hopefully this
shouldn't affect any analysis.
Guillaume Chatelet [Fri, 17 Jun 2022 13:28:47 +0000 (13:28 +0000)]
[libc] Rely on __builtin_memcpy_inline for memcpy implementation
This patch removes usage of `-mllvm -combiner-global-alias-analysis`
and relies on compiler builtin to implement `memcpy`.
Note that `-mllvm -combiner-global-alias-analysis` is actually only useful for
functions where buffers can alias (namely `memcpy` and `memmove`). The other
memory functions where not benefiting from the flag anyways.
The upside is that the memory functions can now be compiled from source with
thinlto (thinlto would not be able to carry on the flag when doing inlining).
The downside is that for compilers other than clang (i.e. not providing
`__builtin_memcpy_inline`) the codegen may be worse.
Differential Revision: https://reviews.llvm.org/D128051
Eric Schweitz [Fri, 17 Jun 2022 14:09:32 +0000 (16:09 +0200)]
[flang] Fix bug in character casting. Add missing sext/trunc in code gen.
This patch is part of the upstreaming effort from fir-dev branch.
It also ensures all descriptors created inline complies with LBOUND
requirement that the lower bound is `1` when the related dimension
extent is zero.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier, PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D128047
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
Joe Nash [Tue, 14 Jun 2022 19:57:17 +0000 (15:57 -0400)]
[AMDGPU] gfx11 waitcnt support for VINTERP and LDSDIR instructions
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D127781
Malhar Jajoo [Fri, 17 Jun 2022 13:01:04 +0000 (14:01 +0100)]
[LoopVectorize] Add support for invariant stores of ordered reductions
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D126772
Nikolas Klauser [Fri, 17 Jun 2022 11:58:22 +0000 (13:58 +0200)]
[libc++] Simplify __config a bit
Simplify logic in `__config` by assuming that we are using Clang in C++03 mode. Also, use standardized feature-test macros instead of compiler-specific checks (like `__has_feature`) in a couple of places.
Reviewed By: ldionne, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D127606
Joe Nash [Thu, 9 Jun 2022 19:10:47 +0000 (15:10 -0400)]
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
Depends on D127664
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D127756
Tue Ly [Fri, 17 Jun 2022 13:32:06 +0000 (09:32 -0400)]
[libc][Obvious] Fix hyperlink and typo in math status page.
Phoebe Wang [Fri, 17 Jun 2022 13:09:19 +0000 (21:09 +0800)]
Reland "Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86 following the psABI""""
This resolves problems reported in commit
1a20252978c76cf2518aa45b175a9e5d6d36c4f0.
1. Promote to float lowering for nodes XINT_TO_FP
2. Bail out f16 from shuffle combine due to vector type is not legal in the version
Joe Nash [Mon, 13 Jun 2022 14:38:48 +0000 (10:38 -0400)]
[AMDGPU] gfx11 ldsdir intrinsics and ISel
Reviewed By: #amdgpu, rampitec
Differential Revision: https://reviews.llvm.org/D127664
Jay Foad [Fri, 17 Jun 2022 13:25:13 +0000 (14:25 +0100)]
[AMDGPU] More GFX11 test coverage
Nikita Popov [Thu, 16 Jun 2022 10:13:37 +0000 (12:13 +0200)]
[InstCombine] Push freeze through recurrence phi
We really want to push freezes through recurrence phis, so that we
freeze only the start value, rather than the IV value on every
iteration. foldOpIntoPhi() already handles this for the case where
the transfer function doesn't produce poison, e.g.
%iv.next = add %iv, 1. However, this does not work if nowrap flags
are present, e.g. the very common %iv.next = add nuw %iv, 1 case.
This patch adds a fold that pushes freeze instructions to the start
value by checking whether all backedge values will be non-poison
after poison generating flags have been dropped. This allows pushing
freezes out of loops in most cases. I suspect that this also
obsoletes the CanonicalizeFreezeInLoops pass, and we can probably
drop it.
Fixes https://github.com/llvm/llvm-project/issues/56048.
Differential Revision: https://reviews.llvm.org/D127960
Nico Weber [Fri, 17 Jun 2022 12:58:48 +0000 (08:58 -0400)]
Revert "[clang] Dont print implicit forrange initializer"
This reverts commit
32805e60c9de1f82887cd2af30d247dcabd2e1d3.
Broke check-clang, see comments on https://reviews.llvm.org/D127863
Sanjay Patel [Fri, 17 Jun 2022 12:19:07 +0000 (08:19 -0400)]
[InstCombine] add tests for FP casts; NFC
Sanjay Patel [Wed, 15 Jun 2022 21:31:58 +0000 (17:31 -0400)]
[InstCombine] add tests for (pow2 >> X) >u C; NFC
Paul Walker [Thu, 9 Jun 2022 03:03:10 +0000 (04:03 +0100)]
[SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases.
WidenVecOp_INSERT_SUBVECTOR only supported cases where widening
effectively converts the insert into a copy. However, when the
widened subvector is no bigger than the vector being inserted into
and we can be sure there's no loss of data, we can simply emit
another INSERT_SUBVECTOR.
Fixes: #54982
Differential Revision: https://reviews.llvm.org/D127508
Nico Weber [Fri, 17 Jun 2022 12:35:45 +0000 (08:35 -0400)]
[gn build] (semi-manually) port
232bd331cbaa
Michał Górny [Fri, 17 Jun 2022 09:16:30 +0000 (11:16 +0200)]
[lldb] [test] Update baseline test status for FreeBSD
Fixes #19721
Fixes #18440
Partially fixes bug #47660
Fixes #47761
Fixes #47763
Sponsored by: The FreeBSD Foundation
Matthias Springer [Fri, 17 Jun 2022 12:01:25 +0000 (14:01 +0200)]
[mlir][bufferize][NFC] Remove BufferizationState
With the recent refactorings, this class is no longer needed. We can use BufferizationOptions in all places were BufferizationState was used.
Differential Revision: https://reviews.llvm.org/D127653
Jolanta Jensen [Fri, 17 Jun 2022 11:15:19 +0000 (12:15 +0100)]
[Clang] Allow 'Complex float __attribute__((mode(HC)))'
Adding half float to types that can be represented by __attribute__((mode(xx))).
Original implementation authored by George Steed.
Differential Revision: https://reviews.llvm.org/D126479
Matthias Springer [Fri, 17 Jun 2022 11:23:25 +0000 (13:23 +0200)]
[mlir][bufferize] Bufferize after TensorCopyInsertion
This change changes the bufferization so that it utilizes the new TensorCopyInsertion pass. One-Shot Bufferize no longer calls the One-Shot Analysis. Instead, it relies on the TensorCopyInsertion pass to make the entire IR fully inplacable. The `bufferize` implementations of all ops are simplified; they no longer have to account for out-of-place bufferization decisions. These were already materialized in the IR in the form of `bufferization.alloc_tensor` ops during the TensorCopyInsertion pass.
Differential Revision: https://reviews.llvm.org/D127652
Jay Foad [Fri, 17 Jun 2022 10:31:50 +0000 (11:31 +0100)]
[AMDGPU] Use explicit -global-isel=0/1 in tests. NFC.
lorenzo chelini [Sat, 11 Jun 2022 14:48:01 +0000 (16:48 +0200)]
[LLVM][IR] Fix typo in DerivedTypes.h (NFC)
Tiehu Zhang [Fri, 17 Jun 2022 10:24:23 +0000 (18:24 +0800)]
[AArch64][LV] AArch64 does not prefer vectorized addressing
TTI::prefersVectorizedAddressing() try to vectorize the addresses that lead to loads.
For aarch64, only gather/scatter (supported by SVE) can deal with vectors of addresses.
This patch specializes the hook for AArch64, to return true only when we enable SVE.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D124612
Kadir Cetinkaya [Wed, 15 Jun 2022 14:56:19 +0000 (16:56 +0200)]
[clang] Dont print implicit forrange initializer
Fixes https://github.com/clangd/clangd/issues/1158
Differential Revision: https://reviews.llvm.org/D127863
Nikita Popov [Fri, 17 Jun 2022 09:21:54 +0000 (11:21 +0200)]
[IR] Check for SignedMin/-1 division in canTrap() (PR56038)
In addition to division by zero, signed division also traps for
SignedMin / -1. This was handled in isSafeToSpeculativelyExecute(),
but not in Constant::canTrap().
Alex Zinenko [Thu, 16 Jun 2022 10:53:49 +0000 (12:53 +0200)]
[mlir] replace 'emit_c_wrappers' func->llvm conversion option with a pass
The 'emit_c_wrappers' option in the FuncToLLVM conversion requests C interface
wrappers to be emitted for every builtin function in the module. While this has
been useful to bootstrap the interface, it is problematic in the longer term as
it may unintentionally affect the functions that should retain their existing
interface, e.g., libm functions obtained by lowering math operations (see
D126964 for an example). Since D77314, we have a finer-grain control over
interface generation via an attribute that avoids the problem entirely. Remove
the 'emit_c_wrappers' option. Introduce the '-llvm-request-c-wrappers' pass
that can be run in any pipeline that needs blanket emission of functions to
annotate all builtin functions with the attribute before performing the usual
lowering that accounts for the attribute.
Reviewed By: chelini
Differential Revision: https://reviews.llvm.org/D127952
Guillaume Chatelet [Fri, 17 Jun 2022 09:07:24 +0000 (09:07 +0000)]
[libc][bazel] Remove memcpy dependency in memmove
Cullen Rhodes [Fri, 17 Jun 2022 08:31:02 +0000 (08:31 +0000)]
[AArch64] NFC: Fix BFMLAL[BT] inst def names
Alexander Potapenko [Wed, 15 Jun 2022 09:30:05 +0000 (11:30 +0200)]
[msan] Allow KMSAN to use -fsanitize-memory-param-retval
Let -fsanitize-memory-param-retval be used together with
-fsanitize=kernel-memory, so that it can be applied when building the
Linux kernel.
Also add clang/test/CodeGen/kmsan-param-retval.c to ensure that
-fsanitize-memory-param-retval eliminates shadow accesses for parameters
marked as undef.
Reviewed By: eugenis, vitalybuka
Differential Revision: https://reviews.llvm.org/D127860
Sven van Haastregt [Fri, 17 Jun 2022 08:53:45 +0000 (09:53 +0100)]
[OpenCL] Fix atomic_fetch_add/sub half overloads
Some of the atomic_fetch_add and atomic_fetch_sub overloads intended
for atomic_half types accidentally had an atomic_float parameter.
Nikita Popov [Fri, 17 Jun 2022 08:14:38 +0000 (10:14 +0200)]
[InstCombine] Add tests for freeze of recurrence with invoke start (NFC)
Muhammad Omair Javaid [Fri, 17 Jun 2022 07:46:27 +0000 (11:46 +0400)]
[LLDB] XFAIL TestLoadUnload fails on Arm/Ubuntu Jammy
This patch marks following tests as XFAIL for Arm/Ubuntu Jammy 22.04:
test_lldb_process_load_and_unload_commands
test_load_unload
Benjamin Kramer [Fri, 17 Jun 2022 07:40:50 +0000 (09:40 +0200)]
Revert "Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86 following the psABI""""
This reverts commit
04a3d5f3a1193fb87576425a385aa0a6115b1e7c.
I see two more issues:
- uitofp/sitofp from i32/i64 to half now generates
__floatsihf/__floatdihf, which exists in neither compiler-rt nor
libgcc
- This crashes when legalizing the bitcast:
```
; RUN: llc < %s -mcpu=skx
define void @main.45(ptr nocapture readnone %retval, ptr noalias nocapture readnone %run_options, ptr noalias nocapture readnone %params, ptr noalias nocapture readonly %buffer_table, ptr noalias nocapture readnone %status, ptr noalias nocapture readnone %prof_counters) local_unnamed_addr {
entry:
%fusion = load ptr, ptr %buffer_table, align 8
%0 = getelementptr inbounds ptr, ptr %buffer_table, i64 1
%Arg_1.2 = load ptr, ptr %0, align 8
%1 = getelementptr inbounds ptr, ptr %buffer_table, i64 2
%Arg_0.1 = load ptr, ptr %1, align 8
%2 = load half, ptr %Arg_0.1, align 8
%3 = bitcast half %2 to i16
%4 = and i16 %3, 32767
%5 = icmp eq i16 %4, 0
%6 = and i16 %3, -32768
%broadcast.splatinsert = insertelement <4 x half> poison, half %2, i64 0
%broadcast.splat = shufflevector <4 x half> %broadcast.splatinsert, <4 x half> poison, <4 x i32> zeroinitializer
%broadcast.splatinsert9 = insertelement <4 x i16> poison, i16 %4, i64 0
%broadcast.splat10 = shufflevector <4 x i16> %broadcast.splatinsert9, <4 x i16> poison, <4 x i32> zeroinitializer
%broadcast.splatinsert11 = insertelement <4 x i16> poison, i16 %6, i64 0
%broadcast.splat12 = shufflevector <4 x i16> %broadcast.splatinsert11, <4 x i16> poison, <4 x i32> zeroinitializer
%broadcast.splatinsert13 = insertelement <4 x i16> poison, i16 %3, i64 0
%broadcast.splat14 = shufflevector <4 x i16> %broadcast.splatinsert13, <4 x i16> poison, <4 x i32> zeroinitializer
%wide.load = load <4 x half>, ptr %Arg_1.2, align 8
%7 = fcmp uno <4 x half> %broadcast.splat, %wide.load
%8 = fcmp oeq <4 x half> %broadcast.splat, %wide.load
%9 = bitcast <4 x half> %wide.load to <4 x i16>
%10 = and <4 x i16> %9, <i16 32767, i16 32767, i16 32767, i16 32767>
%11 = icmp eq <4 x i16> %10, zeroinitializer
%12 = and <4 x i16> %9, <i16 -32768, i16 -32768, i16 -32768, i16 -32768>
%13 = or <4 x i16> %12, <i16 1, i16 1, i16 1, i16 1>
%14 = select <4 x i1> %11, <4 x i16> %9, <4 x i16> %13
%15 = icmp ugt <4 x i16> %broadcast.splat10, %10
%16 = icmp ne <4 x i16> %broadcast.splat12, %12
%17 = or <4 x i1> %15, %16
%18 = select <4 x i1> %17, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>
%19 = add <4 x i16> %18, %broadcast.splat14
%20 = select i1 %5, <4 x i16> %14, <4 x i16> %19
%21 = select <4 x i1> %8, <4 x i16> %9, <4 x i16> %20
%22 = bitcast <4 x i16> %21 to <4 x half>
%23 = select <4 x i1> %7, <4 x half> <half 0xH7E00, half 0xH7E00, half 0xH7E00, half 0xH7E00>, <4 x half> %22
store <4 x half> %23, ptr %fusion, align 16
ret void
}
```
llc: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:977: void (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode *): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::Register) && "Unexpected illegal type!"' failed.
Javier Alvarez [Fri, 17 Jun 2022 07:31:14 +0000 (10:31 +0300)]
[clang] Fix trivially copyable for copy constructor and copy assignment operator
From [class.copy.ctor]:
```
A non-template constructor for class X is a copy constructor if its first
parameter is of type X&, const X&, volatile X& or const volatile X&, and
either there are no other parameters or else all other parameters have
default arguments (9.3.4.7).
A copy/move constructor for class X is trivial if it is not user-provided and if:
- class X has no virtual functions (11.7.3) and no virtual base classes (11.7.2), and
- the constructor selected to copy/move each direct base class subobject is trivial, and
- or each non-static data member of X that is of class type (or array thereof),
the constructor selected to copy/move that member is trivial;
otherwise the copy/move constructor is non-trivial.
```
So `T(T&) = default`; should be trivial assuming that the previous
provisions are met.
This works in GCC, but not in Clang at the moment:
https://godbolt.org/z/fTGe71b6P
Reviewed By: royjacobson
Differential Revision: https://reviews.llvm.org/D127593
ping.deng [Fri, 17 Jun 2022 06:53:19 +0000 (06:53 +0000)]
[RISCV][NFC] Add load/store instructions in rv64*-invalid.s
Reviewed By: benshi001, sunshaoce
Differential Revision: https://reviews.llvm.org/D127721
Fangrui Song [Fri, 17 Jun 2022 06:33:48 +0000 (23:33 -0700)]
[Driver] Pass -X to ld for riscv*-{elf,freebsd,linux}
GNU ld has a hack that defaults to -X (--discard-locals) in the emulation file
`riscvelf.em`. The recommended way, as gcc/config/arm does, is to let the
compiler driver pass -X to ld.
(The motivation is likely to discard a plethora of `.L` symbols due to linker
relaxation.)
lld default to --discard-none. To make clang+lld match GNU ld's behavior, pass
-X to ld.
Note: GNU ld has a special rule to treat ld -r -s as ld -r -S -x. With -X, driver `-r -Wl,-s`
will behave as ld `-r -S -X`. This removes fewer symbols than `-r -S -x` but is safe.
Differential Revision: https://reviews.llvm.org/D127826
Xiang Li [Thu, 16 Jun 2022 21:35:47 +0000 (14:35 -0700)]
[TableGen][DirectX] generate DXIL operation table with TableGen.
Add more feature to tableGen backend gen-dxil-operation.
It will generate getOpCodeProperty, getOpCodeClassName and getOpCodeName when build DirectX target.
Each of these functions has a table which generate based on DXIL operations.
These generated functions will replace the manually written functions which used for query DXIL operation information.
Reviewed By: bogner
Differential Revision: https://reviews.llvm.org/D125520
Fangrui Song [Fri, 17 Jun 2022 05:41:39 +0000 (22:41 -0700)]
[AArch64][test] Add --mattr=-{sve,sve2,sme} to SVE/SVE2/SME MC tests
llvm-objdump will be changed to default to disassemble all instructions.
Add --mattr=-{sve,sve2,sme} to keep the desired testing.
Mingming Liu [Fri, 17 Jun 2022 04:59:54 +0000 (21:59 -0700)]
[MachineBlockPlacementStats] Added check for "-filter-print-funcs"
option to the machine-block-placement-stats.
Differential Revision: https://reviews.llvm.org/D128019
Mingming Liu [Fri, 17 Jun 2022 04:56:08 +0000 (21:56 -0700)]
Revert "[MachineBlockPlacementStats] Add check for `-filter-print-funcs` option to machine-block-placement stats."
This reverts commit
46d45df4516e9a5bc43460429cd02cd04a85db1a. Going to
add differential revision link to commit message and re-commit.
Mingming Liu [Fri, 17 Jun 2022 00:26:02 +0000 (17:26 -0700)]
[MachineBlockPlacementStats] Add check for `-filter-print-funcs` option to machine-block-placement stats.
Phoebe Wang [Fri, 17 Jun 2022 03:25:22 +0000 (11:25 +0800)]
Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86 following the psABI"""
Fix the crash on lowering X86ISD::FCMP.
Jonas Devlieghere [Fri, 17 Jun 2022 03:19:12 +0000 (20:19 -0700)]
[lldb] Remove LogHandler::Create functions (NFC)
Remove the LogHandler::Create functions. Except for the StreamHandler
they were just forwarding their arguments to std::make_shared.
Jez Ng [Fri, 17 Jun 2022 03:49:11 +0000 (23:49 -0400)]
[lld-macho][nfc] Tests for -force_load + regular archive load combinations
I realized we'd forgotten to cover this case (though our existing
behavior is indeed correct / matches ld64's).
Reviewed By: #lld-macho, thakis
Differential Revision: https://reviews.llvm.org/D128025
Jacques Pienaar [Fri, 17 Jun 2022 03:15:13 +0000 (20:15 -0700)]
[mlir] Disable warning in test of deprecated feature (NFC)
Disable warning for deprecation in test of deprecated feature. Also
remove additional test of deprecated feature from TestOps.td.
Jacques Pienaar [Fri, 17 Jun 2022 03:01:54 +0000 (20:01 -0700)]
[mlir] Split MLProgram global load and store to Graph variants
* Split ops into X_graph variants as discussed;
* Remove tokens from non-Graph region variants and rely on side-effect
modelling there while removing side-effect modelling from Graph
variants and relying on explicit ordering there;
* Make tokens required to be produced by Graph variants - but kept
explicit token type specification given previous discussion on this
potentially being configurable in future;
This results in duplicating some code. I considered adding helper
functions but decided against adding an abstraction there early given
size of duplication and creating accidental coupling.
Differential Revision: https://reviews.llvm.org/D127813
Lian Wang [Wed, 15 Jun 2022 03:46:57 +0000 (03:46 +0000)]
[LegalizeTypes][NFC] Merge promote SPLAT_VECTOR and promote SCALAR_TO_VECTOR to one function
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D127825
Jacques Pienaar [Fri, 17 Jun 2022 02:42:56 +0000 (19:42 -0700)]
[mlir][doc] Avoid duplication with constraints and defs
Where a constraint also has a def, emit the def only to avoid duplicate
output (and def has more complete info). Also move attributes and types
to the end rather than some on top and some at end.
Differential Revision: https://reviews.llvm.org/D127823
Lian Wang [Thu, 16 Jun 2022 03:31:48 +0000 (03:31 +0000)]
[LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D127939
Lian Wang [Fri, 17 Jun 2022 02:22:29 +0000 (02:22 +0000)]
[RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll
Reviewed By: victor-eds, frasercrmck
Differential Revision: https://reviews.llvm.org/D127946
Lang Hames [Fri, 17 Jun 2022 01:31:29 +0000 (18:31 -0700)]
[ORC-RT] Make the ORC runtime C API public.
This is a first step towards allowing programs to pre-link against the ORC
runtime, which would allow us to move some code that is currently in the LLVM
OrcTarget library into the ORC runtime instead.
The C API header has limited utility as-is, but serves as a minimal first step
and provides clients with tools for interacting with wrapper functions.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D127324
Matt Arsenault [Fri, 17 Jun 2022 01:35:02 +0000 (21:35 -0400)]
llvm-reduce: Try to fix dynamic libraries build
Maryam Moghadas [Thu, 16 Jun 2022 23:06:05 +0000 (18:06 -0500)]
PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions
This patch is the last prerequisite to switch the default behaviour to -fno-lax-vector-conversions in the future.
The first path ;D124093; fixed the altivec implicit castings.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D126540
Lei Huang [Fri, 17 Jun 2022 01:15:02 +0000 (20:15 -0500)]
[PowerPC][NFC] Undefine __XL_COMPAT_ALTIVEC__ in builtin lit test
Add defines and undefines of the __XL_COMPAT_ALTIVEC__ to ensure
consistent results regardless of the default for this macro.
Jennifer Yu [Thu, 16 Jun 2022 23:32:30 +0000 (16:32 -0700)]
[OpenMP] Initial parsing and sema for 'parallel masked' construct
Differential Revision: https://reviews.llvm.org/D127454
LiaoChunyu [Thu, 16 Jun 2022 12:58:02 +0000 (20:58 +0800)]
[AMDGPU][NFC] Remove isConstantAddr
fix isConstantAddr defined but not used
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D127959
LLVM GN Syncbot [Fri, 17 Jun 2022 00:40:13 +0000 (00:40 +0000)]
[gn build] Port
eea11e7369ca
Matt Arsenault [Thu, 9 Jun 2022 02:09:47 +0000 (22:09 -0400)]
llvm-reduce: Add reduction pass to simplify instructions
Matt Arsenault [Thu, 9 Jun 2022 13:43:09 +0000 (09:43 -0400)]
llvm-reduce: Support replacing FP values with 1.0
Pengxuan Zheng [Wed, 15 Jun 2022 19:50:06 +0000 (12:50 -0700)]
[Object][COFF] Improve section name parsing
Inspired by discussions on D127369, we probably can further improve LLVM's COFF
section name parsing. Hopefully, this makes the logic simpler and handles some
edge cases more elegantly.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D127902
Fangrui Song [Thu, 16 Jun 2022 23:38:01 +0000 (16:38 -0700)]
[sanitizer] Delete empty sanitizer_openbsd.cpp after D89759
Paul Walker [Mon, 13 Jun 2022 16:06:22 +0000 (17:06 +0100)]
[SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks.
Most tests have been updated to make use of vscale_range to reduce
the number of RUN lines. For the remaining RUN lines the check
prefixes have been updated to ensure the original expectation of
the manual CHECK lines is maintained after update_llc_test_checks
is run.
Jonas Devlieghere [Thu, 16 Jun 2022 23:21:26 +0000 (16:21 -0700)]
[lldb] Cleanup Python API reference files after building the docs
The sphinx-automodapi extension requires that the generated RST files
live next to the index file. This means that we generate them in the
source directory rather than the build directory. This patch ensures
these files are removed again when sphinx finishes its build.
The proper solution to this problem would be to move everything in the
doc folder from the source directory to the build directory before
generating the docs.
I believe that old RST files being kept around is the reason that the
Python API references on the website isn't getting updated. This patch
is meant as a speculative fix and a way to confirm that.
Aart Bik [Thu, 16 Jun 2022 19:02:34 +0000 (12:02 -0700)]
[mlir][sparse] improved testing and codegen for semi-ring operations
The semi-ring blocks were simply "inlined" by the sparse compiler but
without any filtering or patching. This revision improves the analysis
(rejecting blocks that use non-invariant computations from outside
their blocks, except for linalg.index) and also improves the codegen
by properly patching up index computations (previous version crashed).
With a regression test. Also updated the documentation now that the
example code is properly working.
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D128000
LLVM GN Syncbot [Thu, 16 Jun 2022 22:31:40 +0000 (22:31 +0000)]
[gn build] Port
ff3989e6ae74
LLVM GN Syncbot [Thu, 16 Jun 2022 22:31:39 +0000 (22:31 +0000)]
[gn build] Port
61fac2c370b9
David Blaikie [Wed, 15 Jun 2022 23:49:32 +0000 (23:49 +0000)]
Incomplete attempt to pull DWARFTypePrinter into its own file for reuse
from lldb
Philip Reames [Thu, 16 Jun 2022 22:25:13 +0000 (15:25 -0700)]
[RISCV] Rename VTy param of RISCVTTIImpl::getArithmeticReductionCost [NFC]
Having it be consistent with getMinMaxReductionCost for ease of copy paste outweights the minor clarity of calling it VTy instead of Ty.
Konstantin Varlamov [Thu, 16 Jun 2022 22:20:53 +0000 (15:20 -0700)]
[libc++][ranges] Implement `ranges::sort`.
Differential Revision: https://reviews.llvm.org/D127557
Lei Huang [Thu, 16 Jun 2022 22:20:10 +0000 (17:20 -0500)]
fix x86 sanitizer failure due to use of or
Jonas Devlieghere [Thu, 16 Jun 2022 22:17:03 +0000 (15:17 -0700)]
[lldb] Remove references to epydoc from the documentation
We no longer rely on epydoc but instead use a sphinx plugin to generate
the Python API reference.
Jonas Devlieghere [Thu, 16 Jun 2022 05:41:47 +0000 (22:41 -0700)]
[lldb] Add RotatingLogHandler
Add a log handler that maintains a circular buffer with a fixed size.
Differential revision: https://reviews.llvm.org/D127937
Craig Topper [Thu, 16 Jun 2022 22:11:16 +0000 (15:11 -0700)]
[RISCV] Implement RISCVTargetLowering::getTargetConstantFromLoad.
This allows computeKnownBits to see the constant being loaded.
This recovers the rv64zbp test case changes from D127520.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127679
Craig Topper [Thu, 16 Jun 2022 22:05:59 +0000 (15:05 -0700)]
[RISCV] Add RISCVISD opcode for PseudoLLA.
Rather than emitting a MachineSDNode from lowering. Let isel match it.
This is consistent with the RISCVISD::HI and ADD_LO nodes that were
also added. Having them both the same will make D127679 consistent.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127714
Mitch Phillips [Thu, 16 Jun 2022 22:10:22 +0000 (15:10 -0700)]
[NFCI] Whitespace in SemaDeclAttr.cpp
Maryam Moghadas [Thu, 16 Jun 2022 01:20:24 +0000 (20:20 -0500)]
[PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions
XL considers different vector types to be incompatible with each other.
For example assignment between variables of types vector float and vector
long long or even vector signed int and vector unsigned int are diagnosed.
clang, however does not diagnose such cases and does a simple bitcast between
the two types. This could easily result in program errors. This patch is to
fix the implicit casts in altivec.h so that there is no incompatible vector
type errors whit -fno-lax-vector-conversions, this is the prerequisite patch
to switch the default to -fno-lax-vector-conversions later.
Reviewed By: nemanjai, amyk
Differential Revision: https://reviews.llvm.org/D124093
Richard [Wed, 18 May 2022 19:29:27 +0000 (13:29 -0600)]
[clang-tidy] Organize check doc files into subdirectories (NFC)
- Rename doc files to subdirs by module
- Update release notes and check list to use subdirs
- Update add_new_check.py to handle doc subdirs
Differential Revision: https://reviews.llvm.org/D126495
Craig Topper [Thu, 16 Jun 2022 21:56:05 +0000 (14:56 -0700)]
[RISCV] Don't emit LUI/ADDI MachineSDNodes from getAddr
Instead add RISCVISD opcodes that will be selected to LUI/ADDI
during isel.
I'm looking into maybe moving doPeepholeLoadStoreADDI into isel.
Having the ADDI as a RISCVISD node will make it visible to isel.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127713
Craig Topper [Thu, 16 Jun 2022 21:45:44 +0000 (14:45 -0700)]
[SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources.
MinRCSize is 4 and prevents constrainRegClass from changing the
register class if the new class has size less than 4.
IMPLICIT_DEF gets a unique vreg for each use and will be removed
by the ProcessImplicitDef pass before register allocation. I don't
think there is any reason to prevent constraining the virtual register
to whatever register class the use needs.
The attached test case was previously creating a copy of IMPLICIT_DEF
because vrm8nov0 has 3 registers in it.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D128005
Mitch Phillips [Thu, 16 Jun 2022 21:51:05 +0000 (14:51 -0700)]
Add DWARF string debug to clang release notes.
D12353 added inline strings to the DWARF info produced by clang. This
turns out to break some debugging software that assumes that a
DW_TAG_variable *must* come with a DW_AT_name. Add a release note to
broadcast this change.
Reviewed By: paulkirth
Differential Revision: https://reviews.llvm.org/D126224
Aart Bik [Thu, 16 Jun 2022 20:25:23 +0000 (13:25 -0700)]
[mlir][sparse] fix asan issue
The LinalgElementwiseOpFusion pass has become smarter, and converts
the simple conversion linalg operation into a sparse dialect convert
operation. However, since our current bufferization does not take the
new semantics into consideration, we leak memory of the allocation.
For now, this has been fixed by making the operation less trivial.
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D128002
Mitch Phillips [Thu, 16 Jun 2022 21:27:38 +0000 (14:27 -0700)]
Make setSanitizerMetadata byval.
This fixes a UaF bug in llvm::GlobalObject::copyAttributesFrom, where a
sanitizer metadata object is captured by reference, and passed by
reference to llvm::GlobalValue::setSanitizerMetadata. The reference
comes from the same map that the new value is going to be inserted to,
and the map insertion triggers iterator invalidation - leading to a
use-after-free on the dangling reference.
This patch fixes that bug by making setSanitizerMetadata's argument
byval. This should also systematically prevent the problem from
happening in future, as it's a very easy pattern to have. This shouldn't
be any performance problem, the SanitizerMetadata struct is a bitfield
POD.
Tue Ly [Wed, 15 Jun 2022 23:57:46 +0000 (19:57 -0400)]
[libc] Add a status page for math functions.
Add a status page for math functions.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D127920
Philip Reames [Thu, 16 Jun 2022 21:34:53 +0000 (14:34 -0700)]
[RISCV] Start merging demanded reasoning - starting with load/stores [nfc]
This change merges the logic for reasoning about demanded portions of the VTYPE register between the main dataflow algorithm and the backwards mutation post pass. In the process, we get to delete a bunch of now redundant code.
This should be entirely NFC. I included a slight hack (see TODO) to avoid changing behavior in the post pass while being able to use the generalized logic in the prepass. I will fix the TODO in a separate change once this lands.
Differential Revision: https://reviews.llvm.org/D127983
Philip Reames [Thu, 16 Jun 2022 21:10:21 +0000 (14:10 -0700)]
[RISCV] Add cost model for scalable scatter and gather
The costing we use for fixed length vector gather and scatter is to simply count up the memory ops, and multiply by a fixed memory op cost. For scalable vectors, we don't actually know how many lanes are active. Instead, we have to end up making a worst case assumption on how many lanes could be active. In the generic +V case, this results in very high costs, but we can do better when we know an upper bound on the VLEN.
There's some obvious ways to improve this - e.g. using information about VL and mask bits from the instruction to reduce the upper bound - but this seems like a reasonable starting point.
The resulting costs do bias us pretty strongly away from generating scatter/gather for generic +V. Without this, we'd be returning an invalid cost and thus definitely not vectorizing, so no major change in practical behavior expected.
Differential Revision: https://reviews.llvm.org/D127541
bixia1 [Wed, 15 Jun 2022 23:00:51 +0000 (16:00 -0700)]
[mlir][complex] Add Python bindings for complex ops.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D127916
Mitch Phillips [Thu, 16 Jun 2022 21:07:54 +0000 (14:07 -0700)]
Revert "[TableGen][DirectX] generate DXIL operation table with TableGen."
This reverts commit
46fcdf23640ebb76271f91720583b0df6bed4481.
Reason: Broke the buildbots:
https://lab.llvm.org/buildbot/#/builders/77/builds/18671
Sterling Augustine [Thu, 16 Jun 2022 21:00:44 +0000 (14:00 -0700)]
Move debug-only code inside LLVM_DEUG to prevent unused variable warnings.
Mitch Phillips [Thu, 16 Jun 2022 17:23:26 +0000 (10:23 -0700)]
Reland "[ASan] Use debuginfo for symbolization."
This reverts commit
99796d06dbe11c8f81376ad1d42e7f17d2eff6ae.
Hint: Looking here because your manual invocation of something in
'check-asan' broke? You need a new symbolizer (after D123538).
An upcoming patch will remove the internal metadata for global
variables. With D123534 and D123538, clang now emits DWARF debug info
for constant strings (the only global variable type it was missing), and
llvm-symbolizer is now able to symbolize all global variable addresses
(where previously it wouldn't give you the file:line information).
Move ASan's runtime over from the internal metadata to DWARF.
Differential Revision: https://reviews.llvm.org/D127552
Xiang Li [Thu, 16 Jun 2022 14:56:26 +0000 (07:56 -0700)]
[TableGen][DirectX] generate DXIL operation table with TableGen.
Add more feature to tableGen backend gen-dxil-operation.
It will generate getOpCodeProperty, getOpCodeClassName and getOpCodeName when build DirectX target.
Each of these functions has a table which generate based on DXIL operations.
These generated functions will replace the manually written functions which used for query DXIL operation information.
Reviewed By: bogner
Differential Revision: https://reviews.llvm.org/D125520
Amanieu d'Antras [Thu, 16 Jun 2022 20:31:33 +0000 (21:31 +0100)]
[MergeFunctions] Preserve symbols used llvm.used/llvm.compiler.used
llvm.used and llvm.compiler.used are often used with inline assembly
that refers to a specific symbol so that the symbol is kept through to
the linker even though there are no references to it from LLVM IR.
This fixes the MergeFunctions pass to preserve references to these
symbols in llvm.used/llvm.compiler.used so they are not deleted from the
IR. This doesn't prevent these functions from being merged, but
guarantees that an alias or thunk with the expected symbol name is kept
in the IR.
Differential Revision: https://reviews.llvm.org/D127751
LLVM GN Syncbot [Thu, 16 Jun 2022 20:34:45 +0000 (20:34 +0000)]
[gn build] Port
6ff49af33d09