Brian Paul [Thu, 20 Jul 2017 15:57:32 +0000 (09:57 -0600)]
mesa: remove pointless assignments in init_teximage_fields_ms()
The NumSamples and FixedSampleLocation fields are set again later at
the end of the function so these earlier assignments aren't needed.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Neha Bhende [Fri, 21 Jul 2017 00:03:19 +0000 (17:03 -0700)]
svga: Limit number of immediates in shader
imm {128.0, -128.0, 2.0, 3.0} is used for lit instruction which
is not used very frequently. So allocate it only if lit instruction is used.
Tested with mtt piglit and mtt glretrace
v2: As per Charmaine's comment
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Charmaine Lee [Tue, 18 Jul 2017 23:13:48 +0000 (16:13 -0700)]
svga: fix constant indices for texcoord scale factors and texture buffer size
This patch fixes the ordering of the constant indices for texcoord scale
factor and texture buffer size to match the order they were added to the
constant buffer in svga_get_extra_constants_common().
Tested with MTT piglit, glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Neha Bhende [Thu, 20 Jul 2017 20:59:36 +0000 (13:59 -0700)]
svga: fix unnormalized->normalized texture coordinate conversion
Sometimes, converting unnormalized coordinates to normalized
coordinates requires an epsilon value to produce the right texels with
nearest filtering. Adding 0.0001 to the coordinates when the min/mag
filter is nearest fixes the issue.
Fixes piglit test fbo-blit-scaled-linear
Tested with mtt-piglit, mtt-glretrace
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 20 Jul 2017 20:53:07 +0000 (14:53 -0600)]
svga: only support 4x, 8x, 16x msaa
Skip 2x MSAA, for example, since it's seldom used and just bloats
the list of pixel formats.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 20 Jul 2017 13:56:03 +0000 (07:56 -0600)]
mesa: include texture size in error messages
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Kenneth Graunke [Sat, 22 Jul 2017 07:51:03 +0000 (00:51 -0700)]
i965: Support the mesa_no_error driconf option.
This allows us to override contexts to use no_error functionality
even if the applications themselves do not.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Sat, 22 Jul 2017 00:18:07 +0000 (17:18 -0700)]
anv/blorp: Assert isl_surf_init success in do_buffer_copy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 22 Jul 2017 00:14:52 +0000 (17:14 -0700)]
anv/blorp: Explicitly set row_pitch in do_buffer_copy
We have a very specific row pitch that we want and we don't want ISL to
be changing it on us so just be explicit about it.
Fixes:
a40f0430347c07bf2d5794642fe02f5dd248a473
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Sat, 22 Jul 2017 07:42:28 +0000 (00:42 -0700)]
i965: Delete gen8_draw_upload.c
For some reason we left an empty file, rather than deleting it.
Karol Herbst [Fri, 23 Jun 2017 18:30:29 +0000 (20:30 +0200)]
nv50/ir: disable mul+add to mad for precise instructions
fixes
missrendering in TombRaider
KHR-GL44.gpu_shader5.precise_qualifier
KHR-GL45.gpu_shader5.precise_qualifier
v4: disable opt only for MAD, it's fine for SAD
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Fri, 23 Jun 2017 18:30:28 +0000 (20:30 +0200)]
nv50/ir/tgsi: handle precise for most ALU instructions
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Fri, 23 Jun 2017 18:30:27 +0000 (20:30 +0200)]
nv50/ir: add precise field to Instruction
v4: initialize field with NULL
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Fri, 23 Jun 2017 18:30:26 +0000 (20:30 +0200)]
st/glsl_to_tgsi: don't optimize mul+add to mad if expression is precise
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Karol Herbst [Fri, 23 Jun 2017 18:30:25 +0000 (20:30 +0200)]
gallium/docs: add precise instruction modifier
v4: add comment about intermediate rounding step to MAD
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Karol Herbst [Fri, 23 Jun 2017 18:30:24 +0000 (20:30 +0200)]
tgsi/text: parse _PRECISE modifier
v2: use str_match_no_case to fix _SAT_PRECISE detection
v4: usd is_digit_alpha_underscore to match end of mods
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Karol Herbst [Fri, 23 Jun 2017 18:30:23 +0000 (20:30 +0200)]
tgsi: populate precise
Only implemented for glsl->tgsi. Other converters just set precise to 0.
v2: remove precise paramter from ureg_tex_insn and ureg_memory_insn
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Karol Herbst [Fri, 23 Jun 2017 18:30:22 +0000 (20:30 +0200)]
st/glsl_to_tgsi: handle precise modifier
all subexpression inside an ir_assignment needs to be tagged as precise.
v2: make precise handling more global inside the visitor
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Karol Herbst [Fri, 23 Jun 2017 18:30:21 +0000 (20:30 +0200)]
tgsi/dump: print _PRECISE modifier on Instructions
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Karol Herbst [Fri, 23 Jun 2017 18:30:20 +0000 (20:30 +0200)]
tgsi: add precise flag to tgsi_instruction
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kenneth Graunke [Sat, 22 Jul 2017 01:08:37 +0000 (18:08 -0700)]
i965: Set lower_vote_trivial in vector_nir_options_gen6 too.
There's a second struct for Gen6+.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dave Airlie [Fri, 21 Jul 2017 22:56:02 +0000 (23:56 +0100)]
radv: reset non-syncobj semaphore context after wait.
When I ported from libdrm, I forgot to add the line to reset
the sem, we just need to reset the context.
This fixes a regression in DOOM.
Fixes:
9ac1432a571 ("radv: port to new libdrm API.")
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Charmaine Lee [Thu, 20 Jul 2017 18:04:14 +0000 (11:04 -0700)]
st/mesa: add destroy_drawable interface
With this patch, the st manager will maintain a hash table for
the active framebuffer interface objects. A destroy_drawable interface
is added to allow the state tracker to notify the st manager to remove
the associated framebuffer interface object from the hash table,
so the associated framebuffer and its resources can be deleted
at framebuffers purge time.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101829
Fixes:
147d7fb772a ("st/mesa: add a winsys buffers list in st_context")
Tested-by: Brad King <brad.king@kitware.com>
Tested-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Dylan Baker [Thu, 20 Jul 2017 00:53:42 +0000 (17:53 -0700)]
radv: rebase radv_entrypoints_gen.py on anv_entrypoints_gen.py
The two generators forked from each other, and they remain basically the
same. This rebases the radv version on the anv version, but with the
radv changes ported over. The result is that we get rid of the "cat |"
madness and gain mako, correct "generated by" attributions, and write
files out directly.
The only differences between the output is whitespace and comments.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Topi Pohjolainen [Tue, 20 Jun 2017 18:20:15 +0000 (21:20 +0300)]
i965/miptree: Clean-up unused
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 27 Jun 2017 15:10:31 +0000 (18:10 +0300)]
i965/miptree: Switch remaining surfaces to isl
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 29 Jun 2017 05:18:24 +0000 (08:18 +0300)]
i965/miptree: Drop miptree_array_layout in get_isl_dim_layout()
This was only needed for checking gen6 stencil which is already
using isl. One could delete GEN6_HIZ_STENCIL layout altogether
but that will be gone with the rest after a while anyway.
The dim_layout converter is needed even after transition to isl
when setting up surface states - see brw_emit_surface_state().
Hence dropping the unneeded argument separately.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 28 Jun 2017 09:11:16 +0000 (12:11 +0300)]
i965/miptree: Relax size alignment for linear surfaces
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 30 Jun 2017 17:17:03 +0000 (20:17 +0300)]
i965/miptree: Store compression flag also for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 21 Jul 2017 08:17:57 +0000 (11:17 +0300)]
i965/miptree: Check tex image allocation failures
allowing graceful failure instead of crash on assert later on.
This can be hit, for example, on SNB when trying to allocate
8kx8k CUBE_MAP against isl: x-tiled buffer size becomes
2421161984 exceeding the maximum of 1 << 31 ==
2147483648.
Another way to hit this on SNB is with multisampling of over
64-bit formats.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 21 Jul 2017 08:49:08 +0000 (11:49 +0300)]
main/teximage: Even on failure use valid format for init()
Otherwise init_teximage_fields_ms() (called by
_mesa_init_teximage_fields()) will always assert as it can't
find valid base format.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 18 Jul 2017 14:10:59 +0000 (17:10 +0300)]
intel/isl/gen7: Don't allow multisampled surfaces with valign2
There is the same constraintg later on as assert in
isl_gen7_choose_image_alignment_el() so catch it earlier in order
to return error instead of crash.
Needed to avoid crashes with piglits on IVB and HSW:
arb_internalformat_query2.image_format_compatibility_type pname checks
arb_internalformat_query2.all internalformat_<x>_type pname checks
arb_internalformat_query2.max dimensions related pname checks
arb_copy_image.arb_copy_image-formats --samples=2/4/6/8
arb_texture_float.multisample-fast-clear gl_arb_texture_float
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 18 Jul 2017 14:06:07 +0000 (17:06 +0300)]
intel/isl/gen7: Allow msaa with signed integer formats
These formats are already allowed by the i965 GL driver, and the
feature seems to work just fine.
There are tests for multisampled rendering in piglit:
tests/spec/ext_framebuffer_multisample which can be patched to
try 16I/32I in addition to GL_RGBA8I.
IvyBridge passed all tests with all sample numbers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 18 Jul 2017 13:25:43 +0000 (16:25 +0300)]
intel/isl/gen7: Allow msaa with 128-bit formats
These formats are already allowed by the i965 GL driver, and the
feature seems to work just fine.
There are tests for multisampled rendering in piglit:
tests/spec/ext_framebuffer_multisample which can be patched to
try GL_RGBA16F/32F/16I/16UI/32I/32UI in addition to GL_RGBA/8I.
IvyBridge passed all tests with all sample numbers and even
with 128-bit formats.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 5 Jul 2017 07:26:03 +0000 (10:26 +0300)]
intel/isl: Allow 1D surfaces with compressed formats
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 28 Jun 2017 09:07:32 +0000 (12:07 +0300)]
intel/isl: Align non-tiled horizontally by cache line
in order to support blit engine.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 20 Jun 2017 17:33:08 +0000 (20:33 +0300)]
i965/miptree/gen4: Prepare x-tiled fallback for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 30 Jun 2017 06:34:48 +0000 (09:34 +0300)]
i965/miptree: Prepare non-tiled fallback for isl based
See brw_miptree_choose_tiling().
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 28 Jun 2017 07:04:10 +0000 (10:04 +0300)]
i965/miptree: Prepare has_color_unresolved() for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Roland Scheidegger [Fri, 21 Jul 2017 18:27:43 +0000 (20:27 +0200)]
gallivm: handle call attributes for llvm < 4.0 in lp_add_function_attr
We had some caller using LLVMAddInstrAttributes, which couldn't be
converted to lp_add_function_attr, because attributes were only handled
for functions in this case, so fix this.
For llvm >= 4.0, this already works correctly.
(radeonsi seems to avoid setting call site attributes prior to llvm 4.0,
the patch then citing it doesn't work when calling intrinsics. But at
least for calling external functions we always used that, albeit only
for actual call attributes, not call parameter attributes, though some
quick test shows llvm seems to handle that as well. The attribute index
is sort of iffy though, since attribute 0 of the call is the actual function,
attribute 1 corresponds to the first parameter of the called function.)
(Verified with GALLIVM_DEBUG=dumpbc plus llvm-dis that the correct
attributes are shown for calls, both for llvm 4.0 and 3.3.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alex Smith [Fri, 21 Jul 2017 16:00:00 +0000 (17:00 +0100)]
radv: Generate storage image descriptors unconditionally
We can also use storage images internally for resolves, which don't
require TRANSFER_DST usage on the image, so currently we may not create
the needed descriptors.
Just create these descriptors unconditionally.
Fixes:
0e1886efb9e ("radv: Fix descriptors for cube images with VK_IMAGE_USAGE_STORAGE_BIT")
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Tim Rowley [Fri, 21 Jul 2017 16:38:39 +0000 (11:38 -0500)]
swr/rast: quit using linux-specific gettid()
Linux-specific gettid() syscall shouldn't be used in portable code.
Fix does assume a 1:1 thread:LWP architecture, but works for our
current target platforms and can be revisited later if needed.
Fixes unresolved symbol in linux scons builds.
v2: add comment in code about the 1:1 assumption.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Dave Airlie [Mon, 27 Feb 2017 19:14:00 +0000 (19:14 +0000)]
radv: initial support for shared semaphores (v2)
This adds support for sharing semaphores using kernel syncobjects.
Syncobj backed semaphores are used for any semaphore which is
created with external flags, and when a semaphore is imported,
otherwise we use the current non-kernel semaphores.
Temporary imports from syncobj fd are also available, these
just override the current user until the next wait, when the
temp syncobj is dropped.
v2: allocate more chunks upfront, fix off by one after
previous refactor of syncobj setup, remove unnecessary null
check.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 18 Jul 2017 05:00:44 +0000 (06:00 +0100)]
radv/winsys: add syncobj hooks
This just adds syncobj create/destroy/export/import paths into
the winsys interface.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 00:54:52 +0000 (01:54 +0100)]
ac/gpu: add code to detect if kernel supports sync objects.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Tim Rowley [Thu, 20 Jul 2017 15:51:30 +0000 (10:51 -0500)]
swr/rast: fix memory paths for avx512 optimized avx/sse
Source/destination will not be AVX512 aligned, use the
unaligned load/store intrinsics.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 20 Jul 2017 14:47:11 +0000 (09:47 -0500)]
swr/rast: cache line align hottile buffers
Prevents unalignment crashes with avx512 code on gcc/clang.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 18 Jul 2017 17:04:41 +0000 (12:04 -0500)]
swr/rast: simdlib changes for clang/gcc
Tested with clang-4.0 and gcc-6.3.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Wladimir J. van der Laan [Fri, 21 Jul 2017 10:49:58 +0000 (12:49 +0200)]
etnaviv: Avoid duplicates in formats table
Remove the following duplicates from the formats table:
- R8G8B8A8_UNORM (V_,_T)
- R8G8B8X8_UNORM (_T,_T)
- DXT3_RGBA (_T,_T)
Only the first has an effect because the _T overrides the V_ initializer,
the latter two were harmless duplications of the same.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Wladimir J. van der Laan [Tue, 18 Jul 2017 10:01:14 +0000 (12:01 +0200)]
etnaviv: Add support for ETC2 texture compression
Add support for ETC2 compressed textures in the etnaviv driver.
One step closer towards GL ES 3 support.
For now, treat SRGB and RGB formats the same. It looks like these are
distinguished using a different bit in sampler state, and not part of
the format, but I have not yet been able to confirm this for sure.
(Only enabled on GC3000+ for now, as the GC2000 ETC2 decoder
implementation is buggy and we don't work around that)
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Wladimir J. van der Laan [Tue, 18 Jul 2017 10:01:13 +0000 (12:01 +0200)]
gallium/util: Implement util_format_is_etc
This is the equivalent of util_format_is_s3tc, but for ETC.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Chih-Wei Huang [Thu, 20 Jul 2017 10:30:57 +0000 (18:30 +0800)]
Android: fix spirv_info.c generation
It's incorrect to use $(LOCAL_PATH) in makefile recipes since it's
changing. The typical way to handle it is to use private variable.
Fortunately in this case we can just simplify them to $^.
See further:
https://patchwork.freedesktop.org/patch/167718/
Also simplify LOCAL_GENERATED_SOURCES.
Fixes:
2dd4e2ec (spirv: Generate spirv_info.c)
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tapani Pälli [Wed, 19 Jul 2017 07:12:47 +0000 (10:12 +0300)]
android: fix libmesa_nir build
current build did not find required include 'spirv_info.h'
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Matt Turner [Fri, 30 Jun 2017 22:48:19 +0000 (15:48 -0700)]
nir: Optimize find_lsb/imsb/umsb error checks
Two of the ARB_shader_ballot piglit tests hit the find_lsb case,
removing some of the noise allowed me to better debug the test when it
was failing.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Matt Turner [Fri, 30 Jun 2017 22:11:15 +0000 (15:11 -0700)]
i965/fs: Match destination type to size for ballot
No use in taking a 64-bit value when we know the high 32-bits are zero.
Matt Turner [Fri, 30 Jun 2017 22:07:10 +0000 (15:07 -0700)]
nir: Reduce destination size of ballot intrinsic when possible
Some hardware, like i965, doesn't support group sizes greater than 32.
In that case, we can reduce the destination size of the ballot
intrinsic, which will simplify our code generation.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Fri, 23 Jun 2017 00:15:28 +0000 (17:15 -0700)]
i965: Enable ARB_shader_ballot on Gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 22 Jun 2017 23:46:39 +0000 (16:46 -0700)]
i965/fs: Implement ARB_shader_ballot operations
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Fri, 30 Jun 2017 21:58:22 +0000 (14:58 -0700)]
i965/fs: Do not move MOVs writing the flag outside of control flow
The implementation of ballotARB() will start by zeroing the flags
register. So, a doing something like
if (gl_SubGroupInvocationARB % 2u == 0u) {
... = ballotARB(true);
[...]
} else {
... = ballotARB(true);
[...]
}
(like fs-ballot-if-else.shader_test does) would generate identical MOVs
to the same destination (the flag register!), and we definitely do not
want to pull that out of the control flow.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 22 Jun 2017 23:42:34 +0000 (16:42 -0700)]
i965/fs: Handle explicit flag sources in flags_read()
The implementations of the ARB_shader_ballot intrinsics will explicitly
read the flag as a source register.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Thu, 6 Jul 2017 04:57:44 +0000 (21:57 -0700)]
nir: Add pass to scalarize read_invocation/read_first_invocation
i965 will want these to be scalar operations.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 22 Jun 2017 23:37:51 +0000 (16:37 -0700)]
nir: Add system values from ARB_shader_ballot
We already had a channel_num system value, which I'm renaming to
subgroup_invocation to match the rest of the new system values.
Note that while ballotARB(true) will return zeros in the high 32-bits on
systems where gl_SubGroupSizeARB <= 32, the gl_SubGroup??MaskARB
variables do not consider whether channels are enabled. See issue (1) of
ARB_shader_ballot.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 22 Jun 2017 23:43:24 +0000 (16:43 -0700)]
nir: Add intrinsics from ARB_shader_ballot
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 22 Jun 2017 19:24:08 +0000 (12:24 -0700)]
i965: Enable ARB_shader_group_vote
Matt Turner [Wed, 21 Jun 2017 05:39:22 +0000 (22:39 -0700)]
i965/fs: Implement ARB_shader_group_vote operations
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 21 Jun 2017 05:38:48 +0000 (22:38 -0700)]
i965/fs: Handle explicit flag destinations in flags_written()
The implementations of the ARB_shader_group_vote intrinsics will
explicitly write the flag as the destination register.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Thu, 22 Jun 2017 19:21:52 +0000 (12:21 -0700)]
i965/vec4: Lower ARB_shader_group_vote intrinsics
I don't expect anyone is going to care about using this in vec4 programs
(vertex/tessellation/geometry on Gen6/7), no one has come up with a good
way to implement it much less test it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 22 Jun 2017 19:20:18 +0000 (12:20 -0700)]
nir: Support lowering vote intrinsics
... trivially (as allowed by the spec!) by reusing the existing
nir_opt_intrinsics code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 22 Jun 2017 19:13:25 +0000 (12:13 -0700)]
nir: Add pass to optimize intrinsics
Specifically, constant fold intrinsics from ARB_shader_group_vote, but I
suspect it'll be useful for other things in the future.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 21 Jun 2017 05:37:43 +0000 (22:37 -0700)]
nir: Add intrinsics from ARB_shader_group_vote
These are intrinsics rather than opcodes, because they operate across
channels.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Thu, 20 Jul 2017 16:29:19 +0000 (17:29 +0100)]
i965: Rename batch->exec_objects to validation_list
Within i965, we have many different objects and confusingly when
submitting an execbuf we have lists of both our internal objects and a
list of the kernel's drm_i915_gem_exec_object with very similar names.
Rename the kernel's validation list to avoid the collison as it is only
used for interfacing with the kernel and so a peripheral use of
"object".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Thu, 20 Jul 2017 04:29:51 +0000 (21:29 -0700)]
Revert "i965: Call intel_prepare_render() from intel_update_state()"
This reverts commit
b7153c3e9f9d2d430b0338313587a00e531e4800.
The point of that commit was to ensure intel_prepare_render() occurred
before color resolves on the current framebuffer. In
0673bbfd9ba16be8
(i965: Move surface resolves back to draw/dispatch time), Jason moved
brw_predraw_resolve_framebuffer back to draw time, which is already
after a intel_prepare_render() call. So, this is no longer necessary.
Furthermore, it caused problems. "mpv" would only display a small
corner of movies, and Android started failing camera CTS tests.
This is because intel_prepare_render() ended up handling DRI2 events
which caused the drawable to be resized at an inopportune time, flagging
ctx->NewState |= _NEW_BUFFERS, but at a point where we've already copied
ctx->NewState, and failed to notice the newly set flag.
The lack of _NEW_BUFFERS caused us to skip 3DSTATE_DRAWING_RECTANGLE,
so the drawing ended up being clipped to an outdated framebuffer size.
Just drop the hack and go back to handling this at the proper time.
Thanks to Matti Hämäläinen (ccr), Tomasz Figa (tfiga), and Tapani Palli
for reporting these issues.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101558
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101704
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:53:04 +0000 (11:53 +0200)]
mesa: remove useless assert in _mesa_TextureView()
Already checked in _mesa_choose_texture_format().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:53:03 +0000 (11:53 +0200)]
mesa: remove duplicated code around framebuffer_renderbuffer()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:53:02 +0000 (11:53 +0200)]
mesa: remove one extra check in _mesa_DeleteTextures()
Already checked above.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:53:01 +0000 (11:53 +0200)]
mesa: make _mesa_generate_texture_mipmap() static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:53:00 +0000 (11:53 +0200)]
mesa: inline save_array_object()
No need to check if ID is not 0 because _mesa_HashFindFreeKeyBlock()
can't generate this value.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:52:59 +0000 (11:52 +0200)]
mesa: inline remove_array_object()
No need to check if ID is not 0 because _mesa_lookup_vao()
already prevents this to happen.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:52:58 +0000 (11:52 +0200)]
mesa: tidy up _mesa_DeleteVertexArrays()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:52:57 +0000 (11:52 +0200)]
mesa: remove useless assert in texture_storage()
Already checked in _mesa_choose_texture_format().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:52:56 +0000 (11:52 +0200)]
mesa: pass the 'caller' function to texstorage()
To be consistent with texturestorage().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 20 Jul 2017 09:52:55 +0000 (11:52 +0200)]
mesa: make _mesa_texture_storage() static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Topi Pohjolainen [Sat, 22 Apr 2017 08:42:02 +0000 (11:42 +0300)]
i965: Represent depth surfaces with isl
v2 (Jason):
- s/separate_stencil_surface/make_separate_stencil_surface/
- drop the check for separate stencil when wrapping an
existing buffer object with miptree. This is dead code as
the first needs_separate_stencil() checks is
MIPTREE_LAYOUT_FOR_BO-flag and says no.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 7 Jun 2017 08:00:43 +0000 (11:00 +0300)]
i965: Drop redundant check for non-tiled depth buffer
Depth buffers are always Y-tiled. In brw_miptree_choose_tiling()
driver opts to use linear buffers for small and 1D but this does
not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT
are considered first.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 7 Jul 2017 05:40:50 +0000 (08:40 +0300)]
intel/isl/gen4: Represent cube maps with 3D layout
v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 28 Jun 2017 09:56:27 +0000 (12:56 +0300)]
i965/miptree: Prepare 3D surfaces with physical 2D layout
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 13 Jun 2017 18:30:45 +0000 (21:30 +0300)]
i965/miptree: Prepare aux state map for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 27 Apr 2017 07:45:05 +0000 (10:45 +0300)]
i965/miptree: Represent y-tiled stencil copies with isl
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 26 May 2017 08:36:38 +0000 (11:36 +0300)]
i965/miptree: Represent w-tiled stencil surfaces with isl
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Mon, 3 Jul 2017 09:57:57 +0000 (12:57 +0300)]
i965/miptree: Prepare compressed offsets for isl based
v2 (Jason): Simply switch to isl_surf_get_image_offset_el()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 28 Jun 2017 05:56:26 +0000 (08:56 +0300)]
i965/miptree: Add support for imported bo offsets for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Sun, 4 Jun 2017 09:36:08 +0000 (12:36 +0300)]
i965/fbo: Add support for isl-based miptrees in rb wrapper
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 22 Jun 2017 18:50:18 +0000 (21:50 +0300)]
i965: Prepare image setup from miptree for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Mon, 24 Apr 2017 14:41:51 +0000 (17:41 +0300)]
i965: Prepare tex, img and rt state emission for isl based miptrees
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Mon, 24 Apr 2017 14:29:01 +0000 (17:29 +0300)]
i965: Refactor miptree to isl converter and adjustment
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 22 Jun 2017 18:28:15 +0000 (21:28 +0300)]
i965: Prepare tex (sub)image for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 22 Jun 2017 18:20:51 +0000 (21:20 +0300)]
i965/wm: Prepare image surfaces for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 19 Jul 2017 13:45:44 +0000 (16:45 +0300)]
i965/wm: Fix number of layers in 3D images
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 22 Jun 2017 18:12:40 +0000 (21:12 +0300)]
i965/miptree: Prepare intel_miptree_copy() for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 22 Jun 2017 18:04:29 +0000 (21:04 +0300)]
i965: Prepare blit engine for isl based miptrees
v2: Do not concern cpp, pitch and tiling which are already
transitioned.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>