Michel Dänzer [Tue, 11 Nov 2014 07:10:20 +0000 (16:10 +0900)]
radeonsi: Disable asynchronous DMA except for PIPE_BUFFER
Using the asynchronous DMA engine for multi-dimensional operations seems
to cause random GPU lockups for various people. While the root cause for
this might need to be fixed in the kernel, let's disable it for now.
Before re-enabling this, please make sure you can hit all newly enabled
paths in your testing, preferably with both piglit and real world apps,
and get in touch with people on the bug reports below for stability
testing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85647
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83500
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Vinson Lee [Sat, 15 Nov 2014 22:07:42 +0000 (14:07 -0800)]
scons: Require glproto >= 1.4.13 for X11.
GLXBadProfileARB and X_GLXCreateContextAtrribsARB require glproto >=
1.4.13. These symbols were added in commit
d5d41112cbccd9301500e8e023be77eb9cb622cd "st/xlib: Generate errors as
specified."
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
José Fonseca [Sun, 16 Nov 2014 11:33:21 +0000 (11:33 +0000)]
draw: Make it more clear that *_jit_context points to pipe_viewport_state structures.
No change in behavior.
José Fonseca [Sun, 16 Nov 2014 11:30:19 +0000 (11:30 +0000)]
draw: Fix breakage due to removal pipe_viewport_state::translate[3] and scale[3].
Unfortunately no LLVM type was generated for pipe_viewport_state -- it
was being treated as a single floating point array --, so llvmpipe (and
any driver that relies on draw/llvm) got totally busted.
José Fonseca [Sun, 16 Nov 2014 10:22:46 +0000 (10:22 +0000)]
gallium/auxiliary: Fix build without LLVM.
Trivial.
José Fonseca [Sun, 16 Nov 2014 10:16:47 +0000 (10:16 +0000)]
gallium/auxiliary: Remove GALLIVM_CPP_SOURCES
Redundant.
Should fix ttps://bugs.freedesktop.org/show_bug.cgi?id=86330
Emil Velikov [Sun, 16 Nov 2014 00:48:18 +0000 (00:48 +0000)]
freedreno: add missing headers in Makefile.sources
... or autotools will fail to pick them up for the distribution tarball.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Tue, 14 Oct 2014 16:44:15 +0000 (17:44 +0100)]
targets: bundle all files in the tarball
We were missing a few files
- The version scripts
- Android & scons build scripts
- A few headers.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sun, 16 Nov 2014 01:07:32 +0000 (01:07 +0000)]
auxiliary: ship all files in the distribution tarball
- Add all headers into Makefile.sources
- Don't forget the target-helpers
- Add the python scripts & the formats table/list (csv)
- Temporary add vl/vl_winsys_dri.c to EXTRA_DIST until we rework the
way VL is build.
- Add the following to EXTRA_DIST - they are included via the
generated u_indices_gen.c thus we should not add them to *SOURCES.
indices/u_indices.c
indices/u_unfilled_indices.c
XXX: Should we nuke gallivm/f.cpp ? It seems that no-one is using it.
v2: Rebase
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Tue, 14 Oct 2014 16:44:13 +0000 (17:44 +0100)]
gallium: ship the gallium API headers
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Tue, 14 Oct 2014 16:44:12 +0000 (17:44 +0100)]
pipe-loader: consolidate sources into Makefile.sources
Drop the unneeded subdir-objects.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Thierry Reding [Thu, 13 Nov 2014 18:05:51 +0000 (19:05 +0100)]
dri/kms: Always zero out struct drm_mode_create_dumb
The DRM_IOCTL_MODE_CREATE_DUMB (and others) IOCTL isn't very rigorously
specified, which has the effect that some kernel drivers do not consider
the .pitch and .size fields of struct drm_mode_create_dumb outputs only.
Instead they will use these as lower bounds and overwrite them only if
the values that they compute are larger than what userspace provided.
This works if and only if userspace initializes the fields explicitly to
either 0 or some meaningful value. However, if userspace just leaves the
values uninitialized and the struct drm_mode_create_dumb is allocated on
the stack for example, the driver may try to overallocate buffers.
Fortunately most userspace does zero out the structure before passing it
to the IOCTL, but there are rare exceptions. Mesa is one of them. In an
attempt to rectify this situation, kernel drivers are being updated to
not use the .pitch and .size fields as inputs. However in order to fix
the issue with older kernels, make sure that Mesa always zeros out the
structure as well.
Future IOCTLs should be more rigorously defined so that structures can
be validated and IOCTLs rejected if output fields aren't set to zero.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Marek Olšák [Sun, 9 Nov 2014 23:37:03 +0000 (00:37 +0100)]
gallium: remove unused pipe_viewport_state::translate[3] and scale[3]
Almost all drivers ignore them.
Marek Olšák [Sat, 8 Nov 2014 15:03:13 +0000 (16:03 +0100)]
radeonsi: implement TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
Required by Nine.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Marek Olšák [Sun, 9 Nov 2014 22:35:08 +0000 (23:35 +0100)]
tgsi/ureg: simplify code for declaring properties
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Marek Olšák [Sat, 8 Nov 2014 15:48:33 +0000 (16:48 +0100)]
gallium/util: add a test for TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
Not testable by OpenGL. Required by Nine.
This is an example of how to implement a piglit-like test using gallium only.
Marek Olšák [Sat, 8 Nov 2014 14:30:54 +0000 (15:30 +0100)]
gallium/util: add a window_space option to the passthrough vertex shader
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Marek Olšák [Sat, 8 Nov 2014 12:35:03 +0000 (13:35 +0100)]
tgsi: fixup the string of VS_WINDOW_SPACE_POSITION
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Rob Clark [Sat, 15 Nov 2014 18:18:06 +0000 (13:18 -0500)]
freedreno/a4xx: implement mem->gmem (restore)
Support to restore gmem (tile buffer) (in case it wasn't glClear'd).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 15 Nov 2014 17:49:22 +0000 (12:49 -0500)]
freedreno/a4xx: move where SP_FS_MRT_REGn is emitted
Addition of color fmt bitfield to this register (compared to a3xx) means
we need to re-emit if either prog or framebuffer state is dirty.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Emil Velikov [Sat, 15 Nov 2014 17:04:10 +0000 (17:04 +0000)]
Revert "mesa: Wrap SSE4.1 code in #ifdef __SSE4_1__."
This reverts commit
8d3f739383fbdf671752fdec707f1c2b9b2aa6a3.
In the last commit we've updated our check to determine if the actual
code is buildable, rather than if the compiler acknowledges the option.
I.e. did anyone provide -mno-sse4.1 vs is my compiler too old.
Now this code will never be attemped to be build, in both cases.
Confirmed by building mesa with
export CFLAGS='-march=native -mno-sse4.1'
./configure && make
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 15 Nov 2014 18:37:22 +0000 (18:37 +0000)]
configure.ac: roll up a program for the sse4.1 check
So when checking/building sse code we have three possibilities:
1 Old compiler, throws an error when using -msse*
2 New compiler, user disables sse* (-mno-sse*)
3 New compiler, user doesn't disable sse
The original code, added code for #1 but not #2. Later on we patched
around the lack of handling #2 by wrapping the code in __SSE4_1__.
Yet it lead to a missing/undefined symbol in case of #1 or #2, which
might cause an issue for #2 when using the i965 driver.
A bit later we "fixed" the undefined symbol by using #1, rather than
updating it to handle #2. With this commit we set things straight :)
To top it all up, conventions state that in case of conflicting
(-enable-foo -disable-foo) options, the latter one takes precedence.
Thus we need to make sure to prepend -msse4.1 to CFLAGS in our test.
v2: Clean the #includes. Suggested by Ilia, Matt & Siavash.
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Siavash Eliasi <siavashserver@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Ilia Mirkin [Thu, 23 Oct 2014 04:43:45 +0000 (00:43 -0400)]
nv50,nvc0: use clip_halfz setting when creating rasterizer state
This enables the ARB_clip_control extension.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Rob Clark [Thu, 31 Jul 2014 19:42:55 +0000 (15:42 -0400)]
freedreno: add adreno 420 support
Very initial support. Basic stuff working (es2gears, es2tri, and maybe
about half of glmark2). Expect broken stuff. Still missing: mem->gmem
(restore), queries, mipmaps (blob segfaults!), hw binning, etc.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 31 Jul 2014 19:09:52 +0000 (15:09 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Kristian Høgsberg [Fri, 14 Nov 2014 00:28:19 +0000 (16:28 -0800)]
i965: Move fs_visitor ra pass to new fs_visitor::allocate_registers()
This will be reused for the scalar VS pass.
v2 (Ken): Rebase on master.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Fri, 14 Nov 2014 00:28:18 +0000 (16:28 -0800)]
i965: Move fs_visitor optimization pass into new method fs_visitor::optimize()
We'll reuse this toplevel optimization driver for the scalar VS.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Fri, 14 Nov 2014 00:28:17 +0000 (16:28 -0800)]
i965: Move more code into codegen-branch of the fs_visitor::run() if statement
These last few operations all only apply when we've actually generated
code, optimized and allocated registers. The dummy and the repclear
shaders don't need the gen4 send workaround, and don't spill. This
means we can move these lines into the else-branch, which will make
the following refactoring easier.
v2 (Ken): Rebase on master, which removed the uncompressed stack.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Fri, 14 Nov 2014 00:28:08 +0000 (16:28 -0800)]
i965: Refactor fs_generator API
We split out SIMD8 and SIMD16 generation into seperate calls to
new method generate_code(), which returns the start offset for the
generated code. A new get_assembly() method returns the generated code.
This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data
in the generator.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
José Fonseca [Fri, 14 Nov 2014 17:20:21 +0000 (17:20 +0000)]
st/wgl: Implement WGL_EXT_create_context_es/es2_profile.
Derived from st/glx's GLX_EXT_create_context_es/es2_profile implementation.
Tested with an OpenGL ES 2.0 ApiTrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Fri, 14 Nov 2014 17:04:26 +0000 (17:04 +0000)]
st/xlib: Generate errors as specified.
Tested with piglit glx tests.
Reviewed-by: Brian Paul <brianp@vmware.com>
Rob Clark [Wed, 5 Nov 2014 17:08:04 +0000 (12:08 -0500)]
freedreno/ir3: move some helpers
Split out a few helpers from fd3_program so we don't have to duplicate
for fd4_program.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 5 Nov 2014 15:42:13 +0000 (10:42 -0500)]
freedreno: rename draw->draw_vbo
Gets rid of a namespace conflict w/ a4xx which wants an fd4_draw()
version of fd_draw()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 5 Nov 2014 15:43:18 +0000 (10:43 -0500)]
freedreno/a3xx: missing u_upload_destroy
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 6 Nov 2014 20:56:43 +0000 (15:56 -0500)]
freedreno: fix borked check for a320.0
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 1 Nov 2014 13:50:18 +0000 (09:50 -0400)]
freedreno/ir3: half vs full reg in standalone compiler output
Handle hrN.c in printing outputs/inputs.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
José Fonseca [Wed, 12 Nov 2014 12:13:42 +0000 (12:13 +0000)]
st/dri: Support EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR/GLX_CONTEXT_DEBUG_BIT_ARB on ES contexts.
The latest version of the specs explicitly allow it, and given that Mesa
universally supports KHR_debug we should definitely support it.
Totally untested. (Just happened to noticed this while implementing
GLX_EXT_create_context_es2_profile for st/xlib.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sat, 1 Nov 2014 13:31:09 +0000 (14:31 +0100)]
egl: remove egl_gallium from the loader
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Informally acked-by: Jose Fonseca
Marek Olšák [Sat, 1 Nov 2014 13:05:16 +0000 (14:05 +0100)]
configure.ac: remove enable flags for EGL and GBM Gallium state trackers
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Informally acked-by: Jose Fonseca
Kenneth Graunke [Tue, 11 Nov 2014 22:40:08 +0000 (14:40 -0800)]
i965/vec4: Combine all the math emitters.
17 insertions(+), 102 deletions(-). Works just as well.
v2: Make emit_math take const references (suggested by Matt),
drop redundant WRITEMASK_XYZW setting (Matt and Curro).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Tue, 11 Nov 2014 01:20:37 +0000 (17:20 -0800)]
i965/vec4: Use const references in emit() functions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Tue, 11 Nov 2014 01:14:48 +0000 (17:14 -0800)]
i965: Use macros to create prototypes for emitter helpers.
We do this almost everywhere else; this should make it easier to modify.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Ben Widawsky [Thu, 13 Nov 2014 02:49:16 +0000 (18:49 -0800)]
i965: Always enable VF statistics
Every other unit in the geometry pipeline automatically enables
statistics gathering. This part of the pipe has been controlled by the
DEBUG_STATS variable, but this is asymmetric. This dates back to the
original implementation, and I am not sure if there is a reason for it.
I need access to these stats to implement ARB_pipeline_statistics_query.
Eric wrote it, and Ken touched it last. Do you have any opposition?
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86145
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ville Syrjälä [Sun, 6 Jul 2014 12:02:15 +0000 (15:02 +0300)]
i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE
According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.
gen3 BSpec no longer has that piece of text, but let's make the same
change there too for symmetry. The spec does still say that the scissor
rectangle must be defined before enabling it, so the new order does seem
more in line with the spec.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Tue, 8 Jul 2014 13:13:58 +0000 (16:13 +0300)]
i915: Don't call _mesa_meta_glsl_Clear() on gen2
Gen2 doesn't have fragment shaders so we shouldn't be calling
_mesa_meta_glsl_Clear() on gen2. Restore the appropriate
ARB_fragment_shader check to the clear path which was lost in:
commit
94f22fbe787214580a1a13a774114d2650c166cb
Author: Tapani Pälli <tapani.palli@intel.com>
Date: Wed Aug 8 20:46:45 2012 +0300
intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2
v2: Fix spelling in commit message
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Mon, 30 Jun 2014 15:42:31 +0000 (18:42 +0300)]
i915: Protect macro argument for TEXTURE_SET()
TEXTURE_SET() is the only register macro that forgets to wrap the
argument evaluation in parens. Only simple integers are passed to this
macro so there's no bug but sitll it seems prudent to add the
parens.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Sun, 6 Jul 2014 12:10:44 +0000 (15:10 +0300)]
i915: Kill intel_context::hw_stencil
ctx.hw_stencil is not used anywhere so kill it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Thu, 3 Jul 2014 12:38:07 +0000 (15:38 +0300)]
i915: Accept GL_DEPTH_STENCIL GL_DEPTH_COMPONENT formats for renderbuffers
Gen2 doesn't support depth/stencil textures, and since
commit
c1d4d4999303f9167b20f4e0674b9436e6295cf7
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Thu Apr 24 14:11:43 2014 +0300
i915: Don't advertise Z formats in TextureFormatSupported on gen2
depth/stencil formats are no longer accepted as texture formats.
However we still want depth/stencil renderbuffers, so add explicit
format checks to intel_alloc_renderbuffer_storage() to allow such
things.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Tue, 8 Jul 2014 12:34:27 +0000 (15:34 +0300)]
i915: Override mip filter to nearest with aniso
gen2 doesn't supporte linear mip filter with anisotropic min/mag
filtering. The hardware would automagically downgrade the min/mag
filters to linear in such cases, which IMO looks worse than forcing
the mip filter to nearest.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Thu, 7 Aug 2014 08:14:35 +0000 (11:14 +0300)]
i915: Use L8A8 instead of I8 to simulate A8 on gen2
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.
v2: Handle the fallback in _mesa_choose_tex_format() and also
do it for all alpha formats that currently accept A8
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72819
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80050
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38873
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville Syrjälä [Thu, 3 Jul 2014 12:55:38 +0000 (15:55 +0300)]
i915: Fix GL_DOT3_RGBA a bit
The spec says using DOT4 for alpha is undefined unless DOT4 is also used
for color. It seems to do the right thing anyway, but better safe than sorry.
Also override numAlphaArgs to 2 for DOT4 since that's what it wants.
This migth fix something in case the specified alpha mode has only one
argument. Also avoids emitting a needless 3DSTATE_MAP_BLEND_ARG if
the specified alpha mode has three arguments.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Neil Roberts [Thu, 13 Nov 2014 15:31:44 +0000 (15:31 +0000)]
linker: Add a missing space in an error message
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Thu, 13 Nov 2014 15:01:19 +0000 (15:01 +0000)]
llvmpipe: Call pipe_thread_wait() on Linux.
To address http://lists.freedesktop.org/archives/mesa-dev/2014-November/070569.html
In short, revert
706ad3b649e6a75fdac9dc9acc3caa9e6067b853 for non-Windows
OSes.
Kenneth Graunke [Wed, 12 Nov 2014 01:08:22 +0000 (17:08 -0800)]
i915g: we also have more than 0 viewports!
See
546d6c8d for the corresponding fix in freedreno.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Eric Anholt [Wed, 12 Nov 2014 22:14:32 +0000 (14:14 -0800)]
vc4: Avoid reusing a pointer from c->outputs[] after add_output().
add_output() can resize the qreg array, so we might use a stale pointer.
Eric Anholt [Fri, 7 Nov 2014 22:26:32 +0000 (14:26 -0800)]
vc4: Fix assumption of TGSI OUT[0] being POSITION in the VS.
All the shaders we've received so far had this be the case, but with
nir-to-tgsi that changed.
I might decide to make nir-to-tgsi keep the outputs in the same order, for
debugging sanity, but I'm not sure.
Ilia Mirkin [Thu, 16 Oct 2014 06:58:28 +0000 (02:58 -0400)]
nvc0: remove unused mm_VRAM_fe0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
José Fonseca [Wed, 12 Nov 2014 12:18:41 +0000 (12:18 +0000)]
st/glx: Implement GLX_EXT_create_context_es2_profile.
apitrace now supports it, and it makes it much easier to test
tracing/replaying on OpenGL ES contexts since
GLX_EXT_create_context_{es2,es}_profile are widely available.
Reviewed-by: Brian Paul <brianp@vmware.com>
Tom Stellard [Wed, 12 Nov 2014 17:28:34 +0000 (12:28 -0500)]
Revert "clover: Fix build after llvm r221375"
This reverts commit
cd93d82ba9ec8cd8e4f54bbee16d7b47c542de71.
llvm r221375 was reverted, so this commit needs to be too.
José Fonseca [Wed, 12 Nov 2014 10:32:38 +0000 (10:32 +0000)]
gallivm: Fix build with LLVM 3.6 (r221751).
Tested with LLVM 3.3, 3.4, 3.5, and 3.6.
Trivial.
Matt Turner [Tue, 11 Nov 2014 06:04:41 +0000 (22:04 -0800)]
i965/cfg: Remove if_block/else_block.
I used these in the SEL peephole, but they require extra tracking and
fix ups. The SEL peephole can pretty easily find the blocks it needs
without these.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Tue, 11 Nov 2014 06:02:38 +0000 (22:02 -0800)]
i965/fs: Don't use if_block/else_block in SEL peephole.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Chia-I Wu [Tue, 11 Nov 2014 07:15:21 +0000 (15:15 +0800)]
ilo: clean up gen6_3DSTATE_SF()
Make the helpers fill out valid Gen7 3DSTATE_SF and 3STATE_SBE. This
prevents the helpers from having to do
dw[0] = GEN7_SBE_DW1_x; // setting DW1 value to dw[0]!?
and simplifies gen7_3DSTATE_{SF,SBE}().
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 05:28:32 +0000 (13:28 +0800)]
ilo: clean up gen7_3DSTATE_STREAMOUT()
Render stream and render enable are independent from so enable. Having a
single return point makes it easier to see that.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 03:53:57 +0000 (11:53 +0800)]
ilo: rework gen7_3DSTATE_SO_DECL_LIST()
Started to make pipe_stream_output_info mandatory, but ended up adding support
for stream id and making a workaround Gen7-specific.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 03:21:01 +0000 (11:21 +0800)]
ilo: add 3DSTATE_SO_BUFFER variants
Add gen7_disable_3DSTATE_SO_BUFFER() to disable SO buffers.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 03:06:12 +0000 (11:06 +0800)]
ilo: add gen6_3dstate_constant()
It replaces gen6_fill_3dstate_constant(). gen6_3DSTATE_CONSTANT_{VS,GS,PS}
are made wrappers of the new function.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 02:38:28 +0000 (10:38 +0800)]
ilo: add variants of 3DSTATE_{HS,DS}
Rename them to gen7_disable_3DSTATE_{HS,DS}() to reflect the fact.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 02:35:24 +0000 (10:35 +0800)]
ilo: add variants of 3DSTATE_GS
Add gen6_so_3DSTATE_GS(), gen6_disable_3DSTATE_GS(), and
gen7_disable_3DSTATE_GS() to do SO on GEN6 or to disable GS.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 02:31:55 +0000 (10:31 +0800)]
ilo: add variants of 3DSTATE_VS
Add gen6_disable_3DSTATE_VS() to disable VS.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 02:50:31 +0000 (10:50 +0800)]
ilo: add variants of 3DSTATE_PS
Add gen7_disable_3DSTATE_PS() to disable PS.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 02:25:20 +0000 (10:25 +0800)]
ilo: add variants of 3DSTATE_WM
Add gen6_hiz_3DSTATE_WM() and gen7_hiz_3DSTATE_WM() for HiZ ops without
dispatching.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 02:21:03 +0000 (10:21 +0800)]
ilo: add variants of 3DSTATE_CLIP
Add gen6_disable_3DSTATE_CLIP to disable clipping.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Tue, 11 Nov 2014 01:11:37 +0000 (09:11 +0800)]
ilo: prefix 3DSTATE_VF with gen75
3DSTATE_VF is Gen7.5+ only.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Michael Varga [Thu, 23 Oct 2014 15:45:20 +0000 (10:45 -0500)]
st/va: MPEG4 call vlVaDecoderFixMPEG4Startcode()
If the VOP and GOV headers were truncated they will be regenerated.
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
Michael Varga [Thu, 23 Oct 2014 15:41:24 +0000 (10:41 -0500)]
st/va: MPEG4 generate GOV and VOP header
Also, Implemented a small locally used interface for writing bits to a buffer.
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
Michael Varga [Thu, 23 Oct 2014 15:36:52 +0000 (10:36 -0500)]
st/va: MPEG4 populate the SPS structure
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
Michael Varga [Thu, 23 Oct 2014 15:18:09 +0000 (10:18 -0500)]
st/va: MPEG4 populate the iq matrix buffers
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
Michael Varga [Thu, 23 Oct 2014 15:13:05 +0000 (10:13 -0500)]
st/va: MPEG4 populate the PPS structure
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
Michael Varga [Fri, 17 Oct 2014 16:05:59 +0000 (11:05 -0500)]
st/va: refactored handleVASliceDataBufferType
This patch cleans the function handleVASliceDataBufferType() for better
readability.
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
Ian Romanick [Fri, 7 Nov 2014 06:56:03 +0000 (22:56 -0800)]
mesa: Remove _mesa_max_buffer_index
It appears to be completely unused since
f9be8543 (February 2012).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 21 Oct 2014 00:02:55 +0000 (17:02 -0700)]
mesa: Uniform logging is very, very unlikely
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Fri, 24 Oct 2014 20:08:06 +0000 (13:08 -0700)]
glsl: Swap the order of glsl_type::name and ::length
On x86-64 this saves 8 bytes of padding in the structure, and this
reduces the size of the structure to 32 bytes.
v2: Fix constructor so that GCC won't warn about the order of
initialization.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Fri, 24 Oct 2014 20:04:24 +0000 (13:04 -0700)]
glsl: Store glsl_type::vector_elements and ::matrix_columns as uint8_t
Due to the total number of bits used in the bitfield, this does not
increase the size of the structure.
It does, however, reduce the number of instructions required each time
one of these fields is accessed. To access ::matrix_columns with the
bitfield, three instructions were required:
movzbl 0x9(%rdx),%eax
shr %al
and $0x7,%eax
As a uint8_t, only one instruction is required.
movzbl 0xa(%rdx),%eax
These fields are accessed *a lot*.
Valgrind callgrind results for a trace of Tesseract:
_mesa_Uniform4fv _mesa_Uniform4f _mesa_Uniform1i
Before (64-bit): 48,103,497 16,556,096 676,447
After (64-bit): 45,722,616 15,737,964 670,607
_mesa_Uniform4fv _mesa_Uniform4f _mesa_Uniform1i
Before (32-bit): 61,472,611 21,051,222 821,361
After (32-bit): 57,987,421 19,872,226 811,609
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Mon, 20 Oct 2014 23:50:53 +0000 (16:50 -0700)]
mesa: Don't check for API_OPENGLES in _mesa_uniform_matrix
There are no uniforms in OpenGL ES 1.x, so we can't even get to this
code in that API.
Also, reorder the checks. First check that transpose is true, then
check whether or not that is legal in the current API. transpose should
never be true in an ES2 context, so this gets one check (the more
expensive one) out of the main path.
Valgrind callgrind results for a trace of Tesseract:
_mesa_UniformMatrix4fv _mesa_UniformMatrix3fv
Before (64-bit): 96,119,025 24,240,510
After (64-bit): 90,726,569 22,926,662
_mesa_UniformMatrix4fv _mesa_UniformMatrix3fv
Before (32-bit): 132,434,452 29,051,808
After (32-bit): 126,658,112 27,989,316
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Mon, 20 Oct 2014 23:40:50 +0000 (16:40 -0700)]
mesa: Rework array error checks in validate_uniform_parameters
Before ARB_explicit_uniform_location, Mesa's location encoding allowed
locations for non-array types that had non-zero array indices.
Basically, part of the location was the uniform and part was the array
index. This meant that some checks had to occur for arrays and
non-arrays. This is no longer possible, we the checks can be split up.
Valgrind callgrind results for a trace of Tesseract:
_mesa_Uniform4fv _mesa_Uniform4f _mesa_Uniform1i
Before (64-bit): 50,499,557 17,487,316 686,227
After (64-bit): 50,023,791 17,274,432 684,293
_mesa_Uniform4fv _mesa_Uniform4f _mesa_Uniform1i
Before (32-bit): 62,968,039 21,732,380 828,147
After (32-bit): 62,373,967 21,490,756 826,223
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Mon, 20 Oct 2014 21:47:45 +0000 (14:47 -0700)]
mesa: Get some gl_shader_program::LinkStatus checking out of the main path
I really wanted to remove 'shProg != NULL' as well, but that would have
required adding a dummy program as the default program. That seemed
like more churn than removing one test was worth.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Mon, 20 Oct 2014 23:21:54 +0000 (16:21 -0700)]
mesa: Rework location == -1 error checking
Only one caller wanted to generate an error when location == -1, so move
the error generation to that caller. There will be more callers in the
future that do not want to generate errors.
Move the location == -1 check later in validate_uniform_parameters. As
currently implemented, glUniform1iv(-1, -1, data) would not generate an
error, but it should due to count being < 0.
The location that I have moved it to will make more sense with the next
commit.
Valgrind callgrind results for a trace of Tesseract:
_mesa_Uniform4fv _mesa_Uniform4f _mesa_Uniform1i
Before (64-bit): 51,241,217 17,740,162 689,181
After (64-bit): 50,499,557 17,487,316 686,227
_mesa_Uniform4fv _mesa_Uniform4f _mesa_Uniform1i
Before (32-bit): 63,940,605 21,987,918 831,065
After (32-bit): 62,968,039 21,732,380 828,147
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Fri, 10 Oct 2014 14:35:31 +0000 (16:35 +0200)]
mesa: Minor clean ups in _mesa_uniform
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Fri, 10 Oct 2014 13:29:31 +0000 (15:29 +0200)]
mesa: Remove GLSL_TYPE_SAMPLER check
Noting the assertion just a few lines earlier, returnType cannot be
GLSL_TYPE_SAMPLER.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Ian Romanick [Thu, 9 Oct 2014 09:00:32 +0000 (11:00 +0200)]
mesa/main: Pass the data that _mesa_uniform actually wants
The GL_ enums were previously used because glsl_types.h couldn't be used
in C code. That was fixed some time ago (and uniforms.c already
includes glsl_types.h), so this is no longer necessary.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Chia-I Wu [Mon, 10 Nov 2014 05:44:45 +0000 (13:44 +0800)]
ilo: derive fb blending caps at bind time
Derive whether a RT supports blending, logicop, and the like when
set_framebuffer_state() is called. This enables us to simplify
gen6_BLEND_STATE().
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Mon, 10 Nov 2014 05:11:40 +0000 (13:11 +0800)]
ilo: remove inlined state functions
We had some inlined state functions for dispatching. They were not needed
with the new top/bottom split.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Mon, 10 Nov 2014 04:55:34 +0000 (12:55 +0800)]
ilo: use top/bottom split for state functions
Follow the builder and split state functions into top (vertex processing) and
bottom (pixel processing).
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Kenneth Graunke [Tue, 4 Nov 2014 01:56:38 +0000 (17:56 -0800)]
i965: Advertise a line width of 40.0 on Cherryview and Skylake.
According to the documentation, line widths higher than 40.0 may have
quality problems. That's already 20 times larger than we've been
exposing, so it seems totally sufficient.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Tue, 4 Nov 2014 01:01:53 +0000 (17:01 -0800)]
i965: Advertise larger line widths.
We've artificially been limiting this to 5 for no particular reason.
On Gen4-5, the limit is [0, 7.5] with a granularity of 0.5 (U3.1).
On Gen6+, the limit is [0, 7.9921875]. Since it's a U3.7, the
granularity should be 0.125 (1/8).
This patch conservatively advertises one granularity smaller than the
hardware's maximum value, just in case there's a problem using the
largest possible value. On Gen4-5, this is 7.5 - 0.5 = 7.0. On Gen6+,
this is 8.0 - 0.125 = 7.875.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Tue, 4 Nov 2014 00:26:48 +0000 (16:26 -0800)]
i965: Use ctx->Const.MaxLineWidth when clamping ctx->Line.Width.
Rather than hardcoding platform values in every code path, just use the
maximum value we set.
Currently, ctx->Const.LineWidth == 5, which is smaller than the hardware
limit. But applications shouldn't be using a value larger than we
support anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Tue, 4 Nov 2014 00:10:55 +0000 (16:10 -0800)]
i965: Set Line Width correctly on Cherryview and Skylake.
Line Width moved to DW1 bits 29:12. It's actually now a U11.7.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Emil Velikov [Sat, 8 Nov 2014 17:15:42 +0000 (17:15 +0000)]
docs: add news item and link release notes for mesa 10.3.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sat, 8 Nov 2014 17:07:34 +0000 (17:07 +0000)]
docs: Add sha256 sums for the 10.3.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
9cc26056ee13f25c5785fef81b31487f1429baa4)