Huihui Zhang [Fri, 7 Feb 2020 22:00:44 +0000 (14:00 -0800)]
Reland "[ARM] Fix data race on RegisterBank initialization."
Update lambda function
static auto InitializeRegisterBankOnce = [this](const auto &TRI) {
with
static auto InitializeRegisterBankOnce = [&]() {
Capture reference instead of passing argument, as there are buildbot
compiling errors related when passing argument.
Davide Italiano [Fri, 7 Feb 2020 21:51:58 +0000 (13:51 -0800)]
[TestConvienceVariable] Clean the directory before running the test.
Petr Hosek [Thu, 6 Feb 2020 03:37:50 +0000 (19:37 -0800)]
[CMake] Use LLVM tools external project build where possible
This reduces the reliance on host tools and makes the build more
hermetic. Some of the runtimes already assume that certain tools are
always available, for example libc++ and libc++abi archive merging
relies on ar to extract files out of the archive, even on Darwin.
Differential Revision: https://reviews.llvm.org/D74107
natashaknk [Fri, 7 Feb 2020 21:35:36 +0000 (16:35 -0500)]
[mlir][spirv] Adding sin op in the GLSL extension
Differential Revision: https://reviews.llvm.org/D74151
Jan Kratochvil [Fri, 7 Feb 2020 21:23:09 +0000 (22:23 +0100)]
[lldb] Fix+re-enable Assert StackFrame Recognizer on Linux
D73303 was failing on Fedora Linux and so it was disabled by Skip the
AssertFrameRecognizer test for Linux.
On Fedora 30 x86_64 I have:
$ readelf -Ws /lib64/libc.so.6 |grep '^Symbol\|.*assert_fail'
Symbol table '.dynsym' contains 2362 entries:
630:
0000000000030520 70 FUNC GLOBAL DEFAULT 14 __assert_fail@@GLIBC_2.2.5
Symbol table '.symtab' contains 22711 entries:
922:
000000000002275a 15 FUNC LOCAL DEFAULT 14 __assert_fail_base.cold
18044:
0000000000030520 70 FUNC LOCAL DEFAULT 14 __GI___assert_fail
20081:
00000000000303a0 370 FUNC LOCAL DEFAULT 14 __assert_fail_base
21766:
0000000000030520 70 FUNC GLOBAL DEFAULT 14 __assert_fail
The patch should never expect __GI___assert_fail:
.symtab can be present or not but that should not change that
__assert_fail always wins - it is always present from .dynsym and it can
never be overriden by __GI___assert_fail as __GI___assert_fail has only
local binding. Global binding is preferred since D63540.
External debug info symbols do not matter since D55859 (and DWARF should
never be embedded in system libc.so.6).
Differential Revision: https://reviews.llvm.org/D74252
Huihui Zhang [Fri, 7 Feb 2020 20:57:24 +0000 (12:57 -0800)]
Reland "[AArch64] Fix data race on RegisterBank initialization."
Update lambda function
static auto InitializeRegisterBankOnce = [this](const auto &TRI) {
with
static auto InitializeRegisterBankOnce = [&]() {
Capture reference instead of passing argument, as there are buildbot
compiling errors related when passing argument.
Nicolas Vasilache [Fri, 7 Feb 2020 20:39:43 +0000 (15:39 -0500)]
[mlir][VectorOps] Introduce a `vector.fma` op that works on n-D vectors and lowers to `llvm.intrin.fmuladd`
Summary:
The `vector.fma` operation is portable enough across targets that we do not want
to keep it wrapped under `vector.outerproduct` and `llvm.intrin.fmuladd`.
This revision lifts the op into the vector dialect and implements the lowering to LLVM by using two patterns:
1. a pattern that lowers from n-D to (n-1)-D by unrolling when n > 2
2. a pattern that converts from 1-D to the proper LLVM representation
Reviewers: ftynse, stellaraccident, aartbik, dcaballe, jsetoain, tetuante
Reviewed By: aartbik
Subscribers: fhahn, dcaballe, merge_guards_bot, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74075
Nemanja Ivanovic [Fri, 7 Feb 2020 20:26:11 +0000 (14:26 -0600)]
[PowerPC] Fix spilling of vector registers in PEI of EH aware functions
On little endian targets prior to Power9, we spill vector registers using a
swapping store (i.e. stdxvd2x saves the vector with the two doublewords in
big endian order regardless of endianness). This is generally not a problem
since we restore them using the corresponding swapping load (lxvd2x). However
if the restore is done by the unwinder, the vector register contains data in
the incorrect order.
This patch fixes that by using Altivec loads/stores for vector saves and
restores in PEI (which keep the order correct) under those specific conditions:
- EH aware function
- Subtarget requires swaps for VSX memops (Little Endian prior to Power9)
Differential revision: https://reviews.llvm.org/D73692
Nicolas Vasilache [Fri, 7 Feb 2020 20:22:06 +0000 (15:22 -0500)]
[mlir][VectorOps] Expose and use llvm.intrin.fma*
Summary:
This revision exposes the portable `llvm.fma` intrinsic in LLVMOps and uses it
in lieu of `llvm.fmuladd` when lowering the `vector.outerproduct` op to LLVM.
This guarantees proper `fma` instructions will be emitted if the target ISA
supports it.
`llvm.fmuladd` does not have this guarantee in its semantics, despite evidence
that the proper x86 instructions are emitted.
For more details, see https://llvm.org/docs/LangRef.html#llvm-fmuladd-intrinsic.
Reviewers: ftynse, aartbik, dcaballe, fhahn
Reviewed By: aartbik
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74219
Alexey Bataev [Fri, 7 Feb 2020 17:22:23 +0000 (12:22 -0500)]
[OPENMP50]Add codegen for acq_rel clause in atomic|flush directives.
Added codegen support for atomic|flush directives with acq_rel clause.
Sourabh Singh Tomar [Fri, 7 Feb 2020 19:54:04 +0000 (01:24 +0530)]
[DebugInfo]: Fix the debuginfo-tests/llgdb-tests/apple-accel.cpp test
failure after 84e5760.
Richard Smith [Fri, 7 Feb 2020 19:53:54 +0000 (11:53 -0800)]
[cxx_status] Fix status of P1766R to not bleed into adjacent cells.
Nico Weber [Fri, 7 Feb 2020 19:49:38 +0000 (14:49 -0500)]
Revert "Support -fstack-clash-protection for x86"
This reverts commit
4a1a0690ad6813a4c8cdb8dc20ea6337aa1f61e0.
Breaks tests on mac and win, see https://reviews.llvm.org/D68720
Richard Smith [Thu, 6 Feb 2020 02:52:38 +0000 (18:52 -0800)]
Implement P1766R1: diagnose giving non-C-compatible classes a typedef name for linkage purposes.
Summary:
Due to a recent (but retroactive) C++ rule change, only sufficiently
C-compatible classes are permitted to be given a typedef name for
linkage purposes. Add an enabled-by-default warning for these cases, and
rephrase our existing error for the case where we encounter the typedef
name for linkage after we've already computed and used a wrong linkage
in terms of the new rule.
Reviewers: rjmccall
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74103
Changpeng Fang [Fri, 7 Feb 2020 19:46:23 +0000 (11:46 -0800)]
AMDGPU: Enhancement on FDIV lowering in AMDGPUCodeGenPrepare
Summary:
The accuracy limit to use rcp is adjusted to 1.0 ulp from 2.5 ulp.
Also, afn instead of arcp is used to allow inaccurate rcp to be used.
Reviewers:
arsenm
Differential Revision: https://reviews.llvm.org/D73588
Fangrui Song [Thu, 6 Feb 2020 22:48:28 +0000 (14:48 -0800)]
[dsymutil] Delete unneeded parameter Triple from DWARFLinker
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D74173
Vladimir Vereschaka [Fri, 7 Feb 2020 18:48:33 +0000 (10:48 -0800)]
Revert "[CMake] Filter libc++abi and libunwind from runtimes build in MSVC"
This reverts commit
9986b88e64f30f5d958eef113bae4c8a098eea93.
These changes break ARM/Aarch64 cross builders on Windows platform
* http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l
* http://lab.llvm.org:8011/builders/llvm-clang-win-x-aarch64
suppressing building libc++abi/libunwind by "just built" toolchain.
Differential Revision: https://reviews.llvm.org/D73812
Kostya Kortchinsky [Thu, 6 Feb 2020 23:46:05 +0000 (15:46 -0800)]
[scudo][standalone] 32-bit improvement
Summary:
This tweaks some behaviors of the allocator wrt 32-bit, notably
tailoring the size-class map.
I had to remove a `printStats` from `__scudo_print_stats` since when
within Bionic they share the same slot so they can't coexist at the
same time. I have to find a solution for that later, but right now we
are not using the Svelte configuration.
Reviewers: rengolin
Subscribers: #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D74178
Jessica Paquette [Fri, 7 Feb 2020 17:07:47 +0000 (09:07 -0800)]
[AArch64][GlobalISel] Reland SLT/SGT TBNZ optimization
The issue in the previous commits was that we swap the LHS and RHS while
looking for the constant. In SLT/SGT, the constant must be on the RHS, or the
optimization is invalid.
Move the swapping logic after the check for the SLT/SGT case and update tests.
Original commits:
d78cefb1601070cb028b61bbc1bd6f25a9c1837c
a3738414072900ace9cbbe209d0195a3443d1d54
Changpeng Fang [Fri, 7 Feb 2020 19:06:33 +0000 (11:06 -0800)]
AMDGPU: Limit the search in finding the instruction pattern for v_swap generation.
Summary:
Current implementation of matchSwap in SIShrinkInstructions searches the entire
use_nodbg_operands set to find the possible pattern to generate v_swap instruction.
This approach will lead to a O(N^3) in compile time for SIShrinkInstructions.
But in reality, the matching pattern only exists within nearby instructions in the
same basic block. This work limits the search to a maximum of 16 instructions, and has
a linear compile time comsumption.
Reviewers:
rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D74180
serge_sans_paille [Mon, 9 Sep 2019 14:59:34 +0000 (16:59 +0200)]
Support -fstack-clash-protection for x86
Implement protection against the stack clash attack [0] through inline stack
probing.
Probe stack allocation every PAGE_SIZE during frame lowering or dynamic
allocation to make sure the page guard, if any, is touched when touching the
stack, in a similar manner to GCC[1].
This extends the existing `probe-stack' mechanism with a special value `inline-asm'.
Technically the former uses function call before stack allocation while this
patch provides inlined stack probes and chunk allocation.
Only implemented for x86.
[0] https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt
[1] https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00556.html
This a recommit of
39f50da2a357a8f685b3540246c5d762734e035f with correct option
flags set.
Differential Revision: https://reviews.llvm.org/D68720
MaheshRavishankar [Fri, 7 Feb 2020 18:28:20 +0000 (10:28 -0800)]
[mlir][Linalg] Implement fusion of linalg.generic operation on tensors.
The initial implementation of the fusion operation exposes a method to
fuse a consumer with its producer, when
- both the producer and consumer operate on tensors
- the producer has only a single result value
- the producer has only "parallel" iterator types
A new interface method hasTensorSemantics is added to verify that an
operation has all operands and results of type RankedTensorType.
Differential Revision: https://reviews.llvm.org/D74172
Sean Fertile [Mon, 27 Jan 2020 20:21:19 +0000 (15:21 -0500)]
[PowerPC] Create a FixedStack object for CR save in linkage area.
hasReservedSpillSlot returns a dummy frame index of '0' on PPC64 for the
non-volatile condition registers, which leads to the CalleSavedInfo
either referencing an unrelated stack object, or an invalid object if
there are no stack objects. The latter case causes the mir-printer to
crash due to assertions that checks if the frame index referenced by a
CalleeSavedInfo is valid.
To fix the problem create an immutable FixedStack object at the correct offset
in the linkage area of the previous stack frame (ie SP + positive offset).
Differential Revision: https://reviews.llvm.org/D73709
Craig Topper [Fri, 7 Feb 2020 18:18:01 +0000 (10:18 -0800)]
[X86] Handle SETB_C32r/SETB_C64r in flag copy lowering the same way we handle SBB
Previously we took the restored flag in a GPR, extended it 32 or 64 bits. Then used as an input to a sub from 0. This requires creating a zero extend and creating a 0.
This patch changes this to just use an ADD with 255 to restore the carry flag and keep the SETB_C32r/SETB_C64r. Exactly like we handle SBB which is what SETB becomes.
Differential Revision: https://reviews.llvm.org/D74152
Jay Foad [Fri, 7 Feb 2020 17:05:48 +0000 (17:05 +0000)]
[AMDGPU] Use @LINE for error checking in gfx10 assembler tests
Summary:
This is a rework of D72611, using @LINE to check that errors are
reported against the right instruction instead of adding lots of extra
*-ERR-NEXT: check lines.
Reviewers: rampitec, arsenm, nhaehnle
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74227
Michael Liao [Fri, 7 Feb 2020 17:58:17 +0000 (12:58 -0500)]
[clang] Fix linkage of nested lambdas.
patch from Philippe Daouadi <blastrock@free.fr>
This is an attempt to fix
[PR#44368](https://bugs.llvm.org/show_bug.cgi?id=44368)
This effectively reverts [D1783](https://reviews.llvm.org/D1783). It
doesn't break the current tests and fixes the test that this commit
adds.
We now decide of a lambda linkage only depending on the visibility of
its parent context.
Differential Revision: https://reviews.llvm.org/D73701
Matt Arsenault [Fri, 7 Feb 2020 15:34:13 +0000 (10:34 -0500)]
AMDGPU/GlobalISel: Fix missing test for select of s64 scalar G_CTPOP
Vedant Kumar [Thu, 6 Feb 2020 21:14:27 +0000 (13:14 -0800)]
[MachineInstr] Add isCandidateForCallSiteEntry predicate
Add the isCandidateForCallSiteEntry predicate to MachineInstr to
determine whether a DWARF call site entry should be created for an
instruction.
For now, it's enough to have any call instruction that doesn't belong to
a blacklisted set of opcodes. For these opcodes, a call site entry isn't
meaningful.
Differential Revision: https://reviews.llvm.org/D74159
Pavel Labath [Sun, 2 Feb 2020 07:48:51 +0000 (08:48 +0100)]
[lldb] Group ABI plugins
Summary:
There's a fair amount of code duplication between the different ABI plugins for
the same architecture (e.g. ABIMacOSX_arm & ABISysV_arm). Deduplicating this
code is not very easy at the moment because there is no good place where to put
the common code.
Instead of creating more plugins, this patch reduces their number by grouping
similar plugins into a single folder/plugin. This makes it easy to extract
common code to a (e.g.) base class, which can then live in the same folder.
The grouping is done based on the underlying llvm target for that architecture,
because the plugins already require this for their operation.
Reviewers: JDevlieghere, jasonmolenda, jfb
Subscribers: sdardis, nemanjai, mgorny, kristof.beyls, fedor.sergeev, kbarton, jrtc27, atanasyan, jsji, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D74138
Med Ismail Bennani [Fri, 7 Feb 2020 17:40:28 +0000 (18:40 +0100)]
[lldb/test] Skip the AssertFrameRecognizer test for Linux
This patch skips the AssertFrameRecognizer test for Linux since it appears to
fail on certain distributions (AFAIK Fedora & ArchLinux).
The failure happen because the thread don't set the current frame to
the most relevant one. So the stopped location doesn't match with what
the test is expecting.
The test will be enabled again after I'll be able to reproduce the failure
on one of those platform and fix the issue.
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Fangrui Song [Fri, 7 Feb 2020 17:43:40 +0000 (09:43 -0800)]
[ELF][ARM][test] Keep arm-thumb-interwork-shared.s
The revert of D73542 (
c29003813ab9bd6ea7b6de40ea8f1fe21979f13f) deleted
the newly added tests to arm-thumb-interwork-shared.s . We should keep
them.
Petar Avramovic [Fri, 7 Feb 2020 16:38:01 +0000 (17:38 +0100)]
[GlobalISel] Add buildMerge with SrcOp initializer list
Allows more flexible use of buildMerge in places where
use operands are available as SrcOp since it does not
require explicit conversion to Register.
Simplify code with new buildMerge.
Differential Revision: https://reviews.llvm.org/D74223
Fangrui Song [Sat, 1 Feb 2020 06:25:16 +0000 (22:25 -0800)]
[yaml2obj][test] Simplify some e_machine EI_CLASS EI_DATA tests
When both little-endian and big-endian are tested, or both 32-bit and 64-bit are tested, use a template like the following with `-D BITS=32 -D ENCODE=LSB`
```
--- !ELF
FileHeader:
Class: ELFCLASS[[BITS]]
Data: ELFDATA2[[ENCODE]]
Type: ET_DYN
Machine: EM_X86_64
```
Reviewed By: grimar, jhenderson
Differential Revision: https://reviews.llvm.org/D73828
Fangrui Song [Mon, 3 Feb 2020 19:12:04 +0000 (11:12 -0800)]
[yaml2obj] Add -D k=v to preprocess the input YAML
Examples:
```
yaml2obj -D MACHINE=EM_386 a.yaml -o a.o
yaml2obj -D MACHINE=0x1234 a.yaml -o a.o
```
where a.yaml contains:
```
--- !ELF
FileHeader:
Class: ELFCLASS64
Data: ELFDATA2MSB
Type: ET_REL
Machine: [[MACHINE]]
```
Reviewed By: grimar, jhenderson
Differential Revision: https://reviews.llvm.org/D73821
aartbik [Fri, 7 Feb 2020 17:09:05 +0000 (09:09 -0800)]
[mlir][VectorOps] Generalized vector.print to i32/i64
Summary:
Lowering to LLVM IR was restricted to float/double.
This CL also adds the integral values.
Reviewers: andydavis1, nicolasvasilache, ftynse
Reviewed By: nicolasvasilache, ftynse
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74179
Pavel Labath [Thu, 6 Feb 2020 22:47:56 +0000 (14:47 -0800)]
[lldb] Delete ValueObjectRegisterContext class
It is unused.
Sanjay Patel [Fri, 7 Feb 2020 16:49:36 +0000 (11:49 -0500)]
[x86] don't create an unused constant vector
Noticed while scanning through debug spew. Creating unused
nodes is inefficient and makes following the debug output harder.
Simon Pilgrim [Fri, 7 Feb 2020 16:38:24 +0000 (16:38 +0000)]
[X86] isNegatibleForFree - allow pre-legalized FMA negation
As long as the FMA operation is legal (which we can proxy for the FMA3/FMA4 variants as well), we don't have to wait for the LegalOperations stage.
Amara Emerson [Fri, 7 Feb 2020 09:07:57 +0000 (01:07 -0800)]
[GlobalISel][IRTranslator] Add special case support for ~memory inline asm clobber.
This is a one off special case, since actually implementing full inline asm
support will be much more involved. This lets us compile a lot more code as a
common simple case.
Differential Revision: https://reviews.llvm.org/D74201
Michał Górny [Sun, 12 Jan 2020 21:49:36 +0000 (22:49 +0100)]
[lldb] Improve debugging 32-bit programs on NetBSD/amd64
Implement detection of ELF binary format, and support for i386 register
context on amd64 when a 32-bit executable is being debugged. This is
roughly based on the code from Linux.
Differential Revision: https://reviews.llvm.org/D73974
Med Ismail Bennani [Fri, 7 Feb 2020 16:28:34 +0000 (17:28 +0100)]
[lldb/test] Prevent TestFrameRecognizer.py to fail because of internal recognizers (NFC)
By clearing the recognizers before starting the test, we ensure that the
recognizers that get initialized when lldb starts won't alter the
expected results of this test (i.e. recognizer index).
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Med Ismail Bennani [Fri, 7 Feb 2020 15:33:33 +0000 (16:33 +0100)]
[lldb/Target] Fix `frame recognizer list` crash when registered with nullptr
One way to register a recognizer is to use RegularExpressionSP for the
module and symbol.
In order to match a symbol regardless of the module, the recognizer can
be registered with a nullptr for the module. However, this cause the
frame recognizer list command to crash because it calls
RegularExpression::GetText without checking if the shared pointer is valid.
This patch adds checks for the symbol and module RegularExpressionSP.
Differential Revision: https://reviews.llvm.org/D74212
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Nuno Lopes [Fri, 7 Feb 2020 16:26:35 +0000 (16:26 +0000)]
[docs] update mathjax path in doxygen
Jinsong Ji [Thu, 6 Feb 2020 16:12:10 +0000 (16:12 +0000)]
[AsmPrinter] Print FP constant in hexadecimal form instead
Printing floating point number in decimal is inconvenient for humans.
Verbose asm output will print out floating point values in comments, it
helps.
But in lots of cases, users still need additional work to covert the
decimal back to hex or binary to check the bit patterns,
especially when there are small precision difference.
Hexadecimal form is one of the supported form in LLVM IR, and easier for
debugging.
This patch try to print all FP constant in hex form instead.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D73566
Miloš Stojanović [Fri, 7 Feb 2020 12:45:10 +0000 (13:45 +0100)]
[llvm-exegesis] Improve error reporting in BenchmarkRunner.cpp
Followup to D74085.
Replace the use of `report_fatal_error()` with returning the error to
`llvm-exegesis.cpp` and handling it there.
To facilitate this, a new `Error` type has been added which is only used
to log errors to the yaml output.
Differential Revision: https://reviews.llvm.org/D74215
Matt Arsenault [Sat, 1 Feb 2020 03:22:00 +0000 (22:22 -0500)]
AMDGPU/GlobalISel: Fix move s.buffer.load to VALU
We were executing this in a waterfall loop as a placeholder, but this
should really be converted to a MUBUF load. Also execute in a
waterfall loop if the resource isn't an SGPR. This is a case where the
DAG handling was wrong because doing the right thing was too hard.
Currently, this will mishandle 96-bit loads. There's currently no way
to track the original memory size with an MMO, so these loads will be
widened andd the resulting memory size will be 128-bits.
Simon Tatham [Fri, 7 Feb 2020 14:59:00 +0000 (14:59 +0000)]
[TableGen] Fix spurious type error in bit assignment.
Summary:
The following example gives the error message "expected value of type
'bits<32>', got 'bit'" on the assignment.
class Instruction { bits<32> encoding; }
def foo: Instruction { let encoding{10} = !eq(0, 1); }
But there's nothing wrong with this code: 'bit' is a perfectly good
type for the RHS of an assignment to a //single bit// of an
instruction encoding.
The problem is that `ParseBodyItem` is accidentally type-checking the
RHS against the full type of the `encoding` field, without adjusting
it in the case where we're only assigning to a subset of the bits. The
fix is trivial.
Reviewers: nhaehnle, hfinkel
Reviewed By: hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74220
Matt Arsenault [Fri, 7 Feb 2020 03:29:23 +0000 (22:29 -0500)]
GlobalISel: Fix narrowing of G_CTPOP
The result type is separate from the source type. Tests will be
included in a future AMDGPU patch which uses this from
RegBankSelect/applyMappingImpl.
Matt Arsenault [Fri, 7 Feb 2020 02:11:52 +0000 (21:11 -0500)]
GlobalISel: Fix lowering of G_CTLZ/G_CTTZ
The type passed to lower was invalid, so I'm not sure how this was
even working before. The source and destination type also do not have
to match, so make sure to use the right ones.
Alexandre Ganea [Fri, 7 Feb 2020 14:35:51 +0000 (09:35 -0500)]
Re-land "[Clang][Driver] Remove -M group options ..." and "[Clang] Avoid crashing when generating crash diagnostics when '#pragma clang __debug ..."
This re-lands commits
f41ec709d9d388dc43469e6ac7f51b6313f7e4af (https://reviews.llvm.org/D74076)
and commit
5fedc2b410853a6aef05e8edf19ebfc4e071e28f (https://reviews.llvm.org/D74070)
The previous build break was caused by '#pragma clang __debug llvm_unreachable' used in a non-assert build. Move it to a separate test in crash-report-with-asserts.c.
Alexey Bataev [Thu, 6 Feb 2020 21:30:23 +0000 (16:30 -0500)]
[OPENMP50]Add parsing/sema for acq_rel clause.
Added basic support (representation + parsing/sema/(de)serialization)
for acq_rel clause in flush/atomic directives.
Sam Parker [Fri, 7 Feb 2020 14:19:34 +0000 (14:19 +0000)]
[NFC][ARM] Update test
OuHangKresnik [Fri, 7 Feb 2020 14:18:55 +0000 (15:18 +0100)]
[mlir] Add NoSideEffect to Affine min max
Add NoSideEffect to Affine min and max operations.
Differential Revision: https://reviews.llvm.org/D74203
Nico Weber [Fri, 7 Feb 2020 13:38:12 +0000 (08:38 -0500)]
Revert "[LLD][ELF][ARM] Do not substitute BL/BLX for non STT_FUNC symbols."
There are still problems after the fix in
"[ELF][ARM] Fix regression of BL->BLX substitution after D73542"
so let's revert to get trunk back to green while we investigate.
See https://reviews.llvm.org/D73542
This reverts commit
5461fa2b1fcfcfcd8e28e3ac3383d2245d5d90bf.
This reverts commit
0b4a047bfbd11fe1f5abda8da0e2391c1918162a.
Sam Parker [Fri, 7 Feb 2020 13:31:45 +0000 (13:31 +0000)]
[NFC][ARM] Modified test with update script
LLVM GN Syncbot [Fri, 7 Feb 2020 13:35:48 +0000 (13:35 +0000)]
[gn build] Port
446268a2234
Miloš Stojanović [Thu, 6 Feb 2020 17:21:01 +0000 (18:21 +0100)]
Recommit: "[llvm-exegesis] Improve error reporting in Target.cpp"
Summary: Commit
141915963b6ab36ee4e577d1b27673fa4d05b409 was reverted in
abe01e17f648a97666d4fbed41f0861686a17972 because it broke builds testing
without libpfm. A preparatory commit <commit_sha1> was added to enable
this recommit.
Original commit message:
Followup to D74085.
Replace the use of `report_fatal_error()` with returning the error to
`llvm-exegesis.cpp` and handling it there.
Differential Revision: https://reviews.llvm.org/D74113
Miloš Stojanović [Thu, 6 Feb 2020 16:18:42 +0000 (17:18 +0100)]
Recommit: "[llvm-exegesis] Improve error reporting"
Summary: Commit
b3576f60ebc8f660afad8120a72473be47517573 was reverted in
abe01e17f648a97666d4fbed41f0861686a17972 because it broke builds testing
without libpfm. A preparatory commit <commit_sha1> was added to enable
this recommit.
Original commit message:
Fix inconsistencies in error reporting created by mixing
`report_fatal_error()` and `ExitOnErr()`, and add additional information
to the error message to make it more user friendly. Minimize the use
`report_fatal_error()` because it's meant for use in very rare cases and
it results in low information density of the error messages.
Summary of the new design:
* For command line argument errors output `llvm-exegesis: <error_message>`,
which is consistent with the error output format emitted by the backend
which checks correctness of the command line arguments.
* For other errors the format `llvm-exegesis error: <error_message>` is used.
** If the error occurred during file access `<error_message>` will have
of two parts: `'<file_name>': <rest_of_the_error_message>`
Differential Revision: https://reviews.llvm.org/D74085
Miloš Stojanović [Thu, 6 Feb 2020 16:08:05 +0000 (17:08 +0100)]
[llvm-exegesis] Add a custom error for clustering
All errors of type `Failure` are `StringError`s. In order for exit code
mapping to detect that specifically a clustering error has occurred it
needs to have a different type.
This patch also prepares D74085 where termination `report_fatal_error()`
will be replaced with emitting `StringError`s.
Differential Revision: https://reviews.llvm.org/D74124
Dmitry Preobrazhensky [Fri, 7 Feb 2020 13:20:37 +0000 (16:20 +0300)]
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- updated description of gfx906 and gfx908;
- added description of gfx1011 and gfx1012 subtargets.
Christian Sigg [Fri, 31 Jan 2020 11:19:36 +0000 (12:19 +0100)]
Rename prettyprinters test to llvm-support.
Summary: Make room for mlir-support pretty printers that I would like to add next.
Reviewers: dblaikie
Reviewed By: dblaikie
Subscribers: merge_guards_bot, mgorny, rriddle, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73726
Raphael Isemann [Fri, 7 Feb 2020 12:24:56 +0000 (13:24 +0100)]
[lldb] Improve error message when running static initializers in an expression fails
Momchil Velikov [Fri, 7 Feb 2020 11:38:46 +0000 (11:38 +0000)]
[AArch64] Predictably disassemble system registers with the same encoding
The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers,
defined by separate extension specifications (ETM and ETE,
respectively), yet they use the same encoding in MSR/MRS.
When performing a system register lookup by encoding, we would
essentially return a random one, depending on the number, relative
position in the TableGen file, whether the TableGen records for system
registers are named or not, and, if they are named, depending on
record (not register!) name as well.
This patch works around the issue by explictly checking for the
TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR.
Differential Revision: https://reviews.llvm.org/D74074
Anastasia Stulova [Thu, 6 Feb 2020 11:56:21 +0000 (11:56 +0000)]
[OpenCL] Restrict addr space conversions in nested pointers
Address space conversion changes pointer representation.
This commit disallows such conversions when they are not
legal i.e. for the nested pointers even with compatible
address spaces. Because the address space conversion in
the nested levels can't be generated to modify the pointers
correctly. The behavior implemented is as follows:
- Any implicit conversions of nested pointers with different
address spaces is rejected.
- Any conversion of address spaces in nested pointers in safe
casts (e.g. const_cast or static_cast) is rejected.
- Conversion in low level C-style or reinterpret_cast is accepted
but with a warning (this aligns with OpenCL C behavior).
Fixes PR39674
Differential Revision: https://reviews.llvm.org/D73360
Hans Wennborg [Fri, 7 Feb 2020 12:00:22 +0000 (13:00 +0100)]
clang-cl: Parse new MSVC flags /Qspectre-load and /Qspectre-load-cf
See https://github.com/MicrosoftDocs/cpp-docs/commit/
2fdf0ba0bf8d3875c754776ca1084654135cb710
Djordje Todorovic [Fri, 7 Feb 2020 11:37:29 +0000 (12:37 +0100)]
[llvm-dwarfdump][Stats] Add the license header
Add the License header into the Statistics.cpp.
Differential Revision: https://reviews.llvm.org/D74207
Florian Hahn [Fri, 7 Feb 2020 10:31:35 +0000 (10:31 +0000)]
[ValueTracking] usub(a, b) cannot overflow if a >= b.
If we know that a >= b (unsigned), usub.with.overflow(a, b) cannot
overflow. Similarly, if b > a, the same expression overflows.
Reviewers: nikic, RKSimon, lebedev.ri, spatel
Reviewed By: nikic, Gerolf
Differential Revision: https://reviews.llvm.org/D74066
Hans Wennborg [Fri, 7 Feb 2020 10:32:24 +0000 (11:32 +0100)]
Fix docs and comments for max_tokens_total pragma
serge-sans-paille [Fri, 7 Feb 2020 10:35:14 +0000 (11:35 +0100)]
Revert "Support -fstack-clash-protection for x86"
This reverts commit
39f50da2a357a8f685b3540246c5d762734e035f.
The -fstack-clash-protection is being passed to the linker too, which
is not intended.
Reverting and fixing that in a later commit.
Balázs Kéri [Fri, 7 Feb 2020 08:09:45 +0000 (09:09 +0100)]
[analyzer] Small StreamChecker refactoring (NFC).
Reviewers: Szelethus
Reviewed By: Szelethus
Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, donat.nagy, Charusso, dkrupp, Szelethus, gamesh411, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73350
Guillaume Chatelet [Tue, 4 Feb 2020 14:30:05 +0000 (15:30 +0100)]
[NFC] Introduce an API for MemOp
Summary: This patch introduces an API for MemOp in order to simplify and tighten the client code.
Reviewers: courbet
Subscribers: arsenm, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jsji, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73964
Florian Hahn [Wed, 5 Feb 2020 16:57:37 +0000 (16:57 +0000)]
[InstCombine] Precommit usub.with.overflow test for D74066.
Florian Hahn [Fri, 7 Feb 2020 10:08:40 +0000 (10:08 +0000)]
[ValueTracking] Update implied reasoning to accept expanded cmp (NFC).
This patch adds versions of isImpliedCondition and
isImpliedByDomCondition that take a predicate, LHS and RHS operands as
instead of a Value representing the condition.
This allows using those functions to check conditions without having a
concrete ICmp instruction.
Reviewers: nikic, RKSimon, lebedev.ri, spatel
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D74065
Raphael Isemann [Fri, 7 Feb 2020 10:24:38 +0000 (11:24 +0100)]
[lldb] Remove all 'clean' targets from test Makefiles
Summary:
To my knowledge we don't actually use or need these rules. And if we need them then
there is probably a better way to implement this than having all these random regexes.
Reviewers: labath, JDevlieghere
Reviewed By: labath, JDevlieghere
Subscribers: jingham, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D74126
Diogo Sampaio [Fri, 7 Feb 2020 10:03:59 +0000 (10:03 +0000)]
[ARM] Follow AACPS for preserving number of loads/stores of volatile bit-fields
Summary:
Following the AAPCS, every store to a volatile bit-field requires to generate one load of that field, even if all the bits are going to be replaced.
This patch allows the user to opt-in in following such rule, whenever the a.
AAPCS Release 2019Q1.1 (https://static.docs.arm.com/ihi0042/g/aapcs32.pdf)
section 8.1 Data Types, page 35, paragraph: Volatile bit-fields – preserving number and width of container accesses
```
When a volatile bit-field is written, and its container does not overlap with any non-bit-field member, its
container must be read exactly once and written exactly once using the access width appropriate to the
type of the container. The two accesses are not atomic.
```
Reviewers: lebedev.ri, ostannard, jfb, eli.friedman
Reviewed By: jfb
Subscribers: rsmith, rjmccall, dexonsmith, kristof.beyls, jfb, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67399
Pierre van Houtryve [Wed, 5 Feb 2020 16:31:03 +0000 (16:31 +0000)]
[ARM][ASMParser] Refuse equal RdHi/RdLo for s/umlal, smlsl, s/umull, umaal
Differential Revision: https://reviews.llvm.org/D74120
serge_sans_paille [Mon, 9 Sep 2019 14:59:34 +0000 (16:59 +0200)]
Support -fstack-clash-protection for x86
Implement protection against the stack clash attack [0] through inline stack
probing.
Probe stack allocation every PAGE_SIZE during frame lowering or dynamic
allocation to make sure the page guard, if any, is touched when touching the
stack, in a similar manner to GCC[1].
This extends the existing `probe-stack' mechanism with a special value `inline-asm'.
Technically the former uses function call before stack allocation while this
patch provides inlined stack probes and chunk allocation.
Only implemented for x86.
[0] https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt
[1] https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00556.html
Differential Revision: https://reviews.llvm.org/D68720
Pierre van Houtryve [Wed, 5 Feb 2020 12:27:46 +0000 (12:27 +0000)]
[Target][AArch64] Remove non-existing system registers ICH_VSEIR_EL2 & ICC_SEIEN_EL1 from AArch64 backend
Differential Revision: https://reviews.llvm.org/D74118
Hans Wennborg [Fri, 7 Feb 2020 08:54:05 +0000 (09:54 +0100)]
Fix the MC/WebAssembly/debug-info.ll test after 84e5760
Konrad Kleine [Fri, 7 Feb 2020 08:22:29 +0000 (09:22 +0100)]
[lldb] removed no longer needed CMakeDependentOption
Summary:
In D66791 I've introduced this [[ https://cmake.org/cmake/help/latest/module/CMakeDependentOption.html | `CMakeDependentOption` ]] but in
D71306 @JDevlieghere has changed the way optional dependencies
are handled in LLDB. Today there's no occurence of
`cmake_dependent_option` inside the lldb source tree.
That's why this include can be removed.
Reviewers: JDevlieghere, labath
Reviewed By: labath
Subscribers: labath, mgorny, lldb-commits, JDevlieghere
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D74160
Sourabh Singh Tomar [Fri, 7 Feb 2020 04:48:54 +0000 (10:18 +0530)]
[DebugInfo]: Reorderd the emission of debug_str section.
Summary:
This patch reorders the emission of debug_str section, so that
string can come after macros.
This is necessary for macro forms like DW_MACRO_define_strp,
which emits macro as a string in debug_str section.
Craig Topper [Fri, 7 Feb 2020 05:31:44 +0000 (21:31 -0800)]
[X86] Turn vXi1 any_extends into sign_extends in PreprocessISelDAG and remove some isel patterns.
Similar to what we do for other vector any_extends, but instead
of zero_extend we need to use sign_extend.
Craig Topper [Fri, 7 Feb 2020 03:29:03 +0000 (19:29 -0800)]
[X86] Use SelectionDAG::getAllOnesConstant to simplify some code. NFC
Jason Molenda [Fri, 7 Feb 2020 04:28:40 +0000 (20:28 -0800)]
Except, get the TARGET_OS_OSX check correct.
Jason Molenda [Fri, 7 Feb 2020 04:28:06 +0000 (20:28 -0800)]
Fix my use of the TARGET_OS_OSX TargetConditional.
Justin Lebar [Wed, 8 Jan 2020 05:16:36 +0000 (21:16 -0800)]
Clarify how llvm-mca detects att vs intel syntax.
Reviewers: andreadb
Subscribers: tschuett, gbedwell, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72385
Matt Arsenault [Fri, 7 Feb 2020 01:33:47 +0000 (20:33 -0500)]
AMDGPU/GlobalISel: Fix non-pow-2 add/sub/mul for 16-bit insts
These wouldn't legalize between 16-bits and 32-bits on targets with
16-bit instructions.
Douglas Yung [Fri, 7 Feb 2020 02:17:04 +0000 (18:17 -0800)]
Fix test after test changes added in da3dc00 caused the test to break
on platforms that default to an older C standard (like the PS4).
This should fix the test failure on the PS4 bots.
River Riddle [Fri, 7 Feb 2020 02:05:32 +0000 (18:05 -0800)]
[mlir][AsmPrinter] Fix edge case when printing floating point values.
Summary: In some edge cases the default APFloat printer will generate something that we can't parse back in. In these cases, fallback to using hex instead.
Differential Revision: https://reviews.llvm.org/D74181
Jordan Rupprecht [Fri, 7 Feb 2020 01:48:06 +0000 (17:48 -0800)]
Revert "[Clang][Driver] Remove -M group options ..." and "[Clang] Avoid crashing when generating crash diagnostics when '#pragma clang __debug ..."
This reverts commits
f41ec709d9d388dc43469e6ac7f51b6313f7e4af and
5fedc2b410853a6aef05e8edf19ebfc4e071e28f. On some buildbots, Clang :: Driver/crash-report.c is broken with:
```
Command Output (stderr):
--
/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm-project/clang/test/Driver/crash-report.c:48:11: error: CHECK: expected string not found in input
// CHECK: Preprocessed source(s) and associated run script(s) are located at:
^
<stdin>:1:1: note: scanning from here
/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm-project/clang/test/Driver/crash-report.c:50:1: error: unknown type name 'BAZ'
```
Example: http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/21321/steps/test-stage1-compiler/logs/stdio
River Riddle [Fri, 7 Feb 2020 01:55:14 +0000 (17:55 -0800)]
[mlir][DialectConversion] Change erroneous return to a continue
This fixes a nasty bug where the loop would return prematurely when
notifying the argument converter that an operation was removed.
Peter Collingbourne [Thu, 6 Feb 2020 19:18:23 +0000 (11:18 -0800)]
Update hwasan docs to cover outlined checks and globals.
Differential Revision: https://reviews.llvm.org/D74150
Stanislav Mekhanoshin [Thu, 6 Feb 2020 22:47:10 +0000 (14:47 -0800)]
[AMDGPU] Cleanup assumptions about generated subregs
We are using countPopulation on a LaneBitmask to determine
a number of registers it covers. This is the assumption which
does not necessarily need to be true. It is not changed but
factored into a single call SIRegisterInfo::getNumCoveredRegs().
Some other places are cleaned up with respect to assumptions
about subreg indexes values and tablegen behavior.
Differential Revision: https://reviews.llvm.org/D74177
Stanislav Mekhanoshin [Fri, 7 Feb 2020 01:38:55 +0000 (17:38 -0800)]
Revert "AMDGPU: Limit the search in finding the instruction pattern for v_swap generation."
This reverts commit
982780648124243131c6617c0d97fc1cb02d4e75.
Jason Molenda [Fri, 7 Feb 2020 01:27:56 +0000 (17:27 -0800)]
Add final description of why attach failed with poss error string.
Craig Topper [Fri, 7 Feb 2020 00:23:54 +0000 (16:23 -0800)]
Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement"
With REQUIRES: x86-register-target added to the tests.
Also remove some unneeded FIXMEs
But add a FIXME for bad IR generation for FMADDSUB/FMSUBADD with
constrained FP.
Original patch by Kevin P. Neal
Changpeng Fang [Fri, 7 Feb 2020 00:40:21 +0000 (16:40 -0800)]
AMDGPU: Limit the search in finding the instruction pattern for v_swap generation.
Summary:
Current implementation of matchSwap in SIShrinkInstructions searches the entire
use_nodbg_operands set to find the possible pattern to generate v_swap instruction.
This approach will lead to a O(N^3) in compile time for SIShrinkInstructions.
But in reality, the matching pattern only exists within nearby instructions in the
same basic block. This work limits the search to a maximum of 16 instructions, and has
a linear compile time comsumption.
Reviewers:
rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D74180
Richard Smith [Fri, 7 Feb 2020 00:19:37 +0000 (16:19 -0800)]
C++ DR2026: static storage duration variables are not zeroed before
constant initialization.
Removing this zeroing regressed our code generation in a few cases, also
fixed here. We now compute whether a variable has constant destruction
even if it doesn't have a constant initializer, by trying to destroy a
default-initialized value, and skip emitting a trivial default
constructor for a variable even if it has non-trivial (but perhaps
constant) destruction.
Jessica Paquette [Fri, 7 Feb 2020 00:30:13 +0000 (16:30 -0800)]
Revert "[AArch64][GlobalISel] Emit TBNZ with G_BRCOND where the condition is SLT"
This reverts commit
a3738414072900ace9cbbe209d0195a3443d1d54.
It looks like this broke set_shadow_test.c, so I'm reverting until I can fix it.
I also reverted the SGT change because it's probably also broken.
Jessica Paquette [Fri, 7 Feb 2020 00:29:00 +0000 (16:29 -0800)]
Revert "[AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1"
This reverts commit
d78cefb1601070cb028b61bbc1bd6f25a9c1837c.
One of this and the SLT change broke set_shadow_test.c, so I'm reverting until
I can fix it.