Richard Sandiford [Wed, 21 Sep 2016 16:11:52 +0000 (17:11 +0100)]
[AArch64] Print spaces after commas in addresses
I got an off-list request to make the AArch64 disassembler print
spaces after commas in addresses. This patch does that.
The same code is used to print operands in "did you mean" errors,
so to keep things consistent, the patch also prints spaces between
operands in those messages.
opcodes/
* aarch64-opc.c (print_immediate_offset_address): Print spaces
after commas in addresses.
(aarch64_print_operand): Likewise.
gas/
* config/tc-aarch64.c (print_operands): Print spaces between
operands.
* testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after ","
in addresses.
* testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
* testsuite/gas/aarch64/symbol.d: Likewise.
* testsuite/gas/aarch64/system.d: Likewise.
* testsuite/gas/aarch64/tls-desc.d: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Expect spaces after ","
in suggested alternatives.
* testsuite/gas/aarch64/verbose-error.l: Likewise.
ld/
* testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after ","
in addresses.
* testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-301.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-302.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-310.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-313.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-515.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-516.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-531.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-532.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-533.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-534.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-535.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-536.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-537.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-538.d: Likewise.
* testsuite/ld-aarch64/erratum835769.d: Likewise.
* testsuite/ld-aarch64/erratum843419.d: Likewise.
* testsuite/ld-aarch64/farcall-b-plt.d: Likewise.
* testsuite/ld-aarch64/farcall-bl-plt.d: Likewise.
* testsuite/ld-aarch64/gc-plt-relocs.d: Likewise.
* testsuite/ld-aarch64/ifunc-21.d: Likewise.
* testsuite/ld-aarch64/ifunc-7c.d: Likewise.
* testsuite/ld-aarch64/tls-desc-ie.d: Likewise.
* testsuite/ld-aarch64/tls-large-desc-be.d: Likewise.
* testsuite/ld-aarch64/tls-large-desc.d: Likewise.
* testsuite/ld-aarch64/tls-large-ie-be.d: Likewise.
* testsuite/ld-aarch64/tls-large-ie.d: Likewise.
* testsuite/ld-aarch64/tls-relax-all.d: Likewise.
* testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise.
* testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise.
* testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise.
* testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise.
* testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise.
* testsuite/ld-aarch64/tls-tiny-desc.d: Likewise.
* testsuite/ld-aarch64/tls-tiny-gd.d: Likewise.
Richard Sandiford [Wed, 21 Sep 2016 16:11:04 +0000 (17:11 +0100)]
[AArch64] Use "must" rather than "should" in error messages
One of the review comments from the SVE series was that it would
be better to use "must" rather than "should" in error messages.
I think this patch fixes all cases in the AArch64 code.
It also uses "must be" instead of "expected to be".
opcodes/
* aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
rather than "should be" or "expected to be" in error messages.
gas/
* config/tc-aarch64.c (output_operand_error_record): Use "must be"
rather than "should be" or "expected to be" in error messages.
(parse_operands): Likewise.
* testsuite/gas/aarch64/diagnostic.l: Likewise.
* testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Likewise.
* testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
Richard Sandiford [Wed, 21 Sep 2016 16:09:59 +0000 (17:09 +0100)]
[AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
Richard Sandiford [Wed, 21 Sep 2016 16:08:58 +0000 (17:08 +0100)]
Fix misplaced ChangeLog
Richard Sandiford [Wed, 21 Sep 2016 15:59:07 +0000 (16:59 +0100)]
[AArch64][SVE 32/32] Add SVE tests
This patch adds new tests for SVE. It also extends diagnostic.[sl] with
checks for some inappropriate uses of MUL and MUL VL in base AArch64
instructions.
gas/testsuite/
* gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for
invalid uses of MUL VL and MUL in base AArch64 instructions.
* gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s,
gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s,
gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l,
gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d,
gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s,
gas/aarch64/sve.d: New tests.
Richard Sandiford [Wed, 21 Sep 2016 15:58:48 +0000 (16:58 +0100)]
[AArch64][SVE 31/32] Add SVE instructions
This patch adds the SVE instruction definitions and associated OP_*
enum values.
include/
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
opcodes/
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
(OP_SVE_XWU, OP_SVE_XXU): New macros.
(aarch64_feature_sve): New variable.
(SVE): New macro.
(_SVE_INSN): Likewise.
(aarch64_opcode_table): Add SVE instructions.
* aarch64-opc.h (extract_fields): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.c (extract_fields): Make global.
(do_misc_decoding): Handle the new SVE aarch64_ops.
* aarch64-dis-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.
Richard Sandiford [Wed, 21 Sep 2016 15:58:22 +0000 (16:58 +0100)]
[AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding. Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.
include/
* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
(sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
(sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
aarch64_insn_classes.
opcodes/
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
* aarch64-asm.c (aarch64_get_variant): New function.
(aarch64_encode_variant_using_iclass): Likewise.
(aarch64_opcode_encode): Call it.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
(aarch64_opcode_decode): Call it.
Richard Sandiford [Wed, 21 Sep 2016 15:57:43 +0000 (16:57 +0100)]
[AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.
Richard Sandiford [Wed, 21 Sep 2016 15:57:22 +0000 (16:57 +0100)]
[AArch64][SVE 28/32] Add SVE FP immediate operands
This patch adds support for the new SVE floating-point immediate
operands. One operand uses the same 8-bit encoding as base AArch64,
but in a different position. The others use a single bit to select
between two values.
One of the single-bit operands is a choice between 0 and 1, where 0
is not a valid 8-bit encoding. I think the cleanest way of handling
these single-bit immediates is therefore to use the IEEE float encoding
itself as the immediate value and select between the two possible values
when encoding and decoding.
As described in the covering note for the patch that added F_STRICT,
we get better error messages by accepting unsuffixed vector registers
and leaving the qualifier matching code to report an error. This means
that we carry on parsing the other operands, and so can try to parse FP
immediates for invalid instructions like:
fcpy z0, #2.5
In this case there is no suffix to tell us whether the immediate should
be treated as single or double precision. Again, we get better error
messages by picking one (arbitrary) immediate size and reporting an error
for the missing suffix later.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
immediate operands.
* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
* aarch64-opc.c (fields): Add corresponding entry.
(operand_general_constraint_met_p): Handle the new SVE FP immediate
operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
(ins_sve_float_zero_one): New inserters.
* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
(aarch64_ins_sve_float_half_two): Likewise.
(aarch64_ins_sve_float_zero_one): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
(ext_sve_float_zero_one): New extractors.
* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
(aarch64_ext_sve_float_half_two): Likewise.
(aarch64_ext_sve_float_zero_one): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (double_precision_operand_p): New function.
(parse_operands): Use it to calculate the dp_p input to
parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
Richard Sandiford [Wed, 21 Sep 2016 15:56:57 +0000 (16:56 +0100)]
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
Richard Sandiford [Wed, 21 Sep 2016 15:56:15 +0000 (16:56 +0100)]
[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:
[<base>, #<offset>, MUL VL]
This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.
For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
Richard Sandiford [Wed, 21 Sep 2016 15:55:49 +0000 (16:55 +0100)]
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
Richard Sandiford [Wed, 21 Sep 2016 15:55:22 +0000 (16:55 +0100)]
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
Richard Sandiford [Wed, 21 Sep 2016 15:54:53 +0000 (16:54 +0100)]
[AArch64][SVE 23/32] Add SVE pattern and prfop operands
The SVE instructions have two enumerated operands: one to select a
vector pattern and another to select a prefetch operation. The latter
is a cut-down version of the base AArch64 prefetch operation.
Both types of operand can also be specified as raw enum values such as #31.
Reserved values can only be specified this way.
If it hadn't been for the pattern operand, I would have been tempted
to use the existing parsing for prefetch operations and add extra
checks for SVE. However, since the patterns needed new enum parsing
code anyway, it seeemed cleaner to reuse it for the prefetches too.
Because of the small number of enum values, I don't think we'd gain
anything by using hash tables.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
(AARCH64_OPND_SVE_PRFOP): Likewise.
(aarch64_sve_pattern_array): Declare.
(aarch64_sve_prfop_array): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
* aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
(FLD_SVE_prfop): Likewise.
* aarch64-opc.c: Include libiberty.h.
(aarch64_sve_pattern_array): New variable.
(aarch64_sve_prfop_array): Likewise.
(fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_enum_string): New function.
(po_enum_or_fail): New macro.
(parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.
Richard Sandiford [Wed, 21 Sep 2016 15:54:30 +0000 (16:54 +0100)]
[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication
This patch adds qualifiers to represent /z and /m suffixes on
predicate registers.
include/
* opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
(AARCH64_OPND_QLF_P_M): Likewise.
opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
AARCH64_OPND_QLF_P_[ZM].
(aarch64_print_operand): Print /z and /m where appropriate.
gas/
* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
(parse_vector_type_for_operand): Assert that the skipped character
is a '.'.
(parse_predication_for_operand): New function.
(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
(vectype_to_qualifier): Handle NT_zero and NT_merge.
Richard Sandiford [Wed, 21 Sep 2016 15:53:54 +0000 (16:53 +0100)]
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
Richard Sandiford [Wed, 21 Sep 2016 15:52:30 +0000 (16:52 +0100)]
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
Richard Sandiford [Wed, 21 Sep 2016 15:51:43 +0000 (16:51 +0100)]
[AArch64][SVE 19/32] Refactor address-printing code
SVE adds addresses in which the base or offset are vector registers.
The addresses otherwise have the same kind of form as normal AArch64
addresses, including things like SXTW with or without a shift, UXTW
with or without a shift, and LSL.
This patch therefore refactors the address-printing code so that it
can cope with both scalar and vector registers.
opcodes/
* aarch64-opc.c (get_offset_int_reg_name): New function.
(print_immediate_offset_address): Likewise.
(print_register_offset_address): Take the base and offset
registers as parameters.
(aarch64_print_operand): Update caller accordingly. Use
print_immediate_offset_address.
Richard Sandiford [Wed, 21 Sep 2016 15:51:37 +0000 (16:51 +0100)]
[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg
Use a macro to define 31 regular registers followed by a supplied
value for 0b11111. The SVE code will also use this for vector base
and offset registers.
opcodes/
* aarch64-opc.c (BANK): New macro.
(R32, R64): Take a register number as argument
(int_reg): Use BANK.
Richard Sandiford [Wed, 21 Sep 2016 15:51:30 +0000 (16:51 +0100)]
[AArch64][SVE 17/32] Add a prefix parameter to print_register_list
This patch generalises the interface to print_register_list so
that it can print register lists involving SVE z registers as
well as AdvSIMD v ones.
opcodes/
* aarch64-opc.c (print_register_list): Add a prefix parameter.
(aarch64_print_operand): Update accordingly.
Richard Sandiford [Wed, 21 Sep 2016 15:51:24 +0000 (16:51 +0100)]
[AArch64][SVE 16/32] Use specific insert/extract methods for fpimm
FPIMM used the normal "imm" insert/extract methods, with a specific
test for FPIMM in the extract method. SVE needs to use the same
extractors, so rather than add extra checks for specific operand types,
it seemed cleaner to use a separate insert/extract method.
opcodes/
* aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
for FPIMM.
* aarch64-asm.h (ins_fpimm): New inserter.
* aarch64-asm.c (aarch64_ins_fpimm): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_fpimm): New extractor.
* aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
(aarch64_ext_fpimm): New function.
* aarch64-dis-2.c: Regenerate.
Richard Sandiford [Wed, 21 Sep 2016 15:51:16 +0000 (16:51 +0100)]
[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers
Several of the SVE operands use the aarch64_operand fields array
to store the fields that make up the operand, rather than hard-coding
the names in the C code. This patch adds helpers for inserting and
extracting those fields.
opcodes/
* aarch64-asm.c: Include libiberty.h.
(insert_fields): New function.
(aarch64_ins_imm): Use it.
* aarch64-dis.c (extract_fields): New function.
(aarch64_ext_imm): Use it.
Richard Sandiford [Wed, 21 Sep 2016 15:51:09 +0000 (16:51 +0100)]
[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size
SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit
elements, treating them as aliases of operations on 64-bit elements in
which the immediate is replicated. This patch therefore replaces the
"32-bit/64-bit" input to aarch64_logical_immediate_p with a more
general "number of bytes" input.
opcodes/
* aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
with an esize parameter.
(operand_general_constraint_met_p): Update accordingly.
Fix misindented code.
* aarch64-asm.c (aarch64_ins_limm): Update call to
aarch64_logical_immediate_p.
Richard Sandiford [Wed, 21 Sep 2016 15:51:00 +0000 (16:51 +0100)]
[AArch64][SVE 13/32] Add an F_STRICT flag
SVE predicate operands can appear in three forms:
1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"
No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped. Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing". This means that some Pg operands have
suffixes and others don't.
It would be possible to use context-sensitive parsing to handle
this difference. The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.
However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier. The normal qualifier matching code can then report cases
where the wrong kind of suffix is used. This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.
The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here. It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.
This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions. The behaviour
for other instructions doesn't change.
include/
* opcode/aarch64.h (F_STRICT): New flag.
opcodes/
* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
gas/
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
instruction with all-NIL qualifiers to fail to match.
Richard Sandiford [Wed, 21 Sep 2016 15:49:31 +0000 (16:49 +0100)]
[AArch64][SVE 12/32] Remove boolean parameters from parse_address_main
In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main. I think we
can just get rid of them and leave the callers to check the addressing
modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).
The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks. This again creates a corner case where:
.equ x2, 1
ldr w0, [x1], x2
was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.
Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.
ADDR_SIMM9_2 appers to be unused. I'll send a separate patch
to remove it.
This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.
gas/
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters. Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Richard Sandiford [Wed, 21 Sep 2016 15:49:24 +0000 (16:49 +0100)]
[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface
aarch64_reg_parse_32_64 is currently used to parse address registers,
among other things. It returns two bits of information about the
register: whether it's W rather than X, and whether it's a zero register.
SVE adds addressing modes in which the base or offset can be a vector
register instead of a scalar, so a choice between W and X is no longer
enough. It's more convenient to pass the type of register around as
a qualifier instead.
As it happens, two callers of aarch64_reg_parse_32_64 already wanted
the information in the form of a qualifier, so the change feels pretty
natural even without SVE.
Also, the function took two parameters to control whether {W}SP
and (W|X)ZR should be accepted. We tend to get slightly better
error messages by accepting them regardless and getting the caller
to do the check, rather than potentially treating "xzr", "sp" etc.
as constants. This is easier to do if the function returns the
reg_entry rather than just the register number.
This does create a corner case where:
.equ sp, 1
ldr w0, [x0, sp]
was previously an acceptable way of writing "ldr w0, [x0, #1]",
but I don't think it's important to continue supporting that.
We already rejected things like:
.equ sp, 1
add x0, x1, sp
To ensure these new error messages "win" when matching against
several candidate instruction entries, we need to use the same
address-parsing code for all addresses, including ADDR_SIMPLE
and SIMD_ADDR_SIMPLE. The next patch also relies on this.
Finally, aarcch64_check_reg_type was written in a pretty
conservative way. It should always be equivalent to a single
bit test.
gas/
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
types.
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
(aarch64_check_reg_type): Simplify.
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
register number. Return the type as a qualifier rather than an
"isreg32" boolean. Remove reject_sp, reject_rz and isregzero
parameters.
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
Use get_reg_expected_msg.
(parse_address_main): Likewise. Use aarch64_check_reg_type.
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
Use aarch64_check_reg_type to test the result.
(parse_operands): Update after the above changes. Parse ADDR_SIMPLE
addresses normally before enforcing the syntax restrictions.
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
zero register and for a stack pointer index.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Also update existing diagnostic messages after the above changes.
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
for 32-bit register bases.
Richard Sandiford [Wed, 21 Sep 2016 15:49:15 +0000 (16:49 +0100)]
[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float
Since some SVE constants are no longer explicitly tied to the 8-bit
FP immediate format, it seems better to move the range checks out of
parse_aarch64_imm_float and into the callers.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
(parse_operands): Check the range of 8-bit FP immediates here instead.
Richard Sandiford [Wed, 21 Sep 2016 15:49:07 +0000 (16:49 +0100)]
[AArch64][SVE 09/32] Improve error messages for invalid floats
Previously:
fmov d0, #2
would give an error:
Operand 2 should be an integer register
whereas the user probably just forgot to add the ".0" to make:
fmov d0, #2.0
This patch reports an invalid floating point constant unless the
operand is obviously a register.
The FPIMM8 handling is only relevant for SVE. Without it:
fmov z0, z1
would try to parse z1 as an integer immediate zero (the res2 path),
whereas it's more likely that the user forgot the predicate. This is
tested by the final patch.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
low-severity error for registers.
(parse_operands): Report an invalid floating point constant for
if parsing an FPIMM8 fails, and if no better error has been
recorded.
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
to FMOV.
Richard Sandiford [Wed, 21 Sep 2016 15:48:59 +0000 (16:48 +0100)]
[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable
SVE has single-bit floating-point constants that don't really
have any relation to the AArch64 8-bit floating-point encoding.
(E.g. one of the constants selects between 0 and 1.) The easiest
way of representing them in the aarch64_opnd_info seemed to be
to use the IEEE float representation directly, rather than invent
some new scheme.
This patch paves the way for that by making the code that converts IEEE
doubles to IEEE floats accept any value in the range of an IEEE float,
not just zero and 8-bit floats. It leaves the range checking to the
caller (which already handles it).
gas/
* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
to...
(can_convert_double_to_float): ...this. Accept any double-precision
value that converts to single precision without loss of precision.
(parse_aarch64_imm_float): Update accordingly.
Richard Sandiford [Wed, 21 Sep 2016 15:48:50 +0000 (16:48 +0100)]
[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V
To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:
.equ x0, 0
add v0.4s, v0.4s, x0
An explicit '#' must be used instead:
.equ x0, 0
add v0.4s, v0.4s, #x0
Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time. For backwards
compatibility, we should continue to allow things like:
.equ p0, 0
add v0.4s, v0.4s, p0
even though p0 is now an SVE register.
However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable. Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.
As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject. This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.
gas/
* config/tc-aarch64.c (parse_immediate_expression): Add a
reg_type parameter.
(parse_constant_immediate): Likewise, and update calls.
(parse_aarch64_imm_float): Likewise.
(parse_big_immediate): Likewise.
(po_imm_nc_or_fail): Update accordingly, passing down a new
imm_reg_type variable.
(po_imm_of_fail): Likewise.
(parse_operands): Likewise.
Richard Sandiford [Wed, 21 Sep 2016 15:48:41 +0000 (16:48 +0100)]
[AArch64][SVE 06/32] Generalise parse_neon_reg_list
Rename parse_neon_reg_list to parse_vector_reg_list and take
in the required register type as an argument. Later patches
will reuse the function for SVE registers.
gas/
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
(parse_vector_reg_list): ...this and take a register type
as input.
(parse_operands): Update accordingly.
Richard Sandiford [Wed, 21 Sep 2016 15:48:34 +0000 (16:48 +0100)]
[AArch64][SVE 05/32] Rename parse_neon_type_for_operand
Generalise the name of parse_neon_type_for_operand to
parse_vector_type_for_operand. Later patches will add SVEisms to it.
gas/
* config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
(parse_vector_type_for_operand): ...this.
(parse_typed_reg): Update accordingly.
Richard Sandiford [Wed, 21 Sep 2016 15:48:25 +0000 (16:48 +0100)]
[AArch64][SVE 04/32] Rename neon_type_el to vector_type_el
Similar to the previous patch, but this time for the neon_type_el
structure.
gas/
* config/tc-aarch64.c (neon_type_el): Rename to...
(vector_type_el): ...this.
(parse_neon_type_for_operand): Update accordingly.
(parse_typed_reg): Likewise.
(aarch64_reg_parse): Likewise.
(vectype_to_qualifier): Likewise.
(parse_operands): Likewise.
(eq_neon_type_el): Likewise. Rename to...
(eq_vector_type_el): ...this.
(parse_neon_reg_list): Update accordingly.
Richard Sandiford [Wed, 21 Sep 2016 15:48:16 +0000 (16:48 +0100)]
[AArch64][SVE 03/32] Rename neon_el_type to vector_el_type
Later patches will add SVEisms to neon_el_type, so this patch renames
it to something more generic.
gas/
* config/tc-aarch64.c (neon_el_type: Rename to...
(vector_el_type): ...this.
(neon_type_el): Update accordingly.
(parse_neon_type_for_operand): Likewise.
(vectype_to_qualifier): Likewise.
Richard Sandiford [Wed, 21 Sep 2016 15:48:06 +0000 (16:48 +0100)]
[AArch64][SVE 02/32] Avoid hard-coded limit in indented_print
The maximum indentation needed by aarch64-gen.c grows as more
instructions are added to aarch64-tbl.h. Rather than having to
increase the indentation limit to a higher value, it seemed better
to replace it with "%*s".
opcodes/
* aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
Richard Sandiford [Wed, 21 Sep 2016 15:47:57 +0000 (16:47 +0100)]
[AArch64][SVE 01/32] Remove parse_neon_operand_type
A false return from parse_neon_operand_type had an overloaded
meaning: either the parsing failed, or there was nothing to parse
(which isn't necessarily an error). The only caller, parse_typed_reg,
would therefore not consume the suffix if it was invalid but instead
(successfully) parse the register without a suffix. It would still
leave inst.parsing_error with an error about the invalid suffix.
It seems wrong for a successful parse to leave an error message,
so this patch makes parse_typed_reg return PARSE_FAIL instead.
The patch doesn't seem to make much difference in practice.
Most possible follow-on errors use set_first_error and so the
error about the suffix tended to win despite the successful parse.
gas/
* config/tc-aarch64.c (parse_neon_operand_type): Delete.
(parse_typed_reg): Call parse_neon_type_for_operand directly.
Maciej W. Rozycki [Wed, 21 Sep 2016 11:55:25 +0000 (12:55 +0100)]
MIPS/testsuite: mips16-thunks: Use `standard_output_file'
Correct a commit
2151ccc56c74 ("Always organize test artifacts in a
directory hierarchy") regression causing:
Running .../gdb/testsuite/gdb.arch/mips16-thunks.exp ...
gdb compile failed, Assembler messages:
Fatal error: can't create .../gdb/testsuite/gdb.arch/mips16-thunks-inmain.o: No such file or directory
gdb compile failed, Assembler messages:
Fatal error: can't create .../gdb/testsuite/gdb.arch/mips16-thunks-main.o: No such file or directory
gdb compile failed, mips-mti-linux-gnu-gcc: error: .../gdb/testsuite/gdb.arch/mips16-thunks-inmain.o: No such file or directory
mips-mti-linux-gnu-gcc: error: .../gdb/testsuite/gdb.arch/mips16-thunks-main.o: No such file or directory
UNSUPPORTED: gdb.arch/mips16-thunks.exp: No MIPS16 support in the toolchain.
by using `standard_output_file' to construct output file names
throughout.
gdb/testsuite/
* gdb.arch/mips16-thunks.exp: Use `standard_output_file'
throughout.
Yao Qi [Fri, 16 Sep 2016 13:58:31 +0000 (14:58 +0100)]
Keep reserved bits in CPSR on write
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html
I cleared reserved bits when reading CPSR. It makes a problem that
these bits (zero) are written back to kernel through ptrace, and it
changes the state of the processor on some recent kernel, which is
unexpected.
In this patch, I keep these reserved bits when write CPSR back to
hardware.
gdb:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
bits 20 to 23.
gdb/gdbserver:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
23.
GDB Administrator [Wed, 21 Sep 2016 00:00:18 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Thu, 21 Jul 2016 19:41:54 +0000 (13:41 -0600)]
Avoid -Wduplicated-cond warnings in gdb/python
I tried building gdb with -Wduplicated-cond. This patch fixes the
simpler issue that was found.
In Python 3, "int" and "long" are synonyms, so code like:
else if (PyLong_Check (obj))
...
else if (PyInt_Check (obj))
.... will trigger this warning. The fix is to conditionalize the
PyInt_Check branches on Python 2.
Tested by rebuilding, with both version of Python, on x86-64 Fedora 24.
2016-09-20 Tom Tromey <tom@tromey.com>
* python/py-value.c (convert_value_from_python): Make PyInt_Check
conditional on Python 2.
* python/py-arch.c (archpy_disassemble): Make PyInt_Check
conditional on Python 2.
Edjunior Barbosa Machado [Tue, 20 Sep 2016 15:24:30 +0000 (12:24 -0300)]
ppc: Fix record support of Store String Word instructions
gdb/ChangeLog
2016-09-20 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
* rs6000-tdep.c (ppc_process_record_op31): Fix record of Store String
Word instructions.
Andrew Burgess [Tue, 20 Sep 2016 14:33:50 +0000 (15:33 +0100)]
ld: Fix mistake in ChangeLog
The previous commit contained a small mistake in the ChangeLog, fixed in
this commit.
Andrew Burgess [Tue, 20 Sep 2016 09:49:39 +0000 (10:49 +0100)]
ld: Extend documentation for EXCLUDE_FILE
There was a gap in the documentation of EXCLUDE_FILE that could cause
confusion to a user. When writing an input section specifier like this:
*(EXCLUDE_FILE (somefile.o) .text .text.*)
this could mean one of the following:
1. All '.text' and '.text.*' from all files except for 'somefile.o',
or
2. All '.text' from all files except 'somefile.o', and all '.text.*'
sections from all files.
It turns out that the second interpretation is correct, but the manual
does not make this clear (to me at least). Hopefully this patch makes
things clearer.
ld/ChangeLog:
* ld/ld.texinfo (Input Section Basics): Expand the description of
EXCLUDE_FILE.
Sergio Durigan Junior [Mon, 19 Sep 2016 21:00:22 +0000 (17:00 -0400)]
Use 'event_ptid' instead of 'resume_ptid' on startup_inferior (fix for regression on my last commit)
Pedro pointed out a regression happening on gdb.mi/mi-exec-run.exp,
and as it turned out, this was a thinko when dealing with some events
on startup_inferior. Basically, one needs to pass 'event_ptid' to
target_mourn_inferior, but I mistakenly passed 'resume_ptid'.
This commit fixes it.
Built and regtested on BuildBot, now with fixed e-mail notifications!
gdb/ChangeLog:
2016-09-20 Sergio Durigan Junior <sergiodj@redhat.com>
* fork-inferior.c (startup_inferior): Pass 'event_ptid' instead of
'resume_ptid' to 'target_mourn_inferior'. Fix regression
introduced by my last commit.
GDB Administrator [Tue, 20 Sep 2016 00:00:23 +0000 (00:00 +0000)]
Automatic date update in version.in
Pedro Alves [Mon, 19 Sep 2016 15:55:35 +0000 (16:55 +0100)]
gdb: Fix build breakage with GCC 4.1 and --disable-nls
Ref: https://sourceware.org/ml/gdb-patches/2016-09/msg00203.html
The std::{min,max} patch caused build failures when configuring GDB
with with --disable-nls and using GCC 4.1.
The reason is this bit in common/gdb_locale.h:
#ifdef ENABLE_NLS
...
#else
# define gettext(Msgid) (Msgid)
...
#endif
This causes problems if the <libintl.h> header is first included at
any point after "gdb_locale.h".
Specifically, the gettext&co declarations in libintl.h:
extern char *gettext (__const char *__msgid)
__THROW __attribute_format_arg__ (1);
end up broken after preprocessing:
extern char *(__const char *__msgid)
throw () __attribute__ ((__format_arg__ (1)));
After the std::min/std::max change to include <algorithm>, this now
happens with at least the GCC 4.1 copy of <algorithm>, which includes
<libintl.h> via <bits/stl_algobase.h>, <iosfwd>, and
<bits/c++locale.h>.
The fix is to simply remove the troublesome *gettext and *textdomain
macros, leaving only the _ and N_ ones.
gdb/ChangeLog:
2016-09-19 Pedro Alves <palves@redhat.com>
* common/gdb_locale.h [!ENABLE_NLS] (gettext, dgettext, dcgettext,
textdomain, bindtextdomain): Delete macros.
* main.c (captured_main) [!ENABLE_NLS]: Skip bintextdomain and
textdomain calls.
Jose E. Marchesi [Mon, 19 Sep 2016 12:19:14 +0000 (05:19 -0700)]
bfd: allow negative offsets to _GLOBAL_OFFSET_TABLE_ in elf64 SPARC
The code compiled with the -fpic model in SPARC uses 13-bit signed
immediate PC-relative loads to fetch entries from the GOT table. In
theory this would allow using a GOT table (.got section) containing up
to 1024 entries in elf32 or 512 entries in elf64.
However, in elf64 sparc GNU targets _GLOBAL_OFFSET_TABLE_ is always
placed at the beginning of the .got section, making it impossible to use
negative offsets. This limits the usage of -fpic to GOT tables
containing a maximum of 257 entries in elf64.
This patch activates an optimization that is already used in sparc-elf32
also in sparc-elf64, that sets _GLOBAL_OFFSET_TABLE_ to point 0x1000
into the .got section if the section size is bigger than 0x1000.
2016-09-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Allow
negative offsets to _GLOBAL_OFFSET_TABLE_ if the .got section is
bigger than 0x1000 bytes.
Alan Modra [Fri, 16 Sep 2016 14:58:05 +0000 (00:28 +0930)]
nm handling of synthetic symbols
Symbol sorting means we can't assume that the last n symbols are
synthetic.
* nm.c (print_symbol): Remove is_synthetic param. Test sym->flags
instead.
(print_size_symbols, print_symbols): Adjust to suit, deleting
now unused synth_count param and fromsynth var.
(display_rel_file): Adjust, localizing synth_count.
Sergio Durigan Junior [Mon, 12 Sep 2016 03:45:31 +0000 (23:45 -0400)]
Consolidate target_mourn_inferior between GDB and gdbserver
This patch consolidates the API of target_mourn_inferior between GDB
and gdbserver, in my continuing efforts to make sharing the
fork_inferior function possible between both.
GDB's version of the function did not care about the inferior's ptid
being mourned, but gdbserver's needed to know this information. Since
it actually makes sense to pass the ptid as an argument, instead of
depending on a global value directly (which GDB's version did), I
decided to make the generic API to accept it. I then went on and
extended all calls being made on GDB to include a ptid argument (which
ended up being inferior_ptid most of the times, anyway), and now we
have a more sane interface.
On GDB's side, after talking to Pedro a bit about it, we decided that
just an assertion to make sure that the ptid being passed is equal to
inferior_ptid would be enough for now, on the GDB side. We can remove
the assertion and perform more operations later if we ever pass
anything different than inferior_ptid.
Regression tested on our BuildBot, everything OK.
I'd appreciate a special look at gdb/windows-nat.c's modification
because I wasn't really sure what to do there. It seemed to me that
maybe I should build a ptid out of the process information there, but
then I am almost sure the assertion on GDB's side would trigger.
gdb/ChangeLog:
2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com>
* darwin-nat.c (darwin_kill_inferior): Adjusting call to
target_mourn_inferior to include ptid_t argument.
* fork-child.c (startup_inferior): Likewise.
* gnu-nat.c (gnu_kill_inferior): Likewise.
* inf-ptrace.c (inf_ptrace_kill): Likewise.
* infrun.c (handle_inferior_event_1): Likewise.
* linux-nat.c (linux_nat_attach): Likewise.
(linux_nat_kill): Likewise.
* nto-procfs.c (interrupt_query): Likewise.
(procfs_interrupt): Likewise.
(procfs_kill_inferior): Likewise.
* procfs.c (procfs_kill_inferior): Likewise.
* record.c (record_mourn_inferior): Likewise.
* remote-sim.c (gdbsim_kill): Likewise.
* remote.c (remote_detach_1): Likewise.
(remote_kill): Likewise.
* target.c (target_mourn_inferior): Change declaration to accept
new ptid_t argument; use gdb_assert on it.
* target.h (target_mourn_inferior): Move function prototype from
here...
* target/target.h (target_mourn_inferior): ... to here. Adjust it
to accept new ptid_t argument.
* windows-nat.c (get_windows_debug_event): Adjusting call to
target_mourn_inferior to include ptid_t argument.
gdb/gdbserver/ChangeLog:
2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com>
* server.c (start_inferior): Call target_mourn_inferior instead of
mourn_inferior; pass ptid_t argument to it.
(resume): Likewise.
(handle_target_event): Likewise.
* target.c (target_mourn_inferior): New function.
* target.h (mourn_inferior): Delete macro.
GDB Administrator [Mon, 19 Sep 2016 00:00:21 +0000 (00:00 +0000)]
Automatic date update in version.in
Pedro Alves [Sun, 18 Sep 2016 23:30:30 +0000 (00:30 +0100)]
gdb/s390: Fix build breakage due to std::min/std::max usage without header
[...]
.../gdb/s390-linux-nat.c: In function 'void s390_prepare_to_resume(lwp_info*)':
.../gdb/s390-linux-nat.c:703:20: error: 'min' is not a member of 'std'
watch_lo_addr = std::min (watch_lo_addr, area->lo_addr);
[...]
gdb/ChangeLog:
2016-09-18 Pedro Alves <palves@redhat.com>
* s390-linux-nat.c: Include <algorithm>.
Pedro Alves [Sun, 18 Sep 2016 22:56:01 +0000 (23:56 +0100)]
gdb: Fix std::{min, max}-related build breakage on 32-bit hosts
Building on a 32-bit host fails currently with errors like:
.../src/gdb/exec.c: In function ‘target_xfer_status section_table_read_available_memory(gdb_byte*, ULONGEST, ULONGEST, ULONGEST*)’:
.../src/gdb/exec.c:801:54: error: no matching function for call to ‘min(ULONGEST, long unsigned int)’
end = std::min (offset + len, r->start + r->length);
^
In file included from /usr/include/c++/5.3.1/algorithm:61:0,
from .../src/gdb/exec.c:46:
/usr/include/c++/5.3.1/bits/stl_algobase.h:195:5: note: candidate: template<class _Tp> const _Tp& std::min(const _Tp&, const _Tp&)
min(const _Tp& __a, const _Tp& __b)
^
/usr/include/c++/5.3.1/bits/stl_algobase.h:195:5: note: template argument deduction/substitution failed:
.../src/gdb/exec.c:801:54: note: deduced conflicting types for parameter ‘const _Tp’ (‘long long unsigned int’ and ‘long unsigned int’)
end = std::min (offset + len, r->start + r->length);
^
In file included from /usr/include/c++/5.3.1/algorithm:61:0,
from .../src/gdb/exec.c:46:
/usr/include/c++/5.3.1/bits/stl_algobase.h:243:5: note: candidate: template<class _Tp, class _Compare> const _Tp& std::min(const _Tp&, const _Tp&, _Compare)
min(const _Tp& __a, const _Tp& __b, _Compare __comp)
^
The problem is that the std::min/std::max function templates use the
same type for both parameters. When the argument types are different,
the compiler can't automatically deduce which template specialization
to pick from the arguments' types.
Fix that by specifying the specialization we want explicitly.
gdb/ChangeLog:
2016-09-18 Pedro Alves <palves@redhat.com>
* breakpoint.c (hardware_watchpoint_inserted_in_range): Explicitly
specify the std:min/std::max specialization.
* exec.c (section_table_read_available_memory): Likewise.
* remote.c (remote_read_qxfer): Likewise.
* target.c (simple_verify_memory): Likewise.
GDB Administrator [Sun, 18 Sep 2016 00:00:23 +0000 (00:00 +0000)]
Automatic date update in version.in
Eli Zaretskii [Sat, 17 Sep 2016 08:50:37 +0000 (11:50 +0300)]
Improve MinGW support in Readline
These changes were already accepted upstream in Readline,
but GDB did not yet import a newer Readline version.
readline/Changelog.gdb:
* util.c: Include rlshell.h.
(_rl_tropen) [_WIN32 && !__CYGWIN__]: Open the trace file in the
user's temporary directory.
* tcap.h [HAVE_NCURSES_TERMCAP_H]: Include ncurses/termcap.h.
* input.c (w32_isatty) [_WIN32 && !__CYGWIN__]: New function, to
replace isatty that is not reliable enough on MS-Windows.
(isatty) [_WIN32 && !__CYGWIN__]: Redirect to w32_isatty.
(rl_getc): Call _getch, not getch, which could be an ncurses
function when linked with ncurses, in which case getch will return
EOF for any keystroke, because there's no curses window.
* tilde.c (tilde_expand_word) [_WIN32]:
* histfile.c (history_filename) [_WIN32]: Windows-specific
environment variable to replace HOME if that is undefined.
* funmap.c (default_funmap): Compile rl_paste_from_clipboard on
all Windows platforms, not just Cygwin.
* readline.h (rl_paste_from_clipboard): Include declaration for
all Windows platforms.
* display.c (insert_some_chars, delete_chars): Don't use the
MinGW-specific code if linked with ncurses.
* configure.in:
* config.h.in: Support ncurses/termcap.h. The configure script
was updated accordingly.
* complete.c [_WIN32 && !__CYGWIN__]: Initialize
_rl_completion_case_fold to 1.
(printable_part, rl_filename_completion_function)
[_WIN32 && !__CYGWIN__]: Handle the drive letter.
GDB Administrator [Sat, 17 Sep 2016 00:00:23 +0000 (00:00 +0000)]
Automatic date update in version.in
Simon Marchi [Fri, 16 Sep 2016 19:44:29 +0000 (15:44 -0400)]
Introduce cleanup to restore current_uiout
Make a globally available cleanup from a pre-existing one in infrun.c.
This is used in a following patch.
gdb/ChangeLog:
* infrun.c (restore_current_uiout_cleanup): Move to ui-out.c.
(print_stop_event): Use make_cleanup_restore_current_uiout.
* python/python.c (execute_gdb_command): Likewise.
* ui-out.c (restore_current_uiout_cleanup): Move from infrun.c.
(make_cleanup_restore_current_uiout): New function definition.
* ui-out.h (make_cleanup_restore_current_uiout): New function
declaration.
* utils.c (do_restore_ui_out): Remove.
(make_cleanup_restore_ui_out): Remove.
* utils.h (make_cleanup_restore_ui_out): Remove.
Pedro Alves [Fri, 16 Sep 2016 18:55:17 +0000 (19:55 +0100)]
gdb: Use std::min and std::max throughout
Otherwise including <string> or some other C++ header is broken.
E.g.:
In file included from /opt/gcc/include/c++/7.0.0/bits/char_traits.h:39:0,
from /opt/gcc/include/c++/7.0.0/string:40,
from /home/pedro/gdb/mygit/cxx-convertion/src/gdb/infrun.c:68:
/opt/gcc/include/c++/7.0.0/bits/stl_algobase.h:243:56: error: macro "min" passed 3 arguments, but takes just 2
min(const _Tp& __a, const _Tp& __b, _Compare __comp)
^
/opt/gcc/include/c++/7.0.0/bits/stl_algobase.h:265:56: error: macro "max" passed 3 arguments, but takes just 2
max(const _Tp& __a, const _Tp& __b, _Compare __comp)
^
In file included from .../src/gdb/infrun.c:21:0:
To the best of my grepping abilities, I believe I adjusted all min/max
calls.
gdb/ChangeLog:
2016-09-16 Pedro Alves <palves@redhat.com>
* defs.h (min, max): Delete.
* aarch64-tdep.c: Include <algorithm> and use std::min and
std::max throughout.
* aarch64-tdep.c: Likewise.
* alpha-tdep.c: Likewise.
* amd64-tdep.c: Likewise.
* amd64-windows-tdep.c: Likewise.
* arm-tdep.c: Likewise.
* avr-tdep.c: Likewise.
* breakpoint.c: Likewise.
* btrace.c: Likewise.
* ctf.c: Likewise.
* disasm.c: Likewise.
* doublest.c: Likewise.
* dwarf2loc.c: Likewise.
* dwarf2read.c: Likewise.
* environ.c: Likewise.
* exec.c: Likewise.
* f-exp.y: Likewise.
* findcmd.c: Likewise.
* ft32-tdep.c: Likewise.
* gcore.c: Likewise.
* hppa-tdep.c: Likewise.
* i386-darwin-tdep.c: Likewise.
* i386-tdep.c: Likewise.
* linux-thread-db.c: Likewise.
* lm32-tdep.c: Likewise.
* m32r-tdep.c: Likewise.
* m88k-tdep.c: Likewise.
* memrange.c: Likewise.
* minidebug.c: Likewise.
* mips-tdep.c: Likewise.
* moxie-tdep.c: Likewise.
* nds32-tdep.c: Likewise.
* nios2-tdep.c: Likewise.
* nto-procfs.c: Likewise.
* parse.c: Likewise.
* ppc-sysv-tdep.c: Likewise.
* probe.c: Likewise.
* record-btrace.c: Likewise.
* remote.c: Likewise.
* rs6000-tdep.c: Likewise.
* rx-tdep.c: Likewise.
* s390-linux-nat.c: Likewise.
* s390-linux-tdep.c: Likewise.
* ser-tcp.c: Likewise.
* sh-tdep.c: Likewise.
* sh64-tdep.c: Likewise.
* source.c: Likewise.
* sparc-tdep.c: Likewise.
* symfile.c: Likewise.
* target-memory.c: Likewise.
* target.c: Likewise.
* tic6x-tdep.c: Likewise.
* tilegx-tdep.c: Likewise.
* tracefile-tfile.c: Likewise.
* tracepoint.c: Likewise.
* valprint.c: Likewise.
* value.c: Likewise.
* xtensa-tdep.c: Likewise.
* cli/cli-cmds.c: Likewise.
* compile/compile-object-load.c: Likewise.
Andreas Arnez [Fri, 16 Sep 2016 17:25:55 +0000 (19:25 +0200)]
S390: Hardware breakpoint support
Add hardware breakpoint support for S390 targets.
gdb/ChangeLog:
* s390-linux-nat.c (PER_BIT, PER_EVENT_BRANCH, PER_EVENT_IFETCH)
(PER_EVENT_STORE, PER_EVENT_NULLIFICATION)
(PER_CONTROL_BRANCH_ADDRESS, PER_CONTROL_SUSPENSION)
(PER_CONTROL_ALTERATION): New macros.
(struct s390_debug_reg_state) <break_areas>: New member.
(s390_forget_process): Free break_areas as well.
(s390_linux_new_fork): Copy break_areas as well.
(s390_prepare_to_resume): Install hardware breakpoints.
(s390_can_use_hw_breakpoint): Indicate support for hardware
breakpoints.
(s390_insert_hw_breakpoint, s390_remove_hw_breakpoint): New
linux_nat target methods.
(_initialize_s390_nat): Register them.
gdb/testsuite/ChangeLog:
* lib/gdb.exp: No longer skip hardware breakpoint tests on s390.
Andreas Arnez [Fri, 16 Sep 2016 17:25:55 +0000 (19:25 +0200)]
linux-nat: Add function lwp_is_stepping
Add the function lwp_is_stepping which indicates whether the given LWP
is currently single-stepping. This is a common interface, usable from
native GDB as well as from gdbserver.
gdb/gdbserver/ChangeLog:
* linux-low.c (lwp_is_stepping): New function.
gdb/ChangeLog:
* nat/linux-nat.h (lwp_is_stepping): New declaration.
* linux-nat.c (lwp_is_stepping): New function.
Andreas Arnez [Fri, 16 Sep 2016 17:25:55 +0000 (19:25 +0200)]
S390: Enable "maint set show-debug-regs"
Implement a new function for dumping the S390 "debug
registers" (actually, the PER info) and invoke it at appropriate places.
Respect the variable show_debug_regs and make it settable by the user.
gdb/ChangeLog:
* s390-linux-nat.c (gdbcmd.h): New include.
(s390_show_debug_regs): New function.
(s390_stopped_by_watchpoint): Call it, if show_debug_regs is set.
(s390_prepare_to_resume): Likewise.
(_initialize_s390_nat): Register the command "maint set
show-debug-regs".
Andreas Arnez [Fri, 16 Sep 2016 17:25:54 +0000 (19:25 +0200)]
S390: Multi-inferior watchpoint support
Support different sets of watchpoints in multiple inferiors.
gdb/ChangeLog:
* s390-linux-nat.c (watch_areas): Remove variable. Replace by a
member of...
(struct s390_debug_reg_state): ...this. New struct.
(struct s390_process_info): New struct.
(s390_process_list): New variable.
(s390_find_process_pid, s390_add_process, s390_process_info_get)
(s390_get_debug_reg_state): New functions.
(s390_stopped_by_watchpoint): Now access the watch_areas VEC via
s390_get_debug_reg_state.
(s390_prepare_to_resume): Likewise.
(s390_insert_watchpoint): Likewise.
(s390_remove_watchpoint): Likewise.
(s390_forget_process, s390_linux_new_fork): New linux_nat target
methods.
(_initialize_s390_nat): Register them.
Andreas Arnez [Fri, 16 Sep 2016 17:25:54 +0000 (19:25 +0200)]
S390: Migrate watch areas from list to VEC type
For S390, the list of active watchpoints is maintained in a list based
at "watch_base". This refactors the list to a vector "watch_areas".
gdb/ChangeLog:
* s390-linux-nat.c (s390_watch_area): New typedef. Define a VEC.
(watch_base): Remove variable.
(watch_areas): New variable.
(s390_stopped_by_watchpoint): Transform operations on the
watch_base list to equivalent operations on the watch_areas VEC.
(s390_prepare_to_resume): Likewise.
(s390_insert_watchpoint): Likewise.
(s390_remove_watchpoint): Likewise.
Andreas Arnez [Fri, 16 Sep 2016 17:25:54 +0000 (19:25 +0200)]
S390: Avoid direct access to lwp_info structure
When using the lwp_info structure, avoid accessing its members directly,
and use the advertised function interfaces instead. This is according
to the instructions in linux-nat.h and prepares for making some of the
code common between gdb and gdbserver.
gdb/ChangeLog:
* s390-linux-nat.c (s390_prepare_to_resume): Use advertised lwp
functions instead of accessing lwp_info structure members.
(s390_mark_per_info_changed): New function.
(s390_new_thread): Use it.
(s390_refresh_per_info_cb): New function.
(s390_refresh_per_info): Remove parameter. Refresh all lwps of
the current process.
(s390_insert_watchpoint): Adjust call to s390_refresh_per_info.
(s390_remove_watchpoint): Likewise.
Jan Kratochvil [Fri, 16 Sep 2016 17:23:22 +0000 (19:23 +0200)]
testsuite: Fix false FAIL in gdb.cp/casts.exp
gcc-6.2.1-1.fc26.x86_64
gdb compile failed, /home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:40:10: error: expected primary-expression before 'int'
decltype(int x)
^~~
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:40:10: error: expected ')' before 'int'
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:40:1: error: expected unqualified-id before 'decltype'
decltype(int x)
^~~~~~~~
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc: In function 'int main(int, char**)':
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:59:14: error: expected primary-expression before 'decltype'
double y = decltype(2);
^~~~~~~~
'decltype' is a registered keyword since C++11 which is now a default for GCC.
On Thu, 15 Sep 2016 14:06:56 +0200, Pedro Alves wrote:
Seems to be exercising the FLAG_SHADOW bits:
...
{"__typeof__", TYPEOF, OP_TYPEOF, 0 },
{"__typeof", TYPEOF, OP_TYPEOF, 0 },
{"typeof", TYPEOF, OP_TYPEOF, FLAG_SHADOW },
{"__decltype", DECLTYPE, OP_DECLTYPE, FLAG_CXX },
{"decltype", DECLTYPE, OP_DECLTYPE, FLAG_CXX | FLAG_SHADOW },
...
/* This is used to associate some attributes with a token. */
enum token_flag
{
...
/* If this bit is set, the token is conditional: if there is a
symbol of the same name, then the token is a symbol; otherwise,
the token is a keyword. */
FLAG_SHADOW = 2
};
So perhaps a better fix is to move that particular test to a
separate testcase that force-compiles with -std=c++03.
gdb/testsuite/ChangeLog
2016-09-16 Jan Kratochvil <jan.kratochvil@redhat.com>
* gdb.cp/casts.cc (decltype): Move it ...
(main): ... with its call to ...
* gdb.cp/casts03.cc: ... a new file.
* gdb.cp/casts.exp: Add new file casts03.cc, move decltype test to it.
Claudiu Zissulescu [Thu, 15 Sep 2016 10:24:24 +0000 (12:24 +0200)]
[ARC] Disassemble correctly extension instructions.
For each MAJOR-MINOR opcode tuple, we can have either a 3-operand, or
2-operand, or a single operand instruction format, depending on the
values present in i-field, and a-field.
The disassembler is reading the section containing the extension
instruction format and stores them in a table. Each table element
represents a linked list with encodings for a particular MAJOR-MINOR
tuple.
The current implementation checks only against the first element of
the list, hence, the issue.
This patch is walking the linked list until empty or finds an opcode
match. It also adds a test outlining the found problem.
opcodes/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Walk the linked list pointed by einsn.
gas/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsnxop.d: New file.
* testsuite/gas/arc/textinsnxop.s: Likewise.
GDB Administrator [Fri, 16 Sep 2016 00:00:18 +0000 (00:00 +0000)]
Automatic date update in version.in
Jan Kratochvil [Thu, 15 Sep 2016 21:45:11 +0000 (23:45 +0200)]
testsuite: Fix C++11 compilation failure for gdb.cp/m-static.exp
gcc-6.2.1-1.fc26.x86_64
g++ -std=c++03:
no warnings
g++:
In file included from /home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.cc:79:0:
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.h:9:34: error: ‘constexpr’ needed for in-class initialization of static
data member ‘const float gnu_obj_4::somewhere’ of non-integral type [-fpermissive]
static const float somewhere = 3.14159;
^~~~~~~
clang++:
In file included from /home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.cc:79:
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.h:9:22: warning: in-class initializer for static data member of type 'const
float' is a GNU extension [-Wgnu-static-float-init]
static const float somewhere = 3.14159;
^ ~~~~~~~
1 warning generated.
clang++ -std=c++11:
In file included from /home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.cc:79:
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.h:9:22: error: in-class initializer for static data member of type 'const
float' requires 'constexpr' specifier [-Wstatic-float-init]
static const float somewhere = 3.14159;
^ ~~~~~~~
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.h:9:3: note: add 'constexpr'
static const float somewhere = 3.14159;
^
constexpr
1 error generated.
OK for check-in?
After the fix out of the 4 combinations above only this one remains non-empty:
clang++:
In file included from /home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.cc:79:
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/m-static.h:9:22: warning: in-class initializer for static data member of type 'const
float' is a GNU extension [-Wgnu-static-float-init]
static const float somewhere = 3.14159;
^ ~~~~~~~
1 warning generated.
On Thu, 15 Sep 2016 15:10:50 +0200, Pedro Alves wrote:
Hmm, OK, now that I read the test, I think you were right in trying to
keep it safe, actually. The .exp file has:
if { $non_dwarf } { setup_xfail *-*-* }
gdb_test "print test4.everywhere" "\\$\[0-9\].* = 317" "static const int initialized in class definition"
if { $non_dwarf } { setup_xfail *-*-* }
gdb_test "print test4.somewhere" "\\$\[0-9\].* = 3.14\[0-9\]*" "static const float initialized in class definition"
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Added by this:
https://sourceware.org/bugzilla/show_bug.cgi?id=11702
https://sourceware.org/ml/gdb-patches/2010-06/msg00677.html
https://sourceware.org/ml/gdb-patches/2010-06/txt00011.txt
So the new patch would make that highlighted tested above not
test what its test message says it is testing.
So I now think your original patch is better. Please push
that one instead.
gdb/testsuite/ChangeLog
2016-09-15 Jan Kratochvil <jan.kratochvil@redhat.com>
* gdb.cp/m-static.h (gnu_obj_4::somewhere): Use constexpr for C++11.
Peter Bergner [Thu, 15 Sep 2016 21:10:05 +0000 (16:10 -0500)]
Update ISA 3.0 / POWER9 gdb tests to match GAS test cases.
* gdb.arch/powerpc-power.s: Update Power9 instruction tests
and sync up the test with tests in gas/testsuite/gas/ppc.
* gdb.arch/powerpc-power.exp: Likewise.
Jan Kratochvil [Thu, 15 Sep 2016 12:04:20 +0000 (14:04 +0200)]
testsuite: Disable ccache
There were always various problems with compatibility with ccache:
https://bugzilla.redhat.com/show_bug.cgi?id=488863
https://bugzilla.redhat.com/show_bug.cgi?id=759592
https://sourceware.org/ml/gdb-patches/2009-02/msg00397.html
IMO in a summary ccache finds more a benefit of faster compilation despite the
debug info is no longer exactly the same (as without ccache).
Although for example in this case ccache helped to find a real GDB bug:
https://sourceware.org/ml/gdb-patches/2015-01/msg00497.html
For the GDB testcases ccache has (IMO) no real performance advantage and it
just brings heisenbugs - false FAILs - from time to time:
Breakpoint 1, main () at gdb/testsuite/gdb.base/vdso-warning.c:21^M
21 return 0;^M
(gdb) PASS: gdb.base/vdso-warning.exp: run: startup
->
Breakpoint 1, main () at gdb/testsuite/gdb.base/hbreak-unmapped.c:21^M
21 return 0;^M
(gdb) FAIL: gdb.base/vdso-warning.exp: run: startup
So I find most safe and easy to just disable ccache for all testsuites.
gdb/testsuite/ChangeLog
2016-09-15 Jan Kratochvil <jan.kratochvil@redhat.com>
* lib/future.exp: Set CCACHE_DISABLE, clear CCACHE_NODISABLE.
Jose E. Marchesi [Thu, 15 Sep 2016 10:20:54 +0000 (12:20 +0200)]
gas: run the sparc test dcti-couples-v9 only in ELF targets.
gas/ChangeLog:
2016-09-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
dcti-couples-v9 only in ELF targets to avoid spurious failures in
sparc-aout and sparc-coff targets.
Ed Maste [Thu, 15 Sep 2016 09:42:08 +0000 (10:42 +0100)]
Fix typo in readelf error message.
* readelf.c (process_mips_specific): Fix typo in error message.
Peter Bergner [Thu, 15 Sep 2016 03:10:51 +0000 (22:10 -0500)]
Modify POWER9 support to match final ISA 3.0 documentation.
opcodes/
* ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3>: Delete mnemonics.
<cp_abort>: Rename mnemonic from ...
<cpabort>: ...to this.
<setb>: Change to a X form instruction.
<sync>: Change to 1 operand form.
<copy>: Delete mnemonic.
<copy_first>: Rename mnemonic from ...
<copy>: ...to this.
<paste, paste.>: Delete mnemonics.
<paste_last>: Rename mnemonic from ...
<paste.>: ...to this.
gas/
* testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
<copy, paste.>: Update tests.
* testsuite/gas/ppc/power9.s: Likewise.
GDB Administrator [Thu, 15 Sep 2016 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Thomas Preud'homme [Wed, 14 Sep 2016 15:02:17 +0000 (16:02 +0100)]
Fix ld --gc-section segfault with ARMv8-M entry function in absolute section
bfd/
2016-09-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf32-arm.c (elf32_arm_gc_mark_extra_sections): Only mark section
not already marked.
ld/
2016-09-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/cmse-veneers.s: Add a test for ARMv8-M Security
Extensions entry functions in absolute section.
* testsuite/ld-arm/cmse-veneers.rd: Adapt expected output accordingly.
Nick Clifton [Wed, 14 Sep 2016 14:32:01 +0000 (15:32 +0100)]
Fix seg-fault in objdump when run on a fuzzed PE binary.
PR binutils/20605
* peicode.h (pe_bfd_read_buildid): Check that the Data Directory
contains a valid size for the Debug directory.
Jose E. Marchesi [Wed, 14 Sep 2016 14:15:24 +0000 (07:15 -0700)]
gas: improve architecture mismatch diagnostics in sparc
Merely dumping the mnemonic name in "architecture mismatch" errors may
not provide enough information to determine what went wrong, as the same
mnemonic can be used for different variants of an instruction pertaining
to different architecture levels.
This little patch makes the assembler to include the instruction
arguments in the error message.
gas/ChangeLog:
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Print the instruction arguments
in "architecture mismatch" error messages.
Jose E. Marchesi [Wed, 14 Sep 2016 14:10:49 +0000 (07:10 -0700)]
gas: detect DCTI couples in sparc
Before SPARC V9 the effect of having a delayed branch instruction in the
delay slot of a conditional delayed branch was undefined.
In SPARC V9 DCTI couples are well defined.
However, starting with the UltraSPARC Architecture 2005, DCTI
couples (of all kind) are deprecated and should not be used, as they may
be slow or behave differently to what the programmer expects.
This patch adds a new command line option --dcti-couples-detect to `as',
disabled by default, that makes the assembler to warn the user if an
unpredictable DCTI couple is found. Tests and documentation are
included.
gas/ChangeLog:
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (md_assemble): Detect and warning on
unpredictable DCTI couples in certain arches.
(dcti_couples_detect): New global.
(md_longopts): Add command line option -dcti-couples-detect.
(md_show_usage): Document -dcti-couples-detect.
(md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests.
* testsuite/gas/sparc/dcti-couples.s: New file.
* testsuite/gas/sparc/dcti-couples-v9c.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v8.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v9.d: Likewise.
* testsuite/gas/sparc/dcti-couples-v9c.l: Likewise.
* testsuite/gas/sparc/dcti-couples-v8.l: Likewise.
* doc/as.texinfo (Overview): Document --dcti-couples-detect.
* doc/c-sparc.texi (Sparc-Opts): Likewise.
Bhushan Attarde [Wed, 14 Sep 2016 12:49:16 +0000 (13:49 +0100)]
Prevent segfault in GDB when searching for architecture matches.
* format.c (struct bfd_preserve): New "build_id" field.
(bfd_preserve_save): Save "build_id".
(bfd_preserve_restore): Restore "build_id".
Claudiu Zissulescu [Wed, 7 Sep 2016 07:47:34 +0000 (09:47 +0200)]
[ARC] Fix parsing dtpoff relocation expression.
The assembler accepts dtpoff complex relocation expression like
identifier@dtpoff + const. However, it doesn't accept an expression such
as identifier@dtpoff@base + const. This patch solves this issue, and adds
a number of tests.
ld/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/tls-dtpoff.dd: New file.
* testsuite/ld-arc/tls-dtpoff.rd: Likewise.
* testsuite/ld-arc/tls-dtpoff.s: Likewise.
* testsuite/ld-arc/tls-relocs.ld: Likewise.
* testsuite/ld-arc/arc.exp: Add new tdpoff test.
gas/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/tls-relocs2.d: New file.
* testsuite/gas/arc/tls-relocs2.s: Likewise.
* config/tc-arc.c (tokenize_arguments): Accept offsets when base
is used.
Anton Kolesov [Wed, 14 Sep 2016 11:20:13 +0000 (12:20 +0100)]
Stop the ARC disassembler from seg-faulting if initialised without a BFD present.
* arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
Nick Clifton [Wed, 14 Sep 2016 09:42:10 +0000 (10:42 +0100)]
Add support for disabling automatic generation of .eh_frame_hdr sections in ELF based linkers.
PR ld/20537
* emultempl/elf32.em: More OPTION_xxx values into an enum. Add
OPTION_NO_EH_FRAME_HDR.
(_add_options): Add support for --no-eh-frame-hdr.
* ld.texinfo: Document new option.
* lexsup.c (elf_shlib_list_options): List new option.
* NEWS: Mention the new option.
GDB Administrator [Wed, 14 Sep 2016 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
Carl E. Love [Tue, 13 Sep 2016 16:58:18 +0000 (09:58 -0700)]
Fix for gdb.server/non-existing-program.exp test case
The last commit was supposed to have the reference to ptrace () removed.
The patch didn't get updated correctly before the commit. This commit
fixes the comment as requested
gdbserver/ChangeLog
2016-09-06 Carl Love <cel@us.ibm.com>
* server.c (start_inferior): Fixed comment, requested comment change
didn't get updated correctly. Removed reference to ptrace () call as
it is only true on Linux systems.
Carl E. Love [Tue, 13 Sep 2016 16:41:54 +0000 (09:41 -0700)]
Fix for gdb.server/non-existing-program.exp test case
The test checks to make sure GDB exits cleanly if there is
no valid target binary. Currently, ppc and S390 fail on this
test. The function target_post_create_inferior () calls
linux_post_create_inferior () which calls the architecture
specific functions s390_arch_setup () and ppc_arch_setup ()
which make ptrace calls to access the architecture specific
registers. These ptrace calls fail because the process does
not exist causing GDB to exit on error.
This patch checks to see if the initial ptrace (PTRACE_TRACEME, ...)
call returned a status of TARGET_WAITKIND_EXITED indicating the
target has already exited. If the target has exited, then the
target_post_create_inferior () is not called since there is no
inferior to be setup. The test to see if the initial ptrace
call succeeded is done after the ptrace (PTRACE_TRACEME, ...)
call and the wait for the inferior process to stop, assuming
it exists, has occurred.
The patch has been tested on X86 64-bit, ppc64 and s390. If
fixes the test failures on ppc64 and s390. The test does not
fail on X86 64-bit. The patch does not introduce any additional
regression failures on any of these three platforms.
gdbserver/ChangeLog
2016-09-06 Carl Love <cel@us.ibm.com>
* server.c (start_inferior): Do not call
function target_post_create_inferior () if the
inferior process has already exited.
GDB Administrator [Tue, 13 Sep 2016 00:00:21 +0000 (00:00 +0000)]
Automatic date update in version.in
Andreas Krebbel [Mon, 12 Sep 2016 14:32:02 +0000 (16:32 +0200)]
S/390: Add alternate processor names.
This patch adds alternate CPU names which adhere to the number of the
architecture document. So instead of having z196, zEC12, and z13 you
can use arch9, arch10, and arch11. The old cpu names stay valid and
should primarily be used.
The alternate names are supposed to improve compatibility with the IBM
XL compiler toolchain which uses the arch numbering.
opcodes/ChangeLog:
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Support alternate arch strings.
gas/ChangeLog:
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Support alternate arch
strings.
* doc/as.texinfo: Document new arch strings.
* doc/c-s390.texi: Likewise.
Andreas Krebbel [Mon, 12 Sep 2016 14:32:02 +0000 (16:32 +0200)]
S/390: Fix facility bit default.
gas/ChangeLog:
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c: Set all facitily bits by default
Patrick Steuer [Mon, 12 Sep 2016 14:32:02 +0000 (16:32 +0200)]
S/390: Fix kmctr instruction type.
opcodes/ChangeLog:
2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
* s390-opc.txt: Fix kmctr instruction type.
gas/ChangeLog:
2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z196.d: Adjust testcase.
Sergio Durigan Junior [Sun, 11 Sep 2016 20:53:09 +0000 (16:53 -0400)]
Fix false FAIL on gdb.base/stap-probe.exp, due to ICF optimization
GCC 6's ICF optimization pass is making the declaration of 'm1' and
'm2', on gdb.base/stap-probe.c, to be unified. However, this leads to
only one instance of the probe 'two' being created, which causes a
failure on the testsuite (which expects a multi-location breakpoint to
be inserted on the probe).
This patch fixes this failure by declaring a dummy variable on 'm1',
and using it as an argument to m1's version of probe 'two'. Since we
do not care about the contents of the functions nor about the
arguments of each probe 'two', this is OK.
gdb/testsuite/ChangeLog:
2016-09-11 Sergio Durigan Junior <sergiodj@redhat.com>
Jan Kratochvil <jan.kratochvil@redhat.com>
* gdb.base/stap-probe.c (m1): New variable 'dummy', necessary to
make m1's definition to be different from m2's. Use 'dummy' as an
argument for probe 'two'.
GDB Administrator [Mon, 12 Sep 2016 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Sun, 11 Sep 2016 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
Jon Beniston [Sat, 10 Sep 2016 20:18:56 +0000 (21:18 +0100)]
Use target_sim_options for sim target.
2016-09-10 Jon Beniston <jon@beniston.com>
* lib/mi-support.exp (mi_gdb_target_load): Use target_sim_options
for sim target.
GDB Administrator [Sat, 10 Sep 2016 00:00:21 +0000 (00:00 +0000)]
Automatic date update in version.in
Andreas Arnez [Fri, 9 Sep 2016 17:59:53 +0000 (19:59 +0200)]
Pass HWCAP to ifunc resolver
On various GNU Elf architectures, including AArch64, ARM, s390/s390x,
ppc32/64, and sparc32/64, the dynamic loader passes HWCAP as a parameter
to each ifunc resolver. Currently there is an open glibc Bugzilla that
requests this to be generalized to all architectures:
https://sourceware.org/bugzilla/show_bug.cgi?id=19766
And various ifunc resolvers already rely on receiving HWCAP. Currently
GDB always calls an ifunc resolver without any arguments; thus the
resolver may receive garbage, and based on that, the resolver may decide
to return a function that is not suited for the given platform.
This patch always passes HWCAP to ifunc resolvers, even on systems where
the dynamic loader currently behaves otherwise. The rationale is
that (1) the dynamic loader may get adjusted on those systems as well in
the future; (2) passing an unused argument should not cause a problem
with existing resolvers; and (3) the logic is much simpler without such
a distinction.
gdb/ChangeLog:
* elfread.c (auxv.h): New include.
(elf_gnu_ifunc_resolve_addr): Pass HWCAP to ifunc resolver.
gdb/testsuite/ChangeLog:
* gdb.base/gnu-ifunc-lib.c (resolver_hwcap): New external
variable declaration.
(gnu_ifunc): Add parameter hwcap. Store it in resolver_hwcap.
* gdb.base/gnu-ifunc.c (resolver_hwcap): New global variable.
* gdb.base/gnu-ifunc.exp: Add test to verify that the resolver
received HWCAP as its argument.
GDB Administrator [Fri, 9 Sep 2016 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Thu, 8 Sep 2016 15:49:07 +0000 (09:49 -0600)]
Remove some unneeded casts from remote.c
I happened to notice a few unneeded casts in remote.c. In some cases
these are no-ops, and in others these cast away const, but in a context
where this is not needed.
I'm checking this in under the obvious rule.
Tested by rebuilding on x86-64 Fedora 24.
2016-09-08 Tom Tromey <tom@tromey.com>
* remote.c (remote_notif_stop_ack, remote_wait_as)
(show_remote_cmd): Remove unneeded casts.
H.J. Lu [Thu, 8 Sep 2016 14:54:16 +0000 (07:54 -0700)]
Allow PROCESSOR_IAMCU for Intel MCU
* config/tc-i386.c (i386_target_format): Allow PROCESSOR_IAMCU
for Intel MCU.
GDB Administrator [Thu, 8 Sep 2016 00:00:20 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Wed, 7 Sep 2016 16:16:25 +0000 (09:16 -0700)]
X86: Allow additional ISAs for IAMCU in assembler
Originally only Pentium integer instructions are allowed for IAMCU.
This patch removes such a restriction. For example, 387 and SSE2
instructions can be enabled by passing "-march=iamcu+sse2+387" to
assembler.
gas/
* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
(set_cpu_arch): Updated.
(md_parse_option): Likewise.
* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
iamcu-inval-2 and iamcu-inval-3.
* testsuite/gas/i386/iamcu-4.d: New file.
* testsuite/gas/i386/iamcu-4.s: Likewise.
* testsuite/gas/i386/iamcu-5.d: Likewise.
* testsuite/gas/i386/iamcu-5.s: Likewise.
* testsuite/gas/i386/iamcu-inval-2.l: Removed.
* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
* testsuite/gas/i386/iamcu-inval-3.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
* i386-init.h: Regenerated.
Richard Earnshaw [Wed, 7 Sep 2016 16:14:54 +0000 (17:14 +0100)]
[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
* opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all
ARMv8-A CPUs except xgene1.
projects / external / binutils.git / log