etnaviv: GC7000: Update screen specs for HALTI5

- This core must load shaders from memory (AFAIK)
- Yet another new location for UNIFORMS

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: GC7000: Update context reset for ..HALTI5

Update context reset for HALTI3..HALTI5, sorting states for the HALTI
version that has them.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: GC7000: No RS align when using BLT

RS align is not necessary and might even be harmful when using the BLT
engine for blitting.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: GC7000: BLT engine blitting support

Add an implemenation of key clear_blit functions using the BLT engine
that replaced the RS on GC7000.

Also set level->size correctly for imported resources. This is important
for the BLT resolve-in-place path to work for them.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: GC7000: Factor out RS blit functionality

Prepare for BLT-based blitting path by moving RS-based
blitting to the RS implementation file, making this
self-contained.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: GC7000: Move etna_coalesce to emit header file

Want to be able to emit state from the texture implementation,
and the blitter implementation.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: GC7000: Support BLT as recipient for etna_stall

When the BLT is involved as source or target, add an extra BLT
enable/disable sequence around the sync sequence.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: Use only DRAW_INSTANCED on GC3000+

The blob does this, as DRAW_INSTANCED can replace fully all the other
draw commands. It is also required to handle integer vertex formats.
The other path is only there for compatibility and might go away (or at
least rot to become buggy due to dis-use) in newer hardware.

As a by-effect this changes the behavior for GC3000-, by no longer using
the index offset for DRAW_INDEXED but instead adding it to INDEX_ADDR.
This should make no difference.

Preparation for GC7000 support.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

etnaviv: Emit SCALE for vertex attributes

This is used by HALTI2+ (GC3000+) when drawing with DRAW_INSTANCED.

It is also necessary when switching between integer and floating point
vertex element formats.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.

We're about to add more of them, and need to pass the whole lot of them
around together when growing them.  Putting them in a struct makes this
much easier.

brw->batch.batch.bo is a bit of a mouthful, but it's nice to have things
labeled 'batch' and 'state' now that we have multiple buffers.

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Don't grow batch/state buffer on every emit after an overflow.

Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we
try and flush.  If we're not allowed to flush, we resort to growing the
buffer so that there's space for the data we need to emit.

We accidentally got the threshold wrong.  The first non-wrappable call
beyond (e.g.) STATE_SZ would grow the buffer to floor(1.5 * STATE_SZ),
The next call would see we were beyond STATE_SZ and think we needed to
grow a second time - when the buffer was already large enough.

We still want to flush when we hit STATE_SZ, but for growing, we should
use the actual size of the buffer as the threshold.  This way, we only
grow when actually necessary.

v2: Simplify the control flow (suggested by Jordan)

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.

The original state buffer was marked with EXEC_OBJECT_CAPTURE.  When
growing it, we want to preserve that flag so we continue to capture it
in GPU hang reports.

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Use old_bo->align when growing batch/state buffer instead of 4096.

The intention here is make the new BO use the same alignment as the old
BO.  This isn't strictly necessary, but we would have to update the
'alignment' field in the validation list when swapping it out, and we
don't bother today.

The batch and state buffers use an alignment of 4096, so this should be
equivalent - it's just clearer than cut and pasting a magic constant.

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

r600: no need to reinit compute regs

Compute setup gets emitted into the normal gfx state buffer,
so no need to reinit the basics.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: split cb setup code out from evergreen compute path.

This just makes it easier to bypass for TGSI later.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: add support for compute pkt flags to debug dumping.

This just lets us see packets marked for compute.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: fix bfe where src/dst are same.

This fixes overlaps where src/dst are the same.

Fixes a bunch of the deqp bitfield tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control

Reviewed-and-tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>

i965: Program the dynamic state heap size to MAX_STATE_SIZE.

STATE_BASE_ADDRESS specifies a maximum size of the dynamic state
section, beyond which data supposedly reads back as 0.  On Gen8+,
we were programming it to the size of the buffer.  This worked fine
until we started growing the state buffer in commit 2dfc119f22f25708.
When the state buffer grows, the value in STATE_BASE_ADDRESS becomes
too small, and our state beyond STATE_SZ bytes would read back as 0.

To avoid having to update the value, we program it to MAX_STATE_SIZE.
We used to program the upper bound to the maximum on older hardware
anyway, so programming it too large isn't a big deal.

Bogus SURFACE_STATE can easily lead to GPU hangs and misrendering.
DiRT Rally was hitting the statebuffer growth path, and suffered from
bad texture corruption and GPU hangs (usually around the same time).

This patch fixes both issues.

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*

and handle PIPE_FLUSH_HINT_FINISH in r300.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove r600_common_screen

Most files in gallium/radeon now include si_pipe.h.

chip_class and family are now here:
    sscreen->info.family
    sscreen->info.chip_class

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove query/apply_opaque_metadata callbacks

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move shader debug helpers out of r600_pipe_common.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: dismantle si_common_screen_init/destroy

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: document our vendor string situation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set all pipe buffer functions in r600_buffer_common.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/uvd: don't call ws->query_info

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move video queries into si_get.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove more functions from r600_pipe_common.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move/remove ac_shader_binary helpers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove R600_CONTEXT_* flags

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: just include si_pipe.h in r600_query.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove some definitions and helpers from r600_pipe_common.h

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't use fast color clear for small surfaces

This removes 35+ clear eliminate passes from DOTA 2.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: unify code setting dirty_level_mask for fast clear

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: clean up si_do_fast_color_clear parameters

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove r600_common_context::clear_buffer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move r600_test_dma.c into si_test_dma.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move si_pipe_clear_buffer into si_cp_dma.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move all clear() code into si_clear.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable DCC with MSAA for VI

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: implement fast color clear for DCC with MSAA for VI

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add a workaround for blending with DCC and MSAA

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: enable DCC computation for MSAA

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix layered DCC fast clear

Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util: Also include endian.h on cygwin

If u_endian.h can't determine the endianess, the default behaviour in sha1.c
is to build for big-endian

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: deal with vs_inputs as 64-bit unsigned integer

Commit 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") uses
vs_prog_data->vs_inputs as if it were a 32-bit unsigned integer.

But actually it is a 64-bit integer, and as such it is used in other
parts of Mesa code. It is worth to note that bits from the entire range
are used, and not only 32-bits. This is due our implementation for
handling 64-bit dual-slot input attributes, which requires to use a
larger bitfield to manage them.

This commit reverts the changes done in brw_draw_upload.c, keeping the
rest of the changes.

This fixes the following tests:

- KHR-GL45.enhanced_layouts.varying_array_locations
- KHR-GL45.enhanced_layouts.varying_locations

Fixes: 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103942
CC: Marek Olšák <marek.olsak@amd.com>
CC: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

mesa: rework _mesa_add_parameter() to only add a single param

This is more inline with what the functions name suggests it should
do, and makes the code much easier to follow.

This will also make adding uniform packing support much simpler.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600: lds load cleanups.

This is just some cleanups on top of the last patch from my compute branch.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600_shader: only load from LDS what is really used

Use the destination write mask to determine which values are really to be
read from LDS and load only these.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>

r600/sb: handle jump after target to end of program. (v2)

This fixes hangs on cayman with
tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test

This has a single if/else in it, and when this peephole activated,
it would set the jump target to NULL if there was no instruction
after the final POP. This adds a NOP if we get a jump in this case,
and seems to fix the hangs, so we have a valid target for the ELSE
instruction to go to, instead of 0 (which causes infinite loops).

v2: update last_cf correctly. (I had some other patches hide this)

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Change a ret == -1 check to ret != 0.

For consistency with most other ret checks.  Suggested by Chris.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Use C99 struct initializers in brw_bufmgr.c.

This is cleaner than using a non-standard memclear macro (which does a
memset to 0) and then initializing fields after the fact.  We move the
declarations to where we initialized the fields.  While we're at it, we
move the declaration of 'ret' that goes with the ioctl, eliminating the
declaration section altogether.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Move perf_debug and WARN_ONCE back to brw_context.h.

These were moved to src/intel/common/gen_debug.h, but they are not
common code.  They assume that brw_context or gl_context variables
exist, named brw or ctx.  That isn't remotely true outside of i965.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

i965: const a few structs and vars to avoid writing to them by accident

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix Smooth Point Enables.

We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.

Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

meson: build virgl driver

Build tested only.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: build svga driver on linux

Build tested only.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: build r600 driver

v4: - Ensure inc_amd_common defined when radeonsi is disabled (needed by
      r600)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: build r300 driver

This is build tested only

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: build i915g driver

Build tested only.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

svga: move svga_is_format_supported() to svga_format.c

where the other format-related functions live.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: s/unsigned/SVGA3dDevCapIndex/

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

i965: perf: add support for CoffeeLake GT3

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: add support for CoffeeLake GT2

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: add busyness metric sets on gen8/9 platforms

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: fix time elapsed counter equations in VME/Media configs

There was a mistake just in those metric sets. We probably didn't
noticed because they're not really interesting for 3D workloads.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: update counter names on gen8/9 platforms

Just fixing names.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: add a debug option to disable oa config loading

This provides a good way to verify we haven't broken using the perf
driver on older kernels (which don't have the oa config loading
mechanism).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: add support for userspace configurations

This allows us to deploy new configurations without touching the
kernel.

v2: Detect loadable configs without creating one (Chris)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: update configs for loading from userspace

When making configs loadable from userspace in the kernel, we left to
userspace more responsability around programming some registers. In
particular one register we use to set directly in the driver has now
been moved into the configs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

util: add mesa-sha1 test to meson

Fixes: 513d7ffa23d42e96f831 "util: Add a SHA1 unit test program"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

compiler: fix typo

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

compiler: use NDEBUG to guard asserts

nir_validate.c's #endif already had the correct NDEBUG comment

Fixes: dcb1acdea00a8f2c29777 "nir/validate: Only build in debug mode"
Fixes: 9ff71b649b4b3808a9e17 "i965/nir: Validate that NIR passes call nir_metadata_preserve()"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

broadcom: use NDEBUG to guard asserts

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: check preprocessor token existence using #ifdef instead of #if

(other uses of USE_VC4_SIMULATOR are already correct)

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

docs/llvmpipe.html: Minor edits

Language and spelling fixups in three places.

Cc: "17.2" "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
[Eric: move two fixes from the other patch to this one.]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

st/dri: replace hard-coded array size with ARRAY_SIZE()

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi/gfx9: simplify condition for on-chip ESGS

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: clarify that si_shader_selector::esgs_itemsize is set for the ES part

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use si_shader_context instead of lp_build_context in more places

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: cleanup si_initialize_color_surface

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have it

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: check that we don't leak fine.buf references

Just as an added precaution.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/surface: fix indentation

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

amd/common: sid.h cleanups

Fix a bunch of labels indicating when registers were added/removed
and normalize the SI-class GRBM_GFX_INDEX.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st_glsl_to_tgsi: check for the tail sentinel in merge_two_dsts

This fixes yet another case where DFRACEXP has only one destination. Found
by address sanitizer.

Fixes tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4-only-mantissa.shader_test

Fixes: 3b666aa74795 ("st/glsl_to_tgsi: fix DFRACEXP with only one destination")
Acked-by: Marek Olšák <marek.olsak@amd.com>

mesa/gles: adjust internal format in glTexSubImage2D error checks

When floating point textures are created on OpenGL ES 2.0, driver
is free to choose used internal format. Mesa makes this decision in
adjust_for_oes_float_texture. Error checking for glTexImage2D properly
checks that sized formats are not used. We use same error checking
path for glTexSubImage2D (since there is lot of overlap), however since
those checks include internalFormat checks, we need to pass original
internalFormat passed by the client. Patch adds oes_float_internal_format
that does reverse adjust_for_oes_float_texture to get that format.

Fixes following test failure:
   ES2-CTS.gtf.GL2ExtensionTests.texture_float.texture_float

(when running test with MESA_GLES_VERSION_OVERRIDE=2.0)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103227
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

radv: Use the suffixed versions of VK_QUEUE_GLOBAL_PRIORITY_*

Acked-by: Dave Airlie <airlied@redhat.com>

vulkan: Update the XML and headers to 1.0.66

Acked-by: Dave Airlie <airlied@redhat.com>

intel/blorp: Drop blorp_resolve_ccs_attachment

The only reason why we needed that version was because the Vulkan driver
needed to be able to create the surface states so it could handle
indirect clear colors.  Now that blorp handles them natively, there's no
need for the extra entrypoint.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv: Let blorp handle indirect clear colors for CCS resolves

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv: Move get_fast_clear_state_address into anv_private.h

While we're at it, we break it into two nicely named functions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/blorp: Take a range of layers in blorp_ccs_resolve

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/blorp: Add initial support for indirect clear colors

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

i965/blorp: Use a designated initializer for blorp_surf

This way uninitialized fields get automatically zeroed and it's safe to
add more fields to blorp_surf.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/blorp: Add fast-clear to the special case in MSAA resolves

This doesn't go all the way of avoiding the txf_ms if it's fast-cleared,
however it does at least make us only do it once.  This should improve
performance of MSAA resolves in the presence of lots of clear color.
Without the patch, enabling fast-clears in the multisampling Sascha demo
drops the framerate by about 10%.  With this patch, enabling fast-clears
increases the demo's framerate by 25%.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>