Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:04 +0000 (15:56 +0100)]
riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().
This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:03 +0000 (15:56 +0100)]
riscv: Define PLATFORM__SET_BIT for generic_set_bit()
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:02 +0000 (15:56 +0100)]
x86: Define PLATFORM__SET_BIT for generic_set_bit()
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Chris Packham [Tue, 15 May 2018 01:31:11 +0000 (13:31 +1200)]
ARM: mvebu: a38x: Add missing SPDX license identfier
mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tom Rini [Tue, 15 May 2018 12:29:24 +0000 (08:29 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Vasily Khoruzhick [Mon, 14 May 2018 15:16:21 +0000 (08:16 -0700)]
dts: sunxi: add PWM node for sun50i
Add PWM definition to sun50i-a64.dtsi
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Mon, 14 May 2018 15:16:20 +0000 (08:16 -0700)]
pwm: sunxi: add support for PWM found on Allwinner A64
This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Mon, 14 May 2018 20:49:53 +0000 (13:49 -0700)]
video: dw_hdmi: fix HSYNC and VSYNC polarity settings
Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
EDID and vice versa. Fix it, since it breaks displays where HSYNC
and VSYNC polarity differs
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Vasily Khoruzhick [Mon, 14 May 2018 20:49:52 +0000 (13:49 -0700)]
sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.
HSYNC is bit 8, and VSYNC is bit 9.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Ramon Fried [Mon, 14 May 2018 12:02:30 +0000 (15:02 +0300)]
mmc: sdhci: Check that ops are defined
The check is necessary to avoid NULL pointer dereference.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Chris Packham [Thu, 3 May 2018 11:00:35 +0000 (23:00 +1200)]
net: add Kconfig for MVGBE
Add Kconfig for MVGBE and update boards to select this.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 3 May 2018 11:00:34 +0000 (23:00 +1200)]
net: mvgbe: remove CONFIG_DOVE
Nothing defines CONFIG_DOVE so remove the code that uses it.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Chris Packham [Thu, 3 May 2018 08:19:03 +0000 (20:19 +1200)]
net: bootp: Fix compile error processing ntpserver option
When the following configuration is set
# CONFIG_CMD_DHCP is not set
CONFIG_CMD_BOOTP=y
CONFIG_BOOTP_NTPSERVER=y
The following compile error is observed
error: used struct type value where scalar is required
if (net_ntp_server)
^~~~~~~~~~~~~~
Resolve this by checking net_ntp_server.s_addr instead.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Chris Packham [Thu, 3 May 2018 08:19:02 +0000 (20:19 +1200)]
net: Add Kconfig option for BOOTP_NTPSERVER
Add a Kconfig option for BOOTP_NTPSERVER to enable the DHCP/BOOTP option
to configure the sntp server address.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mario Six [Fri, 27 Apr 2018 12:52:21 +0000 (14:52 +0200)]
treewide: Move CONFIG_PHY_MARVELL to Kconfig
The CONFIG_PHY_MARVELL has already been migrated to Kconfig (some boards
already had it in their Kconfig), but had not been moved for older
boards.
Move it to the defconfigs for all boards.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 14 May 2018 22:13:59 +0000 (18:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Jonathan Gray [Tue, 8 May 2018 09:49:05 +0000 (19:49 +1000)]
rockchip: clk: rk3288: handle clk_enable requests for GMAC
Since
b0ba1e7e9d9b9441a18048ec67a3b3100c096975
(rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC)
Ethernet no longer probes on RK3288.
Add no-ops for GMAC clocks observed to be requested which match the
clk_enable cases in RK3368 and RK3399.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jonathan Gray [Tue, 8 May 2018 10:43:01 +0000 (20:43 +1000)]
rockchip: set SYS_NS16550_MEM32 for all SoCs
Add back part of patch send out as
'rockchip: enable SYS_NS16550 for all SoCs by default' that seems to have
gotten lost when it got merged to set SYS_NS16550_MEM32.
Allows serial output to work on tinker-rk3288 again after
c3c0331db1fb7b1f4ff41e144fc04353b37c785c.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Mon, 14 May 2018 12:52:48 +0000 (08:52 -0400)]
Merge git://git.denx.de/u-boot-marvell
Marek Behún [Fri, 11 May 2018 08:03:39 +0000 (10:03 +0200)]
phy: marvell: a3700: Fix compatible string for ehci
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:31 +0000 (13:28 +1200)]
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:30 +0000 (13:28 +1200)]
ARM: mvebu: a38x: restore support for setting timing
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit
90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:29 +0000 (13:28 +1200)]
ARM: mvebu: a38x: sync ddr training code with upstream
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT
INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.
Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:28 +0000 (13:28 +1200)]
ARM: mvebu: a38x: remove some unused code
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:27 +0000 (13:28 +1200)]
ARM: mvebu: a38x: move sys_env_device_rev_get
Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:26 +0000 (13:28 +1200)]
ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:31 +0000 (17:21 +0200)]
arm64: mvebu: Add basic support for the Turris Mox board
This adds basic support for the Turris Mox board from CZ.NIC, which is
currently being crowdfunded on Indiegogo.
Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).
The basic module can be extended by different modules. The device tree
binary for the kernel can be dependent on which modules are connected,
and in what order. Because of this, the board specific code creates
in U-Boot a variable called module_topology, which carries this
information.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:30 +0000 (17:21 +0200)]
watchdog: Add support for Armada 37xx CPU watchdog
This adds support for the CPU watchdog found on Marvell Armada 37xx
SoCs.
There are 4 counters which can be set as CPU watchdog counters.
This driver uses the second counter (ID 1, counting from 0)
(Marvell's Linux also uses second counter by default).
In the future it could be adapted to use other counters, with
definition in the device tree.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:29 +0000 (17:21 +0200)]
net: mvneta: Fix fault when wrong device tree
The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:28 +0000 (17:21 +0200)]
phy: marvell: core: Cosmetic fixes
Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:27 +0000 (17:21 +0200)]
clk: armada-37xx: Support soc_clk_dump
Add support for the clk dump command on Armada 37xx.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:26 +0000 (17:21 +0200)]
spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency
Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.
Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:25 +0000 (17:21 +0200)]
driver: clk: Add support for clocks on Armada 37xx
The drivers are based on Linux driver by Gregory Clement.
The TBG clocks support only the .get_rate method.
- since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again
The peripheral clocks support methods .get_rate, .enable and .disable.
- the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)
- the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:24 +0000 (17:21 +0200)]
phy: marvell: a3700: Save/restore selector reg in SGMII init
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting
the PHY. Since comphy_mux already set the selector register to
correct values, we have to store it's value before setting it to 0
and restore it after SGMII init.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:23 +0000 (17:21 +0200)]
phy: marvell: a3700: Use comphy_mux on Armada 37xx.
Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.
This is needed for Armada 37xx.
This introduces new device tree bindings. AFAIK there is currently no
driver for Armada 37xx comphy in Linux. When such a driver will be
pushed into Linux, this will need to be rewritten accordingly.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:22 +0000 (17:21 +0200)]
phy: marvell: a3700: Fix SGMII cfg and stat register addresses
The register addresses on lanes 0 and 1 are switched, first comes 1 and
then 0.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:21 +0000 (17:21 +0200)]
phy: marvell: mux: Support nontrivial node order in selector register
Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.
Add support for nontrivial order, with map stored in device tree
property mux-lane-order.
This is needed for Armada 37xx.
As far as I know, there is no driver for Armada 37xx comphy in the
kernel. When such a driver comes, this will need to be rewritten to
support the device tree bindings from the kernel.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
zachary [Tue, 24 Apr 2018 15:21:20 +0000 (17:21 +0200)]
phy: marvell: a3700: revise the USB3 comphy setting during power on
This commit is based on commit
d9899826 by
zachary <zhangzg@marvell.com>
from u-boot-marvell, see
github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/
d9899826
- According to design specification, the transmitter should be set to high
impedence mode during electrical idle. Thus transmitter should detect RX
at high impedence mode also, and delay is needed to accommodate high
impedence off latency. Otherwise the USB3 will have detection issue that
most of the time the USB3 device can not be detected at all, or be
detected as USB2 device sometimes.
Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1
Bit 6: set to 1 to let Tx detect Rx at HiZ mode
Bit [3:4]: set to 2 to be delayed by 2 clock cycles
Bit 0: set to 1 to set transmitter to high impedance mode during idle.
- USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2
(emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed
to select 0x1(3.5dB emphasize). Thus need to override what comes from
the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the
overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register
0x181 and bit0 of register 0x180).
- According to USB3 application note, need to update below comphy
registers:
Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1)
Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF)
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:19 +0000 (17:21 +0200)]
phy: marvell: a3700: Set USB3 RX wait depending on ref clock
According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:18 +0000 (17:21 +0200)]
phy: marvell: a3700: Access USB3 register indirectly on lane 2
When USB3 is on comphy lane 2 on the Armada 37xx, the registers
have to be accessed indirectly via SATA indirect access.
This is the case of the Turris Mox board from CZ.NIC.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:17 +0000 (17:21 +0200)]
phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets
Create a special function for indirect register setting,
reg_set_indirect, and use it instead of the two calls to reg_set.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:16 +0000 (17:21 +0200)]
phy: marvell: a3700: Use (!ret) instead of (ret == 0)
In U-Boot it is usually written this way.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:15 +0000 (17:21 +0200)]
phy: marvell: a3700: Use same timeout for all register polling
The timeout is set to PLL_LOCK_TIMEOUT in every call to
comphy_poll_reg. Remove this parameter from the function.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:14 +0000 (17:21 +0200)]
phy: marvell: a3700: Don't create functional macro for each register
Currently there is for each register special functional macro, ie:
LANE_CFG1_ADDR(u)
GLOB_CLK_SRC_LO_ADDR(u)
...
where can be either PCIE or USB3.
Change this to one function PHY_ADDR(unit, addr). The code becomes:
phy_addr(PCIE, LANE_CFG1)
phy_addr(PCIE, GLOB_CLK_SRC_LO)
...
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:13 +0000 (17:21 +0200)]
phy: marvell: a3700: Use reg_set16 instead of phy_write16
The macro phy_write16 is not used by the rest of the code,
phy_read16 is not used at all.
We also change the macro SGMIIPHY_ADDR to a static inline function.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:12 +0000 (17:21 +0200)]
phy: marvell: a3700: Change return type of macro MVEBU_REG
All the calls to reg_set and friends have to cast the first argument
to void __iomem *. Lets change the return type of the MVEBU_REG macro
instead.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Vasut [Sat, 14 Apr 2018 22:37:11 +0000 (00:37 +0200)]
mmc: Improve tinification
Drop all the extra content from the MMC core, so that tiny MMC support
is really tiny, no fancy anything. That means the tiny MMC support does
only 1-bit transfers at default speed settings. Moreover, this patch
drops duplicate instance of struct mmc mmc_static, which wasted about
360 bytes. Furthermore, since MMC tiny supports only one controller
at all times, get rid of mallocating the ext csd backup and replace
it with static array. All in all, this patch saves ~4 kiB of bloat
from the MMC core, which on platforms with severe limitations can be
beneficial.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup checkpatch.pl style warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 11 May 2018 19:22:36 +0000 (15:22 -0400)]
Merge git://git.denx.de/u-boot-tegra
Tom Rini [Fri, 11 May 2018 18:54:57 +0000 (14:54 -0400)]
SPDX: Correct SPDX tags from recent xilinx merge
Correct the SPDX tag format.
Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 11 May 2018 15:45:28 +0000 (11:45 -0400)]
Merge tag 'xilinx-for-v2018.07' of git://denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
scsi:
- convert ceva sata to UCLASS_AHCI
timer:
- Add Cadence TTC for ZynqMP r5
watchdog:
- Minor cadence driver cleanup
Tom Rini [Fri, 11 May 2018 11:09:21 +0000 (07:09 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:10 +0000 (12:37 +0530)]
arm64: zynqmp: Enable UHS support for ZCU102 Rev1.0 board
This patch enables UHS support for ZynqMP zcu102 rev 1.0
board.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:09 +0000 (12:37 +0530)]
mmc: zynq_sdhci: Add support for SD3.0
This patch adds support of SD3.0 for ZynqMP.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:08 +0000 (12:37 +0530)]
mmc: sdhci: Read capabilities register1 and update host caps
This patch reads the capabilities register1 and update the host
caps accordingly for mmc layer usage. This patch mainly reads
for UHS capabilities inorder to support SD3.0.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:07 +0000 (12:37 +0530)]
mmc: sdhci: Invoke platform specific tuning and delay routines
This patch adds support to invoke any platform specific tuning
and delay routines if available.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:06 +0000 (12:37 +0530)]
sdhci: Add new sdhci ops for platform specific tuning and delays
This patch adds new hooks for any platform specific tuning and
tap delays programing. These are needed for supporting
SD3.0.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:05 +0000 (12:37 +0530)]
mmc: sdhci: Handle execute tuning command in sdhci_send_command
This patch upadted sdhci_send_command to handle execute tuning
command.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:04 +0000 (12:37 +0530)]
mmc: sdhci: Add support for disabling clock
This patch adds support to disable clock if clk_disable
was set and then enable or set clock if the clock was changed
or clock was disabled when clock needs to be enabled.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Thu, 3 May 2018 06:50:54 +0000 (12:20 +0530)]
mmc: Changed the datatype of the variable to handle 64-bit arch
This patch changed the datatype of variable "start" from uint to ulong
to work properly on 64-bit machines as well. Also the return type of
get_timer() function is ulong.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Apr 2018 15:39:46 +0000 (17:39 +0200)]
arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.
This configuration with uart1 was tested on zcu100-revC.
U-Boot
2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
Model: Xilinx ZynqMP R5
DRAM: 512 MiB
WARNING: Caches not enabled
MMC:
In: serial@
ff010000
Out: serial@
ff010000
Err: serial@
ff010000
Net: Net Initialization Skipped
No ethernet found.
ZynqMP r5>
There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb
20000000 u-boot-r5.elf
setenv autostart no && bootelf -p
20000000
cpu 4 disable && cpu 4 release
10000000 lockstep
or
cpu 4 disable && cpu 4 release
10000000 split
2. Load via jtag when directly to R5
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:52 +0000 (14:18 +0200)]
tools: zynqmpimage: Add bif support
The officially described way to generate boot.bin files for ZynqMP is to
describe the contents of the target binary using a file of the "bif"
format. This file then links to other files that all get packed into a
bootable image.
This patch adds support to read such a .bif file and generate a respective
ZynqMP boot.bin file that can include the normal image and pmu files, but
also supports image partitions now. This makes it a handy replacement for
the proprietary "bootgen" utility that is currently used to generate
boot.bin files with FSBL.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:51 +0000 (14:18 +0200)]
MAINTAINERS: Declare tools/zynqmp* as Xilinx maintained
The zynqmpimage.c and the new zynqmpbif.c files are all maintained by
Xilinx for the Zynq platforms. Let's match them accordingly
in the MAINTAINERS file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:50 +0000 (14:18 +0200)]
tools: zynqmpimage: Move defines to header
We will add support for ZynqMP bif input files later, so let's move
all structure definitions into a header file that can be used by that
one as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:49 +0000 (14:18 +0200)]
tools: zynqmpimage: Add partition read support
The zynqmp image format has support for inline partitions which are
used by FSBL to describe payloads that are loaded by FSBL itself.
While we can't create images that contain partitions (yet), we should
still at least be able to examine them and show the user what's inside
when we analyze an image created by bootgen.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 30 Apr 2018 07:26:47 +0000 (09:26 +0200)]
arm64: zynqmp: Show model information instead of custom IDENT_STRING
DISPLAY_BOARDINFO in OF case show model identification string from DT.
Enable this feature instead of custom IDENT_STRING which does the same
thing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Michal Simek [Wed, 25 Apr 2018 09:10:34 +0000 (11:10 +0200)]
arm64: zynqmp: Simplify boot_target variable composition
Call calloc for space allocation only at one location and include if/else
to sprintf. This will simplify run time device adding based on id aliases.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Nitin Jain [Fri, 20 Apr 2018 07:00:40 +0000 (12:30 +0530)]
arm64: zynqmp: Setup MMU map for DDR at run time
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.
The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.
Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:43:50 +0000 (15:43 +0200)]
arm64: zynqmp: Enable cadence WDT for zcu100
Enable watchdog on zcu100 to make sure if there is a bug in the u-boot
there is proper reset.
Watchdog expires and PMU fw is informed and based on setting proper
action is taken.
The patch is enabling reset-on-timeout feature and also fixing fixed
clock rate for watchdog where 100MHz is max (and also default) clock value.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:43:38 +0000 (15:43 +0200)]
arm64: zynqmp: Wire watchdog internals
Enable watchdog in full U-Boot.
Similar changes were done by:
"arm: zynq: Wire watchdog internals"
(sha1:
e6cc3b25d721c3001019f8b44bfaae2a57255162)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:22:04 +0000 (15:22 +0200)]
watchdog: cadence: Show used timeout value
Debug message was showing timeout value which was passed to start
function but there is a checking if this value can be setup.
The patch is moving this debug printf function below checking.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 12:41:11 +0000 (14:41 +0200)]
arm64: zynqmp: Reset FPD Watchdog on zcu100
Low level configuration didn't reset FPD Watchdog that's why accessing
it caused u-boot hang.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 25 May 2017 06:45:24 +0000 (12:15 +0530)]
nand: zynq: Send address cycles as per onfi parameter page
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 25 May 2017 08:55:55 +0000 (14:25 +0530)]
nand: zynq: Add support for 16-bit buswidth
This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 Apr 2018 13:00:43 +0000 (15:00 +0200)]
MAINTAINERS: zynqmp: Point to proper zynqmp folder
Point to Zynqmp arm64 cpu folder not to Zynq arm32.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 Apr 2018 10:52:48 +0000 (12:52 +0200)]
serial: zynq: Remove header depedency on arm header structure
There is no need to have arm hardware header in this driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 17 Apr 2018 11:40:46 +0000 (13:40 +0200)]
timer: Add Cadence TTC timer counter support
This driver was tested on Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 3 Jan 2018 07:45:29 +0000 (13:15 +0530)]
microblaze: Dont enable UBI support by default
This patch removes UBI support from defconfig and it can
be enabled from menuconfig as per need.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 11 Apr 2018 08:43:05 +0000 (14:13 +0530)]
arm64: zynqmp: Add new defconfig for zc1275 revB
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Apr 2018 11:32:52 +0000 (13:32 +0200)]
scsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSI
In v2018 the patch
"dm: ahci: Correct uclass private data"
(sha1:
bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd)
was causing an issue for ceva_sata.
But this issue is not in v2018.05-rc1 but still converting to
UCLASS_AHCI would make more sense.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 28 Feb 2018 08:50:07 +0000 (09:50 +0100)]
arm: zynq: Remove checkboard and enable DISPLAY_CPUINFO
Now that showing silicon version is part of the CPU
info display, let's remove checkboard().
Note that the generic show_board_info() will still
show the DT 'model' property. For instance:
U-Boot
2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200)
CPU: Zynq 7z045
Silicon: v1.0
Model: Zynq ZC706 Development Board
I2C: ready
Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>,
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
mini configuration doesn't need to show this information.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 17 Jan 2018 13:56:22 +0000 (10:56 -0300)]
arm: zynq: Rework FPGA initialization
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.
Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 10:36:48 +0000 (12:36 +0200)]
arm: zynq: Enable debug_uart_init in spl when enabled
In past this code was commented and was used for debug purpose.
But there is no reason not to enabled it based on macros.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Fri, 11 May 2018 02:57:41 +0000 (22:57 -0400)]
Merge git://git.denx.de/u-boot-socfpga
Tom Rini [Mon, 7 May 2018 21:02:21 +0000 (17:02 -0400)]
SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed. These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict. This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.
Fixes: 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Heinrich Schuchardt [Mon, 7 May 2018 21:00:22 +0000 (23:00 +0200)]
tools/file2include: avoid incorrect comments
Avoid creating incorrect comments like /* ...*/... */ by printing
'.' instead of '*' inside comments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 7 May 2018 20:18:27 +0000 (22:18 +0200)]
include: update log2 header from the Linux kernel
Without the patch gcc 8 produces:
warning: ignoring attribute ‘noreturn’ because it conflicts with
attribute ‘const’ [-Wattributes]
int ____ilog2_NaN(void);
So let's update the include from Linux kernel v4.16.
This removes static checks of ilog2() arguments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 7 May 2018 19:59:34 +0000 (21:59 +0200)]
xyz-modem: va_start() must be matched by va_end()
Every va_start() call must be matched by a va_end() call.
scripts/checkpatch.pl required reformatting the complete function
zm_dprintf().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 7 May 2018 18:38:24 +0000 (20:38 +0200)]
tools/file2include: create Linux style SPDX header
file2include is used to convert a binary file to a C include.
With the patch the SPDX header is written to the first line as
expected by scripts/checkpatch.pl.
Cf. https://www.kernel.org/doc/html/v4.16/process/license-rules.html
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Hannes Schmelzer [Fri, 4 May 2018 08:49:11 +0000 (10:49 +0200)]
bootm: fix 'memory-fixup' for vxWorks boot
The check for having a memory node within the fdt blob is made wrong, we
fix this here.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Alex Kiernan [Thu, 3 May 2018 11:45:08 +0000 (11:45 +0000)]
Fix Ymodem build when DEBUG and CONFIG_USE_TINY_PRINTF are selected
Attempting to build with both DEBUG and CONFIG_USE_TINY_PRINTF along
with CONFIG_SPL_YMODEM_SUPPORT fails at link time:
common/built-in.o: In function `zm_dprintf':
common/xyzModem.c:190: undefined reference to `vsprintf'
Disable Ymodem debug if we don't have full vsprintf support.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Fabio Estevam [Wed, 2 May 2018 23:12:07 +0000 (20:12 -0300)]
board/freescale: Remove invalid fsl email addresses
These fsl email addresses are no longer valid and they do not have a
correspondent nxp.com entry.
Remove all invalid fsl email addresses and mark the boards as orphan.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Wed, 2 May 2018 23:12:06 +0000 (20:12 -0300)]
p1022ds: Change Timur's email address
timur@freescale.com is not a valid email for quite some time, so change
it to Timur's updated email.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Timur Tabi <timur@tabi.org>
Lukasz Majewski [Wed, 2 May 2018 14:10:56 +0000 (16:10 +0200)]
bootcount: display5: config: Enable boot count feature in the display5 board
The boot count is enabled in both SPL and proper u-boot.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Lukasz Majewski [Wed, 2 May 2018 14:10:55 +0000 (16:10 +0200)]
bootcount: display5: spl: Extend DISPLAY5 board SPL to support bootcount checking
This patch is necessary for providing basic bootcount checking in the case
of using "falcon" boot mode in that board.
It forces u-boot proper boot, when we exceed the number of errors.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Lukasz Majewski [Wed, 2 May 2018 14:10:54 +0000 (16:10 +0200)]
bootcount: spl: Extend SPL to support bootcount incrementation
This patch adds support for incrementation of the bootcount in SPL.
Such feature is necessary when we do want to use this feature with
'falcon' boot mode (which loads OS directly in SPL).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lukasz Majewski [Wed, 2 May 2018 14:10:53 +0000 (16:10 +0200)]
bootcount: Rewrite autoboot to use wrapper functions from bootcount.h
The code has been refactored to use common wrappers from bootcount.h
header.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
Lukasz Majewski [Wed, 2 May 2018 14:10:52 +0000 (16:10 +0200)]
bootcount: Add function wrappers to handle bootcount increment and error checking
Those two functions can be used to provide easy bootcount management.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Lukasz Majewski [Wed, 2 May 2018 14:10:51 +0000 (16:10 +0200)]
bootcount: Add include guards into bootcount.h file
This patch adds missing include guards for bootcount.h file.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
Lukasz Majewski [Wed, 2 May 2018 14:10:50 +0000 (16:10 +0200)]
bootcount: spl: Enable bootcount support in SPL
New, SPL related config option - CONFIG_SPL_BOOTCOUNT_LIMIT has been
added to allow drivers/bootcount code re-usage in SPL.
This code is necessary to use and setup bootcount in SPL in the case of
falcon boot mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
Marcel Ziswiler [Tue, 8 May 2018 22:18:40 +0000 (00:18 +0200)]
apalis_t30: fix optional pcie port reset for reliable pcie operation
Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe
port are also left disabled in the device tree by default.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>