platform/kernel/u-boot.git
5 years agoriscv: set CONFIG_SYS_BOOTM_LEN to SZ_64M
David Abdurachmanov [Tue, 9 Apr 2019 10:42:46 +0000 (12:42 +0200)]
riscv: set CONFIG_SYS_BOOTM_LEN to SZ_64M

After updating Fedora/RISCV kernel to 5.1-rc3+ the size increased above
the current threshold. Looking into HiKey, Dragonboards, etc. seems that
SZ_64M is a popular option.

This sucessfully boots Fedora/RISCV with 5.1-rc3+ kernel on QEMU 4.0 (master)
with OpenSBI -> U-Boot (S-mode) [extlinux] -> Kernel setup.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sunxi
Tom Rini [Wed, 8 May 2019 20:21:43 +0000 (16:21 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi

- H6 Beelink GS1 board (ClĂ©ment)
- Olimex A64-Teres-I board (Jonas)
- sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej)
- Change include order (Jagan)
- EPHY clock changes (Jagan)
- EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)

5 years agosunxi: Enable EMAC on the Bananapi M3
Chen-Yu Tsai [Fri, 3 May 2019 02:27:41 +0000 (10:27 +0800)]
sunxi: Enable EMAC on the Bananapi M3

The Bananapi M3 has an RTL8211E PHY connected to the EMAC using
RGMII. The PHY is powered by DCDC1 through SW @ 3.3V.

The board is designed to use 3.3V with RGMII, instead of the standard
reduced voltage of 2.5V we see everywhere. DLDO3, which provides the
I/O voltages, is raised to match.

This patch enables the EMAC and Realtek PHY drivers in the defconfig.
The device tree file already has the EMAC enabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agosunxi: Enable EMAC on the Cubietruck Plus
Chen-Yu Tsai [Fri, 3 May 2019 02:27:40 +0000 (10:27 +0800)]
sunxi: Enable EMAC on the Cubietruck Plus

The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using
RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are
powered by DLDO3 @ 2.5V.

This patch enables the EMAC and Realtek PHY drivers in the defconfig.
The device tree file already has the EMAC enabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agosun50i: a64: Add Olimex A64-Teres-I board initial support
Jonas Smedegaard [Sat, 20 Apr 2019 10:24:16 +0000 (18:24 +0800)]
sun50i: a64: Add Olimex A64-Teres-I board initial support

Olimex A64-Teres-I board is a mainboard (the only one so far)
for Olimex Teres-I DIY laptop kit.

Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- MicroSD Slot
- 16GB eMMC Flash
- eDP LCD display
- HDMI
- USB Host
- Battery management
- 5V DC power supply
- Certified Open Source Hardware (OSHW)

Works:
- i2C
- MMC/SD
- PWM backlight

Known broken:
- Internal keyboard (seems to be because the keyboard firmware loads a
bootloader first, and then disconnects bootloader and connect real
keyboard). External ones connected to the USB port work fine.

This patch enables support for the A64-Teres-I board to u-boot,
including enabling screen backlight (lacking from Linux device-tree).

Linux commit details about the sun50i-a64-teres-i.dts sync:
"arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins"
(sha1: d91ebb95b96c8840932dc3a10c9f243712555467)

Cosmetic warnings regarding whitespace and placement of SPDX notice for
dts file was ignored.

config and .dtsi file are adapted from pinebook files.

Tested-by: Jonas Smedegaard <dr@jones.dk>
Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: move board entry in MAINTAINERS file at proper position]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agonet: sun8i_emac: Add EPHY CLK and RESET support
Jagan Teki [Wed, 27 Feb 2019 18:57:00 +0000 (00:27 +0530)]
net: sun8i_emac: Add EPHY CLK and RESET support

Add EPHY CLK and RESET support for sun8i_emac driver to
enable EPHY TX clock and EPHY reset pins via CLK and RESET
framework.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agotest/dm: reset: Add reset_get_by_index[_nodev] test
Jagan Teki [Wed, 27 Feb 2019 18:56:56 +0000 (00:26 +0530)]
test/dm: reset: Add reset_get_by_index[_nodev] test

Add sample dm reset test for reset_get_by_index and
reset_get_by_index_nodev functionality code.

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoreset: Get the RESET by index without device
Jagan Teki [Wed, 27 Feb 2019 18:56:55 +0000 (00:26 +0530)]
reset: Get the RESET by index without device

Getting a RESET by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process RESET operation for child
without udevice but with ofnode.

So add reset_get_by_index_nodev() and move the common code
in reset_get_by_index_tail() to use for reset_get_by_index()

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotest/dm: clk: Add clk_get_by_index[_nodev] test
Jagan Teki [Tue, 5 Mar 2019 14:12:44 +0000 (19:42 +0530)]
test/dm: clk: Add clk_get_by_index[_nodev] test

Add sample dm clk test for clk_get_by_index and
clk_get_by_index_nodev functionality code.

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoclk: Use clk_get_by_index_tail()
Jagan Teki [Wed, 27 Feb 2019 18:56:53 +0000 (00:26 +0530)]
clk: Use clk_get_by_index_tail()

clk_get_by_index_tail() now handle common clk get by index
code so use it from clk_get_by_indexed_prop().

Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agoclk: Get the CLK by index without device
Jagan Teki [Wed, 27 Feb 2019 18:56:52 +0000 (00:26 +0530)]
clk: Get the CLK by index without device

Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.

So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoserial: sifive: Change include order
Jagan Teki [Wed, 8 May 2019 14:26:16 +0000 (19:56 +0530)]
serial: sifive: Change include order

Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the serial_sifive driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/riscv/include/asm/u-boot.h:23:0,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from drivers/serial/serial_sifive.c:6:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in serial_sifive.c to include first common.h file.

Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agoclk: sifive: fu540-prci: Change include order
Jagan Teki [Wed, 8 May 2019 14:22:18 +0000 (19:52 +0530)]
clk: sifive: fu540-prci: Change include order

Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the fu540-prci driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/riscv/include/asm/u-boot.h:23:0,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from include/clk-uclass.h:13,
                 from drivers/clk/sifive/fu540-prci.c:32:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in fu540-prci.c to include first common.h file.

Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agospi: atcspi200: Change include order
Jagan Teki [Wed, 8 May 2019 14:12:16 +0000 (19:42 +0530)]
spi: atcspi200: Change include order

Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/nds32/include/asm/u-boot.h:24,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from drivers/spi/atcspi200_spi.c:9:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in atcspi200_spi.c to include first common.h file.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Wed, 8 May 2019 13:20:19 +0000 (09:20 -0400)]
Merge git://git.denx.de/u-boot-x86

- Allow x86 boards to use TPL, SPL and U-Boot proper
- Update sysreset x86 driver to utilize ACPI registers to do power off
- Add a new chromebook_samus_tpl board for TPL support
- Several minor changes in binman tool

5 years agoMerge tag 'efi-2019-07-rc2-2' of git://git.denx.de/u-boot-efi
Tom Rini [Wed, 8 May 2019 13:20:04 +0000 (09:20 -0400)]
Merge tag 'efi-2019-07-rc2-2' of git://git.denx.de/u-boot-efi

Pull request for UEFI sub-system for v2019.07-rc2 (2)

Fix a bunch of errors in the UEFI sub-system:

* implement missing UnloadImage(),
* implement missing RegisterProtocolNotify(),
* unload images in Exit(),
* parameter checks.

Provide a unit test for UnloadImage().
Remove a redundant function for unit tests.
Clean up the UEFI sub-system initialization

5 years agox86: samus: Add a target to boot through TPL
Simon Glass [Wed, 8 May 2019 03:41:16 +0000 (21:41 -0600)]
x86: samus: Add a target to boot through TPL

Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: samus: Update device tree for verified boot
Simon Glass [Wed, 8 May 2019 03:41:14 +0000 (21:41 -0600)]
x86: samus: Update device tree for verified boot

Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: samus: Update device tree for SPL
Simon Glass [Wed, 8 May 2019 03:41:13 +0000 (21:41 -0600)]
x86: samus: Update device tree for SPL

Add tags to allow required nodes to be present in SPL / TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a simple TPL implementation
Simon Glass [Thu, 2 May 2019 16:52:12 +0000 (10:52 -0600)]
x86: Add a simple TPL implementation

Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a way to jump from TPL to SPL
Simon Glass [Thu, 2 May 2019 16:52:27 +0000 (10:52 -0600)]
x86: Add a way to jump from TPL to SPL

When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: samus: Increase the pre-reloc memory again
Simon Glass [Thu, 2 May 2019 16:52:22 +0000 (10:52 -0600)]
x86: samus: Increase the pre-reloc memory again

This is again too small, so increase it slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Update PCH to work in TPL
Simon Glass [Thu, 2 May 2019 16:52:26 +0000 (10:52 -0600)]
x86: broadwell: Update PCH to work in TPL

The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Enable the RTC on all boards
Simon Glass [Thu, 2 May 2019 16:52:24 +0000 (10:52 -0600)]
x86: Enable the RTC on all boards

With the move to Kconfig this option should be set in Kconfig, not in the
config header file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Fix device-tree indentation
Simon Glass [Thu, 2 May 2019 16:52:21 +0000 (10:52 -0600)]
x86: Fix device-tree indentation

With the use of a phandle we can outdent the device tree nodes a little.
Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Update device tree for Chromium OS verified boot
Simon Glass [Thu, 2 May 2019 16:52:20 +0000 (10:52 -0600)]
x86: Update device tree for Chromium OS verified boot

The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Update device tree for TPL
Simon Glass [Thu, 2 May 2019 16:52:19 +0000 (10:52 -0600)]
x86: Update device tree for TPL

Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add documentation on the samus flashmap
Simon Glass [Thu, 2 May 2019 16:52:16 +0000 (10:52 -0600)]
x86: Add documentation on the samus flashmap

There are quite a few variables which control where things appear in the
final ROM image. Add a flashmap in the documentation to make this easier
to figure out.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed "x86: Update the memory map a little" in]
[bmeng: fixed typo of 'documentation' in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support PCI VGA ROM when TPL is used
Simon Glass [Fri, 26 Apr 2019 03:59:08 +0000 (21:59 -0600)]
x86: Support PCI VGA ROM when TPL is used

When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Don't generate a bootstage report in SPL
Simon Glass [Fri, 26 Apr 2019 03:59:07 +0000 (21:59 -0600)]
x86: Don't generate a bootstage report in SPL

This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Don't set up MTRRs in SPL
Simon Glass [Fri, 26 Apr 2019 03:59:06 +0000 (21:59 -0600)]
x86: Don't set up MTRRs in SPL

The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support TPL in Intel common code
Simon Glass [Fri, 26 Apr 2019 03:59:05 +0000 (21:59 -0600)]
x86: Support TPL in Intel common code

Update the Makefie rules to ensure that the correct files are built when
TPL is being used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: sysreset: Implement the get_last() method
Simon Glass [Thu, 2 May 2019 16:52:15 +0000 (10:52 -0600)]
x86: sysreset: Implement the get_last() method

Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: sysreset: Implement power-off if available
Simon Glass [Thu, 2 May 2019 16:52:14 +0000 (10:52 -0600)]
x86: sysreset: Implement power-off if available

On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: sysreset: Separate out the EFI code
Simon Glass [Thu, 2 May 2019 16:52:13 +0000 (10:52 -0600)]
x86: sysreset: Separate out the EFI code

The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.

Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Implement PCH_REQ_PMBASE_INFO
Simon Glass [Fri, 26 Apr 2019 03:59:03 +0000 (21:59 -0600)]
x86: broadwell: Implement PCH_REQ_PMBASE_INFO

Implement this ioctl() to support power off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: ivybridge: Implement PCH_REQ_PMBASE_INFO
Simon Glass [Fri, 26 Apr 2019 03:59:02 +0000 (21:59 -0600)]
x86: ivybridge: Implement PCH_REQ_PMBASE_INFO

Implement this ioctl() to support power off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: pch: Add an ioctl to read power-management info
Simon Glass [Fri, 26 Apr 2019 03:59:01 +0000 (21:59 -0600)]
x86: pch: Add an ioctl to read power-management info

Add a new ioctl() request to read information about the power-management
system. This can be used to power off the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: mrccache: Add more debugging
Simon Glass [Fri, 26 Apr 2019 03:58:59 +0000 (21:58 -0600)]
x86: mrccache: Add more debugging

When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support saving MRC data from SPL
Simon Glass [Fri, 26 Apr 2019 03:58:57 +0000 (21:58 -0600)]
x86: Support saving MRC data from SPL

When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add common Intel code for SPL
Simon Glass [Fri, 26 Apr 2019 03:58:56 +0000 (21:58 -0600)]
x86: Add common Intel code for SPL

Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Select refcode and CPU code for SPL
Simon Glass [Fri, 26 Apr 2019 03:58:55 +0000 (21:58 -0600)]
x86: broadwell: Select refcode and CPU code for SPL

Allow broadwell to build for SPL and include the reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Allow booting from SPL
Simon Glass [Fri, 26 Apr 2019 03:58:54 +0000 (21:58 -0600)]
x86: broadwell: Allow booting from SPL

At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Allow 16-bit init to be in TPL
Simon Glass [Fri, 26 Apr 2019 03:58:53 +0000 (21:58 -0600)]
x86: Allow 16-bit init to be in TPL

At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add support for starting from SPL/TPL
Simon Glass [Fri, 26 Apr 2019 03:58:52 +0000 (21:58 -0600)]
x86: Add support for starting from SPL/TPL

When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.

Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Split CPU init
Simon Glass [Fri, 26 Apr 2019 03:58:51 +0000 (21:58 -0600)]
x86: broadwell: Split CPU init

Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Move init of debug UART to cpu.c
Simon Glass [Fri, 26 Apr 2019 03:58:50 +0000 (21:58 -0600)]
x86: broadwell: Move init of debug UART to cpu.c

At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Allow SDRAM init from SPL
Simon Glass [Fri, 26 Apr 2019 03:58:49 +0000 (21:58 -0600)]
x86: broadwell: Allow SDRAM init from SPL

At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Improve SDRAM debugging output
Simon Glass [Fri, 26 Apr 2019 03:58:48 +0000 (21:58 -0600)]
x86: broadwell: Improve SDRAM debugging output

Add debugging during SDRAM init so that problems are easier to
diagnose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a handoff header file
Simon Glass [Fri, 26 Apr 2019 03:58:47 +0000 (21:58 -0600)]
x86: Add a handoff header file

Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support booting with TPL
Simon Glass [Fri, 26 Apr 2019 03:58:46 +0000 (21:58 -0600)]
x86: Support booting with TPL

Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.

Add a new Kconfig option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support SPL and TPL
Simon Glass [Fri, 26 Apr 2019 03:58:45 +0000 (21:58 -0600)]
x86: Support SPL and TPL

At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.

Enable the options for both along with some suitable default options
needed to boot through these phases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: dts: Add device-tree labels for rtc and reset
Simon Glass [Fri, 26 Apr 2019 03:58:43 +0000 (21:58 -0600)]
x86: dts: Add device-tree labels for rtc and reset

Add labels for these nodes so that board DT files can reference them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a way to reinit the cpu
Simon Glass [Fri, 26 Apr 2019 03:58:42 +0000 (21:58 -0600)]
x86: Add a way to reinit the cpu

We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: mp_init: Use proper error numbers
Simon Glass [Fri, 26 Apr 2019 03:58:41 +0000 (21:58 -0600)]
x86: mp_init: Use proper error numbers

At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Update a stale comment about ifdtool
Simon Glass [Fri, 26 Apr 2019 03:58:44 +0000 (21:58 -0600)]
x86: Update a stale comment about ifdtool

We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: start64: Fix copyright message
Simon Glass [Fri, 26 Apr 2019 03:58:40 +0000 (21:58 -0600)]
x86: start64: Fix copyright message

There is a typo in this header. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoRevert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
Simon Glass [Wed, 8 May 2019 03:41:15 +0000 (21:41 -0600)]
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"

This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.

Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.

The offending line is in UCLASS_DRIVER(pci):

.per_device_auto_alloc_size = sizeof(struct pci_controller),

This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.

For now, revert the commit to get things running again.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agocros_ec: Use a hyphen in the uclass name
Simon Glass [Thu, 2 May 2019 16:52:11 +0000 (10:52 -0600)]
cros_ec: Use a hyphen in the uclass name

Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.

This allows device-tree aliases to be used to refer to cros-ec devices,
for example:

aliases {
    cros-ec0 = &ec;
    cros-ec1 = &pd;
};

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agospl: Allow sandbox to build a device-tree file
Simon Glass [Fri, 26 Apr 2019 03:58:38 +0000 (21:58 -0600)]
spl: Allow sandbox to build a device-tree file

At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.

Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:

   $(CONFIG_$(SPL_TPL_)OF_CONTROL)
   $(CONFIG_OF_SEPARATE)
   $(CONFIG_$(SPL_TPL_)OF_PLATDATA)

producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agodm: core: Fix translate condition in ofnode_get_addr_size()
Simon Glass [Fri, 26 Apr 2019 03:58:36 +0000 (21:58 -0600)]
dm: core: Fix translate condition in ofnode_get_addr_size()

Update the condition to translate only if this is enabled for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Allow sections to have an offset
Simon Glass [Fri, 26 Apr 2019 03:58:39 +0000 (21:58 -0600)]
binman: Allow sections to have an offset

At present sections are always placed automatically. Even if an 'offset'
property is provided it is ignored. Update the logic to support an offset
for sections.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Add a missing comment in Entry_vblock
Simon Glass [Fri, 26 Apr 2019 03:58:35 +0000 (21:58 -0600)]
binman: Add a missing comment in Entry_vblock

An important property is missing. Update the entry comment to include
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Don't show image-skip message by default
Simon Glass [Fri, 26 Apr 2019 03:58:34 +0000 (21:58 -0600)]
binman: Don't show image-skip message by default

This message is not very important since it is simply indicating that the
user's instructions are being followed. Only show it when the verbosity
level is above the default.

Also drop the unnecessary extra newline on this message, which causes two
line breaks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Don't generate an error in 'text' entry constructor
Simon Glass [Fri, 26 Apr 2019 03:58:33 +0000 (21:58 -0600)]
binman: Don't generate an error in 'text' entry constructor

It is not good practice to raise an exception in a constructor. In this
case the 'text' entry may not actually be used, if -i is used to filter
out the images that get built.

Move the exception to where the data is actually used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoefi_loader: signature of ExitBootServices()
Heinrich Schuchardt [Sun, 5 May 2019 19:58:35 +0000 (21:58 +0200)]
efi_loader: signature of ExitBootServices()

Consistently use efi_uintn_t as type of memory keys.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <graf@amazon.com>
5 years agoefi_loader: LoadImage() check source size
Heinrich Schuchardt [Sun, 5 May 2019 14:55:06 +0000 (16:55 +0200)]
efi_loader: LoadImage() check source size

If the size of the source buffer is 0, return EFI_LOAD_ERROR.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.6)

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: LoadImage() check parent image
Heinrich Schuchardt [Sun, 5 May 2019 14:55:06 +0000 (16:55 +0200)]
efi_loader: LoadImage() check parent image

If the parent image handle does not refer to a loaded image return
EFI_INVALID_PARAMETER.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.1)

Mark our root node as a loaded image to avoid an error when using it as
parent image.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: HandleProtocol parameter checks
Heinrich Schuchardt [Sun, 5 May 2019 09:24:53 +0000 (11:24 +0200)]
efi_loader: HandleProtocol parameter checks

HandleProtocol() and OpenProtocol() have to return EFI_UNSUPPORTED if the
protocol is not installed on the handle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: use EFI_PRINT instead of debug
Heinrich Schuchardt [Sun, 5 May 2019 09:56:23 +0000 (11:56 +0200)]
efi_loader: use EFI_PRINT instead of debug

For correct indentation of messages in the UEFI API implementation use
EFI_PRINT() instead of debug().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: CloseProtocol() requires valid agent handle
Heinrich Schuchardt [Sun, 5 May 2019 08:37:51 +0000 (10:37 +0200)]
efi_loader: CloseProtocol() requires valid agent handle

Return EFI_INVALID_PARAMETER from CloseProtcol() if the agent handle is not
valid.

Return EFI_INVALID_PARAMETER if the optional controller handle is not
valid.

Return immediately from efi_search_obj if the handle is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_selftest: unit test for RegisterProtocolNotify()
Heinrich Schuchardt [Sat, 4 May 2019 20:44:13 +0000 (22:44 +0200)]
efi_selftest: unit test for RegisterProtocolNotify()

Provide a unit test for the RegisterProtocolNotify() boot service.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: implement RegisterProtocolNotify()
Heinrich Schuchardt [Sat, 4 May 2019 15:27:54 +0000 (17:27 +0200)]
efi_loader: implement RegisterProtocolNotify()

The RegisterProtocolNotify() boot service registers an event to be
notified upon the installation of a protocol interface with the
specified GUID.

Add the missing implementation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: EVT_NOTIFY_SIGNAL events
Heinrich Schuchardt [Sat, 4 May 2019 22:07:34 +0000 (00:07 +0200)]
efi_loader: EVT_NOTIFY_SIGNAL events

The notification function of events of type EVT_NOTIFY_SIGNAL should always
be queued when SignalEvent() is called.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_selftest: remove redundant function efi_st_memcmp()
Heinrich Schuchardt [Sat, 4 May 2019 17:48:38 +0000 (19:48 +0200)]
efi_selftest: remove redundant function efi_st_memcmp()

Function memcmp() is available in efi_freestanding.c. So we do not remove a
further implementation.

Replace all usages of efi_st_memcmp() by memcmp().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: unload applications upon Exit()
Heinrich Schuchardt [Wed, 1 May 2019 18:07:04 +0000 (20:07 +0200)]
efi_loader: unload applications upon Exit()

Implement unloading of images in the Exit() boot services:

* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: implement UnloadImage()
Heinrich Schuchardt [Wed, 1 May 2019 16:25:45 +0000 (18:25 +0200)]
efi_loader: implement UnloadImage()

Implement the UnloadImage() boot service

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: move efi_unload_image() down in source
Heinrich Schuchardt [Wed, 1 May 2019 17:04:32 +0000 (19:04 +0200)]
efi_loader: move efi_unload_image() down in source

Move efi_unload_image() down in source to avoid forward declaration in
follwing page.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: mark started images
Heinrich Schuchardt [Wed, 1 May 2019 12:20:18 +0000 (14:20 +0200)]
efi_loader: mark started images

In UnloadImage() we need to know if an image is already started.

Add a field to the handle structure identifying loaded and started images.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: correct parameter check in LocateHandle()
Heinrich Schuchardt [Sat, 4 May 2019 15:37:32 +0000 (17:37 +0200)]
efi_loader: correct parameter check in LocateHandle()

If LocateHandle() does not find an entry EFI_NOT_FOUND has to be returned
even if BufferSize is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: allowable event types in CreateEventEx()
Heinrich Schuchardt [Sat, 4 May 2019 08:12:50 +0000 (10:12 +0200)]
efi_loader: allowable event types in CreateEventEx()

CreateEventEx() does not allow the following event types:

* EVT_SIGNAL_EXIT_BOOT_SERVICES
* EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE

This check is needed to pass the UEFI SCT conformance test.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@csgraf.de>
5 years agoefi_loader: clean up UEFI sub-system initialization
Heinrich Schuchardt [Sat, 4 May 2019 09:47:48 +0000 (11:47 +0200)]
efi_loader: clean up UEFI sub-system initialization

allow_unaligned(), switch_to_non_secure_mode(), and efi_init_obj_list() are
called in sequence in multiple places.

Move calls to allow_unaligned() and switch_to_non_secure_mode() to
efi_init_obj_list().

Remove unused includes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Tue, 7 May 2019 13:38:00 +0000 (09:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

- RZ/A1 addition.
- Old board removal.

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Tue, 7 May 2019 13:37:11 +0000 (09:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Assorted stratix10 fixes.
- DDR driver DM migration.

5 years agoARM: dts: renesas: Add RZ/A1 GR-Peach board
Chris Brandt [Wed, 23 Aug 2017 19:53:59 +0000 (14:53 -0500)]
ARM: dts: renesas: Add RZ/A1 GR-Peach board

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agoARM: dts: renesas: Add RZ/A1 platform code
Chris Brandt [Wed, 23 Aug 2017 19:53:59 +0000 (14:53 -0500)]
ARM: dts: renesas: Add RZ/A1 platform code

Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agospi: rpc: Add support for operation without clock framework
Marek Vasut [Sat, 4 May 2019 16:52:33 +0000 (18:52 +0200)]
spi: rpc: Add support for operation without clock framework

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agonet: sh_eth: Add support for operation without clock framework
Marek Vasut [Wed, 1 May 2019 22:03:26 +0000 (00:03 +0200)]
net: sh_eth: Add support for operation without clock framework

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agonet: sh_eth: Add RZ/A1 support
Marek Vasut [Wed, 1 May 2019 16:20:48 +0000 (18:20 +0200)]
net: sh_eth: Add RZ/A1 support

Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agoserial: sh: Add RZ/A1 support
Marek Vasut [Wed, 1 May 2019 16:20:00 +0000 (18:20 +0200)]
serial: sh: Add RZ/A1 support

Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agotimer: renesas: Add RZ/A1 R7S72100 OSTM timer driver
Marek Vasut [Sat, 4 May 2019 15:30:58 +0000 (17:30 +0200)]
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver

Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agopinctrl: renesas: Add RZ/A1 R7S72100 pin control driver
Marek Vasut [Sat, 4 May 2019 12:17:10 +0000 (14:17 +0200)]
pinctrl: renesas: Add RZ/A1 R7S72100 pin control driver

Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agogpio: renesas: Add RZ/A1 R7S72100 GPIO driver
Marek Vasut [Sat, 4 May 2019 14:00:17 +0000 (16:00 +0200)]
gpio: renesas: Add RZ/A1 R7S72100 GPIO driver

Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agosh: 7785: Remove CPU support
Marek Vasut [Sat, 4 May 2019 11:28:04 +0000 (13:28 +0200)]
sh: 7785: Remove CPU support

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: sh7785lcr: Remove the board
Marek Vasut [Sat, 4 May 2019 11:21:07 +0000 (13:21 +0200)]
sh: sh7785lcr: Remove the board

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: 7724: Remove CPU support
Marek Vasut [Sat, 4 May 2019 11:31:06 +0000 (13:31 +0200)]
sh: 7724: Remove CPU support

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: ecovec: Remove the board
Marek Vasut [Sat, 4 May 2019 11:24:51 +0000 (13:24 +0200)]
sh: ecovec: Remove the board

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: sh7757lcr: Fix copy-paste error in README
Marek Vasut [Sat, 4 May 2019 11:30:05 +0000 (13:30 +0200)]
sh: sh7757lcr: Fix copy-paste error in README

Update the README to use the correct defconfig.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 6 May 2019 11:18:51 +0000 (07:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

- Various pinctrl / gpio fixes for R-Car

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Mon, 6 May 2019 11:18:28 +0000 (07:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

- Important spi-mem fix