Alyssa Rosenzweig [Sat, 12 Feb 2022 15:33:54 +0000 (10:33 -0500)]
panfrost: Inline pan_emit_sfbd_tiler
Easier to read, the common code was already common.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 15:31:40 +0000 (10:31 -0500)]
panfrost: Remove pan_emit_fbd thunking
Use a common interface.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 15:26:14 +0000 (10:26 -0500)]
panfrost: Remove unrelated comment
Not sure what this was supposed to describe, but it's not the code here.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 19:15:17 +0000 (14:15 -0500)]
panfrost: Use txl instead of tex in the blitter
We always blit from a particular level, so it's a waste to compute the LOD.
This corresponds to a simple texture instruction with implement 0 LOD, which is
the optimal texturing path on Bifrost -- it maps to TEXS_2D but does not require
helper invocations.
Functional change on Bifrost: Blit shaders no longer set .computed_lod or
shader_contains_barrier.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 14:59:28 +0000 (09:59 -0500)]
panfrost: Inline pan_blit_emit_dcd
Easier to follow the logic without having a million arguments passed around.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 14:57:45 +0000 (09:57 -0500)]
panfrost: Decouple tiler job and DCD emit
We can share the "emit quad" logic, even though the DCDs differ.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Tue, 8 Feb 2022 19:31:07 +0000 (14:31 -0500)]
panfrost: Annotate slow clears as such
We should realistically be using the clear shaders from PanVK once they're moved
to common.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Tue, 8 Feb 2022 18:49:40 +0000 (13:49 -0500)]
panfrost: Set defaults for deprecated DCD fields
There are always set to true. Don't pollute the driver code with them, make
their existence a local detail to pre-Valhall XML and that's it.
Functional change: "four components per vertex" is now set on vertex job DCDs.
This should be a no-op.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Tue, 8 Feb 2022 18:44:38 +0000 (13:44 -0500)]
panfrost: Use pan_shader_prepare_rsd in blitter
This reduces code duplication and will ease Valhall porting. Functional changes
on v7:
* Shader contains barrier is now set (perf loss, fixed later in series)
* Shader register allocation is now set (perf win)
* Point sprite inverted, no-op for blit shaders
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 21:43:36 +0000 (16:43 -0500)]
pan/mdg: Fix partial execution mode names
cont -> skip, last -> kill, and fix the special case handling. It's just an
enum. Makes the disassembly easier to read and closer to Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Danylo Piliaiev [Thu, 17 Feb 2022 15:02:06 +0000 (17:02 +0200)]
turnip: Always use GMEM for feedback loops in autotuner
For ordinary feedback loops GMEM is a lot faster than sysmem since
we don't set SINGLE_PRIM mode.
For feedback loops with ordered rasterization GMEM should also be
faster.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Danylo Piliaiev [Fri, 18 Feb 2022 17:15:03 +0000 (19:15 +0200)]
turnip: Implement VK_ARM_rasterization_order_attachment_access
Trivially implemented by using A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE.
This extension is useful for emulators e.g. AetherSX2 PS2 emulator and
could drastically improve performance when blending is emulated.
Relevant tests:
dEQP-VK.rasterization.rasterization_order_attachment_access.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Danylo Piliaiev [Tue, 22 Feb 2022 17:35:18 +0000 (19:35 +0200)]
turnip: Merge LRZ and DEPTH_PLANE draw states
They were emitted at the same time. Frees 1 draw state for us to use.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Danylo Piliaiev [Wed, 23 Feb 2022 09:44:23 +0000 (11:44 +0200)]
turnip: Use LATE_Z when there might be depth/stencil feedback loop
Otherwise a shader invocation would read the value which should have
been set AFTER this shader invocation.
Fixes tests:
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers
Fixes:
71595a189a0c372efd520ad51866ca57aa83298c
("tu: Fix feedback loops in sysmem mode")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Paulo Zanoni [Thu, 17 Feb 2022 01:15:01 +0000 (17:15 -0800)]
iris: fix register spilling on compute shaders on XeHP
XeHP scratch space is handled differently. Commit
ae18e1e707c4
implemented support for it, but handled it differently between render
and compute shaders: it calculates scratch_addr differently and
doesn't pin the buffer on compute. Make it work on compute shaders by
calling pin_scratch_space() from iris_compute_walker(), which fixes
both the address and the pinning.
This commit can be verified by the two-year-old-but-still-unreviewed
Piglit MR 234. You can also verify this by running a very simple
compute shader with INTEL_DEBUG=spill_fs.
References: https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/234
Fixes:
ae18e1e707c4 ("iris: Add support for scratch on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15070>
Kenneth Graunke [Thu, 10 Feb 2022 23:45:23 +0000 (15:45 -0800)]
anv: Raise vertex input bindings and attributes limits slightly
This raises our vertex input bindings limit from 28 to 31, and our
vertex input attribute limit from 28 to 29. We could theoretically
go higher, but it will take additional work.
The 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS limits are 33
vertex buffers, and 34 vertex elements. But we need up to two vertex
elements for system values (FirstVertex, BaseVertex, BaseInstance,
DrawID), and we currently use two vertex bindings for those.
There is another hidden limit: our compiler backend only supports the
push model for VS inputs currently. 3DSTATE_VS only allows URB Read
Lengths between [0, 15], which is measured in pairs of inputs, which
means we can theoretically push no more than 32 vertex elements. This
is no artifical limit either, as a vec4 element takes up 4 registers
in the payload, and 32 * 4 = 128, the entire size of our register file.
Plus, the VS Thread payload needs at least g0 and g1 for other things,
so we can really only push 31.
We can theoretically support one additional binding, by combining our
two SGV bindings into a single upload. In order to support additional
vertex elements, we would need to add support to the backend compiler
for the pull model for VS inputs.
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5917
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14991>
Mike Blumenkrantz [Tue, 22 Feb 2022 01:53:21 +0000 (20:53 -0500)]
zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15067>
Mike Blumenkrantz [Mon, 31 Jan 2022 17:26:52 +0000 (12:26 -0500)]
zink: remove zink_descriptor_util_init_null_set()
no longer used
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15067>
Mike Blumenkrantz [Mon, 31 Jan 2022 17:23:22 +0000 (12:23 -0500)]
zink: allow null descriptor set layouts
I got confused while writing this somehow because of the null descriptor
feature, which enables drivers to consume a null descriptor, which has no
relation to a descriptor layout containing no descriptors
failing to accurately use zero descriptors can put layouts over the maximum
per-stage limits, which causes tests to crash
fixes (lavapipe):
KHR-GL46.shading_language_420pack.binding_uniform_block_array
KHR-GL46.multi_bind.dispatch_bind_buffers_base
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15067>
Timur Kristóf [Thu, 17 Feb 2022 09:57:47 +0000 (10:57 +0100)]
ac/nir/ngg: Fix mixed up primitive ID after culling.
When NGG culling is enabled, make sure that the correct
primitive ID is exported by each lane.
Fixes:
e97f0463a8f55d5d407178f74b0cdb916a42aef8 "ac/nir: Implement NGG deferred attribute culling in NIR."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6050
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15055>
Mike Blumenkrantz [Tue, 15 Feb 2022 03:50:14 +0000 (22:50 -0500)]
zink: prune ci lists
I don't know why I thought running GL3.2 and GL4.6 was a good idea,
but it wasn't
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15065>
Emma Anholt [Tue, 1 Feb 2022 06:13:29 +0000 (22:13 -0800)]
turnip: Request no implicit sync when we have no implicit-sync WSI BOs.
I chose to implement this as a global flag in the device, because
otherwise we would end up with extra draw overhead trying to avoid it in
the implicit-sync WSI case, and you're probably going to end up needing
implicit sync anyway because you used one of the BOs in any of the
submitted cmdbufs. To do better than this, we would probably want a
skip-implicit-sync flag on the BOs in the BO list, rather than global on
the submit.
Reports about venus on turnip say that this flag reduces worst-case
QueueSubmit time in a game workload from ~10ms to ~4ms.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14838>
Samuel Pitoiset [Mon, 21 Feb 2022 11:54:48 +0000 (12:54 +0100)]
radv: fix build on BSD
Just disable inotify for BDS systems.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6060
Fixes:
c50557d9612 ("radv: allow applications to dynamically change RADV_FORCE_VRS")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15105>
Alyssa Rosenzweig [Fri, 18 Feb 2022 21:41:24 +0000 (16:41 -0500)]
pan/bi: Add BIFROST_MESA_DEBUG=nosb option
To disable the new scoreboarding optimizations when debugging.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:09:42 +0000 (11:09 -0500)]
pan/bi: Implement basic scoreboarding pass
Extend our existing bi_scoreboard infrastructure with a simple data flow
analysis pass that calculates which dependency slots need waiting. We
still lack a heuristic for selecting dependency slots.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:09:15 +0000 (11:09 -0500)]
pan/bi: Print scoreboarding state
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Fri, 18 Feb 2022 20:28:38 +0000 (15:28 -0500)]
pan/bi: Add scoreboard state to IR
To a limited degree, scoreboarding must be global, so add the data
structures for tracking this to the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:08:03 +0000 (11:08 -0500)]
pan/bi: Clean up nits in liveness analysis
Fix minor silly things.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:07:35 +0000 (11:07 -0500)]
pan/bi: Use bi_exit_block
The "generic" one is a vestige of Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:06:59 +0000 (11:06 -0500)]
pan/bi: Add bi_{start, exit}_block helpers
Useful for data flow analysis.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 17:14:41 +0000 (12:14 -0500)]
pan/bi: Do not cull post-RA staging writes
Bifrost post-RA dead code elimination can cull the destinations of
regular ALU instructions, by weakening from a register write to a
temporary write. However, there is no way to suppress staging writes, so
culling the destinations will result in invalid code generation.
Fixes a regression in
dEQP-GLES3.functional.shaders.switch.switch_in_for_loop_static_vertex
with scoreboarding. The root cause there is the backend dead code
elimination not being sufficiently aggressive in the presence of control
flow. Usually this does not matter, since the backend optimizations are
intended to be local with global optimizations happening in NIR.
Unfortunately, our implementation of IDVS hits this hard. That will need
to be optimized (probably by specializing IDVS shaders in NIR instead of
the backend). In the mean time, let's fix the actual bug affecting
scoreboarding.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 18:12:19 +0000 (13:12 -0500)]
pan/bi: Cull DTSEL_IMM dests in post-RA DCE
They are useless (given the semantics of DTSEL_IMM) and complicate
scoreboarding. Just remove them in the pass that removes all the other silly
register destinations.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Tue, 22 Feb 2022 16:45:54 +0000 (11:45 -0500)]
pan/bi: Clarify requirement for barriers
Barriers need to wait on all outstanding messages. This is more of an API
requirement than a hardware requirement, but it's still an invariant the
scoreboarding pass must respect.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Erik Faye-Lund [Thu, 27 Jan 2022 08:52:56 +0000 (09:52 +0100)]
docs: add license to the redirects script
I always intended this to be covered by the MIT license like with the
rest of my contributions, but somehow forgot to add it.
Let's add that license to make things clear.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14751>
Adam Jackson [Thu, 10 Feb 2022 16:11:38 +0000 (11:11 -0500)]
mesa: Enable GL_NV_pack_subimage
This just legalizes a few of the pixelstore pack parameters in GLES2
that are already legal in desktop and GLES3. glamor takes advantage of
this in the GetImage and software-fallback paths.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14977>
Alyssa Rosenzweig [Fri, 18 Feb 2022 14:47:30 +0000 (09:47 -0500)]
pan/bi: Enable nir_opt_shrink_vectors
total instructions in shared programs: 1939513 -> 1935815 (-0.19%)
instructions in affected programs: 809066 -> 805368 (-0.46%)
helped: 3195
HURT: 865
helped stats (abs) min: 1.0 max: 15.0 x̄: 1.99 x̃: 1
helped stats (rel) min: 0.10% max: 25.00% x̄: 2.26% x̃: 1.28%
HURT stats (abs) min: 1.0 max: 22.0 x̄: 3.09 x̃: 2
HURT stats (rel) min: 0.10% max: 83.33% x̄: 2.67% x̃: 1.39%
95% mean confidence interval for instructions value: -1.00 -0.82
95% mean confidence interval for instructions %-change: -1.34% -1.08%
Instructions are helped.
total tuples in shared programs: 1523194 -> 1521789 (-0.09%)
tuples in affected programs: 745526 -> 744121 (-0.19%)
helped: 2947
HURT: 1844
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.06 x̃: 1
helped stats (rel) min: 0.15% max: 25.00% x̄: 2.65% x̃: 1.59%
HURT stats (abs) min: 1.0 max: 29.0 x̄: 2.54 x̃: 1
HURT stats (rel) min: 0.09% max: 40.00% x̄: 2.32% x̃: 1.52%
95% mean confidence interval for tuples value: -0.39 -0.20
95% mean confidence interval for tuples %-change: -0.85% -0.62%
Tuples are helped.
total clauses in shared programs: 329158 -> 325350 (-1.16%)
clauses in affected programs: 111654 -> 107846 (-3.41%)
helped: 2787
HURT: 498
helped stats (abs) min: 1.0 max: 17.0 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.76% max: 40.00% x̄: 6.92% x̃: 5.26%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.14 x̃: 1
HURT stats (rel) min: 0.87% max: 50.00% x̄: 4.73% x̃: 3.77%
95% mean confidence interval for clauses value: -1.21 -1.10
95% mean confidence interval for clauses %-change: -5.39% -4.93%
Clauses are helped.
total cycles in shared programs: 172084.50 -> 166827.62 (-3.05%)
cycles in affected programs: 74698.83 -> 69441.96 (-7.04%)
helped: 3706
HURT: 568
helped stats (abs) min: 0.
041665999999999315 max: 19.0 x̄: 1.44 x̃: 1
helped stats (rel) min: 0.24% max: 75.00% x̄: 9.48% x̃: 6.90%
HURT stats (abs) min: 0.
041665999999999315 max: 1.0 x̄: 0.15 x̃: 0
HURT stats (rel) min: 0.25% max: 50.00% x̄: 2.21% x̃: 1.42%
95% mean confidence interval for cycles value: -1.28 -1.18
95% mean confidence interval for cycles %-change: -8.18% -7.67%
Cycles are helped.
total arith in shared programs: 57145.04 -> 57211.37 (0.12%)
arith in affected programs: 27595.12 -> 27661.46 (0.24%)
helped: 1933
HURT: 2259
helped stats (abs) min: 0.
041665999999999315 max: 0.75 x̄: 0.09 x̃: 0
helped stats (rel) min: 0.16% max: 33.33% x̄: 2.74% x̃: 1.52%
HURT stats (abs) min: 0.
04166399999999726 max: 1.
3333329999999997 x̄: 0.11 x̃: 0
HURT stats (rel) min: 0.10% max: 100.00% x̄: 2.79% x̃: 1.62%
95% mean confidence interval for arith value: 0.01 0.02
95% mean confidence interval for arith %-change: 0.07% 0.40%
Arith are HURT.
total texture in shared programs: 12857 -> 12857 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0
total vary in shared programs: 11157.75 -> 10222 (-8.39%)
vary in affected programs: 5643 -> 4707.25 (-16.58%)
helped: 3196
HURT: 0
helped stats (abs) min: 0.125 max: 1.875 x̄: 0.29 x̃: 0
helped stats (rel) min: 2.78% max: 75.00% x̄: 18.49% x̃: 15.00%
95% mean confidence interval for vary value: -0.30 -0.29
95% mean confidence interval for vary %-change: -18.88% -18.11%
Vary are helped.
total ldst in shared programs: 146420 -> 140270 (-4.20%)
ldst in affected programs: 66027 -> 59877 (-9.31%)
helped: 2942
HURT: 10
helped stats (abs) min: 1.0 max: 19.0 x̄: 2.09 x̃: 2
helped stats (rel) min: 0.90% max: 100.00% x̄: 16.81% x̃: 8.33%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 2.22% max: 50.00% x̄: 13.03% x̃: 3.33%
95% mean confidence interval for ldst value: -2.15 -2.02
95% mean confidence interval for ldst %-change: -17.53% -15.89%
Ldst are helped.
total quadwords in shared programs: 1398329 -> 1392117 (-0.44%)
quadwords in affected programs: 704641 -> 698429 (-0.88%)
helped: 3677
HURT: 1299
helped stats (abs) min: 1.0 max: 26.0 x̄: 2.51 x̃: 1
helped stats (rel) min: 0.10% max: 26.92% x̄: 2.64% x̃: 1.89%
HURT stats (abs) min: 1.0 max: 20.0 x̄: 2.31 x̃: 1
HURT stats (rel) min: 0.11% max: 44.44% x̄: 2.34% x̃: 1.55%
95% mean confidence interval for quadwords value: -1.34 -1.16
95% mean confidence interval for quadwords %-change: -1.44% -1.25%
Quadwords are helped.
total threads in shared programs: 35234 -> 35311 (0.22%)
threads in affected programs: 119 -> 196 (64.71%)
helped: 91
HURT: 14
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.60 0.87
95% mean confidence interval for threads %-change: 70.08% 89.92%
Threads are helped.
total loops in shared programs: 125 -> 125 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 149 -> 144 (-3.36%)
spills in affected programs: 22 -> 17 (-22.73%)
helped: 1
HURT: 0
total fills in shared programs: 966 -> 956 (-1.04%)
fills in affected programs: 44 -> 34 (-22.73%)
helped: 1
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
Alyssa Rosenzweig [Sat, 19 Feb 2022 00:20:27 +0000 (19:20 -0500)]
pan/bi: Specialize IDVS in NIR
It's a bit more code, but it's needed to chew through control flow since we
don't have a backend version of dead_cf. Results are really good, meaning I
really screwed this up the first time around (hence the cc mesa-stable).
total instructions in shared programs: 1963576 -> 1939513 (-1.23%)
instructions in affected programs: 671053 -> 646990 (-3.59%)
helped: 4436
HURT: 729
helped stats (abs) min: 1.0 max: 43.0 x̄: 5.75 x̃: 6
helped stats (rel) min: 0.21% max: 100.00% x̄: 6.47% x̃: 5.17%
HURT stats (abs) min: 1.0 max: 22.0 x̄: 2.01 x̃: 1
HURT stats (rel) min: 0.50% max: 50.00% x̄: 10.45% x̃: 9.09%
95% mean confidence interval for instructions value: -4.77 -4.55
95% mean confidence interval for instructions %-change: -4.36% -3.80%
Instructions are helped.
total tuples in shared programs: 1533335 -> 1523194 (-0.66%)
tuples in affected programs: 483167 -> 473026 (-2.10%)
helped: 3414
HURT: 1288
helped stats (abs) min: 1.0 max: 20.0 x̄: 3.73 x̃: 2
helped stats (rel) min: 0.27% max: 100.00% x̄: 4.87% x̃: 3.03%
HURT stats (abs) min: 1.0 max: 19.0 x̄: 2.02 x̃: 1
HURT stats (rel) min: 0.24% max: 38.10% x̄: 8.10% x̃: 5.88%
95% mean confidence interval for tuples value: -2.28 -2.03
95% mean confidence interval for tuples %-change: -1.62% -1.02%
Tuples are helped.
total clauses in shared programs: 351432 -> 329158 (-6.34%)
clauses in affected programs: 142237 -> 119963 (-15.66%)
helped: 5328
HURT: 3
helped stats (abs) min: 1.0 max: 43.0 x̄: 4.18 x̃: 4
helped stats (rel) min: 0.74% max: 100.00% x̄: 19.44% x̃: 17.24%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 9.09% max: 12.50% x̄: 10.90% x̃: 11.11%
95% mean confidence interval for clauses value: -4.25 -4.11
95% mean confidence interval for clauses %-change: -19.72% -19.12%
Clauses are helped.
total cycles in shared programs: 202830.92 -> 172084.50 (-15.16%)
cycles in affected programs: 117078.42 -> 86332 (-26.26%)
helped: 5450
HURT: 1
helped stats (abs) min: 0.083333 max: 49.0 x̄: 5.64 x̃: 5
helped stats (rel) min: 1.42% max: 100.00% x̄: 27.94% x̃: 25.64%
HURT stats (abs) min: 0.25 max: 0.25 x̄: 0.25 x̃: 0
HURT stats (rel) min: 2.46% max: 2.46% x̄: 2.46% x̃: 2.46%
95% mean confidence interval for cycles value: -5.74 -5.54
95% mean confidence interval for cycles %-change: -28.30% -27.58%
Cycles are helped.
total arith in shared programs: 57274.29 -> 57145.04 (-0.23%)
arith in affected programs: 16418.33 -> 16289.08 (-0.79%)
helped: 2442
HURT: 1784
helped stats (abs) min: 0.
041665999999999315 max: 0.75 x̄: 0.14 x̃: 0
helped stats (rel) min: 0.23% max: 100.00% x̄: 5.51% x̃: 2.87%
HURT stats (abs) min: 0.
041665999999999315 max: 0.
9166670000000003 x̄: 0.12 x̃: 0
HURT stats (rel) min: 0.00% max: 100.00% x̄: 25.13% x̃: 9.09%
95% mean confidence interval for arith value: -0.04 -0.03
95% mean confidence interval for arith %-change: 6.61% 8.24%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total texture in shared programs: 12857 -> 12857 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0
total vary in shared programs: 11157.75 -> 11157.75 (0.00%)
vary in affected programs: 0 -> 0
helped: 0
HURT: 0
total ldst in shared programs: 177208 -> 146420 (-17.37%)
ldst in affected programs: 117098 -> 86310 (-26.29%)
helped: 5447
HURT: 0
helped stats (abs) min: 1.0 max: 49.0 x̄: 5.65 x̃: 5
helped stats (rel) min: 1.92% max: 100.00% x̄: 27.91% x̃: 25.64%
95% mean confidence interval for ldst value: -5.75 -5.55
95% mean confidence interval for ldst %-change: -28.27% -27.56%
Ldst are helped.
total quadwords in shared programs: 1436507 -> 1398329 (-2.66%)
quadwords in affected programs: 515101 -> 476923 (-7.41%)
helped: 5150
HURT: 111
helped stats (abs) min: 1.0 max: 39.0 x̄: 7.46 x̃: 6
helped stats (rel) min: 0.17% max: 100.00% x̄: 10.02% x̃: 8.24%
HURT stats (abs) min: 1.0 max: 9.0 x̄: 2.01 x̃: 1
HURT stats (rel) min: 0.43% max: 21.62% x̄: 3.57% x̃: 1.94%
95% mean confidence interval for quadwords value: -7.41 -7.11
95% mean confidence interval for quadwords %-change: -9.98% -9.49%
Quadwords are helped.
total threads in shared programs: 35025 -> 35228 (0.58%)
threads in affected programs: 218 -> 421 (93.12%)
helped: 208
HURT: 5
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.91 0.99
95% mean confidence interval for threads %-change: 93.40% 99.55%
Threads are helped.
total loops in shared programs: 128 -> 125 (-2.34%)
loops in affected programs: 3 -> 0
helped: 3
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
total spills in shared programs: 158 -> 149 (-5.70%)
spills in affected programs: 15 -> 6 (-60.00%)
helped: 9
HURT: 0
total fills in shared programs: 1133 -> 966 (-14.74%)
fills in affected programs: 197 -> 30 (-84.77%)
helped: 9
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
Alyssa Rosenzweig [Mon, 21 Feb 2022 02:29:50 +0000 (21:29 -0500)]
panvk: Use more reliable assert for UBO pushing
The important thing isn't the number of words pushed, it's that there are no
UBOs required for us to upload. Check that instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
Georg Lehmann [Tue, 15 Feb 2022 12:22:40 +0000 (13:22 +0100)]
radv, aco: Add u_foreach_bit to .clang-format.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15083>
Xaver Hugl [Thu, 20 May 2021 16:49:07 +0000 (18:49 +0200)]
gbm: improve documentation about the lifetime of resources
Signed-off-by: Xaver Hugl <xaver.hugl@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10906>
Marek Olšák [Sat, 22 Jan 2022 15:03:16 +0000 (10:03 -0500)]
ac: update shadowed registers
based on PAL
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 21 Jan 2022 09:04:22 +0000 (04:04 -0500)]
radeonsi: move Arcturus code outside the gfx9 branch
preparation for a future commit
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 18 Feb 2022 02:25:21 +0000 (21:25 -0500)]
ac/llvm: replace structured by vindex != NULL in ac_build_buffer_store_common
"raw" (IDXEN=0) and "structured" (IDXEN=1) do bounds checking differently.
From `si_make_buffer_descriptor`:
* - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
* - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
so there is a difference between setting vindex = i32_0 and vindex = NULL.
Instead of having the `structured` flag, we can just check if vindex is NULL.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 18 Feb 2022 02:25:21 +0000 (21:25 -0500)]
ac/llvm: replace structured by vindex != NULL in ac_build_tbuffer_store
"raw" (IDXEN=0) and "structured" (IDXEN=1) do bounds checking differently.
From `si_make_buffer_descriptor`:
* - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
* - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
so there is a difference between setting vindex = i32_0 and vindex = NULL.
Instead of having the `structured` flag, we can just check if vindex is NULL.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Tue, 22 Feb 2022 08:05:35 +0000 (03:05 -0500)]
radeonsi: use SET_SH_REG_INDEX with index=3 for registers containing CU_EN
This matches PAL and RADV behavior. It's for preemption.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Tue, 22 Feb 2022 04:25:06 +0000 (23:25 -0500)]
ac/surface: add more elements to meta equations because HTILE can use them
according to gfx10SwizzlePattern.h
Fixes:
9fabbf2150253d06d - ac/surface: copy the HTILE equations to the surface
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Mon, 21 Feb 2022 01:22:16 +0000 (20:22 -0500)]
ac/surface/tests: fix missing NUM_PKRS extraction in test_modifier
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sun, 20 Feb 2022 07:10:27 +0000 (02:10 -0500)]
radeonsi: apply the LLVM discard bug workaround to LLVM 13 only
It was fixed in LLVM 14.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Thu, 27 Jan 2022 00:38:26 +0000 (19:38 -0500)]
ac,radeonsi: rework and optimize how TMPRING_SIZE is set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Yogesh Mohan Marimuthu [Thu, 10 Feb 2022 19:42:07 +0000 (01:12 +0530)]
radeonsi: prepare clamp, alpha test before mrtz prepare
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Yogesh Mohan Marimuthu [Thu, 10 Feb 2022 19:34:46 +0000 (01:04 +0530)]
radeonsi: move clamp, alpha test from si_export_mrt_color() to new function
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Thu, 27 Jan 2022 00:31:32 +0000 (19:31 -0500)]
radeonsi: fix the unaligned clear_buffer fallback with TC
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 17:27:06 +0000 (12:27 -0500)]
radeonsi: increase the tesselation factor ring size
based on PAL
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 16:26:25 +0000 (11:26 -0500)]
radeonsi: remove bit gaps in SI_RESOURCE_FLAG_*
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 16:25:27 +0000 (11:25 -0500)]
radeonsi: replace SI_RESOURCE_FLAG_UNMAPPABLE with PIPE_RESOURCE_FLAG_UNMAPPABLE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 16:11:43 +0000 (11:11 -0500)]
radeonsi: don't map buffers that VK made unmappable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 16:04:21 +0000 (11:04 -0500)]
radeonsi: more fixes for si_buffer_from_winsys_buffer for GL-VK interop
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
jiadozhu [Tue, 30 Jul 2019 09:21:02 +0000 (05:21 -0400)]
radeonsi: fix crash in flush_resource when used with buffers
glWaitSemaphoreEXT triggers si_flush_resource callback
on pipe buffer resources, which may cause segmentation fault.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 15:21:01 +0000 (10:21 -0500)]
radeonsi: reduce the max TBO/SSBO binding size to 512 MB to help 32-bit builds
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 15:02:19 +0000 (10:02 -0500)]
radeonsi: document an unexpected behavior of PS_DONE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 10:25:34 +0000 (05:25 -0500)]
radeonsi: change ACCUM_ISOLINE to 12
based on PAL
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 10:04:22 +0000 (05:04 -0500)]
radeonsi: program SQ_THREAD_TRACE_CTRL.AUTO_FLUSH_MODE on gfx10.3
discovered internally
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 21 Jan 2022 12:14:26 +0000 (07:14 -0500)]
radeonsi: always set FLUSH_ON_BINNING_TRANSITION
The hardware does the right thing automatically.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 21 Jan 2022 09:03:09 +0000 (04:03 -0500)]
radeonsi: add assertions to check if buffer_map/texture_map calls are valid
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 15:17:47 +0000 (10:17 -0500)]
winsys/amdgpu: fix a warning of defining radeon_screen_create_t twice
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 15:17:30 +0000 (10:17 -0500)]
ac/llvm: remove unused function dpp_row_sl
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 15:15:51 +0000 (10:15 -0500)]
ac/surface: don't set the display flag for 1D textures
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 18 Feb 2022 00:04:43 +0000 (19:04 -0500)]
ac/gpu_info: print units for some radeon_info fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 14:55:15 +0000 (09:55 -0500)]
ac: add a gfx9 workaround for high priority compute
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Tue, 1 Feb 2022 16:34:13 +0000 (11:34 -0500)]
amd: add a workaround for an SQ perf counter bug
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 22 Jan 2022 09:13:23 +0000 (04:13 -0500)]
amd: remove the _UMD suffix from register definitions
It was mistakenly added to indicate it's for a User-Mode Driver,
but all defined registers in Mesa are.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Sat, 19 Feb 2022 03:23:55 +0000 (22:23 -0500)]
winsys/radeon: fix a hang due to introducing spi_cu_en
Fixes:
5406ad93 "radeonsi: set COMPUTE_DESTINATION_EN_SEn to spi_cu_en"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5989
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Iago Toral Quiroga [Tue, 22 Feb 2022 09:27:00 +0000 (10:27 +0100)]
broadcom/compiler: fix register class patching for postponed spills
If we have a postponed spill, the temp we create at ip is no longer
the spilled temp and therefore is affected by the thrsw injection.
Fixes corruption in the additive blending animation demo from
Three.js.
Fixes:
f3c3228522 ('broadcom/compiler: do not rebuild the interference graph after each spill')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15112>
Tapani Pälli [Thu, 3 Feb 2022 12:02:42 +0000 (14:02 +0200)]
iris: setup internal_format for memory object resources
We need to setup internal_format for resource in case main surface was
not configured (iris_resource_configure_main) which is the case with
vertex buffer objects, otherwise transfer helper will make wrong
decisions when copying such a resource.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14925>
Erik Faye-Lund [Mon, 19 Jul 2021 13:34:01 +0000 (15:34 +0200)]
vulkan/wsi: use buffer-image code-path on Windows
This means we no longer map optimal-tiling images in order to display
them on screen, but instead copy via a buffer, which is guaranteed to
linearize.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12210>
Erik Faye-Lund [Mon, 19 Jul 2021 13:32:19 +0000 (15:32 +0200)]
vulkan/wsi: add transition to/from transfer-src state
Without these barriers, we'll try to blit from the image when it's in
the incorrect layout, which is illegal.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12210>
Erik Faye-Lund [Thu, 3 Feb 2022 09:57:16 +0000 (10:57 +0100)]
vulkan/wsi: untangle buffer-images from prime
Not all Vulkan implementations allows rendering to linear images, so in
order to support scanning out from these on Windows we might have to copy
through a buffer like we do in the PRIME path.
To avoid reimplementing the same, let's instead generalize the code a
bit so it doesn't have to specfy any PRIME-specific details.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12210>
Boris Brezillon [Fri, 18 Feb 2022 08:28:49 +0000 (09:28 +0100)]
vulkan/wsi: Don't open-code vk_format_get_blocksize()
We already have a standard helper to retrieve the texel block size from
a VkFormat, let's use it instead of adding a new helper.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12210>
Boris Brezillon [Fri, 18 Feb 2022 08:25:05 +0000 (09:25 +0100)]
vulkan/wsi: Use ALIGN_POT() instead of open-coding it
align_u32() and ALIGN_POT() are doing the same thing.
Replace align_u32() calls by ALIGN_POT() ones and get rid
of align_u32().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12210>
Erik Faye-Lund [Mon, 19 Jul 2021 10:21:04 +0000 (12:21 +0200)]
vulkan/wsi: pass win32-swapchain directly
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12210>
Marcin Ślusarz [Fri, 18 Feb 2022 13:31:00 +0000 (14:31 +0100)]
anv: cleanup begin_subpass & end_subpass
Share values of some expressions instead of duplicating the same logic.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15079>
Marcin Ślusarz [Fri, 18 Feb 2022 12:16:07 +0000 (13:16 +0100)]
intel/compiler: remove redundant code from fs_visitor::run_*
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15079>
Gert Wollny [Tue, 15 Feb 2022 09:48:41 +0000 (10:48 +0100)]
virgl: Enable PIPE_CAP_TGSI_TEXCOORD when the host supports it
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15025>
Juan A. Suarez Romero [Fri, 18 Feb 2022 12:53:30 +0000 (13:53 +0100)]
vc4: remove redundant initialization
These assignments are not required.
Partially fixes https://gitlab.freedesktop.org/mesa/mesa/-/issues/3966
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15080>
Samuel Pitoiset [Wed, 16 Feb 2022 09:07:08 +0000 (10:07 +0100)]
radv,aco,llvm: lower adjusting vertex alpha in NIR
Instead of duplicating the same lowering in both compiler backends.
This pass will be used to do more VS input lowering.
fossils-db (Polaris10):
Totals from 48 (0.04% of 135960) affected shaders:
VGPRs: 1692 -> 1684 (-0.47%)
CodeSize: 54016 -> 53964 (-0.10%); split: -0.11%, +0.01%
MaxWaves: 339 -> 341 (+0.59%)
Instrs: 11260 -> 11247 (-0.12%); split: -0.13%, +0.02%
Latency: 88165 -> 88113 (-0.06%); split: -0.07%, +0.01%
InvThroughput: 36153 -> 36093 (-0.17%)
Copies: 583 -> 568 (-2.57%)
fossils-db (Pitcairn):
Totals from 43 (0.03% of 135960) affected shaders:
VGPRs: 1548 -> 1552 (+0.26%)
CodeSize: 47900 -> 47820 (-0.17%)
Instrs: 10751 -> 10731 (-0.19%)
Latency: 83029 -> 82873 (-0.19%)
VClause: 168 -> 164 (-2.38%)
SClause: 393 -> 391 (-0.51%)
Copies: 705 -> 685 (-2.84%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15076>
Qiang Yu [Tue, 8 Feb 2022 09:49:28 +0000 (17:49 +0800)]
util/util_vertex_state_cache: remove error check when deinit
Application may exit without freeing created display list, this
may leave the cache not empty.
This is triggered by Abaqus which just close X11 display without
calling any of GLX cleanup functions like glXDestroyContext. But
GLX hook to X11 display close function to free GLX screen resource.
So display list as a context resource has not been freed, but
cache as a screen resource is freed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14926>
Qiang Yu [Tue, 8 Feb 2022 02:14:15 +0000 (10:14 +0800)]
driconf: add Abaqus configs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14926>
Qiang Yu [Mon, 7 Feb 2022 09:54:57 +0000 (17:54 +0800)]
glx: keep native window glx drawable by driconf option
DRI3 window back buffer is a client resource, so it's destroyed
when context switch drawable for native window.
But some application like Abaqus may leave a dirty back buffer
and reuse it when switch back. So add a driconf option for these
kind of app to keep the entire GLX drawable for native window.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14926>
Qiang Yu [Mon, 7 Feb 2022 07:00:03 +0000 (15:00 +0800)]
glx: merge drawable release to the same function
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14926>
Qiang Yu [Wed, 9 Feb 2022 08:00:30 +0000 (16:00 +0800)]
glx: fix pbuffer refcount init
glXMakeCurrent* may miss release pbuffer if pbuffer is created
with refcount=0. This won't happen when pbuffer had different
GLX id and X pixmap id.
cc: mesa-stable
Fixes:
bc8a51a79a5 ("glx: no need to create extra pixmap for pbuffer")
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14926>
Iago Toral Quiroga [Mon, 21 Feb 2022 13:09:33 +0000 (14:09 +0100)]
broadcom/compiler: only patch temps that existed before the current spill
When we spill we add new temps. We should be careful not to access
liveness for these until we have re-computed it after all spills and
fill for that the spilled temp have been processed so as to avoid
out-of-bounds accesses to the c->temp_start and c->temp_end arrays.
This fixes a crash in a Three.js demo when we try to patch register
classes after a TMU spill that was caused because we would incorrectly
try to patch the same temps we had just added for the spill itself,
which is not only unnecessary but also incorrect since we these temps
would not have liveness information available yet and thus would
cause out of bounds accesses.
Fixes:
f3c3228522 ('broadcom/compiler: do not rebuild the interference graph after each spill')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15107>
Marek Olšák [Sat, 12 Feb 2022 01:20:35 +0000 (20:20 -0500)]
gallivm: fix build with LLVM 15
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15095>
Marek Olšák [Sat, 19 Feb 2022 17:58:18 +0000 (12:58 -0500)]
ci: bump piglit version
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14750>
Marek Olšák [Sat, 22 Jan 2022 16:22:40 +0000 (11:22 -0500)]
gallium: add PIPE_RESOURCE_FLAG_UNMAPPABLE for shared unmappable buffers
We need to handle this in u_threaded_context for GL-VK interop.
Drivers should set this when importing buffers if needed.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14750>
Jiadong Zhu [Tue, 30 Jul 2019 08:48:53 +0000 (04:48 -0400)]
st/mesa: set GL_DYNAMIC_STORAGE_BIT for GL-VK interop buffers
GL_DYNAMIC_STORAGE_BIT needs to be set to make glBufferSubData work.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14750>
Erik Faye-Lund [Fri, 18 Feb 2022 17:29:34 +0000 (18:29 +0100)]
nir/spirv: guard macros in case of redefinition
On some systems, these macros are already defined, and being defined
slightly differently causes them to emit redefinition-warnings.
Let's wrap them in ifdefs to avoid the warnings.
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15084>
Alyssa Rosenzweig [Mon, 21 Feb 2022 16:50:59 +0000 (11:50 -0500)]
asahi: Fix use-after-free in shader key
We need to take ownership of shader keys before we can insert them into
the hash table. Caught by ASan.
==6343==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x00016bc51410 at pc 0x00010498d6cc bp 0x00016bc50240 sp 0x00016bc4f9d0
READ of size 592 at 0x00016bc51410 thread T0
#0 0x10498d6c8 in MemcmpInterceptorCommon(void*, int (*)(void const*, void const*, unsigned long), void const*, void const*, unsigned long)+0x208 (libclang_rt.asan_osx_dynamic.dylib:arm64e+0x196c8)
#1 0x10498da08 in wrap_memcmp+0x98 (libclang_rt.asan_osx_dynamic.dylib:arm64e+0x19a08)
#2 0x10b7f3f18 in asahi_shader_key_equal agx_state.c:867
#3 0x10a482e7c in hash_table_search hash_table.c:325
#4 0x10b7f4e94 in agx_update_shader agx_state.c:899
#5 0x10b7f0dc4 in agx_draw_vbo agx_state.c:1590
#6 0x10a7c28c4 in u_vbuf_draw_vbo u_vbuf.c:1498
#7 0x10a5db03c in cso_multi_draw cso_context.c:1639
#8 0x10aed03d0 in _mesa_validated_drawrangeelements draw.c:1812
#9 0x10aed08d4 in _mesa_DrawElements draw.c:1945
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15109>
Michel Dänzer [Thu, 16 Dec 2021 11:23:08 +0000 (12:23 +0100)]
ci: Remove unused is-for-marge YAML anchor
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14225>
Michel Dänzer [Thu, 16 Dec 2021 11:09:10 +0000 (12:09 +0100)]
ci: Use $CI_PIPELINE_SOURCE
Instead of $CI_MERGE_REQUEST_SOURCE_BRANCH_NAME. Shorter and clearer.
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14225>
Michel Dänzer [Thu, 16 Dec 2021 11:03:18 +0000 (12:03 +0100)]
ci: Use $CI_COMMIT_BRANCH
This was recently added to indicate pipelines for branches.
v2:
* Modify .gitlab-ci/test-source-dep.yml as well.
Acked-by: Emma Anholt <emma@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14225>