Samuel Pitoiset [Fri, 5 Feb 2021 14:21:51 +0000 (15:21 +0100)]
radv/winsys: remove unused fields in radv_amdgpu_cs_request
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Samuel Pitoiset [Fri, 5 Feb 2021 13:59:03 +0000 (14:59 +0100)]
radv/winsys: simplify the user fence logic for submission
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Samuel Pitoiset [Thu, 4 Feb 2021 14:12:51 +0000 (15:12 +0100)]
radv/winsys: remove unused radeon_bo_usage enum
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Samuel Pitoiset [Wed, 3 Feb 2021 14:13:12 +0000 (15:13 +0100)]
radv/winsys: remove useless is_local check in radv_amdgpu_cs_add_buffer()
radv_cs_add_buffer() already guarantees that and virtual buffers
are added via radv_amdgpu_cs_add_virtual_buffer().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Samuel Pitoiset [Wed, 3 Feb 2021 13:40:05 +0000 (14:40 +0100)]
radv/winsys: remove useless continue preamble CS for IBs path
It's only used for the sysmem path which is GFX6.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Samuel Pitoiset [Wed, 3 Feb 2021 13:11:49 +0000 (14:11 +0100)]
radv/winsys: remove the radv_amdgpu_winsys_bo::ws indirection
This saves a 64-bit pointer from radv_amdgpu_winsys_bo and it's
also common to pass a winsys pointer as the first parameter.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Samuel Pitoiset [Wed, 3 Feb 2021 09:47:08 +0000 (10:47 +0100)]
radv/winsys: use an array for the global BO list instead of a list
This allows to remove one 64-bit pointer from radv_amdgpu_winsys_bo.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
Arcady Goldmints-Orlov [Sun, 7 Feb 2021 18:17:03 +0000 (13:17 -0500)]
Revert "broadcom/compiler: improve generation of if conditions"
This reverts commit
93f8f83a95383e38769bca8cd3c236d3b1c4c87f.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8903>
Eric Anholt [Mon, 1 Feb 2021 22:27:50 +0000 (14:27 -0800)]
ci/freedreno: Run a3xx gles3 in parallel and increase coverage.
It seems that recent fixes have made its results stable (other than
existing flakiness in texturegrad), so we can use all the CPUs and a
couple more boards and get more coverage.
Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>
Eric Anholt [Mon, 1 Feb 2021 22:24:31 +0000 (14:24 -0800)]
ci/freedreno: bump VK coverage to 1/4 of the CTS.
With the runner fixes, we were down to 2 minutes of boot time and 2
minutes of CTS time for a total of 4 minutes. We've got plenty of time
budget now to increase our coverage.
Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>
Eric Anholt [Fri, 29 Jan 2021 20:58:38 +0000 (12:58 -0800)]
ci/deqp: Bump runner to 0.5.1 for recent runtime perf improvements.
3 commits in 0.5.0:
- 20-40s savings on many of our CI runs by dropping the clever test size
scaling code.
- Even bigger savings (especially on deqp-vk runs) by increasing maximuim
test group size (~1/4 of runtime was spawning deqp on cheza, that cost
is cut by ~75%)
- No more needing to manually set MESA_DEBUG=silent
2 commits in 0.5.1:
- Fixed automatic thread pool sizing to keep all CPUs busy (thanks for
catching that Bas!).
- Automatically size down test groups on short test lists and many CPUs,
so split the list evenly between CPUs (such as on freedreno -options
jobs).
Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>
Ian Romanick [Fri, 17 Jan 2020 21:33:20 +0000 (13:33 -0800)]
nir/algebraic: Partially revert
3f782cdd2591
I'm not sure what the logic was, but there is no opportunity for
anything to flush to zero here. 'a' is a Boolean value, and b2f
produces 1.0 or 0.0.
This was originally part of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3765/.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Andres Gomez <agomez@igalia.com>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8910>
Ian Romanick [Fri, 10 Jan 2020 01:13:37 +0000 (17:13 -0800)]
nir/algebraic: add patterns for a >> #b << #b and a << #b >> #b
Commit
5476d181830 ("nir/algebraic: add patterns for a >> #b << #b")
added the ushr version, but it missed the ishr. A bunch of compute
shaders with stores to shared storage generate the ishr pattern.
Enabling this optimization also enables the iadd/iand reassociation
(right after this hunk), and that enables merging of stores to shared
storage. A couple shaders have spills and fills hurt on some
platforms. These all occur in shaders that also have SENDs helped.
On Gen9 and Gen11, the helped SENDs more than makes up for the extra
spills and fills.
On Gen7 and Gen8, it's not as clear. All of the shaders affected are
compute shaders in DiRT Rally 2 or Bioshock Inifinite. The most
affected Bioshock shader on Broadwell looks like:
Before: CS SIMD8 shader: 1335 inst, 0 loops, 22411 cycles, 42:36 spills:fills, 159 sends, scheduled with mode lifo, Promoted 2 constants, compacted 21360 to 16528 bytes.
After: CS SIMD8 shader: 1175 inst, 0 loops, 25916 cycles, 96:135 spills:fills, 72 sends, scheduled with mode lifo, Promoted 2 constants, compacted 18800 to 13648 bytes.
The results on Haswell and Ivy Bridge are similar. Given that there
are only 2 promoted constants, MR !7698 won't have any effect.
There were no statistically significant changes on Gen9+ in Bioshock in
our performance CI. Gen8 isn't in that CI, and DiRT Showdown 2 is also
not included in that CI. It is possible that these shaders aren't used
in the settings or demos used in the CI.
The other pattern, which switches the order of the shifts, only helps a
couple shaders. If I wasn't already adding another pattern, I
definitely wouldn't bother with that one.
v2: s/ishr/ushr/ in the replacement for the ushr pattern. Noticed by
Rhys.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tiger Lake
total instructions in shared programs:
21052760 ->
21049269 (-0.02%)
instructions in affected programs: 59497 -> 56006 (-5.87%)
helped: 46
HURT: 0
helped stats (abs) min: 2 max: 552 x̄: 75.89 x̃: 53
helped stats (rel) min: 0.28% max: 43.43% x̄: 5.87% x̃: 4.10%
95% mean confidence interval for instructions value: -108.96 -42.82
95% mean confidence interval for instructions %-change: -8.38% -3.35%
Instructions are helped.
total cycles in shared programs:
855229761 ->
855148518 (<.01%)
cycles in affected programs: 8491373 -> 8410130 (-0.96%)
helped: 33
HURT: 15
helped stats (abs) min: 42 max: 26940 x̄: 6200.70 x̃: 4329
helped stats (rel) min: 0.09% max: 38.78% x̄: 7.97% x̃: 4.29%
HURT stats (abs) min: 2 max: 18132 x̄: 8225.33 x̃: 7288
HURT stats (rel) min: <.01% max: 13.37% x̄: 5.72% x̃: 4.53%
95% mean confidence interval for cycles value: -4331.52 946.40
95% mean confidence interval for cycles %-change: -6.78% -0.61%
Inconclusive result (value mean confidence interval includes 0).
total sends in shared programs: 989947 -> 989694 (-0.03%)
sends in affected programs: 523 -> 270 (-48.37%)
helped: 5
HURT: 0
helped stats (abs) min: 9 max: 87 x̄: 50.60 x̃: 37
helped stats (rel) min: 25.71% max: 54.72% x̄: 43.49% x̃: 42.53%
95% mean confidence interval for sends value: -93.95 -7.25
95% mean confidence interval for sends %-change: -58.48% -28.50%
Sends are helped.
Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs:
20033498 ->
20030552 (-0.01%)
instructions in affected programs: 59220 -> 56274 (-4.97%)
helped: 48
HURT: 0
helped stats (abs) min: 1 max: 465 x̄: 61.38 x̃: 39
helped stats (rel) min: 0.03% max: 42.27% x̄: 5.19% x̃: 3.90%
95% mean confidence interval for instructions value: -89.57 -33.18
95% mean confidence interval for instructions %-change: -7.49% -2.89%
Instructions are helped.
total cycles in shared programs:
979993675 ->
979840773 (-0.02%)
cycles in affected programs: 6738454 -> 6585552 (-2.27%)
helped: 46
HURT: 0
helped stats (abs) min: 42 max: 6265 x̄: 3323.96 x̃: 3579
helped stats (rel) min: 0.09% max: 37.38% x̄: 4.34% x̃: 2.39%
95% mean confidence interval for cycles value: -3664.70 -2983.21
95% mean confidence interval for cycles %-change: -6.63% -2.06%
Cycles are helped.
total spills in shared programs: 10659 -> 10661 (0.02%)
spills in affected programs: 36 -> 38 (5.56%)
helped: 1
HURT: 1
total fills in shared programs: 11551 -> 11551 (0.00%)
fills in affected programs: 70 -> 70 (0.00%)
helped: 1
HURT: 1
total sends in shared programs: 1032117 -> 1031785 (-0.03%)
sends in affected programs: 711 -> 379 (-46.69%)
helped: 5
HURT: 0
helped stats (abs) min: 18 max: 87 x̄: 66.40 x̃: 74
helped stats (rel) min: 27.69% max: 54.72% x̄: 44.49% x̃: 44.31%
95% mean confidence interval for sends value: -101.79 -31.01
95% mean confidence interval for sends %-change: -58.42% -30.55%
Sends are helped.
Broadwell
total instructions in shared programs:
17865005 ->
17862757 (-0.01%)
instructions in affected programs: 66438 -> 64190 (-3.38%)
helped: 49
HURT: 0
helped stats (abs) min: 1 max: 266 x̄: 45.88 x̃: 39
helped stats (rel) min: 0.03% max: 11.99% x̄: 3.73% x̃: 3.92%
95% mean confidence interval for instructions value: -59.15 -32.61
95% mean confidence interval for instructions %-change: -4.35% -3.12%
Instructions are helped.
total cycles in shared programs:
1031298803 ->
1031219023 (<.01%)
cycles in affected programs: 7253602 -> 7173822 (-1.10%)
helped: 45
HURT: 2
helped stats (abs) min: 18 max: 7828 x̄: 1928.33 x̃: 1918
helped stats (rel) min: <.01% max: 10.51% x̄: 1.58% x̃: 1.31%
HURT stats (abs) min: 3490 max: 3505 x̄: 3497.50 x̃: 3497
HURT stats (rel) min: 15.56% max: 15.64% x̄: 15.60% x̃: 15.60%
95% mean confidence interval for cycles value: -2174.88 -1220.01
95% mean confidence interval for cycles %-change: -2.00% 0.30%
Inconclusive result (%-change mean confidence interval includes 0).
total spills in shared programs: 20799 -> 20924 (0.60%)
spills in affected programs: 843 -> 968 (14.83%)
helped: 0
HURT: 4
total fills in shared programs: 27110 -> 27334 (0.83%)
fills in affected programs: 1824 -> 2048 (12.28%)
helped: 1
HURT: 4
total sends in shared programs: 1017935 -> 1017603 (-0.03%)
sends in affected programs: 711 -> 379 (-46.69%)
helped: 5
HURT: 0
helped stats (abs) min: 18 max: 87 x̄: 66.40 x̃: 74
helped stats (rel) min: 27.69% max: 54.72% x̄: 44.49% x̃: 44.31%
95% mean confidence interval for sends value: -101.79 -31.01
95% mean confidence interval for sends %-change: -58.42% -30.55%
Sends are helped.
Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs:
16397496 ->
16395411 (-0.01%)
instructions in affected programs: 59384 -> 57299 (-3.51%)
helped: 49
HURT: 0
helped stats (abs) min: 1 max: 208 x̄: 42.55 x̃: 39
helped stats (rel) min: 0.03% max: 8.18% x̄: 3.74% x̃: 3.91%
95% mean confidence interval for instructions value: -53.59 -31.51
95% mean confidence interval for instructions %-change: -4.24% -3.23%
Instructions are helped.
total cycles in shared programs:
1035483504 ->
1035397592 (<.01%)
cycles in affected programs: 9379739 -> 9293827 (-0.92%)
helped: 45
HURT: 4
helped stats (abs) min: 10 max: 5600 x̄: 2164.51 x̃: 2350
helped stats (rel) min: <.01% max: 11.61% x̄: 1.93% x̃: 1.56%
HURT stats (abs) min: 2 max: 5756 x̄: 2872.75 x̃: 2866
HURT stats (rel) min: <.01% max: 24.65% x̄: 12.29% x̃: 12.26%
95% mean confidence interval for cycles value: -2293.06 -1213.56
95% mean confidence interval for cycles %-change: -2.42% 0.88%
Inconclusive result (%-change mean confidence interval includes 0).
total spills in shared programs: 17672 -> 17803 (0.74%)
spills in affected programs: 364 -> 495 (35.99%)
helped: 2
HURT: 2
total fills in shared programs: 20752 -> 20937 (0.89%)
fills in affected programs: 656 -> 841 (28.20%)
helped: 2
HURT: 2
total sends in shared programs: 1044703 -> 1044450 (-0.02%)
sends in affected programs: 523 -> 270 (-48.37%)
helped: 5
HURT: 0
helped stats (abs) min: 9 max: 87 x̄: 50.60 x̃: 37
helped stats (rel) min: 25.71% max: 54.72% x̄: 43.49% x̃: 42.53%
95% mean confidence interval for sends value: -93.95 -7.25
95% mean confidence interval for sends %-change: -58.48% -28.50%
Sends are helped.
No changes on Gen6 or earlier GPUs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8852>
Ian Romanick [Wed, 3 Feb 2021 00:04:57 +0000 (16:04 -0800)]
nir/algebraic: Fix a >> #b << #b for sizes other than 32-bit
The base mask previously used was 0xffffffff. This is not correct (but
should still work) for 16-bit and 8-bit values, but it means the high
32-bits of 64-bit values will get chopped off.
Instead of just restricting the pattern to 32-bits (as was done before
00b28a50b2c), this extends the optimization in two ways:
1. Make it correct for other bit sizes.
2. Make it work for arbitrary shift counts.
This has the added benefit of reducing the number of patterns actually
added (7 previously, 4 now).
The "Reassociate for improved CSE" part is just reverted to its
pre-
00b28a50b2c behavior. I doubt that pattern is likely to have much
impact outside 32-bits.
This change fixes the piglit tests
tests/spec/arb_gpu_shader_int64/fs-shl-of-shr-int64.shader_test and
tests/spec/arb_gpu_shader_int64/fs-iand-of-iadd-int64.shader_test.
All of the shaders helped in shader-db are vertex shaders on platforms
with vector-oriented vertex processing. The shaders contain ((x >> 16)
<< 16). These platforms set lower_extract_word, so the optimization
that transforms (x >> 16) to extract_u16 doesn't trigger. With only ~60
shaders involved, I didn't bother trying to add extract_XYZ versions of
these patterns to try to get those cases.
Fixes:
00b28a50b2c ("nir/algebraic: trivially enable existing 32-bit patterns for all bit sizes")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Haswell and earlier Intel GPUs had simlar results. (Haswell shown)
total instructions in shared programs:
16397554 ->
16397496 (<.01%)
instructions in affected programs: 7961 -> 7903 (-0.73%)
helped: 58
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.36% max: 1.89% x̄: 0.99% x̃: 0.78%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -1.13% -0.85%
Instructions are helped.
total cycles in shared programs:
1035483770 ->
1035483504 (<.01%)
cycles in affected programs: 75922 -> 75656 (-0.35%)
helped: 44
HURT: 2
helped stats (abs) min: 2 max: 12 x̄: 6.14 x̃: 2
helped stats (rel) min: 0.05% max: 1.67% x̄: 0.87% x̃: 0.72%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.06% max: 0.06% x̄: 0.06% x̃: 0.06%
95% mean confidence interval for cycles value: -7.28 -4.29
95% mean confidence interval for cycles %-change: -1.03% -0.63%
Cycles are helped.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8852>
Mike Blumenkrantz [Fri, 7 Aug 2020 13:41:12 +0000 (09:41 -0400)]
zink: force 4 component formats for samplerview/render textures
this fixes a bunch of issues with 3-component formats, which aren't supported
for various operations on certain drivers
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8697>
Mauro Rossi [Fri, 5 Feb 2021 20:55:57 +0000 (21:55 +0100)]
android: radv: fix building error in radv_android.c
Fixes the following building error:
external/mesa/src/amd/vulkan/radv_android.c:752:77: error: too few arguments to function call, expected 4, have 3
VkResult result = radv_image_create_layout(device, create_info, mem->image);
~~~~~~~~~~~~~~~~~~~~~~~~ ^
external/mesa/src/amd/vulkan/radv_private.h:2175:1: note: 'radv_image_create_layout' declared here
VkResult
^
1 error generated.
Fixes:
7f7da82dbb78 ("radv: Add image layout with drm format modifiers.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8899>
Mauro Rossi [Fri, 5 Feb 2021 20:31:53 +0000 (21:31 +0100)]
android: radv: port to using common dispatch code.
Fixes the following building error in Android:
FAILED: ninja: 'external/mesa/src/amd/vulkan/radv_entrypoints_gen.py',
needed by 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_radv_common_intermediates/radv_entrypoints.c',
missing and no known rule to make it
Fixes:
23f8ca0c9dba ("radv: port to using common dispatch code.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8899>
Simon Ser [Thu, 14 Jan 2021 18:12:32 +0000 (19:12 +0100)]
nouveau/nv50: fix linear buffer alignment for scan-out/cursors
The hardware can only scan-out linear buffers with a pitch
aligned to 256. It can only use packed buffers for cursors.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8500>
Simon Ser [Thu, 14 Jan 2021 18:02:41 +0000 (19:02 +0100)]
nouveau/nvc0: fix linear buffer alignment for scan-out/cursors
The hardware can only scan-out linear buffers with a pitch
aligned to 256. It can only use packed buffers for cursors.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/36
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8500>
Ilia Mirkin [Thu, 4 Feb 2021 17:15:43 +0000 (12:15 -0500)]
nouveau: reinstate fencing on screen destroy
As it turns out, the wait is required as the driver expects for
rendering to be quiesced on exit. This can trigger channel failures,
which in turn trigger recovery. This can fail and destroy the whole
system.
Fixes:
28a781323fb ("nouveau: change fence destruction logic on screen destroy")
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4223
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8867>
Ilia Mirkin [Thu, 4 Feb 2021 17:11:48 +0000 (12:11 -0500)]
ci: remove nouveau from shader-db runs
This is needed since we're about to reinstate the fencing mechanism on
screen destruction. Until we figure out another way to handle it, this
will cause hangs on exit with the shim.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable # 21.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8867>
Bas Nieuwenhuizen [Wed, 23 Sep 2020 01:04:27 +0000 (03:04 +0200)]
radv: Improve spilling on discrete GPUs.
The linked bug gets better performance and I personally verified
better spilling performance on HZD so let us make this step for now.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3183
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3698
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6833>
Mauro Rossi [Fri, 5 Feb 2021 22:17:49 +0000 (23:17 +0100)]
android: iris: implement iris layer of INTEL_MEASURE
Fixes the following building errors in Android:
FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so
...
ld.lld: error: undefined symbol: _iris_measure_snapshot
ld.lld: error: undefined symbol: iris_init_batch_measure
ld.lld: error: undefined symbol: iris_measure_batch_end
ld.lld: error: undefined symbol: iris_destroy_batch_measure
ld.lld: error: undefined symbol: iris_destroy_ctx_measure
ld.lld: error: undefined symbol: iris_measure_frame_end
ld.lld: error: undefined symbol: iris_destroy_screen_measure
ld.lld: error: undefined symbol: iris_init_screen_measure
Fixes:
e67b8f504b4c ("iris: implement iris layer of INTEL_MEASURE")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8887>
Mauro Rossi [Fri, 5 Feb 2021 21:46:08 +0000 (22:46 +0100)]
android: anv: implement anv layer of INTEL_MEASURE
Fixes the following building errors in Android:
FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.android-x86_intermediates/LINKED/vulkan.android-x86.so
...
ld.lld: error: undefined symbol: _anv_measure_add_secondary
ld.lld: error: undefined symbol: anv_measure_init
ld.lld: error: undefined symbol: anv_measure_destroy
ld.lld: error: undefined symbol: anv_measure_reset
ld.lld: error: undefined symbol: anv_measure_device_destroy
ld.lld: error: undefined symbol: anv_measure_device_init
ld.lld: error: undefined symbol: _anv_measure_submit
ld.lld: error: undefined symbol: anv_measure_acquire
ld.lld: error: undefined symbol: _anv_measure_snapshot
ld.lld: error: undefined symbol: _anv_measure_endcommandbuffer
ld.lld: error: undefined symbol: _anv_measure_beginrenderpass
Fixes:
4a2d9e44ff26 ("anv: implement anv layer of INTEL_MEASURE")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8887>
Mauro Rossi [Fri, 5 Feb 2021 22:06:32 +0000 (23:06 +0100)]
android: intel: Print GPU timing data based on INTEL_MEASURE
Fixes the following building errors in Android:
FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.android-x86_intermediates/LINKED/vulkan.android-x86.so
...
ld.lld: error: undefined symbol: intel_measure_init
ld.lld: error: undefined symbol: intel_measure_state_changed
ld.lld: error: undefined symbol: intel_measure_snapshot_string
ld.lld: error: undefined symbol: intel_measure_gather
ld.lld: error: undefined symbol: intel_measure_frame_transition
Fixes:
0f4143ec3787 ("intel: Print GPU timing data based on INTEL_MEASURE")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8887>
Marek Olšák [Wed, 3 Feb 2021 07:07:15 +0000 (02:07 -0500)]
winsys/amdgpu: try not to skip any code with RADEON_NOOP=1 to test CPU perf
This enables more accurate estimation of the maximum achievable CPU-bound
performance.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 06:48:08 +0000 (01:48 -0500)]
winsys/amdgpu: don't set unused usage for backing BOs of sparse BOs
This is never used.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 06:46:39 +0000 (01:46 -0500)]
winsys/amdgpu: don't inc/dec num_active_ioctls for backing BOs of sparse BOs
It's not correct.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 05:03:22 +0000 (00:03 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::use_reusable_pool to the u.real union
It's never true with slab and sparse buffers.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 05:03:22 +0000 (00:03 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::is_user_ptr to the u.real union
It's never true with slab and sparse buffers.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 05:03:22 +0000 (00:03 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::is_shared to the u.real union
It's never true with slab and sparse buffers.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 04:57:28 +0000 (23:57 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::cpu_ptr into the u.real union
It's never used with slab and sparse buffers.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 04:52:58 +0000 (23:52 -0500)]
winsys/amdgpu: pack amdgpu_winsys_bo::is_shared and protect it by a mutex
The initialization of abs_timeout fixes a warning that started appearing
with this commit.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Wed, 3 Feb 2021 03:37:28 +0000 (22:37 -0500)]
winsys/amdgpu: remove amdgpu_winsys_bo::num_cs_references to remove atomics
This decreases the CPU time percentage of amdgpu_cs_add_buffer by 50%
on Ryzen 3900X.
We don't need to call amdgpu_bo_is_referenced_by_any_cs
in amdgpu_bo_can_reclaim. The reclaim function is only called for buffers
that have 0 references.
The only downside is that amdgpu_bo_is_referenced_by_cs might be slower
in some very rare cases. Overall the driver overhead is better.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Marek Olšák [Tue, 2 Feb 2021 01:24:07 +0000 (20:24 -0500)]
winsys/amdgpu: optimize out conditionals in amdgpu_lookup_buffer
Move them to a wrapper function.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>
Chia-I Wu [Fri, 5 Feb 2021 22:57:39 +0000 (14:57 -0800)]
targets/libgl-xlib: add support for virgl
This allows testing virgl over vtest by setting GALLIUM_DRIVER=virpipe
when the X server uses a proprietary driver.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Tested-by: John Bates <jbates@chromium.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8888>
Vinson Lee [Fri, 5 Feb 2021 05:00:14 +0000 (21:00 -0800)]
virgl: Convert errno to string.
Fix defect reported by Coverity Scan.
Invalid type in argument to printf format specifier (PRINTF_ARGS)
invalid_type: Argument *__errno_location() to format specifier %s was expected to have type char * but has type int.
Fixes:
d37124b065c ("virgl: add support for VIRGL_CAP_V2_UNTYPED_RESOURCE")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8874>
Mike Blumenkrantz [Wed, 3 Feb 2021 12:17:17 +0000 (07:17 -0500)]
radv: zero the bo descriptor array when allocating a new set
this must be reset to avoid issues when using VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT_EXT
when some descriptors in the set may not have been bound
fixes #4219
Fixes:
126d5adb11e ("radv: Use host memory pool for non-freeable descriptors.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8840>
Mike Blumenkrantz [Wed, 3 Feb 2021 00:59:12 +0000 (19:59 -0500)]
radv: null bo list pointer for null descriptors on update
failing to unset any existing pointers here leads to stale bo entries in
the list and then the kernel rejecting the cmdbuf with ENOENT
Fixes:
126d5adb11e ("radv: Use host memory pool for non-freeable descriptors.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8840>
Ilia Mirkin [Fri, 5 Feb 2021 16:08:40 +0000 (11:08 -0500)]
nv50,nvc0: clear internal vbo masks based on the trailing slots
Fixes:
0278d1fa323c (gallium: add unbind_num_trailing_slots to set_vertex_buffers)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8882>
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:09:46 +0000 (14:09 -0500)]
pan/bi: Implement ACMPXCHG
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Alyssa Rosenzweig [Wed, 3 Feb 2021 18:49:49 +0000 (13:49 -0500)]
pan/bi: Implement AXCHG
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:35:02 +0000 (14:35 -0500)]
pan/bi: Respect side effects in DCE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:33:48 +0000 (14:33 -0500)]
pan/bi: Add side_effects helper
DCE needs to be tuned for this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:11:44 +0000 (14:11 -0500)]
pan/bi: Fix NULL deref with empty shader
Fixes regression in dEQP-GLES31.functional.compute.basic.empty
Fixes:
d0902aa2d4d ("pan/bi: Pass through wait_{6, 7} flags")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Boris Brezillon [Mon, 25 Jan 2021 11:08:15 +0000 (12:08 +0100)]
pan/bi: Make sure we never branch to an non-existing clause
Branch instructions can point to the last shader block, which might be
empty. In this case, the branch points to a clause that doesn't exists,
leading to INVALID_ENC faults when the GPU tries to jump to this clause.
Check if the block is a terminal block before updating the branch
offset: jumping/branching to NULL is equivalent to a shader termination,
so the default value of 0 works just fine for terminal branches.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Boris Brezillon [Mon, 25 Jan 2021 11:02:21 +0000 (12:02 +0100)]
pan/bi: Add an is_terminal_block() helper
Needed to decide what to do with JUMPs/BRANCHes to such blocks.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>
Michel Dänzer [Mon, 25 Jan 2021 11:01:28 +0000 (12:01 +0100)]
ci: Update to newer ci-fairy
To get the fix for
https://gitlab.freedesktop.org/freedesktop/ci-templates/-/issues/29 .
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8690>
Michel Dänzer [Tue, 15 Dec 2020 17:02:04 +0000 (18:02 +0100)]
ci: Fix MESA_TEMPLATES_COMMIT value
The intention was to set it to the commit used for debian.yml, but I
accidentally set it to the ci-fairy.yml commit instead.
v2:
* While we're at it, put two dashes between the base tag and the
ci-templates commit hash, making them easier to tell apart.
v3:
* While we're at it, fix the year of some recently bumped tags.
Fixes:
48f78dfd1ac1 "ci: Define global variable MESA_TEMPLATES_COMMIT
for ci-templates commit"
Reviewed-by: Eric Anholt <eric@anholt.net> # v2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8690>
Rhys Perry [Wed, 27 Jan 2021 14:04:10 +0000 (14:04 +0000)]
aco: always set exec_live=false
Register demand calculation for exec masks doesn't always match
get_live_changes() and get_temp_registers(). For now, just set
exec_live=false.
fossil-db (GFX10.3):
Totals from 108230 (77.64% of 139391) affected shaders:
SGPRs: 5759658 -> 5756818 (-0.05%); split: -0.08%, +0.03%
VGPRs: 4061104 -> 4061248 (+0.00%); split: -0.00%, +0.01%
SpillSGPRs: 14114 -> 15198 (+7.68%); split: -0.10%, +7.78%
CodeSize:
266548396 ->
266603288 (+0.02%); split: -0.01%, +0.03%
MaxWaves: 1390885 -> 1390855 (-0.00%); split: +0.00%, -0.00%
Instrs:
50983353 ->
50992972 (+0.02%); split: -0.02%, +0.04%
Cycles:
1733042048 ->
1735443264 (+0.14%); split: -0.02%, +0.16%
VMEM:
41933625 ->
41914722 (-0.05%); split: +0.04%, -0.09%
SMEM: 7197675 -> 7197789 (+0.00%); split: +0.16%, -0.16%
VClause: 1050885 -> 1050978 (+0.01%); split: -0.02%, +0.03%
SClause: 2074913 -> 2071844 (-0.15%); split: -0.23%, +0.08%
Copies: 3181464 -> 3188125 (+0.21%); split: -0.38%, +0.59%
Branches: 1127526 -> 1127716 (+0.02%); split: -0.10%, +0.12%
PreSGPRs: 3376687 -> 3586076 (+6.20%); split: -0.00%, +6.20%
PreVGPRs: 3339740 -> 3339811 (+0.00%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8807>
Erik Faye-Lund [Wed, 2 Dec 2020 16:26:26 +0000 (17:26 +0100)]
zink: support using lavapipe
This is really nasty, and shouldn't really be needed, but we have a
problem where both Zink and Lavapipe checks $GALLIUM_DRIVER, meaning that
Zink tries to use Lavapipe, and Lavapipe tries to use Zink.
This patch side-steps that by temporarily setting $GALLIUM_DRIVER to
"llvmpipe", giving Lavapipe a chance to succeed.
This is not great at all. The most obvious problem is that this is super
thread-unsafe, effectively modifying global state without any care. In
reality, we'd only want the pipe-loader in the *same thread* to ignore
Zink, but it's not so obvious how to do that without introducing lots of
ugly zink-specific cruft.
People shouldn't be using Zink if they don't have a GPU, it's going to
be much better to use LLVMpipe in that case. So let's not worry too much
about this case, and instead guard this dangerous logic with an
ZINK_USE_LAVAPIPE environment variable. This means this behavior only
happens if people opt in to it.
With this in place, we can start using Zink + Lavapipe on CI.
In the longer run, it might be better to use Adam Jackson's copper
loader instead, and drop exposing Zink as a software rasterizer
entirely. But that's something for the great future where we have flying
cars and all.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7881>
Erik Faye-Lund [Fri, 5 Feb 2021 11:49:50 +0000 (12:49 +0100)]
zink: explicitly check for VK_NULL_HANDLE
This seems a bit less like magic to me.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7881>
Erik Faye-Lund [Fri, 5 Feb 2021 11:48:37 +0000 (12:48 +0100)]
zink: check for error when calling vkEnumeratePhysicalDevices
It seems it's possible for Lavapipe to fail to enumerate the physical
devices, so let's handle that and fail all the way up here.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7881>
Rhys Perry [Wed, 9 Dec 2020 12:52:21 +0000 (12:52 +0000)]
aco: add fallback algorithm in get_reg()
The generated code is often terrible, but the situations where this is
needed are rare.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8713>
Leo Liu [Wed, 3 Feb 2021 02:41:55 +0000 (21:41 -0500)]
radeon/vcn: enable dynamic dpb Tier1 support
For Raven and Navixx family i.e. VCN1 and VCN2 with VP9 codec
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>
Leo Liu [Wed, 3 Feb 2021 02:24:47 +0000 (21:24 -0500)]
radeon/vcn: add dynamic dpb buffer Tier1 support
Also add its buffer index and fill up messages for the buffer.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>
Leo Liu [Sun, 31 Jan 2021 18:34:43 +0000 (13:34 -0500)]
radeon/vcn: add dynamic dpb interface
The new message buffer will save the dpb buffers from previous
allocation based on the max resolution.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>
Leo Liu [Wed, 3 Feb 2021 02:22:00 +0000 (21:22 -0500)]
radeon/vcn: clean the message buffers and their indexes logic
So the new buffer and index can be added sequentially.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>
Mike Blumenkrantz [Mon, 17 Aug 2020 14:58:08 +0000 (10:58 -0400)]
zink: be a little more precise about query types in one conditional
just for readability, no functional changes
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8516>
Mike Blumenkrantz [Fri, 29 Jan 2021 15:07:06 +0000 (10:07 -0500)]
zink: unify shader image unbind codepath
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8780>
Iago Toral Quiroga [Fri, 5 Feb 2021 10:36:42 +0000 (11:36 +0100)]
v3dv: allow a component swizzle in copy_buffer_to_image_shader
This is trivial because this path relies on our blit_shader interface
which supports this already, so it just needs to pass it along.
I don't think this is ever triggered practice, since we should be
able to handle any case that could require this with the texel buffer
path, but at least it allows us to simplify a bit the code.
Tested by manually disabling the priority paths to ensure we exercise
component swizzles with this path.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8875>
Iago Toral Quiroga [Fri, 5 Feb 2021 07:56:14 +0000 (08:56 +0100)]
v3dv: batch copies in the copy_buffer_to_image_blit path
This path is very memory hungry and batching allows us to reduce
this by allocating memory just once and reuse it for all regions
in the batch instead of allocating once per region.
v2: document return value for this function (apinheiro).
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8875>
Iago Toral Quiroga [Thu, 4 Feb 2021 07:17:43 +0000 (08:17 +0100)]
v3dv: handle D/S buffer to image copies with the texel buffer path
We do this by converting them to a compatible color copy and using a
destination color mask as well as a source component swizzle to handle
D24 format semantics according to the V3D hardware requirements,
similar to what we do with our blit shader interface.
This path is faster than the terrible copy_buffer_to_image_blit,
which requires to copy the source buffer to a tiled image first
and should be avoided as much as possible, since it is slow and
can also quickly increase device memory usage.
This fixes occasional OOM errors when loading traces in renderdoc.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8875>
Boris Brezillon [Wed, 3 Feb 2021 07:44:03 +0000 (08:44 +0100)]
panfrost: Don't add the tiler BO when it's not accessed
Only batches involving the tiler block need to add the tiler heap to the
list of accessed BOs. While at it, clarify who's accessing this heap.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8822>
Boris Brezillon [Tue, 2 Feb 2021 08:32:41 +0000 (09:32 +0100)]
panfrost: Fix a polygon list corruption in the multi-context case
The polygon list is written by tiler jobs and read by fragment ones,
and nothing should re-use the heap until the fragment job is done.
4fec6c944817 ("panfrost: Add the tiler heap to fragment jobs") fixed
this for the !multi-context case by adding the heap BO to fragment job.
But the tiler heap is shared accross contexts, and vertex/tiler+fragment
job submission is done through 2 separate ioctls, meaning that
vertex/tiler and fragment jobs from 2 different context might be
interleaved.
Add a lock at the device level to ensure tiler/vertex+fragment jobs are
submitted sequentially, with no other jobs using the same tiler heap
in-between.
Cc: mesa-stable
Fixes:
d8deb1eb6a22 ("panfrost: Share tiler_heap across batches/contexts")
Reported-by: Icecream95 <ixn@disroot.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8822>
Caio Marcelo de Oliveira Filho [Tue, 12 Jan 2021 19:30:52 +0000 (11:30 -0800)]
spirv: Skip creating unused variables in SPIR-V >= 1.4
Newer versions of SPIR-V require that all the global variables used by
the entry point are declared (in contrast to only I/O in previous
versions), so there's no need to remove dead variables or keep track
of the indirectly used variables.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8456>
Caio Marcelo de Oliveira Filho [Tue, 12 Jan 2021 18:25:58 +0000 (10:25 -0800)]
spirv: Count variables *after* unused ones are removed
Previous code was counting more variables than those used by the entry
point.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8456>
Caio Marcelo de Oliveira Filho [Tue, 12 Jan 2021 17:55:46 +0000 (09:55 -0800)]
spirv: Use OpEntryPoint to identify valid I/O variables
OpEntryPoint declares the list of variables in Input and Output
storage classes that are used. Use that information to skip creating
other variables from such storage classes that are unused by the entry
point.
After that change, is not necessary to use remove dead variables for
those types of variables; and because of that is also not necessary to
lower initalizers for output variables.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8456>
Vinson Lee [Mon, 19 Oct 2020 23:23:45 +0000 (16:23 -0700)]
nv50/ir: Initialize BindArgumentsPass member sub in constructor.
Fix defect reported by Coverity.
Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member sub is not initialized in
this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7229>
Eric Anholt [Thu, 4 Feb 2021 22:20:16 +0000 (14:20 -0800)]
freedreno/a6xx: Add support for glDrawTransformFeedback().
It's exposed with ARB_tf2, which we claimed support for. All the KHR-GL33
TF tests pass for me locally except for no_errors, which I have some
outstanding fixes for with khronos. Our CI build seems to be having some
issue with exceptions inside of deqp.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8843>
Eric Anholt [Wed, 3 Feb 2021 18:43:42 +0000 (10:43 -0800)]
docs: Document PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME.
It does more than the name suggests!
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8843>
Eric Anholt [Wed, 3 Feb 2021 18:20:31 +0000 (10:20 -0800)]
freedreno/a6xx: Skip guessing VSC size with indirect TF draw counts.
Fixes an assertion failure when we try to figure out how many bits to
store the "0" draw count.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8843>
James Park [Thu, 4 Feb 2021 20:54:20 +0000 (12:54 -0800)]
radv: Pointer arithmetic without void*
Fixes:
736834931bb ("radv: memset the alignment hole in cache_entry to 0")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8871>
Jason Ekstrand [Sat, 30 Jan 2021 04:40:39 +0000 (22:40 -0600)]
anv: Move extension tables to anv_device.c
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>
Jason Ekstrand [Sat, 30 Jan 2021 16:08:37 +0000 (10:08 -0600)]
anv,vulkan: Move anv_icd.py to a common location
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>
Jason Ekstrand [Sat, 30 Jan 2021 15:57:27 +0000 (09:57 -0600)]
anv: Make anv_icd.py more generic and independent
Instead of depending on anv_extensions.py, fetch the patch version from
the XML ourselves. This way it can be moved to common code and used by
other ICDs going forward.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>
Jason Ekstrand [Sat, 30 Jan 2021 16:04:00 +0000 (10:04 -0600)]
anv: Pull the patch version from the XML
For years, I've maintained that I like to bump this number manually
because it gives me a point at which to say, "I've looked at most of the
issues and I think we're up to date." The reality, however, is that I
just bump it every few months and don't really do any thorough checking.
We may as well just bump it on header updates.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>
Jason Ekstrand [Sat, 30 Jan 2021 17:13:33 +0000 (11:13 -0600)]
vulkan: Rework extension disabling on Android
Instead of building it into the auto-generated condition we use for the
per-driver ${driver}_physical_device_get_supported_extensions()
function, generate a table and handle it inside the various common
extension enumeration and verification routines. This reduces our
reliance on code-gen for extension enables.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>
Jason Ekstrand [Sat, 30 Jan 2021 17:03:27 +0000 (11:03 -0600)]
vulkan: Add a common helper for enumerating instance extension properties
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>
Danylo Piliaiev [Thu, 4 Feb 2021 16:52:59 +0000 (18:52 +0200)]
freedreno/a2xx: fix scissors clamp bounds
a2xx has maximum viewport dimensions of 4096
Fixes:
6ae726b79988addc50c1ed149151a351d0343d9d ("freedreno: clamp scissor bounds")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8866>
Eric Anholt [Sat, 30 Jan 2021 00:49:12 +0000 (16:49 -0800)]
freedreno: Drop pointless clear of used providers.
We don't reuse batches, no need to do anything special here.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>
Eric Anholt [Thu, 28 Jan 2021 01:19:15 +0000 (17:19 -0800)]
freedreno: Backport a5xx/a6xx fix for active query handling.
The batch might not have stage == FD_STAGE_BLIT set because
fd_blitter_pipe_begin was sticking the stage on some random batch (or none
at all) rather than the one that would be used in the meta operation.
What we actually wanted to be looking at was set_active_query_state(),
which is already called by util_blitter and whose state we just needed to
track.
Fixes these piglit tests on a307:
occlusion_query_meta_fragments
occlusion_query_meta_save
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>
Eric Anholt [Sat, 30 Jan 2021 00:52:26 +0000 (16:52 -0800)]
freedreno: rename batch->active_providers to query_providers_used.
It's not the set of currently active providers, it's what's been used at
all in the current batch (this is used for doing the initialization of
query providers at initial HW setup in a submit).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>
Eric Anholt [Mon, 1 Feb 2021 19:52:12 +0000 (11:52 -0800)]
freedreno: Make sure that queries are disabled during shadow blits.
They shouldn't count toward occlusion queries.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>
Mike Blumenkrantz [Wed, 3 Feb 2021 20:29:39 +0000 (15:29 -0500)]
zink: move maintenance2 extension to right file
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8862>
Jesse Natalie [Fri, 29 Jan 2021 17:53:23 +0000 (09:53 -0800)]
drisw: Disable automatic use of layered drivers with LIBGL_ALWAYS_SOFTWARE
If LIBGL_ALWAYS_SOFTWARE is set, then drisw is selected, and internally,
drisw should choose one of the actual software drivers. If it's not set,
but drisw is still selected (no hardware DRM driver, like in WSL), then
layered drivers are preferred over pure software.
Fixes:
4a3b42a7 ("drisw: Prefer hardware-layered sw-winsys drivers over pure sw")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4171
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8782>
Danylo Piliaiev [Wed, 23 Dec 2020 12:54:22 +0000 (14:54 +0200)]
freedreno: clamp scissor bounds
We don't have negative scissor coords and maximum dimensions are:
a3xx - 4096
a4xx+ - 16384
Fixes piglit tests:
fbo-viewport
viewport-clamp
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/30
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8209>
Mike Blumenkrantz [Tue, 2 Feb 2021 17:42:49 +0000 (12:42 -0500)]
radv: print image array size in debug mode
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8863>
Erik Faye-Lund [Wed, 3 Feb 2021 10:16:52 +0000 (11:16 +0100)]
docs: fix invalid rst syntax
We need a newline here to avoid syntax errors while builind the
sphinx-documentation.
The errors don't lead the build fail, so we didn't notice this on CI.
Which is a shame IMO. Instead, the blocks simply fail to render.
Fixes:
2e2edaa89b4 ("docs/ci: Document setting up the http cache for traces.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8839>
SureshGuttula [Fri, 8 Jan 2021 02:09:31 +0000 (07:39 +0530)]
frontends/va: Update conditional checks for code stability.
Added parameter checks and updated returns based on that.
https://github.com/intel/libva-utils/tree/master/test
run test_va_api
Signed-off-by: SureshGuttula <sguttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8374>
Alyssa Rosenzweig [Wed, 3 Feb 2021 18:49:39 +0000 (13:49 -0500)]
nir/lower_io: Fix grammar errors
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8846>
Iago Toral Quiroga [Wed, 3 Feb 2021 08:14:00 +0000 (09:14 +0100)]
broadcom/compiler: let QPUs stall on TMU input/config overflows
We have been trying to avoid this by tracking fifo usages in the driver and
flushing all outstanding TMU sequences if we overflowed any of these, however,
this is actually not the most efficient strategy. Instead, we would like to
flush only enough operations to get things going again, which is better for
pipelining. Doing that in the driver would require some additional work, but
thankfully, it is not required, since this seems to be what the hardware does
automatically, so we can just remove overflow tracking for these two fifos
and enjoy the benefits.
This also further improves shader-db stats:
total instructions in shared programs: 8975062 -> 8955145 (-0.22%)
instructions in affected programs: 1637624 -> 1617707 (-1.22%)
helped: 4050
HURT: 2241
Instructions are helped.
total threads in shared programs: 236802 -> 237042 (0.10%)
threads in affected programs: 252 -> 492 (95.24%)
helped: 122
HURT: 2
Threads are helped.
total sfu-stalls in shared programs: 19901 -> 19592 (-1.55%)
sfu-stalls in affected programs: 4744 -> 4435 (-6.51%)
helped: 1248
HURT: 1051
Sfu-stalls are helped.
total inst-and-stalls in shared programs: 8994963 -> 8974737 (-0.22%)
inst-and-stalls in affected programs: 1636184 -> 1615958 (-1.24%)
helped: 4050
HURT: 2239
Inst-and-stalls are helped.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Tue, 2 Feb 2021 09:12:07 +0000 (10:12 +0100)]
broadcom/compiler: log spilling shaders to perf output
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Tue, 2 Feb 2021 08:20:47 +0000 (09:20 +0100)]
broadcom/compiler: disallow spilling if TMU pipelining was enabled
TMU pipelining makes TMU spilling difficult and can easily lead to
doing large amounts of spills to compile a shader. It is best to
only use pipelining if we can compile without spilling.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Mon, 1 Feb 2021 10:01:47 +0000 (11:01 +0100)]
broadcom/compiler: disable TMU pipelining if we fail to register allocate
TMU pipelining can severely reduce our capacity to emit TMU spills,
causing us to fail to compile a shader we may otherwise be able to
compile. This is because pipelining extends the liveness of TMU
sequences by posponing the thread switch and LDTMU until a result
is needed, and we can't emit TMU spills while in the middle of a
TMU sequence.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Thu, 28 Jan 2021 08:27:09 +0000 (09:27 +0100)]
broadcom/compiler: support pipelining of image load/store instructions
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Thu, 28 Jan 2021 08:29:11 +0000 (09:29 +0100)]
broadcom/compiler: refactor image load/store TMU emission code
This mostly moves code around to group together the code involved with
actually emitting a TMU sequence. This will make it a bit easier to
then implement pipelining while reusing this code, similar to how we
handled other cases of TMU pipelining.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Wed, 27 Jan 2021 08:45:52 +0000 (09:45 +0100)]
broadcom/compiler: support pipelining of tex instructions
This follows the same idea as for TMU general instructions of reusing
the existing infrastructure to first count required register writes and
flush outstanding TMU dependencies, and then emit the actual writes, which
requires that we split the code that decides about register writes to
a helper.
We also need to start using a component mask instead of the number
of components that we need to read with a particular TMU operation.
v2: update tmu_writes for V3D_QPU_WADDR_TMUOFF
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Tue, 26 Jan 2021 11:18:43 +0000 (12:18 +0100)]
broadcom/compiler: implement pipelining for general TMU operations
This creates the basic infrastructure to implement TMU pipelining and
applies it to general TMU. Follow-up patches will expand this
to texture and image/load store operations.
TMU pipelining means that we don't immediately end TMU sequences,
and instead, we postpone the thread switch and LDTMU (for loads)
or TMUWT (for stores) until we really need to do them.
For loads, we may need to flush them if another instruction reads
the result of a load operation. We can detect this because in that
case ntq_get_src() will not find the definition for that ssa/reg
(since we have not emitted the LDTMU instructions for it yet), so
when that happens, we flush all pending TMU operations and then
try again to find the definition for the source.
We also need to flush pending TMU operations when we reach the end
of a control flow block, to prevent the case where we emit a TMU
operation in a block, but then we read the result in another block
possibly under control flow.
It is also required to flush across barriers and discards to honor
their semantics.
Since this change doesn't implement pipelining for texture and
image load/store, we also need to flush outstanding TMU operations
if we ever have to emit one of these. This will be corrected with
follow-up patches.
Finally, the TMU has 3 fifos where it can queue TMU operations.
These fifos have limited capacity, depending on the number of threads
used to compile the shader, so we also need to ensure that we
don't have too many outstanding TMU requests and flush pending
TMU operations if a new TMU operation would overflow any of these
fifos. While overflowing the Input and Config fifos only leads
to stalls (which we want to avoid anyway), overflowing the Output
fifo is incorrect and would end up with a broken shader. This means
that we need to know how many TMU register writes are required
to emit a TMU operation and use that information to decide if we need
to flush pending TMU operations before we emit any register
writes for the new TMU operation.
v2: fix TMU flushing for NIR registers reads (jasuarez)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
Iago Toral Quiroga [Wed, 27 Jan 2021 12:00:30 +0000 (13:00 +0100)]
broadcom/compiler: prepare TMU spilling code to account for TMU pipelining
Follow-up patches will implement support for TMU pipelining in the
compiler, which basically means that we will be able to have more
than one outstanding TMU operation.
Our spilling code currently relies on properly identifying the end
of a TMU sequence (since we can't emit a new TMU sequence for a spill
in the middle of an existing TMU sequence), however, that code expects
that only one TMU sequence may be outstanding, which won't be true
once we implement pipelining.
This change fixes the 'end of TMU sequence' checks to account for this
in preparation for upcoming patches.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>