zink: add a mechanism for managing TRANSFER_DST buffer barriers

this enables successive or unrelated transfer writes to avoid triggering
barriers, and ensuing reads of those writes should trigger their own
barriers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

zink: track the last write access for resources

this enables some optimization

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

radeonsi: Add support for DPB resize

This patch will add support for dpb resize when low to high resolution
change/ svc use-cases.

With DPB tier1 type,vp9 svc decoder use cases are failed. This
Change will fix this[VCN1/VCN2].

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21548>

asahi: disable disk cache in debug runs

With debug flags enabled, shaders might get compiled differently and
running compilation might be desired e.g. for logging, so don't try to
cache them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21776>

agx: isolate compiler debug flags

The gallium disk cache is about to depend on these, and I don't want to
create a dependency on agx_opcodes.h.py for that. So, make a new header
for them that doesn't have build dependencies.
Rename them to agx_compiler_* too, to avoid collisions with the other
driver debug flags.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21776>

intel/ci: Remove skipped float_controls tests from hasvk xfails

These tests are skipped now because preserving denorms isn't supported.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>

intel/ci: Remove hasvk xfails missing from the CTS

These broken tests no longer exist in the CTS and all dynamic rendering
tests pass now.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>

intel/ci: Remove outdated hasvk copy_and_blit xfails

These were fixed by commit e509afac.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>

mesa/program: fix memory leak triggered by arb alias

The function _mesa_symbol_table_add_symbol() copies the string with strdup(),
the original string should be freed.

For instance, with "piglit/fp-fragment-position -auto -fbo":
Direct leak of 7 byte(s) in 1 object(s) allocated from:
    #0 0xffff99c59050 in __interceptor_strdup (/usr/lib64/libasan.so.6+0x59050)
    #1 0xffff8f53d24c in handle_ident ../src/mesa/program/program_lexer.l:129
    #2 0xffff8f53d24c in _mesa_program_lexer_lex ../src/mesa/program/program_lexer.l:312
    #3 0xffff8f529d10 in yylex ../src/mesa/program/program_parse.y:289
    #4 0xffff8f529d10 in yyparse src/mesa/program/program_parse.tab.c:2140
    #5 0xffff8f5341a4 in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2589
    #6 0xffff8f51e96c in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
    #7 0xffff8f4d867c in set_program_string ../src/mesa/main/arbprogram.c:402

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>

mesa/program: fix memory leak triggered by multiple targets used on one texture image unit

For instance, with "piglit-2000/bin/asmparsertest ARBfp1.0 tests/asmparsertest/shaders/ARBfp1.0/shadow-02.txt":
Direct leak of 192 byte(s) in 2 object(s) allocated from:
    #0 0x7f6e8378f987 in calloc (/usr/lib64/libasan.so.6+0xb1987)
    #1 0x7f6e7769d620 in asm_instruction_copy_ctor ../src/mesa/program/program_parse.y:2146
    #2 0x7f6e7769d620 in yyparse ../src/mesa/program/program_parse.y:439
    #3 0x7f6e776a6725 in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2590
    #4 0x7f6e77687f69 in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
    #5 0x7f6e77630765 in set_program_string ../src/mesa/main/arbprogram.c:402
    #6 0x7f6e76ec3e8a in _mesa_unmarshal_ProgramStringARB src/mapi/glapi/gen/marshal_generated2.c:4152
    #7 0x7f6e76a0e585 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:122
    #8 0x7f6e76a1031d in _mesa_glthread_finish ../src/mesa/main/glthread.c:383
    #9 0x7f6e76a1031d in _mesa_glthread_finish ../src/mesa/main/glthread.c:348
    #10 0x7f6e76e6a062 in _mesa_marshal_GetError src/mapi/glapi/gen/marshal_generated1.c:1809

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>

mesa/program: fix memory leak triggered by invalid extended swizzle selector

For instance, with "piglit/bin/asmparsertest ARBfp1.0 tests/asmparsertest/shaders/ARBfp1.0/swz-04.txt":
Direct leak of 18 byte(s) in 2 object(s) allocated from:
    #0 0x7f97e99050 in __interceptor_strdup (/usr/lib64/libasan.so.6+0x59050)
    #1 0x7f8d4160ac in handle_ident ../src/mesa/program/program_lexer.l:129
    #2 0x7f8d4160ac in _mesa_program_lexer_lex ../src/mesa/program/program_lexer.l:312
    #3 0x7f8d402b50 in yylex ../src/mesa/program/program_parse.y:289
    #4 0x7f8d402b50 in yyparse src/mesa/program/program_parse.tab.c:2140
    #5 0x7f8d40d01c in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2590
    #6 0x7f8d3f77ac in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
    #7 0x7f8d3ad468 in set_program_string ../src/mesa/main/arbprogram.c:402

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>

aco/assembler/gfx11: simplify 16bit VOP12C promotion to VOP3

With the shared struct for modifies, this is can be a lot cleaner now.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21761>

radeonsi/gfx11: only allocate GDS OA for streamout, GDS memory is not needed

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>

amd/llvm,radeonsi/gfx11: switch to using GDS_STRMOUT registers

This is required by register shadowing (required by the new PAIRS packets),
preemption, user queues, and we only have to wait for VS after streamout,
not PS. This is how gfx11 streamout should have been done.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>

amd: add nir_intrinsic_xfb_counter_sub_amd and fix overflowed streamout offsets

Fixes: 5ec79f989988ba - ac/nir/ngg: nogs support streamout

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>

intel/fs: use generated workaround helpers for Wa_14017989577

Wa_14017989577 is a clone of Wa_14015360517, which applies to several
platforms beyond INTEL_PLATFORM_DG2_G10.

Update references to Wa_14017989577, and use the generated workaround
helper to ensure application to the proper platforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21744>

ci/etnaviv: Drop the dEQP-GLES2.functional.uniform_api.random.94 xfail.

This has been consistently passing.  I think I just missed it in my
previous update.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21769>

ci: Add some xfail updates from VKCTS 1.3.5.0 for the manual jobs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21769>

llvmpipe: fix LP_PERF=no_depth to ignore depth format

cc: mesa-stable

Reviewed-by: Brian Paul brianp@vmware.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21582>

v3d/v3dv: define performance counters in common

Both OpenGL and Vulkan drivers share the same performance counters.

Let's move them to a common place instead of duplicating.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21420>

iris: Add support for 2d images created from buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

llvmpipe: Add new caps PIPE_CAP_LINEAR_IMAGE_(PITCH_ALIGNMENT|BASE_ADDRESS_ALIGNMENT)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

rusticl: Implement spec for cl_khr_image2d_from_buffer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

gallium: Add new caps PIPE_CAP_LINEAR_IMAGE_(PITCH_ALIGNMENT|BASE_ADDRESS_ALIGNMENT)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

lvmpipe/cs: Add support for 2d images created from buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

mesa/st, nine, nouveau: Fix uninitialized pipe_sampler_view structs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

gallium, rusticl: Add tex2d_from_buf in image_view and sampler_view

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

rusticl: Enable mapImage for images created from buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

rusticl: Enable copy for images created from buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

rusticl: Enabling image fill for images created from buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

rusticl: Enabling reading/writing for images created from buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>

radv/rt: move radv_pipeline_key from rt_variables to traversal_data

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>

radv: remove unused parameters from radv_compute_pipeline_compile()

Also make this function static.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>

radv/rt: introduce and use radv_rt_pipeline_compile()

This is essentially a code-duplication of radv_compute_pipeline_compile()
but will later be more specialized for the needs of RT pipelines.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>

radv: expose radv_pipeline_capture_shaders()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>

radv: expose radv_postprocess_nir()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>

radv: fix defining RADV_USE_WSI_PLATFORM

RADV_USE_WSI_PLATFORM was unused in radv_CreateImage().

Fixes: 2a5d7f4926c ("radv: fix missing implementation of creating images from swapchains")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21763>

iris: Move iris_bo_wait_gem() to i915/iris_bufmgr.c

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>

iris: Move iris_bo_busy_gem() to i915/iris_bufmgr.c

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>

iris: Move bo_set_caching to kmd backend

For the platforms that call it, it a function in the hot path so
moving it to kmd backend.

After this patch i915/iris_bufmgr.c is empty but not removing it
as next patch will add functions to it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>

iris: Move bo_madvise to kmd backend

bo_madvise() is on hot path, so moving it to kmd backend.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>

intel/common: Implement the Xe functions for intel_gem

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21699>

intel/common: Implement the Xe functions for intel_engine

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21699>

radv: fix border color swizzle for stencil-only format on GFX9+

Swizzle of 8-bit stencil format is defined as _x__ but the hw expects
BC_SWIZZLE_XYZW.

Fixes dEQP-VK.pipeline.monolithic.sampler.border_swizzle.*s8_uint*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21482>

anv: fix sends_count_expectation assert on simd32

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21758>

ac/surface: only adjust pitch if surf_pitch was modified

Modifying pitch for all LINEAR surface isn't correct;
the original change that modified surf_pitch was only
intended for YUV textures.

This fixes vkGetImageSubresourceLayout rowPitch return value
for VK_FORMAT_BC3_UNORM_BLOCK + VK_IMAGE_TILING_LINEAR.

Fixes: fcc499d5 (ac/surface: adjust gfx9.pitch[*] based on surf->blk_w)

v2: add check for UYVY format (Pierre-Eric)
v3: move blk_w division to above if check (Pierre-Eric)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21595>

ci/lavapipe: fixes typo

Fixes: 5ee724e180bd ("ci/lavapipe: add recent occasional flake")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21759>

aco: use bitfield array helpers for valu modifiers

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco: add bitfield array helper classes

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco: remove VOP[123C]P? structs

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco/optimizer: simplify using VALU instruction

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco/print_ir: simplify using VALU instruction

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco: validate VALU modifiers

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco/ra: set opsel_hi to zero when converting to VOP2

Otherwise the new modifier validation will fail.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco/ir: rework IR to have one common valu instruction struct

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

aco: treat VINTERP_INREG as VALU

It's just v_fma with fixed DPP8 and builtin s_waitcnt_expcnt, so it can mostly
be handled as a pure VALU instruction.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>

radv: fix incorrect stride for primitives generated query with GDS

When the query pool uses GDS (for NGG), the stride is 40.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8412
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21650>

nir: fix nir_ishl_imm

Both GLSL & SPIRV have undefined values for shift > bitsize. But SM5
says :

   "This instruction performs a component-wise shift of each 32-bit
    value in src0 left by an unsigned integer bit count provided by
    the LSB 5 bits (0-31 range) in src1, inserting 0."

Better to not hard code the wrong behavior in NIR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e227bb9fd5 ("nir/builder: add ishl_imm helper")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@colllabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21720>

radv: do not add descriptor BOs on update when the global BO list is used

It's unnecessary and already checked elsewhere like in
vkCmdBindDescriptorSets(). This improves performance of vkoverhead
test #76 (descriptor_1image) by +18%. It's the same performance as
PRO on my Threadripper 1950X now. This should also slightly improve
texel and buffer descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20699>

gallivm: fix lp_vec_add_offset_ptr for 32 bit builds

The function assumed ptrs are always 64 bit sized.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8267
Fixes: 442d1fe5ad6 ("gallivm: use masked intrinsics for global and scratch access.")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21604>

rusticl/kernel: Images arg sizes also have to match the host pointer size

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8267
Fixes: b0d698c5328 ("rusticl: correctly check global argument size")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21604>

agx: Assert that memory index is 32-bit reg

Semantics will be wrong otherwise (reading garbage).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

agx/lower_address: Handle 16-bit offsets

These need to be upconverted for correctness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

agx/lower_address: Fix handling of 64-bit immediates

We can't add a 64-bit immediate with the hardware iadd, that won't work. What we
can do is add a 32-bit immediate, derived as the low 32-bits of a 64-bit
nir_ssa_def.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

agx/lower_address: Handle 8-bit load/store

Should work ok with the implicit up-conversion that the backend does.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

agx/lower_address: Handle large shifts

If we manage to fold in a left shift that's bigger than the hardware can do, we
should at least avoid generating a useless right shift to feed the hardware
rather bailing completely.

For motivation, this form of address arithmetic is encountered when indexing
into arrays with large power-of-two element sizes (array-of-structs).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

agx/lower_address: Optimize "shift + constant"

Optimize address arithmetic of the form

   base + u2u64((index << shift) + const)

into hardware operands

   base, index << (shift - format_shift) + const'

which (if format_shift = shift) can be simply

   base, index + const'

rather than the current naive translation

   base, ((index << shift) + const) >> format_shift

This saves at least one pointless shift. We can't do this optimization with
nir_opt_algebraic, because explicitly optimizing "(a << #b) >> #b" to "a" isn't
sound due to overflow. But there's no overflow issue here, which is what this
whole pass is designed around.

For motivation, this address arithmetic implements "dynamically indexing into an
array inside of a C structure", where the const is the offset of the array
relative to the structure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

agx/lower_address: Break on match

Once we've matched a summand, commit to it. This avoids needlessly checking the
second source if the first matched, and removes some indentation/funny control
flow.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>

Revert "ci: disable Collabora's LAVA lab for maintance"

This reverts commit https://gitlab.freedesktop.org/mesa/mesa/-/commit/6be7469df1e12bd57c697ff7e34bbda8286d67a2

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21356>

zink: always set batch usage for descriptors after barrier

this otherwise breaks unordered promotion calc

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: set dynamic pcp for unordered cmdbuf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: bind descriptor buffers to unordered cmdbuf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: always set color writes on the unordered cmdbuf

this state has to be set, so ensure it is

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: explicitly flush src clears when u_blittering

this otherwise relies on set_framebuffer_state flushing them,
which may or may not be accurate/desired

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: don't unset existing access when adding resource binds

this breaks barrier calcs, but it was fine since there was a pre-barrier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: eliminate pre barrier for adding resource binds

this will automatically be handled by the copies below

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: check for layout updates when unbinding samplerviews

not sure if it's a bug, but it should be consistent with shader image
unbinding, so here it is

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: propagate valid_buffer_range when replacing buffer storage

this is otherwise unreliable

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: fix descriptor update flagging on null ssbo set

this could unset the update flag if the last ssbo was null, which would
be a bug if it could ever be triggered

found by inspection

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

zink: only add deferred barrier on fb unbind when layout needs to change

this otherwise may have been a surface that was never drawn to or
already had its layout corrected, in which case a deferred barrier
is not only unnecessary, it might be broken

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>

intel/fs: use generated helpers for Wa_1209978020 / Wa_18012201914

Wa_1209978020 is a clone of Wa_18012201914.  Update references to
refer to the originating bug, and use generated helpers to ensure it
is applied to future platforms as needed.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21741>

intel/compiler: Drop non-scoped barrier handling

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

gallivm: Drop non-scoped barrier handling

Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

ir3: Drop non-scoped barrier handling

Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

pan/mdg: Drop control_barrier handling

Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

pan/bi: Drop control_barrier handling

Now unreachable.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

glsl/nir: Use scoped_barrier for control barrier

Rather than control_barrier. This avoids the need to handle control_barrier at
all for backends that set use_scoped_barrier. This effectively matches what
spirv_to_nir emits, so Vulkan-capable compilers should be ok.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

intel/compiler: Drop brw_nir_lower_scoped_barriers

Now that we handle scoped barriers with execution scope during
NIR -> Backend IR translation, this lowering is not needed anymore.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

intel/vec4: Handle scoped barriers with execution scope

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

intel/fs: Handle scoped barriers with execution scope

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21634>

venus: revert back the warn order

This reverts
- commit 4ae4e4362cfdab91be81c48195674d354ef45602
- commit f54aa49c1439440c88a1c6a1046be11dba3ab44e

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>

venus: vn_relax to abort on ring fatal status upon warn order

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>

venus: propagate vn_ring to vn_relax

This is to prepare for vn_relax to check ring status as well as pinging
renderer.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>

venus: abort ring submit when ring is in fatal status

This change also migrates to use the protocol defined status enums.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>

venus: sync to latest protocol for ring status enum

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21542>

intel/fs: use generated workaround helpers for Wa_14010017096

This workaround does not apply beyond gen 12.0.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21746>

meson: forcefully disable libdrm when host doesn't have it

Signed-off-by: Mark Collins <mark@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21724>

nir/opt_barrier: Generalize to control barriers

For GLSL, we want to optimize code like

   memoryBarrierBuffer();
   controlBarrier();

into a single scoped_barrier intrinsic for the backend to consume. Now that
backends can get scoped_barriers everywhere, what's left is enabling backends to
combine these barriers together. We already have an Intel-specific pass for
combining memory barriers; it just needs a teensy bit of generalization to allow
combining all sorts of barriers together.

This avoids code quality regression on Asahi when switching to purely scoped
barriers. It's probably useful for other backends too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21661>

intel: Use nir_lower_tex_options::lower_index_to_offset

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21546>

ir3: Use lower_index_to_offset

Instead of doing the add ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21546>