Pierre-Eric Pelloux-Prayer [Tue, 8 Dec 2020 09:57:45 +0000 (10:57 +0100)]
radeonsi: pass radeon_cmdbuf to emit_cache_flush
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
Alistair Popple [Mon, 7 Dec 2020 01:23:17 +0000 (12:23 +1100)]
gv100/ir: Use system wide atomics
Increase the scope of atomic operations from GPU to system. This is
required for support of SVM to ensure atomic access is maintained for
memory buffers that are not local to the current GPU.
Signed-off-by: Alistair Popple <apopple@nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>
Alistair Popple [Mon, 7 Dec 2020 01:42:52 +0000 (12:42 +1100)]
gv100/ir: Make emitATOM consistent with emitRED
GV100 code generation uses ATOM instructions for compare-and-swap and
RED instructions for other atomic operations. Make the scope consistent
for both types of operations.
Signed-off-by: Alistair Popple <apopple@nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>
Marek Olšák [Tue, 5 Jan 2021 23:57:41 +0000 (18:57 -0500)]
radeonsi: remove si_gs_prolog_bits::gfx9_prev_is_vs
It didn't do anything useful. GS doesn't use the other user SGPRs.
If we decrease the number of user SGPRs we declare for the GS prolog,
we can remove gfx9_prev_is_vs.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8344>
Marek Olšák [Tue, 5 Jan 2021 08:23:08 +0000 (03:23 -0500)]
radeonsi: fix hang caused by for loop with exec=0 in LS and ES
LLVM expects that exec != 0 when entering loops and generates this code
that becomes an infinite loop if exec == 0:
BB5_1:
vcc_lo = (inverted terminating condition)
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_cbranch_vccnz BB5_3 // jump if vcc != 0 (break statement)
// ... loop body ...
s_branch BB5_1
BB5_3:
For non-monolithic VS before TCS, VS before GS, and TES before GS,
we set exec = (thread enabledmask), which sets 0 for HS-only and GS-only
waves, causing the infinite loop condition above.
Fix it as follows:
- set exec = ~0 at the beginning
- wrap the whole shader (LS and ES) in a conditional block, so that HS-only
and GS-only waves jump over it and never enter such a loop
The TES before GS hang can be reproduced by gfxbench:
testfw_app --gfx egl -w 1920 -h 1080 --gl_api gles -t gl_tess
Fixes:
68d6d097f15 - radeonsi/gfx9: add GFX9 and VEGA10 enums
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8344>
Dylan Baker [Tue, 5 Jan 2021 22:23:32 +0000 (14:23 -0800)]
bin/gen_calendar_entries: Add support for making a release
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
Dylan Baker [Tue, 5 Jan 2021 19:46:49 +0000 (11:46 -0800)]
bin/gen_calendar_entries: Add support for extending a release
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
Dylan Baker [Tue, 5 Jan 2021 00:04:45 +0000 (16:04 -0800)]
bin: Add script for manipulating the release calendar
Currently it only handles creating entries for a new rc.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
Dylan Baker [Tue, 5 Jan 2021 00:39:27 +0000 (16:39 -0800)]
docs: store the release-calendar information in csv (and fix tests)
Restructured text (and markdown) is painful to programatically
manipulate, most python parsers are geared towards writing markdown and
generating html. I'd like to move the calendar updates to being
scripted, as such using csv to store them will be convenient. This also
allows us to simplify our scripting that manipulates the table
considerably.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
Eric Anholt [Wed, 6 Jan 2021 23:11:08 +0000 (15:11 -0800)]
freedreno: Add missing dep on u_tracepoints.
Fixes:
a02dcb970fff ("freedreno: Add GPU tracepoints")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8355>
Eric Anholt [Mon, 4 Jan 2021 22:53:34 +0000 (14:53 -0800)]
freedreno: Mark a615/a618 as also lacking Z24_UINT_S8_UINT support.
Rob says it's also the case on 618, and presumably 615 as well then, so
make it take the same path as a630.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
Eric Anholt [Fri, 18 Dec 2020 01:07:48 +0000 (17:07 -0800)]
freedreno: Disable UBWC on z24s8 on a630.
Stencil texture sampling (such as what we have to do for BlitFramebuffer)
is broken with UBWC enabled. We can't just take the
fd_resource_uncompress() path, because that's a blit just like
BlitFramebuffer.
Fixes failure in dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8,
but also the uncaught rendering fails of 4_samples.stencil_index8 and
depth24_stencil8.
Prior to "
911ce374caf0 freedreno/a6xx: Fix MSAA clear" we would usually
pass and sometimes flake fail on this test occasionally, thus it being
listed as a flake (though the rendering was actually broken). Since that
commit, though, we consistently fail on a pixel of the broken rendering,
and thus this was brought to my attention by the #freedreno-ci channel
spam.
Rob took a look at the performance impact of this, and the worst was maybe
up to .5% fps hit on trex.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
Eric Anholt [Mon, 4 Jan 2021 19:34:00 +0000 (11:34 -0800)]
freedreno/a6xx: Fix z24s8 non-ubwc blits on a630.
Taken from the logic in turnip (though they have the format table have
8888_unorm and override to z24s8_as_rgba for blits in the ubwc case)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
Eric Anholt [Fri, 18 Dec 2020 18:51:24 +0000 (10:51 -0800)]
freedreno/a6xx: Move the IBO pipe2tex down to where it's used.
For the texture path, the pipe2tex happens in fd6_tex_const_0().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
Eric Anholt [Thu, 17 Dec 2020 23:52:28 +0000 (15:52 -0800)]
turnip: Move the limited_z24s8 flag to the shared device info.
I want to do the same logic in freedreno, so use the same flag. On
suggestion by robclark, rename it to what it specifically means.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
Neil Armstrong [Wed, 4 Nov 2020 08:18:03 +0000 (08:18 +0000)]
kmsro: sync Android.mk GALLIUM_TARGET_DRIVERS
Sync Android.mk GALLIUM_TARGET_DRIVERS names from kmsro meson.build,
notably adding the missing mediatek, meson and rockchip display drivers
names.
It also fixes the imx name into imx-drm as referenced in meson.build
and src/gallium/targets/dri/target.c
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7443>
Eric Engestrom [Sun, 6 Dec 2020 17:33:24 +0000 (18:33 +0100)]
docs: use a single cell for the branch number
Fixes:
94c6511757254da6c3b6 ("docs: add release schedule for 20.3")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7950>
Rhys Perry [Mon, 23 Nov 2020 14:14:57 +0000 (14:14 +0000)]
vtn: support SpvCapabilitySparseResidency
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Mon, 7 Dec 2020 13:36:47 +0000 (13:36 +0000)]
nir/lower_tex: fix lower_tg4_offsets with sparse fetches
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Mon, 7 Dec 2020 13:36:22 +0000 (13:36 +0000)]
nir: add sparse_residency_code_and
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Wed, 25 Nov 2020 17:07:20 +0000 (17:07 +0000)]
nir,spirv: implement SpvOpImageSparseTexelsResident
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Fri, 20 Nov 2020 16:14:26 +0000 (16:14 +0000)]
nir,spirv: add sparse image loads
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Fri, 20 Nov 2020 15:10:42 +0000 (15:10 +0000)]
nir,spirv: add sparse texture fetches
Like SPIR-V and GL_ARB_sparse_texture2, these return a residency code. It
is placed in the destination after the rest of the result. If it's zero,
then the texel is resident. Otherwise, it's not resident.
Besides the larger destination and the residency code, sparse fetches
work the same as normal fetches.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Mon, 23 Nov 2020 13:05:58 +0000 (13:05 +0000)]
nir: allow 5 component vectors
These will be useful for sparse texture instructions and image load
intrinsics.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Fri, 13 Mar 2020 16:09:06 +0000 (16:09 +0000)]
nir/tests: fix callback for load/store vectorizer tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Daniel Schürmann [Wed, 6 Jan 2021 18:06:51 +0000 (19:06 +0100)]
nir/opt_vectorize: fix call to filter function
Due to the typo, it could happen that instructions
got further vectorized than intended.
Fixes:
8eaf9c61d17370d3f272ca39256de58231c02127 ('nir/opt_vectorize: don't hash filtered instructions')
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8352>
Vinson Lee [Fri, 1 Jan 2021 02:29:04 +0000 (18:29 -0800)]
freedreno/afuc: Replace readfile with os_read_file.
Tested afuc-disasm produced same output.
$ ./builddir/src/freedreno/afuc/afuc-disasm -g 6 src/freedreno/.gitlab-ci/reference/afuc_test.fw > /tmp/afuc_test.asm
$ diff ./src/freedreno/.gitlab-ci/reference/afuc_test.asm /tmp/afuc_test.asm
$ echo $?
0
Suggested-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8290>
Dylan Baker [Tue, 1 Dec 2020 21:07:56 +0000 (13:07 -0800)]
bin/remove get-pick-list.sh files
These haven't been used for a long time, they've been supersceeded by
pick-ui
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7863>
Dylan Baker [Tue, 1 Dec 2020 21:06:04 +0000 (13:06 -0800)]
pick-ui: don't handle the mouse
It's annoying, since it prevents linux "midle click" copy-n-paste
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7863>
Erik Faye-Lund [Mon, 4 Jan 2021 09:35:36 +0000 (10:35 +0100)]
gallium/util: do not perform n^2 stencil blits
We already loop n times here, no point in doing n instances as well.
Fixes:
e8a40715a8b ("gallium/util: add blitter-support for stencil-fallback")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8301>
Rob Clark [Tue, 5 Jan 2021 20:38:02 +0000 (12:38 -0800)]
freedreno/ir3/parser: Fix pre-a6xx stib parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 5 Jan 2021 20:28:53 +0000 (12:28 -0800)]
freedreno/ir3/parser: a6xx ldib/stib parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 5 Jan 2021 19:39:26 +0000 (11:39 -0800)]
freedreno/ir3: Fix pre-a6xx ldgb/stib parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 5 Jan 2021 18:47:08 +0000 (10:47 -0800)]
freedreno/ir3: Explicitly flag disasm test vectors that don't parse
Mark the test cases which aren't supported by ir3_parser.y explicitly,
so we notice future regressions. And likewise, fail when we see an
unexpected pass, so we don't forget to update the test vectors in the
future as ir3_parser improves.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 4 Jan 2021 20:47:36 +0000 (12:47 -0800)]
freedreno/ir3: Fix ldg decoding/parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 4 Jan 2021 19:30:32 +0000 (11:30 -0800)]
freedreno/ir3/parser: Fixup stg parsing and add more tests
The offset can also be a register, in which case we need to shuffle
around the src order. Add a few more test vectors to cover each
permutation (no offset, immed offset, gpr offset).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 3 Jan 2021 18:08:21 +0000 (10:08 -0800)]
freedreno/ir3/parser: Add stgb support
Note that this conflicts with `stc` on a6xx+, so a good test that the
(new) disasm can handle both cases properly.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Thu, 31 Dec 2020 19:08:37 +0000 (11:08 -0800)]
freedreno/ir3/parser: Add ldgb support
Gives us at least better coverage of pre-a6xx-bindless-ibo instructions.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Thu, 31 Dec 2020 00:58:09 +0000 (16:58 -0800)]
freedreno/ir3/parser: Fix pre-a6xx resinfo
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Thu, 31 Dec 2020 00:04:55 +0000 (16:04 -0800)]
freedreno/ir3/parser: Fix atomic support
1) Handle a6xx bindless form
2) Fix shared vs global encoding
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Wed, 30 Dec 2020 23:18:16 +0000 (15:18 -0800)]
freedreno/ir3/parser: Add ldc support
Note that this shows up a slight encoding difference compared to test
vector extracted from blob deqp runs. We think these should be dontcare
bits. For now, add a note and replace the encoded value in the disasm
test.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Wed, 30 Dec 2020 23:00:44 +0000 (15:00 -0800)]
freedreno/ir3: Add cat5/cat6 nonuniform flag
Not yet used by the compiler, but needed so we don't loose information
between ir3 parser and instruction encoding.
Currently ignored for cat5, because the uniform vs non-uniform default
is swapped there.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Wed, 30 Dec 2020 21:23:18 +0000 (13:23 -0800)]
freedreno/ir3: Disambiguate a6xx+ "bindless" instructions
Add a `.b`.. for the atomic instructions it should be `atomic.b.op` but
for now put the `.b` at the end to simplify life for the existing disasm
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 28 Dec 2020 17:05:08 +0000 (09:05 -0800)]
freedreno/ir3: Don't leak disk_cache
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 20:35:08 +0000 (12:35 -0800)]
freedreno/ir3: Add parsing and assembler testing
In theory we should be able to round-trip from disasm->asm and get a
bitwise match.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 19:08:05 +0000 (11:08 -0800)]
freedreno/ir3: Tweak ldib/resinfo encoding
The blob is using '0' for the low bit in these (except for ldib where it
seems to randomly use either '0' or '1'). The upcoming xml based ISA
spec maps this bit to 'dontcare' in the ldib case.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 18:59:15 +0000 (10:59 -0800)]
freedreno/ir3/parser: Add initial cat6 IBO instructions
Well, really just resinfo.. dealing with the different ldib/stib syntax
for a6xx+ vs earlier seems a bit too painful to deal with. But resinfo
at least gives us some encoding test coverage of this group of instrs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 17:34:13 +0000 (09:34 -0800)]
freedreno/ir3/parser: Relative gpr/const can have modifiers too
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 17:15:54 +0000 (09:15 -0800)]
freedreno/ir3/parser: Add missing (sat) modifier
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 17:05:05 +0000 (09:05 -0800)]
freedreno/ir3: Don't set bit for dest conversion for p0.c
This appears to be ignored when writing to predicate registers (which I
guess makes sense, since they are boolean). So no real harm in setting
it, other than it makes some of the ir3_parser test vectors not match
the expected result for encoding.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 16:44:49 +0000 (08:44 -0800)]
freedreno/ir3/parser: Fixup cat5 s2en instructions
Currently ir3 (incl emit_cat5()) expects the samp/tex src register to be
first.. which requires some fixup for the parser to match.
TODO we might want to revisit the src reg order when adding new instr
packing/encoding. For now, lets just make the parser match the rest of
ir3.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 20:52:08 +0000 (12:52 -0800)]
freedreno/ir3/parser: Fix dsxpp/dsypp encoding
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 20:35:27 +0000 (12:35 -0800)]
freedreno/ir3/parser: Fix cat6 store encoding
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 19:05:57 +0000 (11:05 -0800)]
freedreno/ir3: Cleanup cat6 load instructions
There was some src2 vs src3 confusion, but since the syntax is like:
ldl.f32 rDst, l[rBase+off], ncomp
it makes more sense to call the offset src2 and ncomp src3, than the
way we had it. This is also easier to deal with for the ir3 assembly
parser.
Also, src_offset was only ever used by the assembly parser, and was
handled incorrectly in emit_cat6(), resulting that cat6 load instrs
would not work properly in (for ex) computerator. Since we are
cleaning things up, drop src_offset and make the asm parser work in
the same way as the nir->ir3 frontend.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 17:58:45 +0000 (09:58 -0800)]
freedreno/ir3: Clean up instruction creation
Convert everything remaining over to the version which takes # of
register (src + dst) and drop the ir3_instr_create2() version.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 23:36:24 +0000 (15:36 -0800)]
freedreno/ir3/parser: Handle half-immed
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 23:14:26 +0000 (15:14 -0800)]
freedreno/ir3/parser: cat1 updates (mova1, movmsk)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 22:15:13 +0000 (14:15 -0800)]
freedreno/ir3/parser: cat1 instructions can write relative GPR
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 22:05:58 +0000 (14:05 -0800)]
freedreno/ir3/parser: Add new cat0 instructions
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 21:46:59 +0000 (13:46 -0800)]
freedreno/ir3: Various cat0 updates
Update the IR and packer to handle the additional cat0 fields, in
prep for adding support in the assembler (in prep for adding round
trip parsing/packing test coverage).
We don't actually use these yet from the ir3 compiler, but at least
this is one less thing to worry about when we start trying to use
them.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 21:17:36 +0000 (13:17 -0800)]
freedreno/ir3/parser: Reset lexer when input changes
Otherwise, in case of parse errors, the lexer state can still contain
buffered input from the previous parse.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 19:45:31 +0000 (11:45 -0800)]
freedreno/ir3: Move assembler error handling
Move out of ir3_parse_asm() so we can re-use it in disasm test for
round-tripping asm/disasm. We don't want failures to be fatal (yet)
as there are still some things missing from the assembler.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 15 Dec 2020 17:58:15 +0000 (09:58 -0800)]
freedreno/ir3: Add some more disasm test vectors
Various things that I noticed which were initially wrong with the xml
based disasm.
These were extracted from a collection of unique instructions extracted
from deqp traces, which unfortunately looses the link back to the
original test case.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 15 Dec 2020 18:50:28 +0000 (10:50 -0800)]
freedreno/ir3: Fix mova1 disasm
Yet another mnemonic for mov
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 14 Dec 2020 18:56:04 +0000 (10:56 -0800)]
freedreno/ir3: Fix half-immed decoding issues
For mov, half-float immeds are packed in 16b. In other cases, the
syntax for a half-immed is a bit different (ie. `h(1)`)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Connor Abbott [Mon, 14 Sep 2020 10:15:16 +0000 (12:15 +0200)]
ir3: Support MOVMSK
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Connor Abbott [Wed, 16 Sep 2020 14:44:08 +0000 (16:44 +0200)]
ir3: Better rules for shared src copy propagation
It turns out that the actual rule for when a source/dest can be shared
is that it has to be cat1, cat2, or cat3. Allow this and silence
warnings.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Connor Abbott [Thu, 10 Sep 2020 10:14:24 +0000 (12:14 +0200)]
ir3: Rename high registers to shared registers
This more accurately reflects what they are.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Danylo Piliaiev [Wed, 30 Dec 2020 13:59:46 +0000 (15:59 +0200)]
freedreno: Enable GLSL 3.30, updating us to GL 3.3 contexts
All necessary features are already supported.
GL33 CTS failures:
KHR-GL33.texture_swizzle.smoke - timeouts, passes otherwise
KHR-GL33.cull_distance.coverage - see
https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/2673
fix is not in the public repo yet.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8270>
Christian Gmeiner [Sat, 2 Jan 2021 08:32:56 +0000 (09:32 +0100)]
pan: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:29:05 +0000 (09:29 +0100)]
microsoft/compiler: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:14:32 +0000 (09:14 +0100)]
anv: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:14:08 +0000 (09:14 +0100)]
intel/compiler: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:13:30 +0000 (09:13 +0100)]
intel/blorp: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:51:29 +0000 (08:51 +0100)]
vc4: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:43:52 +0000 (08:43 +0100)]
iris: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:40:37 +0000 (08:40 +0100)]
d3d12: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:31:11 +0000 (08:31 +0100)]
tu: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 06:42:52 +0000 (07:42 +0100)]
zink: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 06:36:02 +0000 (07:36 +0100)]
st: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 20:33:35 +0000 (21:33 +0100)]
ir3: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:52:20 +0000 (20:52 +0100)]
v3dv: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:51:03 +0000 (20:51 +0100)]
v3d: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:37:53 +0000 (20:37 +0100)]
nir: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:53:51 +0000 (20:53 +0100)]
tgsi_to_nir: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:33:32 +0000 (20:33 +0100)]
mesa/prog_to_nir: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Mike Blumenkrantz [Fri, 7 Aug 2020 20:19:19 +0000 (16:19 -0400)]
nir: preserve explicit_binding in lower_atomics_to_ssbo
it's important to be able to tell whether this is explicitly set by the
user
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7489>
Erik Faye-Lund [Wed, 6 Jan 2021 05:59:27 +0000 (06:59 +0100)]
zink: remove support for fcsel
fcsel is only emitted by bool -> float lowering. We used to do that a
long time ago, but no longer. So we don't need to support this opcode
any longer.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8347>
Erik Faye-Lund [Wed, 6 Jan 2021 06:38:41 +0000 (07:38 +0100)]
zink: also lower scmp for soft-fp
We recently added two versions of these options, due to soft-fp support.
So let's also add the lowering to the soft-fp version.
Fixes:
43302ead383 ("zink: use lower_scmp instead of open-coding")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8347>
Boris Brezillon [Tue, 5 Jan 2021 13:02:07 +0000 (14:02 +0100)]
panfrost: Fix AFBC on Bifrost v6
The AFBC layout of RT/ZS-extension descriptors on Bifrost v6 matches the
v7 one except for the Block Format field. Update the set_buf() functions
accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8328>
Yogesh mohan marimuthu [Mon, 14 Dec 2020 15:56:27 +0000 (21:26 +0530)]
radeonsi: enable vrs2x2 coarse shading if flat shading (v9)
Enable vrs2x2 coarse shading if flat shading as per
idea and guidance given by Marek.
is_flat_shading variable in struct si_shader_info is set
based on the data from gather_intrinsic_info() function
and struct si_state_rasterizer. If is_flat_shading_variable
is set, then in function si_emit_db_render_state() vrs2x2
shading is enabled in hardware.
v2: Fix review comments from Pierre-Eric. Code optimizations.
v3: Fix indentation style issue.
v4: Fix review comments from Marek. Fixed logical issue pointed
by Marek where info->is_flat_shading variable can be corrupted
and other code cleanup.
v5: Make the code compact as suggested by Pierre-Eric.
v6: Fix new review comments from Marek.
v7: use info->uses_interp_color variable fix from Marek.
v8: Fix coding style comment from Marek.
v9: Add uses_fbfetch_output check as suggested by Marek.
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8161>
Eric Anholt [Mon, 21 Dec 2020 23:29:19 +0000 (15:29 -0800)]
gallium/ntt: Add support for PIPE_CAP_LOAD_CONSTBUF.
We needed to do this anyway to finish enabling NTT in general, but more
importantly: when we enabled sending NIR to the draw module, that broke
PIPE_CAP_LOAD_CONSTBUF drivers in the select/feedback paths if LLVM was
disabled.
Fixes:
44b7e1497f91 ("st/mesa: don't generate TGSI for the draw VS because it now supports NIR too")
(along with the rest of this MR)
Closes: #3996
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 22 Dec 2020 00:22:03 +0000 (16:22 -0800)]
gallium/ntt: Fix load_ubo_vec4 buffer index setup.
I had a funny +1 in nir_to_tgsi's load_ubo lowering on the buffer index,
because I hadn't set lower_uniform_to_ubo for softpipe. This removes that
weirdness in favor of just using lower_uniform_to_ubo, regardless of
driver preference (which matters if a NIR-native driver had it set, and
then the gallium draw module triggered the non-LLVM TGSI fallback path
that hit NTT).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 22 Dec 2020 01:12:02 +0000 (17:12 -0800)]
gallium/ntt: Fix dynamic indirect indexing of per_vertex_input.
It was off by one due to some copy and paste from UBO handling.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Fri, 11 Dec 2020 21:11:26 +0000 (13:11 -0800)]
gallium/ntt: Fix emitting UBO declarations.
Fixes:
d70fff99c5bc ("nir: Use a single list for all shader variables")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 5 Jan 2021 19:15:06 +0000 (11:15 -0800)]
gallium/tgsi_exec: Add support for PIPE_CAP_LOAD_CONSTBUF.
Now that we can end up in nir-to-tgsi in the draw fallback paths of
drivers with that flag set, we need to support it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 5 Jan 2021 19:12:11 +0000 (11:12 -0800)]
gallium/tgsi_exec: Refactor to fix CS local memory overflow checks.
It was OK because right now we only execute in the first channel of the
CS, but if you wanted to extend that then you'd need to check each
channel. We already had what we needed for SSBOs, so just reuse it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Thu, 10 Dec 2020 19:34:48 +0000 (11:34 -0800)]
gallium/tgsi_exec: Fix assertion failure about missing constbufs.
GL by default gives you UB when you access a missing constbuf, and we were
crashing on debug builds in that case. More importantly, we were
assertion failing even under valid circumstances, when a !ExecMask channel
had a bad value for the indirect buffer index and we tried to load from it
anyway.
In removing the assertion, also sink the buf declaration to after we've
done the bounds check that determines that there's a constbuf actually
bound to this index.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Jesse Natalie [Mon, 14 Dec 2020 19:59:53 +0000 (11:59 -0800)]
d3d12: Don't allocate mappable textures
There's not really a reason to directly map textures. Doing so
requires the texture to be allocated in system RAM instead of
video RAM, which means all GPU access to it would be needlessly slow.
Notably, the one texture type that was allocated this way is the
display target texture for the software driver path. Instead, use
pipe_transfer_map to be able to copy the texture to system RAM.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
Jesse Natalie [Mon, 14 Dec 2020 19:53:39 +0000 (11:53 -0800)]
d3d12: Use an appropriate pipe resource usage for map intermediates
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
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