GDB Administrator [Wed, 3 Feb 2016 00:00:58 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Tue, 2 Feb 2016 16:14:43 +0000 (08:14 -0800)]
Store estimated distances in compressed_size
elf_x86_64_convert_load is very time consuming since it is called on
each input section and has a loop over input text sections to estimate
the branch distrance. We can store the estimated distances in the
compressed_size field of the output section, which is only used to
decompress the compressed input section.
Before the patch, linking clang 3.9 takes 52 seconds. After the patch,
it only takes 2.5 seconds.
Backport from master
PR ld/19542
* elf64-x86-64.c (elf_x86_64_convert_load): Store the estimated
distances in the compressed_size field of the output section.
H.J. Lu [Tue, 2 Feb 2016 14:36:52 +0000 (06:36 -0800)]
Add a testcase for PR ld/18591
Backport from master
PR ld/18591
* testsuite/ld-x86-64/pr18591.d: New file.
* testsuite/ld-x86-64/pr18591.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run pr18591.
GDB Administrator [Tue, 2 Feb 2016 00:00:56 +0000 (00:00 +0000)]
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John David Anglin [Mon, 1 Feb 2016 21:31:58 +0000 (16:31 -0500)]
Fix /usr/bin/ld: final link failed: File truncated error on hppa
GDB Administrator [Mon, 1 Feb 2016 00:00:51 +0000 (00:00 +0000)]
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GDB Administrator [Sun, 31 Jan 2016 00:00:44 +0000 (00:00 +0000)]
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H.J. Lu [Fri, 29 Jan 2016 15:47:45 +0000 (07:47 -0800)]
Replace == with = in gas/configure.ac
Backport from master
PR gas/19532
* configure.ac (compressed_debug_sections): Replace == with =.
* configure: Regenerated.
H.J. Lu [Fri, 29 Jan 2016 15:47:13 +0000 (07:47 -0800)]
Replace == with = in ld/configure.ac
Backport from master
PR ld/19533
* configure.ac (compressed_debug_sections): Replace == with =.
* configure: Regenerated.
GDB Administrator [Sat, 30 Jan 2016 00:00:54 +0000 (00:00 +0000)]
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GDB Administrator [Fri, 29 Jan 2016 00:00:51 +0000 (00:00 +0000)]
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GDB Administrator [Thu, 28 Jan 2016 00:00:55 +0000 (00:00 +0000)]
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GDB Administrator [Wed, 27 Jan 2016 00:00:50 +0000 (00:00 +0000)]
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GDB Administrator [Tue, 26 Jan 2016 00:00:58 +0000 (00:00 +0000)]
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Tristan Gingold [Mon, 25 Jan 2016 09:54:54 +0000 (10:54 +0100)]
Bump to 2.26.0
bfd/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* version.m4: Bump version to 2.26.0
* configure: Regenerate.
binutils/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
gas/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
gprof/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
ld/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
opcodes/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
Tristan Gingold [Mon, 25 Jan 2016 09:20:17 +0000 (10:20 +0100)]
Add generated files
Tristan Gingold [Mon, 25 Jan 2016 09:16:49 +0000 (10:16 +0100)]
Bump version to 2.26
bfd/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* version.m4: Bump version to 2.26
* configure: Regenerate.
binutils/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
gas/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
gprof/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
ld/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
opcodes/
2016-01-25 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
GDB Administrator [Mon, 25 Jan 2016 00:00:59 +0000 (00:00 +0000)]
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GDB Administrator [Sun, 24 Jan 2016 00:00:50 +0000 (00:00 +0000)]
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GDB Administrator [Sat, 23 Jan 2016 00:00:56 +0000 (00:00 +0000)]
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GDB Administrator [Fri, 22 Jan 2016 00:00:49 +0000 (00:00 +0000)]
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GDB Administrator [Thu, 21 Jan 2016 00:00:54 +0000 (00:00 +0000)]
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GDB Administrator [Wed, 20 Jan 2016 00:00:56 +0000 (00:00 +0000)]
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Nick Clifton [Tue, 19 Jan 2016 09:58:18 +0000 (09:58 +0000)]
Fix PR18735 test for RL78.
* ld-elf/pr18735.d: Allow for extra symbols between
foo@FOO and bar@@FOO.
GDB Administrator [Tue, 19 Jan 2016 00:00:54 +0000 (00:00 +0000)]
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Alan Modra [Mon, 18 Jan 2016 05:36:49 +0000 (16:06 +1030)]
Provide AC_PROG_LEX that copes with LEX=missing from top-level
config/
PR binutils/19481
* override.m4 (AC_PROG_LEX): Define.
binutils/
* configure: Regenerate.
gas/
* configure: Regenerate.
ld/
* configure: Regenerate.
Nick Clifton [Mon, 18 Jan 2016 11:23:00 +0000 (11:23 +0000)]
Skip linker plugin tests if the linker has not been configured to support plugins.
* ld-plugin/plugin.exp: Skip plugin tests if the linker is not
configured to support plugins.
GDB Administrator [Mon, 18 Jan 2016 00:00:54 +0000 (00:00 +0000)]
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GDB Administrator [Sun, 17 Jan 2016 00:00:47 +0000 (00:00 +0000)]
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GDB Administrator [Sat, 16 Jan 2016 00:00:52 +0000 (00:00 +0000)]
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GDB Administrator [Fri, 15 Jan 2016 00:00:47 +0000 (00:00 +0000)]
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Alan Modra [Thu, 14 Jan 2016 08:32:18 +0000 (19:02 +1030)]
Revert "Strip undefined symbols from .symtab"
This reverts commit
d983c8c5503d680c6d4955ceb610a9beebc64460 and
db95bb7c5946a109e1584ab2c43c052ff39e63bd
The PR4317 patch introduced a ppc64le linux kernel build problem.
PR ld/19421
PR ld/4317
bfd/
* elflink.c (elf_link_input_bfd): Revert 2015-02-19 changes.
(elf_link_output_extsym): Likewise.
ld/
* ld-aarch64/gc-tls-relocs.d: Revert 2015-02-19 changes.
* ld-cris/locref2.d: Likewise.
* ld-elf/ehdr_start-weak.d: Likewise.
* ld-elf/group1.d: Likewise.
* ld-i386/compressed1.d: Likewise.
* ld-ia64/error1.d: Likewise.
* ld-ia64/error2.d: Likewise.
* ld-ia64/error3.d: Likewise.
* ld-mips-elf/pic-and-nonpic-1.nd: Likewise.
* ld-mmix/undef-3.d: Likewise.
* ld-powerpc/tlsexe.r: Likewise.
* ld-powerpc/tlsexetoc.r: Likewise.
* ld-powerpc/tlsso.r: Likewise.
* ld-powerpc/tlstocso.r: Likewise.
* ld-x86-64/compressed1.d: Likewise.
* ld-x86-64/pie1.d: Likewise.
GDB Administrator [Thu, 14 Jan 2016 00:00:53 +0000 (00:00 +0000)]
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Nick Clifton [Wed, 13 Jan 2016 10:01:35 +0000 (10:01 +0000)]
Mark the linker's -Bsymbolic-functions test as an expected failure for MIPS targets.
* ld-elf/elf.exp (-Bymsolic-functions): Expect to fail
for MIPS targets.
Nick Clifton [Wed, 13 Jan 2016 09:41:04 +0000 (09:41 +0000)]
Mark the linker's extract symbols test as an expected failure for MIPS targets.
* ld-scripts/script.exp (extract_symbol_test): Expect to
fail for MIPS targets.
Nick Clifton [Wed, 13 Jan 2016 09:28:02 +0000 (09:28 +0000)]
Mark the rgn-at11 test as an expected failure for MIPS targets.
* ld-scripts/rgn-at11.d: Expect this test to fail for
MIPS targets.
GDB Administrator [Wed, 13 Jan 2016 00:00:46 +0000 (00:00 +0000)]
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Peter Bergner [Tue, 12 Jan 2016 15:20:19 +0000 (09:20 -0600)]
Delete opcodes that have been removed from ISA 3.0.
opcodes/
Apply from master.
2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c <xscmpnedp>: Delete.
<xvcmpnedp>: Likewise.
<xvcmpnedp.>: Likewise.
<xvcmpnesp>: Likewise.
<xvcmpnesp.>: Likewise.
gas/testsuite/
Apply from master.
2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp.,
xvcmpnesp, xvcmpnesp.>: Delete tests.
* gas/ppc/power9.s: Likewise.
* gas/ppc/vsx3.d: Likewise.
* gas/ppc/vsx3.s: Likewise.
GDB Administrator [Tue, 12 Jan 2016 00:01:00 +0000 (00:01 +0000)]
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Kwok Cheung Yeung [Thu, 10 Dec 2015 16:11:07 +0000 (16:11 +0000)]
ld: Fix LTO for MinGW targets
When creating a dummy BFD for an IR file, the output BFD is used as
a template for the new BFD, when it needs to be the input BFD passed
into the function when not dealing with a BFD plugin.
On most targets this is not an issue as the input and output formats
are the same anyway, but on MinGW targets, there are two variant
formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are
similar but not interchangeable here.
PR ld/18199
* plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the
template when calling bfd_create if it does not use the BFD
plugin target vector.
(Cherry-picked from commit
4a07dc81356ed8728e204e9aabeb256703c59aef)
Jiong Wang [Mon, 11 Jan 2016 10:49:57 +0000 (10:49 +0000)]
[BACKPORT][ARM] PR ld/19368: Add missing relocation type class for R_ARM_IRELATIVE
Apply from master
2016-01-08 Richard Sandiford <richard.sandiford@arm.com>
Jiong Wang <jiong.wang@arm.com>
bfd/
PR ld/19368
* elf32-arm.c (elf32_arm_reloc_type_class): Map R_ARM_IRELATIVE to
reloc_class_ifunc.
ld/testsuite/
* testsuite/ld-arm/ifunc-3.rd: Update expected result.
* testsuite/ld-arm/ifunc-4.rd: Likewise.
* testsuite/ld-arm/ifunc-9.rd: Likewise.
* testsuite/ld-arm/ifunc-10.rd: Likewise.
* testsuite/ld-arm/ifunc-12.rd: Likewise.
* testsuite/ld-arm/ifunc-13.rd: Likewise.
GDB Administrator [Mon, 11 Jan 2016 00:00:49 +0000 (00:00 +0000)]
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GDB Administrator [Sun, 10 Jan 2016 00:00:58 +0000 (00:00 +0000)]
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GDB Administrator [Sat, 9 Jan 2016 00:00:53 +0000 (00:00 +0000)]
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GDB Administrator [Fri, 8 Jan 2016 00:00:55 +0000 (00:00 +0000)]
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GDB Administrator [Thu, 7 Jan 2016 00:00:56 +0000 (00:00 +0000)]
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Maciej W. Rozycki [Mon, 4 Jan 2016 23:16:45 +0000 (23:16 +0000)]
MIPS/BFD: Propagate the return status in attribute merging
Fix the issue of any failure from `_bfd_elf_merge_object_attributes' not
being propagated by `mips_elf_merge_obj_attributes'.
bfd/
* elfxx-mips.c (mips_elf_merge_obj_attributes): Propagate the
return status from `_bfd_elf_merge_object_attributes'.
GDB Administrator [Wed, 6 Jan 2016 00:01:18 +0000 (00:01 +0000)]
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GDB Administrator [Tue, 5 Jan 2016 00:00:46 +0000 (00:00 +0000)]
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GDB Administrator [Sat, 2 Jan 2016 00:00:52 +0000 (00:00 +0000)]
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GDB Administrator [Fri, 1 Jan 2016 00:00:53 +0000 (00:00 +0000)]
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GDB Administrator [Thu, 31 Dec 2015 00:00:51 +0000 (00:00 +0000)]
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GDB Administrator [Wed, 30 Dec 2015 00:00:46 +0000 (00:00 +0000)]
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GDB Administrator [Tue, 29 Dec 2015 00:00:49 +0000 (00:00 +0000)]
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GDB Administrator [Mon, 28 Dec 2015 00:00:55 +0000 (00:00 +0000)]
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GDB Administrator [Sun, 27 Dec 2015 00:00:52 +0000 (00:00 +0000)]
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GDB Administrator [Sat, 26 Dec 2015 00:00:52 +0000 (00:00 +0000)]
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GDB Administrator [Fri, 25 Dec 2015 00:00:54 +0000 (00:00 +0000)]
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GDB Administrator [Wed, 23 Dec 2015 00:00:52 +0000 (00:00 +0000)]
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Andre Vieira [Wed, 25 Nov 2015 13:56:55 +0000 (13:56 +0000)]
Fix ldah being disassembled as ldaexh
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
opcodes/
* arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
<ldah>: ... to this.
gas/testsuite/
* gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ...
<ldah>: ... to this.
GDB Administrator [Tue, 22 Dec 2015 00:00:50 +0000 (00:00 +0000)]
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GDB Administrator [Mon, 21 Dec 2015 00:00:53 +0000 (00:00 +0000)]
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GDB Administrator [Sun, 20 Dec 2015 00:00:56 +0000 (00:00 +0000)]
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GDB Administrator [Sat, 19 Dec 2015 00:00:59 +0000 (00:00 +0000)]
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Andreas Krebbel [Thu, 19 Nov 2015 10:10:06 +0000 (11:10 +0100)]
[S/390] Add null ptr check + port GOTOFF handling from 32 bit over to 64 bit
bfd/ChangeLog:
PR ld/19263
* elf32-s390.c (elf_s390_gc_sweep_hook): Add null ptr check.
* elf64-s390.c (elf_s390_check_relocs): Port the GOTOFF handling
over from the 32 bit code.
(elf_s390_relocate_section): Likewise.
GDB Administrator [Fri, 18 Dec 2015 00:01:00 +0000 (00:01 +0000)]
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Ramana Radhakrishnan [Thu, 17 Dec 2015 16:44:08 +0000 (16:44 +0000)]
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that
Add missing ChangeLog entry.
Ramana Radhakrishnan [Thu, 17 Dec 2015 10:55:54 +0000 (10:55 +0000)]
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.
In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.
This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.
2015-12-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
TAG_ARCH_profile for armv8-a.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
Roland McGrath [Thu, 17 Dec 2015 00:35:59 +0000 (16:35 -0800)]
PR gold/17473: Fix gold build with system C++ headers that use <ctype.h>.
gold/
PR gold/17473
* binary.cc: Move #include "safe-ctype.h" to be last #include.
(cherry picked from commit
95c29a83ebadd0038fd304539a83c5e90798c1b9)
GDB Administrator [Thu, 17 Dec 2015 00:00:57 +0000 (00:00 +0000)]
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GDB Administrator [Wed, 16 Dec 2015 00:00:56 +0000 (00:00 +0000)]
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Nick Clifton [Tue, 15 Dec 2015 16:27:28 +0000 (16:27 +0000)]
Remove references to non-existent silicon errata.
* doc/c-msp430.texi (MSP430 Options): Remove references to a
non-existent silicon errata.
* config/tc-msp430.c: Likewise.
Matthew Wahab [Mon, 14 Dec 2015 16:28:46 +0000 (16:28 +0000)]
[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patch
A mistake with rebasing the ARMv8.2 AT instruction patch left this part
+ /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
+ if ((reg->value == CPENS (0, C7, C9, 0)
+ || reg->value == CPENS (0, C7, C9, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
in aarch64_pstatefield_supported_p rather than in
aarch64_sys_ins_reg_supported_p, where it was supposed to be.
The patch adding support for id_aa64mmfr2_el1, also had the effect of
removing a conditional branch in aarch64_sys_reg_supported_p.
The effect of both of these is to suppress an error if some ARMv8.2
system registers are used with the wrong -march settings.
This patch fixes these mistakes.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
removed statement.
(aarch64_pstatefield_supported_p): Move feature checks for AT
registers ..
(aarch64_sys_ins_reg_supported_p): .. to here.
Change-Id: I48783d118eaaf0f3312e8b08a8340ef7af4e36a4
Matthew Wahab [Mon, 14 Dec 2015 17:46:21 +0000 (17:46 +0000)]
[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
Matthew Wahab [Mon, 14 Dec 2015 17:40:03 +0000 (17:40 +0000)]
[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.
The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, #<imm>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_VSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD shift by immediate group.
Change-Id: I3480f63883d54db46562573185da6982f2365ee8
Matthew Wahab [Mon, 14 Dec 2015 17:35:47 +0000 (17:35 +0000)]
[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
Pairwise instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_PAIR_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
Matthew Wahab [Mon, 14 Dec 2015 17:27:52 +0000 (17:27 +0000)]
[AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.
The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
take into account new vector type 2H.
(vectype_to_qualifier): Likewise.
include/opcode/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (enum aarch64_opnd_qualifier): Add
AARCH64_OPND_QLF_V_2H.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
and adjust calculation to ignore qualifier for type 2H.
* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
Matthew Wahab [Mon, 14 Dec 2015 17:25:35 +0000 (17:25 +0000)]
[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.
The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.
The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.
This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
qualifier from per-type base and offet.
Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
Matthew Wahab [Mon, 14 Dec 2015 17:22:36 +0000 (17:22 +0000)]
[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.
The instruction added is: FMOV.
The form of this instructions is
<OP> <Hd>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SIMD_IMM_H): New.
(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
modified immediate group.
Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
Matthew Wahab [Mon, 14 Dec 2015 17:16:50 +0000 (17:16 +0000)]
[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.
The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
fminnmv, fminv to the Adv.SIMD across lanes group.
Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
Matthew Wahab [Mon, 14 Dec 2015 17:07:51 +0000 (17:07 +0000)]
[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <Hd>, <Hs>, <V>.h[<idx>]
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
fmls, fmul and fmulx to the scalar indexed element group.
Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
Matthew Wahab [Mon, 14 Dec 2015 17:01:56 +0000 (17:01 +0000)]
[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
where T is 4h or 8h
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
fmulx to the vector indexed element group.
Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
Matthew Wahab [Mon, 14 Dec 2015 16:57:04 +0000 (16:57 +0000)]
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
Matthew Wahab [Mon, 14 Dec 2015 16:54:38 +0000 (16:54 +0000)]
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
Matthew Wahab [Mon, 14 Dec 2015 16:49:34 +0000 (16:49 +0000)]
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
Matthew Wahab [Mon, 14 Dec 2015 16:44:02 +0000 (16:44 +0000)]
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
Matthew Wahab [Mon, 14 Dec 2015 16:34:47 +0000 (16:34 +0000)]
[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.
The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
Immediate.
This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_simd_f16): New.
(SIMD_F16): New.
Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f
GDB Administrator [Tue, 15 Dec 2015 00:00:59 +0000 (00:00 +0000)]
Automatic date update in version.in
Matthew Wahab [Fri, 11 Dec 2015 10:22:40 +0000 (10:22 +0000)]
[AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.
A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
(parse_barrier_psb): New.
(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
(md_begin): Set up aarch64_hint_opt_hsh.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: Enable the statistical profiling
extension. Update the expected output.
* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
* gas/aarch64/system.d: Update the expected output.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): Add "csync".
(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_feature_stat_profile): New.
(STAT_PROFILE): New.
(aarch64_opcode_table): Add "psb".
(AARCH64_OPERANDS): Add "BARRIER_PSB".
Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
Matthew Wahab [Fri, 11 Dec 2015 10:11:27 +0000 (10:11 +0000)]
[AArch64][Patch 4/5] Support HINT aliases taking operands.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_hint_options): Declare.
(aarch64_opnd_info): Add field hint_option.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm.c (aarch64_ins_hint): New.
* aarch64-asm.h (aarch64_ins_hint): Declare.
* aarch64-dis.c (aarch64_ext_hint): New.
* aarch64-dis.h (aarch64_ext_hint): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): New.
* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
Matthew Wahab [Fri, 11 Dec 2015 09:56:07 +0000 (09:56 +0000)]
[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
Change-Id: I131044bf6e0fe0940a9e7478d9bf52137748907d
Matthew Wahab [Fri, 11 Dec 2015 09:52:11 +0000 (09:52 +0000)]
[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
pmscr_el2.
(aarch64_sys_reg_supported_p): Add architecture feature tests for
the new registers.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
system registers.
* gas/aarch64/sysreg-2.d: Enable the statistical profiling
extension and update the expected output.
Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
Matthew Wahab [Fri, 11 Dec 2015 09:30:26 +0000 (09:30 +0000)]
[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.
The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.
This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "profile".
* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_PROFILE): New.
Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
Matthew Wahab [Thu, 10 Dec 2015 16:58:51 +0000 (16:58 +0000)]
[Aarch64] Support ARMv8.2 AT instructions
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
Matthew Wahab [Thu, 10 Dec 2015 16:38:44 +0000 (16:38 +0000)]
[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.
Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
Matthew Wahab [Thu, 10 Dec 2015 16:31:35 +0000 (16:31 +0000)]
[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.
The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
(F_HASXT): New.
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
(aarch64_sys_regs_dc): Likewise.
(aarch64_sys_regs_at): Likewise.
(aarch64_sys_regs_tlbi): Likewise.
(aarch64_sys_ins_reg_has_xt): New.
Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
Matthew Wahab [Thu, 10 Dec 2015 16:01:29 +0000 (16:01 +0000)]
[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/uao-directive.d: New.
* gas/aarch64/uao.d: New.
* gas/aarch64/uao.s: New.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "uao".
(aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
(aarch64_pstatefields): Add "uao".
(aarch64_pstatefield_supported_p): Add checks for "uao".
Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
projects / external / binutils.git / log