pan/mdg: Don't print zero

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Reduced printed parens

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Don't print mem addr brackets

Already comma separated.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Don't print explicit .rte

Default round mode.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Suppress most attribute tables

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Don't print zero shifts

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: More concise RMU name

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Hide units behind MIDGARD_MESA_DEBUG=verbose

Not usually interesting unless debugging bundling.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Key blend shaders to the input types

On Bifrost, fragment shaders might output either FP16 or FP32. The blend
shader will access the output as-is within the register, so depending on
the precision of the blend shader's logic, it may need to insert a
f2f16 or f2f32 conversion. This requires expanding the blend shader key.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/blend: Emit explicit conversions for all types

Needed so we can mix and match.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/lower_framebufffer: Don't use i2imp

Fails when converting from i2i8, which is possible.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Assume lower_fragcolor has been called

Allows us to clean up quite a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Call nir_lower_fragcolor based on key

We only want it to trigger if MRT is actually in use. This is a cheap
key (only require multiple variants for an obscure edge case) and avoids
the perf regression of using this pass which is needed for conformance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Prepare for lower_fragcolor

FRAG_RESULT_COLOR means something a bit different.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Distribute to_c_factor

Easier to understand, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Workaround a v7 implementation-detail

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Fix outdated comments

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/lower_blend: Rename is_bifrost->scalar

Don't leak ISA details.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/lower_blend: Use NIR helpers

Deletes a bunch of indentations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/lower_blend: Clean up type size handling

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Don't clobber RT0 if RTn is disabled

Fixes: a124c47b9f9 ("panfrost: Fix NULL derefs in pan_cmdstream.c")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Minor cleanup of blend CSO

No need to cast.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Support alpha_to_one

Gets rid of a bogus assert in the blend CSO create.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Make comment less confusing

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Lower 8-bit fragment input

Same reasons/technique as fragment output lowering, just need the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Handle swizzles in i2i8

Otherwise they get copypropped away.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Add single-component 8-bit mkvec lowering

So we can implement scalar i2i8.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Handle different sizes of LD_TILE

v2: Fix overflow.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Track dual-src blend type

Will be needed for fp16 outputs. I am acutely aware dual-src blending is
broken on Bifrost right now anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

venus: query extended resource info from gralloc

Creating Android swapchain image from gralloc buffer requires to use
VkImageDrmFormatModifierExplicitCreateInfoEXT. To fill the struct info,
we need to query extended resource info from gralloc.

With the queried modifier from gralloc, we can ask the driver for the
plane count of the given format and modifier pair.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10553>

tgsi: Mark the tgsi_exec_channel and tgsi_double_channel ALIGN16.

We allocate them all align16, so mark the unions (and their container
structs) that way so the compiler can do aligned SSE load/stores.

glmark2 -b loop FPS +0.197265% +/- 0.117633% (n=1906)

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10604>

radv: Add a STONEY baseline for dEQP.

See:
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9286188
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297109
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297110

v2.
  - Clarify that the dEQP-VK.texture.explicit_lod.2d tests are skipped
  due to slow APU-based STONEY test devices.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10559>

v3d: choose a larger CSD supergroup size if possible

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

broadcom/common: move CSD supergroup sizing to a common helper

We want to use this in GL too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

v3dv: limit supergroup size in presence of TSY barriers

When a TSY barrier is hit, the entire supergroup will be synchronized.
If the supergoup is large and uses all available QPU threads it would
mean that we would sychronize and stall all running threads until all
of them reach the barrier, which may be inefficient.

This patch makes it so that if the compute shader has any such barriers
we limit the supergroup size so each supergroup only takes half of the
QPU threads available at most, so that if one supergroup hits a
barrier we have at least one other supergroup we can run, reducing
idle QPU time.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

broadcom/compiler: track if a shader has control barriers in prog_data

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

v3dv: choose a larger CSD supergroup size if possible

Each supergroup executes a number batches. Each batch has 16 elements
(one per QPU lane), except possibly the last batch which might be
incomplete. Until now, we packed a single workgroup in each supergroup,
which can lead to more incomplete batches and less efficient use
of the QPUs depending on the configuration of workgroups being dispatched.

This patch computes a number of workgroups per supergroup so that
we reduce or completely eliminate incomplete batches if possible.

It should be noted however, that TSY barriers act on supergroups,
so larger supergroups lead to larger syncpoints on barriers too.
A follow-up patch will try to find a good balance for compute shaders
that use such barriers.

This improves performance of the Sascha Willem's computecloth demo
by ~13%.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

compiler/nir: add a divergence analysis option for non-uniform workgroup id

The V3D hardware allows us to pack multiple workgroups together to avoid
wasting execution lanes in shader cores.

For example, if we dispatch 16 workgroups with a local size of 1 element, we
can pack all 16 workgroups in a single 16-wide dispatch where each lane
executes a different workgroup, instead of 16 1-wide dispatches.

When we do this, we don't have a uniform workgroup id any more.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

intel/compiler: Remove unused exported functions

Now that all drivers are using brw_cs_get_dispatch_info() we can
remove one function (which is now unused) and reduce the scope of the
other.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

i965: Use brw_cs_get_dispatch_info()

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

anv: Use brw_cs_get_dispatch_info()

And since right_mask is already provided as part of dispatch_info,
just use that instead of storing it.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

iris: Use brw_cs_get_dispatch_info()

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

intel/compiler: Add common function for CS dispatch info

We have this small calculations repeated in each Intel driver, so move
them to a single place to be reused.  Also includes "right_mask" since
is always used in the same context and depends on the dispatch info
values.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

nir: Remove now unnecessary conditions from emit_load/store helpers

The mode one was used before 0bc5a829dd6 ("nir: Remove shared support from
lower_io").

The others were used before 5f7c7c9a7f7 ("nir: add src and dest types
to all IO loads and stores for mediump").

All conditions now are always true, so drop them.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10533>

panfrost/ci: Run the full deqp-gles3 testsuite

We recently added 5 more VIM3s to the lavalab, this should be more than
enough to run the full GLES 3.0 testsuite on G52.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10614>

docs: update gallium doxygen docs

Gallium's background as a Tungstend Graphics technology is no longer
significant; it's a historical detail. Besides, since Tungsten Graphics
were acquired by VMware more than a decade ago, the website no longer
exists.

While we're at it, replace the docs link with a link to the mesa docs,
and point to archive.org copy of the Tungsten Graphics paper.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2770
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10452>

nir/opt_algebraic: optimizations for add umax/umin with zero

For unsigned comparisons with zero these ops can be eliminated.

v2: Add comparison optimizations with -1 (Rhys Perry)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10583>

lavapipe: consistently use nir macros

NIR provides two helper macros to run transformation passes correctly,
NIR_PASS() and NIR_PASS_V(). So far we've seemingly been a bit haphazard
about when to use them.

Let's correct that, and consistently use the NIR helpers here. This
helps us in two ways:

1. We now run nir_validate_shader after each pass, ensuring we didn't
   break the shader
2. We now respect the NIR_PRINT environment variable for all NIR passes,
   making debugging much less surprising.

In addition, we had an OPT()-macro that doesn't seem to provide much
help other than to hiding some trivial details. But they make our code
different to other users of NIR, which doesn't seem ideal. So let's drop
that macro while we're at it.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10585>

radv: implement RADV_FORCE_VRS for the LLVM backend

Just to make it consistent compared to ACO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10432>

util: fix (re-enable) L3 cache pinning

cores_per_L3 was uninitialized, so it was always disabled.
Remove the variable and do it differently.

Fixes: 11d2db17c52 - util: rework AMD cpu L3 cache affinity code.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>

util: print CPU caps in release builds too

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>

i965: drop old brw ff gs code.

This isn't needed anymore.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>

i965: port fixed function geom shader to use compiler paths

This just moves to the common code in the compiler.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>

intel/compiler: add support for compiling fixed function gs

This is ported from i965, but the interface is cleaned up

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>

intel: move brw_ff_gs_prog_key/data to compiler.

Step one to moving the ff_gs emitter to compiler for sharing,
move BRW_MAX_SOL_BINDINGS up so the keys are in same area

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9721>

ci/freedreno: Add another db820c flake that's appeared in the last few months.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10597>

ci/freedreno: Fix the recent-a5xx-texture-flakes matches.

We've had about 1/day of the texelfetch group in the IRC flake reports
since apr 23, and tex-miplevel-selection that I marked before is actually
all the subtests it looks like.  Also, you can't include the ",Fail" if
you want to actually match a test name.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10597>

gallivm: Remove unused GALLIVM_NAN_RETURN_NAN

In the review, Roland says, "I think the unused nan behaviors was there
just for completeness, so it can easily go."

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>

gallivm: Use GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN for norm clamping

Since the second source is always a constant that is known to be a
number, this should have the same performance as
GALLIVM_NAN_BEHAVIOR_UNDEFINED.

A lofty goal is to eventually remove GALLIVM_NAN_BEHAVIOR_UNDEFINED.
There's still a lot of (mostly implicit) users, and I don't feel like
tackling that right now. :)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>

gallivm: Use range analysis to generate better fmin and fmax code

If it is known that one of the source must be a number, then the (more
efficient) GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN path can be used.

v2: s/know to be/known to be/.  Noticed by Roland.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>

gallivm: Fix NaN behavior of min and max

Like softpipe in mesa!10419, llvmpipe suffers from improper handling
of NaN in nir_op_fmax and nir_op_fmin.  nir_op_fsat is already handled
correctly.  OpenCL strictly requires the "NaN cleansing" behavior, so
all of the functionality is in place.  Just make the graphics APIs use
the OpenCL path.

The majority of the possible performance penalty incurred here should
be resolved in the next commit.

v2: Add updated checksum for bgfx/39-assao.rdc trace.  Rendering goes
from mostly garbage to looking correct to me.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>

tgsi_exec: Use C99 functions for min and max instead of open coding

I don't know what I was thinking when I wrote 939bf7a4198 ("tgsi_exec:
Fix NaN behavior of min and max") and d1c0f62b429 ("tgsi_exec: Fix NaN
behavior of saturate").  I knew that C99 had fmin and fmax... I just
forgot to use them.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>

intel/nir: Set lower txs with non-zero LOD

There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes.  The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds.  Fortunately, not many shaders
actually use textureSize() with LOD.

Shader-db results on Ice Lake:

    total instructions in shared programs: 19948537 -> 19948564 (<.01%)
    instructions in affected programs: 3859 -> 3886 (0.70%)
    helped: 0
    HURT: 7

One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>

intel/fs: Don't use pixel_z for Gen4-5 source_depth_to_render_target

The source_depth_to_render_target flag can get set on old gen4-5 HW in a
few cases which are independent of the app writing gl_FragDepth.  It
should be safe to just use fetch_payload_reg in that case instead of
depending in interpolation setup.  This fixes a bug with certain very
simple shaders where we might end up not including the depth when we
should have.

While we're here, rework the logic around setting src_depth and add a
comment so it's more clear what's going on.

Fixes: 6d4070f3ddb5 "intel/compiler: add support for fragment coordinate..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10596>

freedreno/query/acc: Set needs_flush

Somehow this was missed, but when we emit a query start/stop we need
have something that will need to be flushed in the batch.

Detected due to TC assert, but this had the potential to cause problems
in the non-TC case as well.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10599>

freedreno: Consolidate needs_flush and clearing last_fence

Add a helper to both set batch->needs_flush and clear ctx->last_fence so
that the two related bits of state do not get out of sync.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10599>

i915c: Add a symlink for i830_dri.so

The gallium driver doesn't support gen2, so let's make it possible to
keep both i915g and i830 drivers installed in parallel.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10554>

include: Remove unused i810_pci_ids.h

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10554>

panfrost: Meson dependency

Declare a meson dependency for libpanfrost and wrap some key functions
within an extern C block allowing proper compilation by C++ compilers.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10462>

venus: clean up vn_device_fix_create_info

The extension list should be more correct now.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: add extension check for ANDROID_native_buffer

We only do it on Android for now, to keep the driver working with older
renderers on X11.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: init supported extensions in one place

This also guarantees that physical_dev->extension_spec_versions[X] is
set when extension X is supported.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: refactor vn_physical_device_init_supported_extensions

Native extensions are those do not require direct renderer support.
Passthrough extensions are those require direct renderer support.

Native extensions usually require translation to other extensions that
the renderer supports.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: avoid strcmp for spec version override

Add VN_EXTENSION_TABLE_INDEX for use with VK_ANDROID_native_buffer spec
version override.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: refactor vn_physical_device_init_extensions

Split up into two functions, one initializes the renderer extension
table and one initializes the supported extension table.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: clarify/fix device renderer version

Mostly docs and cleanups, except that renderer_version is now also
capped by the xml version.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: clarify/fix instance renderer versions

Add vn_instance::renderer_version to indicate the maximum renderer
instance version we can use internally.  It is not all that useful
because we only use 1.1 instance features and VN_MIN_RENDERER_VERSION is
set to 1.1, but whatever.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: rename vn_instance::renderer_version

Rename renderer_version to renderer_api_version.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: add VN_MAX_API_VERSION

Use VN_MAX_API_VERSION for the instance version such that we don't
suddenly advertise 1.3 when the header is updated to 1.3 for example.

Use it to cap the device version as well.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10556>

venus: fix dmabuf import fail path

When we fail, we should not close gem_handle when there is already a bo
with the same gem handle.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10592>

venus: fix dmabuf import mmap_size check

Do not set mmap_size to info.size.  We do not track the size of the BO
anymore.

This fixes
dEQP-VK.api.external.memory.dma_buf.suballocated.device_only.fd_properties
where the test allocates a 1KB VkDeviceMemory, export and call
vkGetMemoryFdPropertiesKHR.  It can happen that bo->mmap_size is less
than the aligned info.size.

FWIW, the test fails because it violates a VU:

  VUID-vkGetMemoryFdPropertiesKHR-fd-00673
  fd must be an external memory handle created outside of the Vulkan API

Fixes: 88f481dd742 ("venus: make sure gem_handle and vn_renderer_bo are 1:1")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10592>

venus: fix render pass without attachments

It was treated as VK_ERROR_OUT_OF_HOST_MEMORY because
vn_get_intercepted_attachments would return NULL.  This fixes various
dEQP tests.

Fixes: 174fca5498e ("venus: handle VK_IMAGE_LAYOUT_PRESENT_SRC_KHR transfer")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10592>

ir3: Don't assume regs[1] exists in ir3_fixup_src_type()

It won't exist for phi nodes because they are only partially constructed
beforehand. Move it into the switch arguments where we know it's needed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3: Rework outputs

Instead of using a separate outputs array, make the "end" instruction
(or chmask) take the outputs as sources. This works better for the new
RA, because it better models the fact that outputs are consumed all at
the same time. With the old model, each output collect would be assumed
dead after it was processed and subsequent collects could use it when
inserting shuffle code, which wouldn't work, and the new RA also deletes
collect instructions after lowering them to moves so the information
would be gone after RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3: Make predecessors an array

We need a stable order in order to create phi instructions. In the
future we can make this more sophisticated in order to make manipulating
the CFG easier, but for now that only happens after RA, so we won't have
to worry about it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3: Refactor nir->ir3 block handling

Originally I wrote this to support multiple ir3 blocks per NIR block,
but this turned out to be more useful for creating a stable ordering to
the predecessors. We compute the predecessors ourselves, rather than
relying on NIR, so that the array of predecessors we create in the next
commit has a stable order we can rely on when creating phi nodes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/cp_postsched: Fixup SSA use pointer for direct reads

There's an optimization here to sink direct (i.e. not relative) reads of
an array past unrelated direct writes. However, since each write
actually reads, modifies, and then writes again to the array, this means
that we need to read the latest updated array. The old RA used the array
id instead of the SSA information, so it didn't care, but the new RA
uses ->instr instead and ignores the array id because arrays are now SSA
so it needs to be correct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/postsched: Fix ir3_postsched_node::delay calculation

This wasn't using the same calculation that add_reg_dep() was using to
get the index into state->regs, so it was using the wrong register. Fix
this by folding it into add_reg_dep().

This shouldn't fix anything, because it's just used for scheduler
priorities, but it should reduce nop's and syncs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/delay: Remove special case for array deps

The case it was trying to handle (array read-after-write depedendencies)
is already handled by the normal SSA source handling, so this is just
useless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/postsched: Use correct src index

Match what ir3_delay_calc() does. Caught by an assert later.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/sched: Use correct src index

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/cp: Clone registers for compare-folding optimization

Sharing the same register between instructions happened to work with the
old RA, but not with the new RA because they may get different register
assignments.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

ir3/postsched: Fix dependencies for a0.x/p0.x

a0.x is written as a half-reg, but just interpreting it as "hr61.x" will
result in it overlapping with r30.z in merged mode, which is not what
the hardware does at all. This introduced a spurious dependency on
a write to r30.z which resulted in an assert tripping. Just pretend it's
a full reg instead.

This fixes
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
with the new RA.

Fixes: 0f78c32 ("freedreno/ir3: post-RA sched pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>

panfrost: Remove old dEQP workaround

Nobody else needs it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10589>

Revert "glx: s/Display */struct glx_display */ over internal API"

This broke texture-from-pixmap in OBS Studio so I must have done
something wrong and also we need better tfp testing.

This reverts commit b02b26b87cd124b05a409b680817ee1950d6d94a.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4718
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10593>

ir3: do not fold cmps from different blocks with non-null address

Scheduling don't like address being in the different block from
the instruction.

Fixes a crash in the trace of "War Thunder" (DX11)

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10355>

iris: fix indirect drawid

iteration needs to be added to the offset now

Fixes: dae3113c3d8 ("gallium: split drawid out of pipe_draw_info and as a separate draw_vbo param")

Tested-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10555>

intel/eu: Set message subtype properly for SIMD8 FB fetch

There were two bugs which crep in here as part of 64551610d1e6:
forgetting that exec sizes in HW are in log2 space and having the
exec_size condition for the subtype backwards.

Fixes: 64551610d1e6 "intel/compiler: rework message descriptors..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10588>

panfrost: Don't unroll loops in GLSL

GLSL loop analysis is trouble. Just use NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10392>

pan/bi: Workaround *V2F32_TO_V2F16 erratum

Exact conditions this workaround is needed unknown. Determined
experimentally.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10392>