testuite: Check pthread for omp module testing

gcc/testsuite/ChangeLog:

* g++.dg/modules/omp-1_a.C: Check pthread is available.
* g++.dg/modules/omp-1_b.C: Ditto.
* g++.dg/modules/omp-1_c.C: Ditto.
* g++.dg/modules/omp-2_a.C: Ditto.
* g++.dg/modules/omp-2_b.C: Ditto.

arm: Fix ICE with CMSE nonsecure calls on Armv8.1-M [PR100333]

As the PR shows, we ICE shortly after expanding nonsecure calls for Armv8.1-M.
For Armv8.1-M, we have TARGET_HAVE_FPCXT_CMSE. As it stands, the expander
(arm.md:nonsecure_call_internal) moves the callee's address to a register (with
copy_to_suggested_reg) only if !TARGET_HAVE_FPCXT_CMSE.

However, looking at the pattern which the insn appears to be intended to
match (thumb2.md:*nonsecure_call_reg_thumb2_fpcxt), it requires the
callee's address to be in a register.

This patch therefore just forces the callee's address into a register in
the expander.

gcc/ChangeLog:

PR target/100333
* config/arm/arm.md (nonsecure_call_internal): Always ensure
callee's address is in a register.

gcc/testsuite/ChangeLog:

PR target/100333
* gcc.target/arm/cmse/pr100333.c: New test.

arm/testsuite: Fix testcase for PR99977

Some targets (eg arm-none-uclinuxfdpiceabi) do not support Thumb-1,
and since the testcase forces -march=armv8-m.base, we need to check
whether this option is actually supported.

Using dg-add-options arm_arch_v8m_base ensure that we pass -mthumb as
needed too.

2021-05-19  Christophe Lyon  <christophe.lyon@linaro.org>

PR target/99977
gcc/testsuite/
* gcc.target/arm/pr99977.c: Require arm_arch_v8m_base.

RISC-V: Properly parse the letter 'p' in '-march'.

gcc/ChangeLog:
* common/config/riscv/riscv-common.c
(riscv_subset_list::parsing_subset_version): Properly parse the letter
'p' in '-march'.
(riscv_subset_list::parse_std_ext,
 riscv_subset_list::parse_multiletter_ext): To handle errors generated
in riscv_subset_list::parsing_subset_version.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-12.c: New.
* gcc.target/riscv/attribute-19.c: New.

aarch64: Use correct type attributes for RTL generating XTN(2)

Use the correct "neon_move_narrow_q" type attribute in RTL patterns
that generate XTN/XTN2 instructions.

This makes a material difference because these instructions can be
executed on both SIMD pipes in the Cortex-A57 core model, whereas the
"neon_shift_imm_narrow_q" attribute (in use until now) would suggest
to the scheduler that they could only execute on one of the two
pipes.

gcc/ChangeLog:

2021-05-18  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd.md: Use "neon_move_narrow_q"
type attribute in patterns generating XTN(2).

aarch64: Use an expander for quad-word vec_pack_trunc pattern

The existing vec_pack_trunc RTL pattern emits an opaque two-
instruction assembly code sequence that prevents proper instruction
scheduling. This commit changes the pattern to an expander that emits
individual xtn and xtn2 instructions.

This commit also consolidates the duplicate truncation patterns.

gcc/ChangeLog:

2021-05-17  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd.md (aarch64_simd_vec_pack_trunc_<mode>):
Remove as duplicate of...
(aarch64_xtn<mode>): This.
(aarch64_xtn2<mode>_le): Move position in file.
(aarch64_xtn2<mode>_be): Move position in file.
(aarch64_xtn2<mode>): Move position in file.
(vec_pack_trunc_<mode>): Define as an expander.

testsuite: aarch64: Add tests for high-half narrowing instructions

Add tests to confirm that a *2 (write to high-half) Neon instruction
is generated from vcombine* of a narrowing intrinsic sequence.

gcc/testsuite/ChangeLog:

2021-05-14  Jonathan Wright  <jonathan.wright@arm.com>

* gcc.target/aarch64/narrow_high_combine.c: New test.

aarch64: Refactor aarch64_<sur>q<r>shr<u>n_n<mode> RTL pattern

Split the aarch64_<sur>q<r>shr<u>n_n<mode> pattern into separate
scalar and vector variants. Further split the vector pattern into
big/little endian variants that model the zero-high-half semantics
of the underlying instruction - allowing for more combinations with
the write-to-high-half variant (aarch64_<sur>q<r>shr<u>n2_n<mode>.)

gcc/ChangeLog:

2021-05-14  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Split builtin
generation for aarch64_<sur>q<r>shr<u>n_n<mode> pattern into
separate scalar and vector generators.
* config/aarch64/aarch64-simd.md
(aarch64_<sur>q<r>shr<u>n_n<mode>): Define as an expander and
split into...
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): This and...
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): This.
* config/aarch64/iterators.md: Define SD_HSDI iterator.

aarch64: Relax aarch64_sqxtun2<mode> RTL pattern

Use UNSPEC_SQXTUN instead of UNSPEC_SQXTUN2 in aarch64_sqxtun2<mode>
patterns. This allows for more more aggressive combinations and
ultimately better code generation. The now redundant UNSPEC_SQXTUN2
is removed.

gcc/ChangeLog:

2021-05-14  Jonathn Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd.md: Use UNSPEC_SQXTUN instead
of UNSPEC_SQXTUN2.
* config/aarch64/iterators.md: Remove UNSPEC_SQXTUN2.

aarch64: Relax aarch64_<sur>q<r>shr<u>n2_n<mode> RTL pattern

Implement saturating right-shift and narrow high Neon intrinsic RTL
patterns using a vec_concat of a register_operand and a VQSHRN_N
unspec - instead of just a VQSHRN_N unspec. This more relaxed pattern
allows for more aggressive combinations and ultimately better code
generation.

gcc/ChangeLog:

2021-03-04  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n2_n<mode>):
Implement as an expand emitting a big/little endian
instruction pattern.
(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Define.
(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Define.

aarch64: Relax aarch64_<sur><addsub>hn2<mode> RTL pattern

Implement v[r]addhn2 and v[r]subhn2 Neon intrinsic RTL patterns using
a vec_concat of a register_operand and an ADDSUBHN unspec - instead
of just an ADDSUBHN2 unspec. This more relaxed pattern allows for
more aggressive combinations and ultimately better code generation.

This patch also removes the now redundant [R]ADDHN2 and [R]SUBHN2
unspecs and their iterator.

gcc/ChangeLog:

2021-03-03  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>):
Implement as an expand emitting a big/little endian
instruction pattern.
(aarch64_<sur><addsub>hn2<mode>_insn_le): Define.
(aarch64_<sur><addsub>hn2<mode>_insn_be): Define.
* config/aarch64/iterators.md: Remove UNSPEC_[R]ADDHN2 and
UNSPEC_[R]SUBHN2 unspecs and ADDSUBHN2 iterator.

middle-end/100672 - fix bogus right shift folding

This fixes the bogus use of TYPE_PRECISION on vector types
from optimizing -((int)x >> 31) into (unsigned)x >> 31.

2021-05-19  Richard Biener  <rguenther@suse.de>

PR middle-end/100672
* fold-const.c (fold_negate_expr_1): Use element_precision.
(negate_expr_p): Likewise.

* gcc.dg/torture/pr100672.c: New testcase.

Fix typos.

PR testsuite/100658

gcc/cp/ChangeLog:

* mangle.c (write_encoding): Fix typos.

gcc/jit/ChangeLog:

* libgccjit.c (gcc_jit_context_new_function): Fix typos.

gcc/testsuite/ChangeLog:

* gcc.dg/local1.c: Fix typos.
* gcc.dg/ucnid-5-utf8.c: Likewise.
* gcc.dg/ucnid-5.c: Likewise.

aarch64: Enable aarch64_load to use UNSPEC_PRED_X loads

This patch will enable the use of loads using the UNSPEC_PRED_X enum in the
aarch64_load pattern, thus enabling combine to combine such loads with extends.

gcc/ChangeLog:
2021-05-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* config/aarch64/iterators.md (SVE_PRED_LOAD): New iterator.
(pred_load): New int attribute.
* config/aarch64/aarch64-sve.md
(aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>): Use
SVE_PRED_LOAD enum iterator and corresponding pred_load attribute.
* config/aarch64/aarch64-sve-builtins-base.cc (expand): Update call to
code_for_aarch64_load.

gcc/testsuite/ChangeLog:
2021-05-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* gcc.target/aarch64/sve/logical_unpacked_and_2.c: Change
scan-assembly-times to scan-assembly not for superfluous uxtb.
* gcc.target/aarch64/sve/logical_unpacked_and_3.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_and_4.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_and_6.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_and_7.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_2.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_3.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_4.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_6.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_7.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_2.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_3.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_4.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_6.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_7.c: Likewise.
* gcc.target/aarch64/sve/ld1_extend.c: New test.

Avoid marking TARGET_MEM_REF bases addressable

The following does no longer mark TARGET_MEM_REF bases addressable,
mimicing MEM_REFs beahvior here.  In contrast to the latter,
TARGET_MEM_REF RTL expansion expects to always operate on memory
though, so make sure we expand them so.

2021-05-19  Richard Biener  <rguenther@suse.de>

* cfgexpand.c (discover_nonconstant_array_refs_r): Make
sure TARGET_MEM_REF bases are expanded as memory.
* tree-ssa-operands.c (operands_scanner::get_tmr_operands):
Do not mark TARGET_MEM_REF bases addressable.
* tree-ssa.c (non_rewritable_mem_ref_base): Handle
TARGET_MEM_REF bases as never rewritable.
* gimple-walk.c (walk_stmt_load_store_addr_ops): Do not
walk TARGET_MEM_REF bases as address-takens.
* tree-ssa-dce.c (ref_may_be_aliased): Handle TARGET_MEM_REF.

Enable more WITH_SIZE_EXPR processing

This enables the alias machinery for WITH_SIZE_EXPR which can appear
in call LHS and arguments.  In particular this drops the NULL
return from get_base_address and it adjusts get_ref_base_and_extent
and friends to use the size information in WITH_SIZE_EXPR and
look through it for further processing.

2021-05-19  Richard Biener  <rguenther@suse.de>

* builtins.c (get_object_alignment_1): Strip outer
WITH_SIZE_EXPR.
* tree-dfa.c (get_ref_base_and_extent): Handle outer
WITH_SIZE_EXPR for size processing and process the
containing ref.
* tree-ssa-alias.c (ao_ref_base_alias_set): Strip
outer WITH_SIZE_EXPR.
(ao_ref_base_alias_ptr_type): Likewise.
(refs_may_alias_p_2): Allow WITH_SIZE_EXPR in ref->ref
and handle that accordingly, stripping it for the
core alias workers.
* tree.c (get_base_address): Handle WITH_SIZE_EXPR by
looking through it instead of returning NULL.

Add 'libgomp.oacc-c-c++-common/private-atomic-1.c' [PR83812]

... to at least document/test/XFAIL nvptx offloading: PR83812 "operation not
supported on global/shared address space".

libgomp/
PR target/83812
* testsuite/libgomp.oacc-c-c++-common/private-atomic-1.c: New.

Add 'libgomp.oacc-c-c++-common/loop-gwv-2.c'

libgomp/
* testsuite/libgomp.oacc-c-c++-common/loop-gwv-2.c: New.

builtins: Fix ICE with unprototyped builtin call [PR100576]

For unprototyped builtins the checking we perform is only about whether
the used argument is integral, pointer etc., not the exact precision.
We emit a warning about the problem though:
pr100576.c: In function ‘foo’:
pr100576.c:9:11: warning: implicit declaration of function ‘memcmp’ [-Wimplicit-function-declaration]
    9 |   int n = memcmp (p, v, b);
      |           ^~~~~~
pr100576.c:1:1: note: include ‘<string.h>’ or provide a declaration of ‘memcmp’
  +++ |+#include <string.h>
    1 | /* PR middle-end/100576 */
pr100576.c:9:25: warning: ‘memcmp’ argument 3 type is ‘int’ where ‘long unsigned int’ is expected in a call to built-in function declared without prototype
+[-Wbuiltin-declaration-mismatch]
    9 |   int n = memcmp (p, v, b);
      |                         ^
It means in the testcase below where the user incorrectly called memcmp
with last argument int rather then size_t, the warning stuff in builtins.c
ICEs because it compares a wide_int from such a bound with another wide_int
which has precision of size_t/sizetype and wide_int asserts the compared
wide_ints are compatible.

Fixed by forcing the bound to have the right type.

2021-05-19  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/100576
* builtins.c (check_read_access): Convert bound to size_type_node if
non-NULL.

* gcc.c-torture/compile/pr100576.c: New test.

apply TLC to GIMPLE reference verification

This inlines verify_types_in_gimple_min_lval and makes sure we
also verify call lhs and arguments.  It also asserts that
WITH_SIZE_EXPR in plain assignments does not happen, instead
those should have become memcpy/memset.

2021-05-18  Richard Biener  <rguenther@suse.de>

* tree-cfg.c (verify_types_in_gimple_min_lval): Inline...
(verify_types_in_gimple_reference): ... here.  Sanitize.
(verify_gimple_call): Verify references in LHS and arguments.
(verify_gimple_assign_single): Reject WITH_SIZE_EXPR.

i386: Allow 64bit vector modes in general registers

Allow V8QI, V4HI and V2SI modes in 64bit general registers for
TARGET_64BIT and add alternatives using general registers
to 64bit vector logic instructions.

2021-05-19  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
* config/i386/i386.h (VALID_INT_MODE_P):
Add V8QI, V4HI and V2SI modes for TARGET_64BIT.
* config/i386/i386.md (isa): Add x64_bmi.
(enabled): Handle x64_bmi.
* config/i386/mmx.md (mmx_andnot<MMXMODEI:mode>3):
Add alternative using 64bit general registers.
(*mmx_<any_logic:code><MMXMODEI:mode>3): Ditto.

Fix commit mistake in testcase gcc.dg/tree-ssa/ssa-sink-3.c

the test case was accidenally changed to empty file.

2021-05-19  Bernd Edlinger  <bernd.edlinger@hotmail.de>

* gcc.dg/tree-ssa/ssa-sink-3.c: Fix test case.

openmp: Handle lastprivate on combined target correctly [PR99928]

This patch deals with 2 issues:
1) the gimplifier couldn't differentiate between
 #pragma omp parallel master
 #pragma omp taskloop simd
and
 #pragma omp parallel master taskloop simd
when there is a significant difference for clause handling between
the two; as master construct doesn't have any clauses, we don't currently
represent it during gimplification by an gimplification omp context at all,
so this patch makes sure we don't set OMP_PARALLEL_COMBINED on parallel master
when not combined further.  If we ever add a separate master context during
gimplification, we'd use ORT_COMBINED_MASTER vs. ORT_MASTER (or MASKED probably).
2) lastprivate when combined with target should be map(tofrom:) on the target,
this change handles it only when not combined with firstprivate though, that
will need further work (similarly to linear or reduction).

2021-05-19  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/99928
gcc/
* tree.h (OMP_MASTER_COMBINED): Define.
* gimplify.c (gimplify_scan_omp_clauses): Rewrite lastprivate
handling for outer combined/composite constructs to a loop.
Handle lastprivate on combined target.
(gimplify_expr): Formatting fix.
gcc/c/
* c-parser.c (c_parser_omp_master): Set OMP_MASTER_COMBINED on
master when combined with taskloop.
(c_parser_omp_parallel): Don't set OMP_PARALLEL_COMBINED on
parallel master when not combined with taskloop.
gcc/cp/
* parser.c (cp_parser_omp_master): Set OMP_MASTER_COMBINED on
master when combined with taskloop.
(cp_parser_omp_parallel): Don't set OMP_PARALLEL_COMBINED on
parallel master when not combined with taskloop.
gcc/testsuite/
* c-c++-common/gomp/pr99928-2.c: Remove all xfails.
* c-c++-common/gomp/pr99928-12.c: New test.

gcc/go/ChangeLog: remove entry for reverted change

gofrontend: revert startswith change

This file is copied from a different repo and should not be changed
directly in the GCC repo.

libgo: update configure to current sources

Change-Id: I12766baf02bfdf2233f1c5bde1a270f06b020aa7
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/321076
Trust: Ian Lance Taylor <iant@golang.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Than McIntosh <thanm@google.com>

libgo: update bzip2 binary test cases to match source repo

Run pass_sink_code once more before store_merging

Gimple sink code pass runs quite early, there may be some new
oppertunities exposed by later gimple optmization passes, this patch
runs the sink code pass once more before store_merging.  For detailed
discussion, please refer to:
https://gcc.gnu.org/pipermail/gcc-patches/2020-December/562352.html

Tested the SPEC2017 performance on P8LE, 544.nab_r is improved
by 2.43%, but no big changes to other cases, GEOMEAN is improved quite
small with 0.25%.

gcc/ChangeLog:

2021-05-18  Xionghu Luo  <luoxhu@linux.ibm.com>

* passes.def: Add sink_code pass before store_merging.
* tree-ssa-sink.c (pass_sink_code:clone): New.

gcc/testsuite/ChangeLog:

2021-05-18  Xionghu Luo  <luoxhu@linux.ibm.com>

* gcc.dg/tree-ssa/ssa-sink-1.c: Adjust.
* gcc.dg/tree-ssa/ssa-sink-2.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-3.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-4.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-5.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-6.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-7.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-8.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-9.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-10.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-13.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-14.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-16.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-17.c: Ditto.
* gcc.dg/tree-ssa/ssa-sink-18.c: New.

libgo: use Windows line endings in testwinsignal

c++: ICE with bad definition of decimal32 [PR100261]

The change to only look at the global binding for non-classes meant that
here, when dealing with decimal32 which is magically mangled like its first
non-static data member, we got a collision with the mangling for float.
Fixed by also looking up an existing binding for such magical classes.

PR c++/100261

gcc/cp/ChangeLog:

* rtti.c (get_tinfo_decl_direct): Check TYPE_TRANSPARENT_AGGR.

gcc/testsuite/ChangeLog:

* g++.dg/dfp/mangle-6.C: New test.

c++: template template parm pack expansion [PR100372]

Here we have a pack expansion of a template template parameter pack, of
which the pattern is a TEMPLATE_DECL, which strip_typedefs doesn't want to
see.

PR c++/100372

gcc/cp/ChangeLog:

* tree.c (strip_typedefs): Only look at the pattern of a
TYPE_PACK_EXPANSION if it's a type.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/alias-decl-ttp1.C: New test.

Daily bump.

sim: depend on gnulib

We're going to start using gnulib in the sim, so make sure it exists.

ChangeLog:

* Makefile.def: Add configure-sim dependency on all-gnulib.
* Makefile.in: Regenerated.

rs6000: Remove old psabi warnings

Long ago we were forced to make some small ABI breaks to correct errors
in the implementation, and we added warning messages for the changes
from GCC 4.9 to GCC 5.  Enough time has passed that these are now just
irritants, so let's remove them.  Also clean up associated macros using
rs6000_special_adjust_field_align_p, which has been always returning
false for a long time.

2021-05-18  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
* config/rs6000/freebsd64.h (ADJUST_FIELD_ALIGN): Remove call to
rs6000_special_adjust_field_align_p.
* config/rs6000/linux64.h (ADJUST_FIELD_ALIGN): Likewise.
* config/rs6000/rs6000-call.c (rs6000_function_arg_boundary):
Remove ABI warning.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-protos.h
(rs6000_special_adjust_field_align_p): Remove prototype.
* config/rs6000/rs6000.c (rs6000_special_adjust_field_align_p):
Remove.
* config/rs6000/sysv4.h (ADJUST_FIELD_ALIGN): Remove call to
rs6000_special_adjust_field_align_p.

gcc/testsuite/
* gcc.target/powerpc/ppc64-abi-warn-1.c: Remove.
* gcc.target/powerpc/ppc64-abi-warn-2.c: Remove.
* gcc.target/powerpc/ppc64-abi-warn-3.c: Remove.

d: Use filename_ncmp instead of strncmp

gcc/d/ChangeLog:

* d-incpath.cc (prefixed_path): Use filename_ncmp instead of strncmp.

d: Use startswith function instead of strncmp

gcc/d/ChangeLog:

* types.cc (TypeVisitor::visit (TypeEnum *)): Use startswith function
instead of strncmp.

d: Revert "Come up with startswith function."

This reverts changes to the DMD front-end in commit
6ba3079dce89d9b63bf5dbd5e320ea2bf96f196b.

Changes were incorrectly committed directly to the GCC repo instead of
the master repository.

gcc/d/ChangeLog:

* dmd/dinterpret.c (evaluateIfBuiltin): Revert last change.
* dmd/dmangle.c: Likewise.
* dmd/hdrgen.c: Likewise.
* dmd/identifier.c (Identifier::toHChars2): Likewise.

c++: Prune dead functions.

I was looking at the LCOV coverage report for the C++ FE and
found a bunch of unused functions that I think we can remove.
Obviously, I left alone various dump_* and debug_* routines.
I haven't removed cp_build_function_call although it is also
currently unused.

* lambda_return_type: was used in parser.c in GCC 7, unused since r255950,
* classtype_has_non_deleted_copy_ctor: appeared in GCC 10, its usage
  was removed in c++/95350,
* contains_wildcard_p: used in GCC 9, unused since r276764,
* get_template_head_requirements: seems to never have been used,
* check_constrained_friend: seems to never have been used,
* subsumes_constraints: unused since r276764,
* push_void_library_fn: usage removed in r248328,
* get_template_parms_at_level: unused since r157857,
* get_pattern_parm: unused since r275387.

(Some of the seemingly unused functions, such as set_global_friend, are
actually used in libcc1.)

gcc/cp/ChangeLog:

* class.c (classtype_has_non_deleted_copy_ctor): Remove.
* constraint.cc (contains_wildcard_p): Likewise.
(get_template_head_requirements): Likewise.
(check_constrained_friend): Likewise.
(subsumes_constraints): Likewise.
* cp-tree.h (classtype_has_non_deleted_copy_ctor): Likewise.
(push_void_library_fn): Likewise.
(get_pattern_parm): Likewise.
(get_template_parms_at_level): Likewise.
(lambda_return_type): Likewise.
(get_template_head_requirements): Likewise.
(check_constrained_friend): Likewise.
(subsumes_constraints): Likewise.
* decl.c (push_void_library_fn): Likewise.
* lambda.c (lambda_return_type): Likewise.
* pt.c (get_template_parms_at_level): Likewise.
(get_pattern_parm): Likewise.

c++: non-static member, decltype, {} [PR100205]

This test was fixed by my second patch for PR93314, which distinguishes
between constant-expression and potentially-constant-evaluated contexts in a
way that my first patch did not.

PR c++/100205
PR c++/99314

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/decltype-nonstatic1.C: New test.

c++: "perfect" implicitly deleted move [PR100644]

Here we were ignoring the template constructor because the implicit move
constructor had all perfect conversions.  But CWG1402 says that an
implicitly deleted move constructor is ignored by overload resolution; we
implement that instead by preferring any other candidate in joust, to get
better diagnostics, but that means we need to handle that case here as well.

gcc/cp/ChangeLog:

PR c++/100644
* call.c (perfect_candidate_p): An implicitly deleted move
is not perfect.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/implicit-delete1.C: New test.

analyzer: fix missing leak after call to strsep [PR100615]

PR analyzer/100615 reports a missing leak diagnostic.
The issue is that the code calls strsep which the analyzer doesn't
have special knowledge of, and so conservatively assumes that it
could free the pointer, so drops malloc state for it.

Properly "teaching" the analyzer about strsep would require it
to support bifurcating state at a call, which is currently fiddly to
do, so for now this patch notes that strsep doesn't affect the
malloc state machine, allowing the analyzer to correctly detect the leak.

gcc/analyzer/ChangeLog:
PR analyzer/100615
* sm-malloc.cc: Include "analyzer/function-set.h".
(malloc_state_machine::on_stmt): Call unaffected_by_call_p and
bail on the functions it recognizes.
(malloc_state_machine::unaffected_by_call_p): New.

gcc/testsuite/ChangeLog:
PR analyzer/100615
* gcc.dg/analyzer/pr100615.c: New test.

i386: Implement 4-byte vector support [PR100637]

Add infrastructure, logic and arithmetic support for 4-byte vectors.
These can be used with SSE2 targets, where movd instructions from/to
XMM registers are available.  x86_64 ABI passes 4-byte vectors in
integer registers, so also add logic operations with integer registers.

2021-05-18  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
PR target/100637
* config/i386/i386.h (VALID_SSE2_REG_MODE):
Add V4QI and V2HI modes.
(VALID_INT_MODE_P): Ditto.
* config/i386/mmx.md (VI_32): New mode iterator.
(mmxvecsize): Handle V4QI and V2HI.
(Yv_Yw): Ditto.
(mov<VI_32:mode>): New expander.
(*mov<mode>_internal): New insn pattern.
(movmisalign<VI_32:mode>): New expander.
(neg<VI_32:mode>): New expander.
(<plusminus:insn><VI_32:mode>3): New expander.
(*<plusminus:insn><VI_32:mode>3): New insn pattern.
(mulv2hi3): New expander.
(*mulv2hi3): New insn pattern.
(one_cmpl<VI_32:mode>2): New expander.
(*andnot<VI_32:mode>3): New insn pattern.
(<any_logic:code><VI_32:mode>3): New expander.
(*<any_logic:code><VI_32:mode>3): New insn pattern.

gcc/testsuite/

PR target/100637
* gcc.target/i386/pr100637-1b.c: New test.
* gcc.target/i386/pr100637-1w.c: Ditto.

* gcc.target/i386/pr92658-avx2-2.c: Do not XFAIL scan for pmovsxbq.
* gcc.target/i386/pr92658-avx2.c: Do not XFAIL scan for pmovzxbq.
* gcc.target/i386/pr92658-avx512vl.c: Do not XFAIL scan for vpmovdb.
* gcc.target/i386/pr92658-sse4-2.c: Do not XFAIL scan for
pmovsxbd and pmovsxwq.
* gcc.target/i386/pr92658-sse4.c: Do not XFAIL scan for
pmovzxbd and pmovzxwq.

config: delete unused sim macros

Nothing in gcc or binutils or gdb or anything anywhere uses these.

config/

* acinclude.m4 (CYG_AC_PATH_SIM, CYG_AC_PATH_DEVO): Delete.

Fortran/OpenMP: Add missing EXEC_OMP_DEPOBJ case val [PR100642]

PR fortran/100642

gcc/fortran/ChangeLog:

* openmp.c (omp_code_to_statement): Add missing EXEC_OMP_DEPOBJ.

gcc/testsuite/ChangeLog:

* gfortran.dg/goacc-gomp/depobj.f90: New test.

libstdc++: Fix access issue in elements_view::_Sentinel [PR100631]

In the earlier commit r12-854 I forgot to also rewrite the other operator-
overload in terms of the split-out member function _M_distance_from.

libstdc++-v3/ChangeLog:

PR libstdc++/100631
* include/std/ranges (elements_view::_Sentinel::operator-): Use
_M_distance_from in the other operator- overload too.
* testsuite/std/ranges/adaptors/elements.cc (test06): Augment test.

i386: Fix <any_extend:insn>v4qiv4di2 expander

Fix a mode mismatch.

2021-05-18  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
* config/i386/sse.md (<any_extend:insn>v4qiv4di2):
Fix a mode mismatch with operand 1.

i386: Fix split_double_mode with paradoxical subreg [PR100626]

split_double_mode calls simplify_gen_subreg, which fails for the
high half of the paradoxical subreg.  Return temporary register
instead of NULL RTX in this case.

2021-05-18  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
PR target/100626
* config/i386/i386-expand.c (split_double_mode): Return
temporary register when simplify_gen_subreg fails with
the high half od the paradoxical subreg.

Avoid setting TREE_ADDRESSABLE on stack vars during RTL expansion

This avoids setting TREE_ADDRESSABLE on variables we want to force to
the stack.  Instead track those in a temporary bitmap and force
stack expansion that way, leaving TREE_ADDRESSABLE alone, not
pessimizing future alias queries.

2021-05-17  Richard Biener  <rguenther@suse.de>

* cfgexpand.c (expand_one_var): Pass in forced_stack_var
and honor it when expanding.
(expand_used_vars_for_block): Pass through forced_stack_var.
(expand_used_vars): Likewise.
(discover_nonconstant_array_refs_r): Set bits in
forced_stack_vars instead of marking vars TREE_ADDRESSABLE.
(avoid_type_punning_on_regs): Likewise.
(discover_nonconstant_array_refs): Likewise.
(pass_expand::execute): Create and pass down forced_stack_var
bitmap.  For parameters and returns temporarily set
TREE_ADDRESSABLE when expand_function_start.

[libgomp, testsuite] Don't shadow global 'offload_targets' variable

See local 'offload_targets' variable in
'libgomp/testsuite/lib/libgomp.exp:libgomp_check_effective_target_offload_target'
vs. global 'libgomp/testsuite/libgomp-test-support.exp.in:offload_targets'
variable.

libgomp/
* testsuite/lib/libgomp.exp
(check_effective_target_offload_target_nvptx): Don't shadow global
'offload_targets' variable.

'libgomp.c-c++-common/reduction-{5,6}.c': Restrict '-latomic' to nvptx offloading compilation

Fix-up for recent commit 33b647956caa977d1ae489f9baed9cef70b4f382
"OpenMP: Fix SIMT for complex/float reduction with && and ||"; see
commit d42088e453042f4f8ba9190a7e29efd937ea2181 "Avoid -latomic for amdgcn
offloading".

libgomp/
* testsuite/libgomp.c-c++-common/reduction-5.c: Restrict
'-latomic' to nvptx offloading compilation.
* testsuite/libgomp.c-c++-common/reduction-6.c: Likewise.

'libgomp.c/target-44.c': Restrict '-latomic' to nvptx offloading compilation

Fix-up for recent commit f87990a2a8fc9e20d30462a0a4c9047582af0cd9
"[openmp, simt] Disable SIMT for user-defined reduction"; see commit
d42088e453042f4f8ba9190a7e29efd937ea2181 "Avoid -latomic for amdgcn
offloading".

libgomp/
* testsuite/libgomp.c/target-44.c: Restrict '-latomic' to nvptx
offloading compilation.

Add 'dg-note', 'dg-lto-note'

That's 'dg-message "note: [...]"' with a twist: inhibit default notes pruning,
such that "if 'dg-note' is used at least once in a testcase, [notes] are not
pruned and instead must *all* be handled explicitly".

The rationale is that either you're not interested in notes at all (default
behavior of pruning all notes), but often, when you're interested in one note,
you're in fact interested in all notes, and especially interested if
*additional* notes appear over time, as GCC evolves.

gcc/testsuite/
* lib/gcc-dg.exp: Implement 'dg-note'.
* lib/prune.exp: Likewise.
* gcc.dg/vect/nodump-vect-opt-info-2.c: Use 'dg-note', and
'dg-prune-output "note: ".
* gfortran.dg/goacc/routine-external-level-of-parallelism-2.f: Use
'dg-note', match up additional notes, one class of them with
XFAILed 'dg-bogus'.
* lib/lto.exp: Implement 'dg-lto-note'.
* g++.dg/lto/odr-1_0.C: Use 'dg-lto-note', match up additional
notes.
* g++.dg/lto/odr-1_1.C: Likewise.
* g++.dg/lto/odr-2_1.C: Likewise.
libstdc++-v3/
* testsuite/lib/prune.exp: Add note about 'dg-note'.
gcc/
* doc/sourcebuild.texi: Document 'dg-note'.

gcc/configure.ac: Fix cross build by using $(CFLAGS-$@) [PR100598]

BUILD_CFLAGS is set by configure; by default, BUILD_CFLAGS = $(ALL_CFLAGS)
is used. The latter contains (see gcc/Makefile.in) $(CFLAGS-$@), which is used
to pass .o-file specific flags to the compiler.
For cross builds, BUILD_CFLAGS is constructed in configure{,.ac} and missed
the $(CFLAGS-$@) - despite the comment above ALL_CFLAGS that configure.ac
might have to kept in sync.

gcc/ChangeLog:

PR other/100598
* configure: Regenerate.
* configure.ac (BUILD_CFLAG, BUILD_CXXFLAGS): Add $(CFLAGS-$@).

[OMP] Tighten 'is_gimple_omp_oacc'

No overall change in behavior.

gcc/
* gimple.h (is_gimple_omp_oacc): Tighten.
* omp-low.c (check_omp_nesting_restrictions): Adjust.

operand scanner TLC

This applies some TLC to mark_address_taken which ends up setting
TREE_ADDRESSABLE on nodes where it doesn't have any semantics.
It also does work (incomplete) that get_base_address already does,
likewise we'll never get WITH_SIZE_EXPR in this context and thus
get_base_address never fails.

2021-05-18  Richard Biener  <rguenther@suse.de>

* tree-ssa-operands.c (mark_address_taken): Simplify.

startswith: Fix offloading targets.

gcc/ChangeLog:

* config/gcn/mkoffload.c (STR): Redefine.
* config/i386/intelmic-mkoffload.c (STR): Likewise.
* config/nvptx/mkoffload.c (STR): Likewise.

gcc-changelog: Remove use of non-strict mode

contrib/ChangeLog:

* gcc-changelog/git_email.py: Remove use of non-strict mode.

Use startswith in targets.

gcc/ChangeLog:

* common/config/aarch64/aarch64-common.c (aarch64_parse_extension):
Use startswith function instead of strncmp.
* common/config/bfin/bfin-common.c (bfin_handle_option): Likewise.
* common/config/riscv/riscv-common.c (riscv_subset_list::parse): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc (parse_type): Likewise.
* config/aarch64/aarch64.c (aarch64_process_one_target_attr): Likewise.
* config/alpha/alpha.c (alpha_elf_section_type_flags): Likewise.
* config/arm/aarch-common.c (arm_md_asm_adjust): Likewise.
* config/arm/arm.c (arm_file_start): Likewise.
(arm_valid_target_attribute_rec): Likewise.
(thumb1_md_asm_adjust): Likewise.
* config/arm/driver-arm.c (host_detect_local_cpu): Likewise.
* config/avr/avr.c (STR_PREFIX_P): Likewise.
(avr_set_current_function): Likewise.
(avr_handle_addr_attribute): Likewise.
(avr_asm_output_aligned_decl_common): Likewise.
(avr_asm_named_section): Likewise.
(avr_section_type_flags): Likewise.
(avr_asm_select_section): Likewise.
* config/c6x/c6x.c (c6x_in_small_data_p): Likewise.
(c6x_section_type_flags): Likewise.
* config/darwin-c.c (darwin_cfstring_ref_p): Likewise.
(darwin_objc_declare_unresolved_class_reference): Likewise.
(darwin_objc_declare_class_definition): Likewise.
* config/darwin.c (indirect_data): Likewise.
(darwin_encode_section_info): Likewise.
(darwin_objc2_section): Likewise.
(darwin_objc1_section): Likewise.
(machopic_select_section): Likewise.
(darwin_globalize_label): Likewise.
(darwin_label_is_anonymous_local_objc_name): Likewise.
(darwin_asm_named_section): Likewise.
(darwin_asm_output_dwarf_offset): Likewise.
* config/frv/frv.c (frv_string_begins_with): Likewise.
(frv_in_small_data_p): Likewise.
* config/gcn/mkoffload.c (STR): Likewise.
(main): Likewise.
* config/i386/i386-builtins.c (get_builtin_code_for_version): Likewise.
* config/i386/i386-options.c (ix86_option_override_internal): Likewise.
* config/i386/i386.c (x86_64_elf_section_type_flags): Likewise.
(ix86_md_asm_adjust): Likewise.
* config/i386/intelmic-mkoffload.c (STR): Likewise.
* config/i386/winnt.c (i386_pe_asm_named_section): Likewise.
(i386_pe_file_end): Likewise.
* config/ia64/ia64.c (ia64_in_small_data_p): Likewise.
(ia64_section_type_flags): Likewise.
* config/mips/driver-native.c (host_detect_local_cpu): Likewise.
* config/mips/mips.c (mips_handle_interrupt_attr): Likewise.
(mips16_stub_function_p): Likewise.
(mips_function_rodata_section): Likewise.
* config/msp430/msp430.c (msp430_mcu_name): Likewise.
(msp430_function_section): Likewise.
(msp430_section_type_flags): Likewise.
(msp430_expand_helper): Likewise.
* config/nios2/nios2.c (nios2_small_section_name_p): Likewise.
(nios2_valid_target_attribute_rec): Likewise.
* config/nvptx/mkoffload.c (process): Likewise.
(STR): Likewise.
* config/pa/som.h: Likewise.
* config/pdp11/pdp11.c (pdp11_output_ident): Likewise.
* config/riscv/riscv.c (riscv_elf_select_rtx_section): Likewise.
* config/rs6000/rs6000.c (VTABLE_NAME_P): Likewise.
(rs6000_inner_target_options): Likewise.
* config/s390/driver-native.c (s390_host_detect_local_cpu): Likewise.
* config/sparc/driver-sparc.c (host_detect_local_cpu): Likewise.
* config/vax/vax.c (vax_output_int_move): Likewise.
* config/vms/vms-ld.c (startswith): Likewise.
(process_args): Likewise.
(main): Likewise.
* config/vms/vms.c: Likewise.

regcprop: Avoid DCE of asm goto [PR100590]

The following testcase ICEs, because copyprop_hardreg_forward_1 decides
to DCE asm goto with REG_UNUSED notes (because the output is unused and
asm isn't volatile).  But that DCE just removes the asm goto, leaving
a bb with two successors and no insn at the end that would allow that.

The following patch makes sure we drop that way only INSNs and not
JUMP_INSNs or CALL_INSNs.

2021-05-18  Jakub Jelinek  <jakub@redhat.com>

PR rtl-optimization/100590
* regcprop.c (copyprop_hardreg_forward_1): Only DCE dead sets if
they are NONJUMP_INSN_P.

* gcc.dg/pr100590.c: New test.

function: Set dummy DECL_ASSEMBLER_NAME in push_dummy_function [PR100580]

Last year I've added cgraph_node::get_create calls for the dummy
functions used for -fdump-passes, so that it interacts well with pass
disabling/enabling which is cgraph uid based.
Unfortunately, as the following testcase shows, when assembler hash
is present, that wants to compute DECL_ASSEMBLER_NAME and the C++ FE
is unprepared to handle it on the dummy functions which don't have
DECL_NAME etc.
The following patch fixes it by setting up a dummy DECL_ASSEMBLER_NAME
on these, so that the FEs don't need to compute it.

2021-05-18  Jakub Jelinek  <jakub@redhat.com>

PR c++/100580
* function.c (push_dummy_function): Set DECL_ARTIFICIAL and
DECL_ASSEMBLER_NAME on the fn_decl.

* g++.dg/other/pr100580.C: New test.

phiopt: Optimize partial_ordering spaceship >= 0 -ffinite-math-only [PR94589]

As mentioned earlier, spaceship_replacement didn't optimize partial_ordering
>= 0 comparisons, because the possible values are -1, 0, 1, 2 and the
>= comparison is implemented as (res & 1) == res to choose the 0 and 1
cases from that.  As we optimize that only with -ffinite-math-only, the
2 case is assumed not to happen and my earlier match.pd change optimizes
(res & 1) == res into (res & ~1) == 0, so this patch pattern matches
that case and handles it like res >= 0.

2021-05-18  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/94589
* tree-ssa-phiopt.c (spaceship_replacement): Pattern match
phi result used in (res & ~1) == 0 comparison as res >= 0 as
res == 2 would be UB with -ffinite-math-only.

* g++.dg/opt/pr94589-2.C: Adjust scan-tree-dump count from 14 to 12.

genversion should depend on DATESTAMP

gcc/ChangeLog:

* Makefile.in: genversion.o should depend on DATESTAMP.

arc: Fix typo in negv2si2 pattern

gcc/
2021-05-18  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/simdext.md (negv2si2): Remove round bracket.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>

Fix gcc.target/i386/pr100582.c with AVX512

Which generates vpblendmb.

2021-05-18  Richard Biener  <rguenther@suse.de>

gcc/testsuite/
* gcc.target/i386/pr100582.c: Adjust for AVX512.

c/100522 - avoid invalid GIMPLE in GIMPLE parsing

This plugs a few easy holes avoiding ICEs down the route.

2021-05-18  Richard Biener  <rguenther@suse.de>

PR c/100522
gcc/c/
* gimple-parser.c (c_parser_gimple_postfix_expression_after_primary):
Diagnose calls to non-functions.
(c_parser_gimple_statement): Diagnose unexpected assignment RHS.

gcc/testsuite/
* gcc.dg/gimplefe-error-10.c: New testcase.

c/100547 - reject overly large vector_size attributes

This rejects a number of vector components that does not fit an 'int'
which is an internal limitation of RTVEC.  This requires adjusting
gcc.dg/attr-vector_size.c which checks for much larger
supported vectors.  Note that the RTVEC limitation is a host specific
limitation (unless we change this 'int' to int32_t), but should be
32bits in practice everywhere.

2021-05-12  Richard Biener  <rguenther@suse.de>

PR c/100547
gcc/c-family/
* c-attribs.c (type_valid_for_vector_size): Reject too large nunits.
Reword existing nunit diagnostic.

gcc/testsuite/
* gcc.dg/pr100547.c: New testcase.
* gcc.dg/attr-vector_size.c: Adjust.

IBM Z: Support vector _Bool language extension

_Bool needs to be defined as macro in order to trigger the
context-sensitive macro expansion mechanism.

gcc/ChangeLog:

* config/s390/s390-c.c (s390_cpu_cpp_builtins_internal): Define
_Bool as macro expanding to _Bool.

gcc/testsuite/ChangeLog:

* gcc.target/s390/zvector/vec-_Bool.c: New test.

PR100281 C++: Fix SImode pointer handling

The problem appears to be triggered by two locations in the front-end
where non-POINTER_SIZE pointers aren't handled right now.

1. An assertion in strip_typedefs is triggered because the alignment
of the types don't match. This in turn is caused by creating the new
type with build_pointer_type instead of taking the type of the
original pointer into account.

2. An assertion in cp_convert_to_pointer is triggered which expects
the target type to always have POINTER_SIZE.

gcc/cp/ChangeLog:

PR c++/100281
* cvt.c (cp_convert_to_pointer): Use the size of the target
pointer type.
* tree.c (cp_build_reference_type): Call
cp_build_reference_type_for_mode with VOIDmode.
(cp_build_reference_type_for_mode): Rename from
cp_build_reference_type.  Add MODE argument and invoke
build_reference_type_for_mode.
(strip_typedefs): Use build_pointer_type_for_mode and
cp_build_reference_type_for_mode for pointers and references.

gcc/ChangeLog:

PR c++/100281
* tree.c (build_reference_type_for_mode)
(build_pointer_type_for_mode): Pick pointer mode if MODE argument
is VOIDmode.
(build_reference_type, build_pointer_type): Invoke
build_*_type_for_mode with VOIDmode.

gcc/testsuite/ChangeLog:

PR c++/100281
* g++.target/s390/pr100281-1.C: New test.
* g++.target/s390/pr100281-2.C: New test.

libstdc++: Fix up semiregular-box partial specialization [PR100475]

This makes the in-place constructor of our partial specialization of
__box for already-semiregular types perform direct-non-list-initialization
(in accordance with the specification of the primary template), and
additionally makes the member function data() use std::__addressof.

libstdc++-v3/ChangeLog:

PR libstdc++/100475
* include/std/ranges (__box::__box): Use non-list-initialization
in member initializer list of in-place constructor of the
partial specialization for semiregular types.
(__box::operator->): Use std::__addressof.
* testsuite/std/ranges/adaptors/detail/semiregular_box.cc
(test02): New test.
* testsuite/std/ranges/single_view.cc (test04): New test.

libstdc++: Fix condition for memoizing reverse_view::begin() [PR100621]

A range being a random access range isn't a sufficient condition for
ranges::next(iter, sent) to have constant time complexity -- it must
also have a sized sentinel.  This adjusts the memoization condition for
reverse_view accordingly.

libstdc++-v3/ChangeLog:

PR libstdc++/100621
* include/std/ranges (reverse_view::_S_needs_cached_begin):
Set to true if the underlying non-common random-access range
doesn't have a sized sentinel.

libstdc++: Fix miscellaneous issues with elements_view::_Sentinel [PR100631]

libstdc++-v3/ChangeLog:

PR libstdc++/100631
* include/std/ranges (elements_view::_Iterator): Also befriend
_Sentinel<!_Const>.
(elements_view::_Sentinel::_M_equal): Templatize.
(elements_view::_Sentinel::_M_distance_from): Split out from ...
(elements_view::_Sentinel::operator-): ... here.  Depend on
_Base2 instead of _Base in the return type.
* testsuite/std/ranges/adaptors/elements.cc (test06, test07):
New tests.

Daily bump.

Once a range becomes constant, make it invariant.

Once a range is forced to a constant globally, simply make it invariant.
Unify this with the code which makes non-zero pointer ranges invariant.

gcc/
PR tree-optimization/100512
* gimple-range-cache.cc (ranger_cache::set_global_range): Mark const
and non-zero pointer ranges as invariant.
* gimple-range.cc (gimple_ranger::range_of_stmt): Remove pointer
processing from here.

gcc/testsuite/
PR tree-optimization/100512
* gcc.dg/pr100512.c: New.

MAINTAINERS: Add myself for write after approval

ChangeLog:

2021-05-17  Serge Belyshev  <belyshev@depni.sinp.msu.ru>

* MAINTAINERS (Write After Approval): Add myself.

openmp: Notify team barrier of pending tasks in omp_fulfill_event

The team barrier should be notified of any new tasks that become runnable
as the result of a completing task, otherwise the barrier threads might
not resume processing available tasks, resulting in a hang.

2021-05-17  Kwok Cheung Yeung  <kcy@codesourcery.com>

libgomp/
* task.c (omp_fulfill_event): Call gomp_team_barrier_set_task_pending
if new tasks generated.
* testsuite/libgomp.c-c++-common/task-detach-13.c: New.

c++: Fix diagnostic for binding lvalue reference to volatile rvalue [PR 100635]

The current diagnostic assumes the reference binding fails because the
reference is non-const, but it can also fail if the rvalue is volatile.

Use the current diagnostic for non-const cases, and a modified
diagnostic otherwise.

gcc/cp/ChangeLog:

PR c++/100635
* call.c (convert_like_internal): Print different diagnostic if
the lvalue reference is const.

gcc/testsuite/ChangeLog:

* g++.dg/conversion/pr100635.C: New test.

PR fortran/98411 - Pointless warning for static variables

Variables with explicit SAVE attribute cannot end up on the stack.
There is no point in checking whether they should be moved off the
stack to static storage.

gcc/fortran/ChangeLog:

PR fortran/98411
* trans-decl.c (gfc_finish_var_decl): Add check for explicit SAVE
attribute.

gcc/testsuite/ChangeLog:

PR fortran/98411
* gfortran.dg/pr98411.f90: New test.

libstdc++: Fix wrong thread waking on notify [PR100334]

Fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100334

libstdc++-v3/ChangeLog:
* include/bits/atomic_wait.h (__waiter::_M_do_wait_v): loop
until value change observed.
(__waiter_base::_M_laundered): New member.
(__waiter_base::_M_notify): Check _M_laundered to determine
whether to wake one or all.
(__detail::__atomic_compare): Return true if call to
__builtin_memcmp() == 0.
(__waiter_base::_S_do_spin_v): Adjust predicate.
* testsuite/29_atomics/atomic/wait_notify/100334.cc: New
test.

[nvptx] Handle memmodel for atomic ops

The atomic ops in nvptx.md have memmodel arguments, which are currently
ignored.

Handle these, fixing test-case fails libgomp.c-c++-common/reduction-{5,6}.c
on volta.

Tested libgomp on x86_64-linux with nvptx accelerator.

gcc/ChangeLog:

2021-05-17  Tom de Vries  <tdevries@suse.de>

PR target/100497
* config/nvptx/nvptx-protos.h (nvptx_output_atomic_insn): Declare
* config/nvptx/nvptx.c (nvptx_output_barrier)
(nvptx_output_atomic_insn): New function.
(nvptx_print_operand): Add support for 'B'.
* config/nvptx/nvptx.md: Use nvptx_output_atomic_insn for atomic
insns.

libstdc++: Fix filesystem::path constraints for volatile [PR 100630]

The constraint check for filesystem::path construction uses
decltype(__is_path_src(declval<Source>())) which mean it considers
conversion from an rvalue.  When Source is a volatile-qualified type
it cannot use is_path_src(const Unknown&) because a const lvalue
reference can only bind to a non-volatile rvalue.

Since the relevant path members all have a const Source& parameter,
the constraint should be defined in terms of declval<const Source&>(),
not declval<Source>(). This avoids the problem of volatile-qualified
rvalues, because we no longer use an rvalue at all.

libstdc++-v3/ChangeLog:

PR libstdc++/100630
* include/experimental/bits/fs_path.h (__is_constructible_from):
Test construction from a const lvalue, not an rvalue.
* testsuite/27_io/filesystem/path/construct/100630.cc: New test.
* testsuite/experimental/filesystem/path/construct/100630.cc:
New test.

libstdc++: diagnose some misuses of [locale.convenience] functions [PR 89728]

This patch provides better diagnostics for common misuse of
[locale.convenience] functions with std::string as a character type.

libstdc++-v3/ChangeLog:

PR libstdc++/89728
* include/bits/locale_facets.h (ctype<basic_string<C,T,A>>):
Declare (but do not define) partial specialization.
* testsuite/22_locale/ctype/is/string/89728_neg.cc: New test.

libstdc++: Fix std::jthread assertion and re-enable skipped test

libstdc++-v3/ChangeLog:

* include/std/thread (jthread::_S_create): Fix static assert
message.
* testsuite/30_threads/jthread/95989.cc: Re-enable test.
* testsuite/30_threads/jthread/jthread.cc: Do not require
pthread effective target.
* testsuite/30_threads/jthread/2.cc: Moved to...
* testsuite/30_threads/jthread/version.cc: ...here.

Bail in bounds_of_var_in_loop if scev returns NULL.

Both initial_condition_in_loop_num and evolution_part_in_loop_num
can return NULL.  This patch exits if either one is NULL.  Presumably
this didn't happen before, because adjust_range_with_scev was called
far less frequently than in ranger, which can call it for every PHI.

gcc/ChangeLog:

PR tree-optimization/100349
* vr-values.c (bounds_of_var_in_loop): Bail if scev returns
  NULL.

gcc/testsuite/ChangeLog:

* gcc.dg/pr100349.c: New test.

AArch64: Have -mcpu=native and -march=native enable extensions when CPU is unknown

Currently when using -mcpu=native or -march=native on a CPU that is unknown to
the compiler the compiler currently just used -march=armv8-a and enables none
of the extensions.

To make this a bit more useful this patch changes it to still use -march=armv8.a
but to enable the extensions.  We still cannot do tuning but at least if using
this on a future SVE core the compiler will at the very least enable SVE etc.

gcc/ChangeLog:

* config/aarch64/driver-aarch64.c (DEFAULT_ARCH): New.
(host_detect_local_cpu): Use it.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/info_16: New test.
* gcc.target/aarch64/cpunative/info_17: New test.
* gcc.target/aarch64/cpunative/native_cpu_16.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_17.c: New test.

Docs: add 2 missing dots.

gcc/ChangeLog:

* doc/invoke.texi: Add 2 missing dots.

c/100625 - avoid building invalid labels in the GIMPLE FE

When duplicate labes are diagnosed, avoid building a GIMPLE_LABEL.

2021-05-17  Richard Biener  <rguenther@suse.de>

PR c/100625
gcc/c/
* gimple-parser.c (c_parser_gimple_label): Avoid building
a GIMPLE label with NULL label decl.

gcc/testsuite/
* gcc.dg/gimplefe-error-9.c: New testcase.

IBM Z: Avoid bash-specific substitution in configure

Fix a bootstrap error observed on NetBSD.

2021-05-17  Marius Hillenbrand  <mhillen@linux.ibm.com>

gcc/ChangeLog:

PR bootstrap/100552
* configure.ac: Replace pattern substitution with call to sed.
* configure: Regenerate.

middle-end/100582 - fix array_at_struct_end_p for vector indexing

Vector indexing leaves us with ARRAY_REFs of VIEW_CONVERT_EXPRs,
sth which array_at_struct_end_p considers a array-at-struct-end
even when there's an underlying decl visible.  The following fixes
the latter.

2021-05-17  Richard Biener  <rguenther@suse.de>

PR middle-end/100582
* tree.c (array_at_struct_end_p): Get to the base of the
reference before looking for the underlying decl.

* gcc.target/i386/pr100582.c: New testcase.

Improve message for wrong number of alternatives.

gcc/
* genoutput.c (validate_insn_alternatives) Make "wrong number of
alternatives" message more specific, and remove assumption on where
the problem is.

arm: Auto-vectorization for MVE: add __fp16 support to VCMP

This patch adds __fp16 support to the previous patch that added vcmp
support with MVE. For this we update existing expanders to use VDQWH
iterator, and add a new expander vcond<VH_cvtto><mode>.  In the
process we need to create suitable iterators, and update v_cmp_result
as needed.

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/iterators.md (V16): New iterator.
(VH_cvtto): New iterator.
(v_cmp_result): Added V4HF and V8HF support.
* config/arm/vec-common.md (vec_cmp<mode><v_cmp_result>): Use VDQWH.
(vcond<mode><mode>): Likewise.
(vcond_mask_<mode><v_cmp_result>): Likewise.
(vcond<VH_cvtto><mode>): New expander.

gcc/testsuite/
* gcc.target/arm/simd/mve-compare-3.c: New test with GCC vectors.
* gcc.target/arm/simd/mve-vcmp-f16.c: New test for
auto-vectorization.
* gcc.target/arm/armv8_2-fp16-arith-1.c: Adjust since we now
vectorize float16_t vectors.

arm: Auto-vectorization for MVE: vcmp

Since MVE has a different set of vector comparison operators from
Neon, we have to update the expansion to take into account the new
ones, for instance 'NE' for which MVE does not require to use 'EQ'
with the inverted condition.

Conversely, Neon supports comparisons with #0, MVE does not.

For:
typedef long int vs32 __attribute__((vector_size(16)));
vs32 cmp_eq_vs32_reg (vs32 a, vs32 b) { return a == b; }

we now generate:
cmp_eq_vs32_reg:
vldr.64 d4, .L123       @ 8     [c=8 l=4]  *mve_movv4si/8
vldr.64 d5, .L123+8
vldr.64 d6, .L123+16    @ 9     [c=8 l=4]  *mve_movv4si/8
vldr.64 d7, .L123+24
vcmp.i32  eq, q0, q1    @ 7     [c=16 l=4]  mve_vcmpeqq_v4si
vpsel q0, q3, q2        @ 15    [c=8 l=4]  mve_vpselq_sv4si
bx      lr      @ 26    [c=8 l=4]  *thumb2_return
.L124:
.align  3
.L123:
.word   0
.word   0
.word   0
.word   0
.word   1
.word   1
.word   1
.word   1

For some reason emit_move_insn (zero, CONST0_RTX (cmp_mode)) produces
a pair of vldr instead of vmov.i32, qX, #0

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-protos.h (arm_expand_vector_compare): Update
prototype.
* config/arm/arm.c (arm_expand_vector_compare): Add support for
MVE.
(arm_expand_vcond): Likewise.
* config/arm/iterators.md (supf): Remove VCMPNEQ_S, VCMPEQQ_S,
VCMPEQQ_N_S, VCMPNEQ_N_S.
(VCMPNEQ, VCMPEQQ, VCMPEQQ_N, VCMPNEQ_N): Remove.
* config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>): Add '@' prefix.
(@mve_vcmp<mve_cmp_op>q_f<mode>): Likewise.
(@mve_vcmp<mve_cmp_op>q_n_f<mode>): Likewise.
(@mve_vpselq_<supf><mode>): Likewise.
(@mve_vpselq_f<mode>"): Likewise.
* config/arm/neon.md (vec_cmp<mode><v_cmp_result): Enable for MVE
and move to vec-common.md.
(vec_cmpu<mode><mode>): Likewise.
(vcond<mode><mode>): Likewise.
(vcond<V_cvtto><mode>): Likewise.
(vcondu<mode><v_cmp_result>): Likewise.
(vcond_mask_<mode><v_cmp_result>): Likewise.
* config/arm/unspecs.md (VCMPNEQ_U, VCMPNEQ_S, VCMPEQQ_S)
(VCMPEQQ_N_S, VCMPNEQ_N_S, VCMPEQQ_U, CMPEQQ_N_U, VCMPNEQ_N_U)
(VCMPGEQ_N_S, VCMPGEQ_S, VCMPGTQ_N_S, VCMPGTQ_S, VCMPLEQ_N_S)
(VCMPLEQ_S, VCMPLTQ_N_S, VCMPLTQ_S, VCMPCSQ_N_U, VCMPCSQ_U)
(VCMPHIQ_N_U, VCMPHIQ_U): Remove.
* config/arm/vec-common.md (vec_cmp<mode><v_cmp_result): Moved
from neon.md.
(vec_cmpu<mode><mode>): Likewise.
(vcond<mode><mode>): Likewise.
(vcond<V_cvtto><mode>): Likewise.
(vcondu<mode><v_cmp_result>): Likewise.
(vcond_mask_<mode><v_cmp_result>): Likewise. Added unsafe math
condition.

gcc/testsuite
* gcc.target/arm/simd/mve-compare-1.c: New test with GCC vectors.
* gcc.target/arm/simd/mve-compare-2.c: New test with GCC vectors.
* gcc.target/arm/simd/mve-compare-scalar-1.c: New test with GCC
vectors.
* gcc.target/arm/simd/mve-vcmp-f32.c: New test for
auto-vectorization.
* gcc.target/arm/simd/mve-vcmp.c: New test for auto-vectorization.

Fix ICE [PR target/100549]

When arg0 is same as arg1 in __builtin_ia32_pcmpgtw,
gimple_build (&stmts, GT_EXPR, cmp_type, arg0, arg1) will simplify the
comparison to vector constant 0, no stmts is generated, which causes
ICE in gsi_insert_before (gsi, stmts, GSI_SAME_STMT). So use
gsi_insert_seq_before instead which will handle NULL seq.

gcc/ChangeLog:

PR target/100549
* config/i386/i386.c (ix86_gimple_fold_builtin): Use
gsi_insert_seq_before instead.

gcc/testsuite/ChangeLog:

PR target/100549
* gcc.target/i386/pr100549.c: New test.

testsuite/arm: Add mve-vadd-scalar-1.c test

This patch adds a test for the scalar mode of vadd, precisely noting
that we do not yet use the T2 variants of vadd, which take a scalar as
final argument.

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/simd/mve-vadd-scalar-1.c: New.

testsuite/arm: Add mve-vadd-1.c test

Support for vadd has been present for a while, but it was lacking a
test.

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/simd/mve-vadd-1.c: New.

testsuite/arm: Factorize and increase coverage in mve-sub_1.c

Use a template macro to factorize the existing test functions.

This patch also adds a version to check subtraction with __fp16 type.

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/simd/mve-vsub_1.c: Factorize and add __fp16 test.

testsuite/arm: Improve mve-vshr.c

Vector right shifts by immediate use vshr, while right shifts by
vectors instead use vneg and vshl.

This patch adds the corresponding scan-assembler-times that were
missing.

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/simd/mve-vshr.c: Add more scan-assembler-times.

testsuite/arm: Fix and rename arm_qbit_ok into arm_sat_ok effective-target

The acle/saturation.c test uses __[su]sat() and
__saturation_occurred() intrinsics but __[su]sat() are defined in
acle.h if __ARM_FEATURE_SAT true, while __saturation_occurred()
depends on __ARM_FEATURE_QBIT.

QBIT is a v5te feature, while SAT is available since v6, so the test
really needs __ARM_FEATURE_SAT, to have both available.

This patch renames arm_qbit_ok into arm_sat_ok and checks
__ARM_FEATURE_SAT. It updates acle/saturation.c accordingly.

This enables the test to pass on arm-eabi with default cpu/fpu/mode,
where arm_qbit previously used -march=armv5te instead of armv6 now.

2021-05-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* doc/sourcebuild.texi (arm_qbit_ok): Rename into...
(arm_sat_ok): ...this.

gcc/testsuite/
* gcc.target/arm/acle/saturation.c: Use arm_sat_ok effective
target.
* lib/target-supports.exp
(check_effective_target_arm_qbit_ok_nocache): Rename into...
(check_effective_target_arm_sat_ok_nocache): ... this. Check
__ARM_FEATURE_SAT and use armv6.

OpenMP/Fortran: Reject nonintrinsic assignments in OMP WORKSHARE [PR100633]

PR fortran/100633

gcc/fortran/ChangeLog:

* resolve.c (gfc_resolve_code): Reject nonintrinsic assignments in
OMP WORKSHARE.

gcc/testsuite/ChangeLog:

* gfortran.dg/gomp/workshare-59.f90: New test.

libstdc++: Allow lualatex to be used for Doxygen PDF

This allows the Doxygen PDF to be built using lualatex instead of
pdflatex, which solves a problem with pdflatex running out of memory
sometimes. This is done by adding a --latex_cmd option to the
run_doxygen script, which then sets the specified command in the
generated user.cfg file used by Doxygen. The makefile is adjusted to
pass --latex_cmd=$(LATEX_CMD) to the script, so using running make with
LATEX_CMD=lualatex will override the default.

Additionally, this does some refactoring of the doc/Makefile.am rules
and the run_doxygen script.

libstdc++-v3/ChangeLog:

* doc/Makefile.am: Simplify doxygen recipes and use --latex_cmd.
* doc/Makefile.in: Regenerate.
* doc/doxygen/user.cfg.in (LATEX_CMD_NAME): Add placeholder
value.
* scripts/run_doxygen (print_usage): Always print to stdout and
do not exit.
(fail): New function for exiting on error.
(parse_options): Handle --latex_cmd. Do not treat --help the
same as errors. Simplify handling of required arguments.

Avoid outputting corrupt string constructor when host/target chars mismatch.

* c-common.c (braced_list_to_string): Return CTOR unchanged
if host and target character sizes don't match.