Alyssa Rosenzweig [Wed, 9 Jun 2021 20:43:29 +0000 (16:43 -0400)]
pan/decode: Handle cache flush jobs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 19:42:05 +0000 (15:42 -0400)]
pan/decode: Fix image attribute counting
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 22:07:09 +0000 (18:07 -0400)]
panfrost: Advertise GLES3.1
We have CI, we're just a few tests away from conformance on v7, and
Midgard is just a few hundred tests behind. Given the branch point isn't
for another month, I think this is a good time to flip the switch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 20:42:54 +0000 (16:42 -0400)]
panfrost: Add "Cache Flush" job XML
Likely useful for efficient memory_barrier and texture_barrier
operations.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 10 Jun 2021 17:16:44 +0000 (13:16 -0400)]
panfrost: Set vertex job_barrier
Fixes KHR-GLES31.core.vertex_attrib_binding.advanced-iterations which
pingpongs XFB/attributes
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 15:33:52 +0000 (11:33 -0400)]
panfrost: Flush before compute jobs
Suboptimal but fixes KHR-GLES31.core.compute_shader.pipeline-post-xfb,
which is stubbornly still broken with memory barriers implemented and
cache flush jobs inserted. More investigation needed but probably not
right now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:36:07 +0000 (18:36 -0400)]
panfrost: Flush everything for glMemoryBarrier
This is inefficient but so far I see the DDK doing the same thing. Fixes
KHR-GLES31.core.shader_storage_buffer_object.advanced-usage-sync-vsfs
In the future we should look into cache flush jobs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 19:28:08 +0000 (15:28 -0400)]
panfrost: Clean up vertex/instance ID on Midgard
Use the proper XML.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 19:26:05 +0000 (15:26 -0400)]
panfrost: Add XML for vertex/instance ID records
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:42:26 +0000 (13:42 -0400)]
panfrost: Set valid_buffer_range for GPU writes
Transform feedback, SSBO writes, and image writes in particular can
affect this and have bad interactions. Fixes
KHR-GLES31.core.shader_atomic_counters.basic-usage-vs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:42:03 +0000 (20:42 -0400)]
panfrost: Remove pan_image_state
Instead just group the fields about validity into a simpler structure in
panfrost_resource. Panvk can do the same. Common code shouldn't be
thinking in terms of this 'larger' structure anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:32:43 +0000 (20:32 -0400)]
panfrost: Make data_valid a bitset
More compact and will allow simpler code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:09:44 +0000 (13:09 -0400)]
panfrost: Don't clobber indirect dispatch fields
These should be kept as zero so they can be packed correctly. Fixes a
number of KHR-GLES31 fails.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 15:20:42 +0000 (11:20 -0400)]
panfrost: Use direct dispatch with shared memory
This would require memory allocations we don't handle.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:36:54 +0000 (12:36 -0400)]
pan/indirect_dispatch: Use extracted values
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:31:10 +0000 (12:31 -0400)]
pan/indirect_dispatch: Expand split expressions
Careful algebraic transforms makes these much simpler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:08:19 +0000 (12:08 -0400)]
pan/indirect_dispatch: Distinguish minus-1 defs
This makes the logic clearer and allows the original values to be
accessed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:00:20 +0000 (12:00 -0400)]
pan/indirect_dispatch: Simplify empty command case
Job type is alone with bitsize in the bottom byte of the addressed
worse, so if we use an 8-bit store we avoid the RMW complexity.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 15:50:37 +0000 (11:50 -0400)]
pan/indirect_dispatch: Indent NIR blocks
Easier to visualize the control flow this way.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:27:52 +0000 (20:27 -0400)]
panfrost: Reduce pan_image_state indirection
In actuality, this just shadows the crc_valid for pan_cs... the
data_valid checks are contained in the caller and just add noise.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:17:23 +0000 (20:17 -0400)]
panfrost: Don't CRC mipmapped textures
CRC is intended for final render targets and especially for UI, not the
kind of things you'd mipmap. Meanwhile CRC only works for a single
level, meaning at any given point, half the CRC buffer would be wasted
for a full miptree.
"Arm Mali Best Practices Guide" tells developers that the DDK only
enables CRC for non-mipmapped resources (at least the Vulkan DDK), so
let's do the same, save some memory, and simplify our code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:28:36 +0000 (18:28 -0400)]
panfrost: Drop todo on PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
They work fine.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 13:21:22 +0000 (09:21 -0400)]
panfrost: Set PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
Fixes KHR-GLES31.core.gpu_shader5.images_array_indexing
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:28:16 +0000 (18:28 -0400)]
panfrost: Set PIPE_COMPUTE_CAP_SUBGROUP_SIZE
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 21:40:17 +0000 (17:40 -0400)]
panfrost: Lower max compute size
Match the DDK's limit (Mali G52), I think there's undocumented errata
here. Fixes
KHR-GLES31.core.texture_buffer.texture_buffer_operations_image_store
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:47:49 +0000 (18:47 -0400)]
panfrost: Make image buffers robust
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 21:01:59 +0000 (17:01 -0400)]
panfrost: Fix BUFFER image handling
Fixes:
KHR-GLES31.core.shader_image_load_store.advanced-allMips-cs
KHR-GLES31.core.shader_image_load_store.advanced-allMips-fs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 19:25:49 +0000 (15:25 -0400)]
panfrost: Allocate XFB buffers per-instance
Somehow XFB gets so little use we never noticed. Fixes:
KHR-GLES31.core.vertex_attrib_binding.basic-input-case9
KHR-GLES31.core.vertex_attrib_binding.basic-input-case11
KHR-GLES31.core.vertex_attrib_binding.basic-inputI-case2
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 18:08:42 +0000 (14:08 -0400)]
panfrost: Don't set a blend shader for no_colour
It's pointless and confuses the hardware. Fixes (on Bifrost)
KHR-GLES31.core.draw_buffers_indexed.color_masks
Yes, this is a silly edge case. Yes, we still have to handle it
correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 17:38:45 +0000 (13:38 -0400)]
panfrost: Remove scissor_culls_everything
Based on a misunderstanding of how the scissor test works, and in
particular breaks transform feedback and SSBO writes from vertex
shaders.
Replace it with a moral equivalent to rasterizer_discard so vertex
shaders still run.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Sat, 5 Jun 2021 00:23:33 +0000 (20:23 -0400)]
panfrost: Add some missing BGRA formats
Fixes:
KHR-GLES3.copy_tex_image_conversions.forbidden.*
KHR-GLES3.packed_pixels.pbo_rectangle.rgb5_a1
KHR-GLES3.packed_pixels.pbo_rectangle.rgba
KHR-GLES3.packed_pixels.pbo_rectangle.rgba4
KHR-GLES3.packed_pixels.pbo_rectangle.rgba8
KHR-GLES3.packed_pixels.rectangle.rgb5_a1
KHR-GLES3.packed_pixels.rectangle.rgba
KHR-GLES3.packed_pixels.rectangle.rgba4
KHR-GLES3.packed_pixels.rectangle.rgba8
KHR-GLES3.packed_pixels.varied_rectangle.rgb5_a1
KHR-GLES3.packed_pixels.varied_rectangle.rgba
KHR-GLES3.packed_pixels.varied_rectangle.rgba4
KHR-GLES3.packed_pixels.varied_rectangle.rgba8
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:18:23 +0000 (19:18 -0400)]
panfrost: Emulate indirect draws on Midgard
I can't really justify spending time on this right now, even to myself.
So take the perf hit and get out checkbox.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:06:36 +0000 (19:06 -0400)]
panfrost: Fix dirty state emission
If we have per-draw state (vertex ID stuff), there's an ordering
mismatch. Fixes
dEQP-GLES31.functional.draw_base_vertex.draw_elements_instanced_base_vertex.builtin_variable.vertex_id
on Midgard, and I'm not sure why it was passing on Bifrost before. Also
should fix (on both architectures) DRAWID issues.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:19:41 +0000 (13:19 -0400)]
pan/mdg: Insert moves to load/store registers
Ensures a valid schedule/regalloc is possible when vectors are used in
funny ways, as occurs in dEQP-GLES31 resulting in a scheduler hang (or
with prior patches, an RA failure).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:18:13 +0000 (13:18 -0400)]
pan/mdg: Assert scheduled instructions are reasonable
Would've got a scheduler hang.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:17:39 +0000 (13:17 -0400)]
pan/mdg: Don't skip unit-based checks in choose_instruction
If an explicit unit isn't specified, we still should check.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:17:04 +0000 (13:17 -0400)]
pan/mdg: Use more accurate ld/st reg estimates
And assert that we got them right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:07:41 +0000 (19:07 -0400)]
pan/mdg: Lower away gl_VertexID offset
Technically we can stick the offset in the vertex ID attribute record,
but this is a faster way to get the test passing and Midgard perf?
what's that?
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 22:57:28 +0000 (18:57 -0400)]
pan/mdg: Wire in PAN_SYSVAL_VERTEX_INSTANCE_OFFSETS
If we're going to advertise the CAP, better not crash..
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 22:36:43 +0000 (18:36 -0400)]
panfrost: Don't allocate WLS when not needed
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:36:26 +0000 (17:36 -0400)]
panfrost: Mark 16/32_UNORM as non-renderable (v5)
You'd just get a blend shader anyway, and since they're not spec
requirements, let's not worry about backporting the Midgard lowerings.
Takes dEQP-GLES31.functional.fbo.color.tex2d.* on Midgard from crashing
to not supported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:17:28 +0000 (17:17 -0400)]
pan/mdg: Fix incorrect rewrite in Midgard scheduler
Fixes on Midgard
dEQP-GLES31.functional.shaders.builtin_functions.uniform.findLSBMinusOne.highp_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:04:43 +0000 (17:04 -0400)]
pan/mdg: Update r1.w comment
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 19:26:30 +0000 (15:26 -0400)]
pan/mdg: Handle {i,u}{add,sub}_sat
As SATADD with different modifiers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 19:24:44 +0000 (15:24 -0400)]
pan/mdg: Fix units for SUBSAT
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:55:14 +0000 (14:55 -0400)]
panfrost: Respect early-Z force on Midgard
Fixes dEQP-GLES31.functional.image_load_store.early_fragment_tests.* on
Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:50:53 +0000 (14:50 -0400)]
panfrost: Don't force early-z with occlusion query
..even if there is no z/s enabled. Fixes
dEQP-GLES31.functional.fbo.no_attachments.* on Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:43:10 +0000 (14:43 -0400)]
panfrost: Simplify Midgard blend disable
Probably a bit faster too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:42:56 +0000 (14:42 -0400)]
panfrost: Clarify how fs_sidefx works with oq
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 17:38:02 +0000 (13:38 -0400)]
pan/mdg: Stub memory_barrier{_image}
Same as we do for Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 16:50:46 +0000 (12:50 -0400)]
pan/mdg: Make -Wswitch happy
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 16:04:50 +0000 (12:04 -0400)]
pan/mdg: Use consistent casing in midgard_print
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:15:01 +0000 (15:15 -0400)]
panfrost: Assert alignment of indirect records
Continuation records need alignment, this shows they already have it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:14:00 +0000 (15:14 -0400)]
panfrost: Make instancing code more obvious
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:09:06 +0000 (15:09 -0400)]
panfrost: Fix src_offset data type
We treat it as signed but had it marked as unsigned. It can be negative
in obscure cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:06:05 +0000 (15:06 -0400)]
panfrost: Align NPOT divisor records
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 18:09:18 +0000 (14:09 -0400)]
panfrost: Add util_draw_indirect() debug path
Useful for finding problems with the GPU indirect path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 15:07:45 +0000 (11:07 -0400)]
panfrost: Zero r_dimension for buffer textures
Instead of reading wrong side of the union (undefined behaviour). Fixes
a GenXML assertion failure in
KHR-GLES31.core.texture_buffer.texture_buffer_texture_buffer_range
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 21:08:53 +0000 (17:08 -0400)]
panfrost: Fix crc_valid condition
Fixes fails in dEQP-GLES31.functional.texture.border_clamp.* when run in
parallel with certain other tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 21:07:10 +0000 (17:07 -0400)]
panfrost: Simplify compute_checksum_size formula
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 19:45:51 +0000 (15:45 -0400)]
panfrost: Fix vertex image attribute overrun
Images take a continuation record, don't scribble zeroes over.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes:
dc85f65e059 ("panfrost: emit shader image attribute descriptors")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 18:52:56 +0000 (14:52 -0400)]
pan/bi: Force u32 for flat varyings
Since the GLSL compilers will pack together flat varyings with no regard
to type, under the assumption the backend can deal with it. I guess we
can deal with it then... Fixes fails in
dEQP-GLES31.functional.separate_shader.random.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 20:15:17 +0000 (16:15 -0400)]
panfrost: Use varying format from frag shader
Needed to fix up flat varyings to u32 due to TGSI brokenness. If we wack
TGSI, we can drop this.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 18:52:36 +0000 (14:52 -0400)]
panfrost: Correctly size varyings
The same slot could be specified multiple times with different
location_frac out of order, so we use two passes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:47:03 +0000 (19:47 -0400)]
pan/indirect_draw: Fix 1 instance, nonzero divisor
Instead of doing a complicated hack with the POT divisor, just zero the
stride of the linear attribute buffer like we do on the CPU.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:35:46 +0000 (19:35 -0400)]
pan/indirect_draw: Use unsigned comparisons
Instead of signed -- get the types right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:32:43 +0000 (19:32 -0400)]
pan/indirect: Factor out is_power_of_two_or_zero
The function is complicated enough as it is -- hide the bit twiddling
behind a helper function.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:42:54 +0000 (19:42 -0400)]
panfrost: Default indirect attributes to 1D type
Avoids some complexity in the indirect draw happy path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:14:06 +0000 (19:14 -0400)]
panfrost: Use util_last_bit for images
Probbaly more correct for hols in image_mask.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:09:00 +0000 (19:09 -0400)]
panfrost: Be explicit in image modifier handling
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 20 May 2021 13:40:43 +0000 (09:40 -0400)]
panfrost: Separate image attribute and buffer emit
Trying to disentangle attributes and attribute buffers, so here's
a leaf node for that change.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 19 May 2021 22:34:25 +0000 (18:34 -0400)]
panfrost: Don't duplicate attribute buffers
If the (vbi, divisor) tuple matches, we can save an attribute buffer
descriptor. We do the linking at CSO create time. This should be a bit
more cache friendly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 21:38:35 +0000 (17:38 -0400)]
panfrost: Disable AFBC on v7
Broken in several ways. Hide it until we can get this sorted, and have a
test plan to keep it sorted.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 21:51:05 +0000 (17:51 -0400)]
panfrost: Add missing 'Reverse issue order flag'
Should fix an issue I'm seeing. Spoiler alert, it does not.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 19:47:20 +0000 (15:47 -0400)]
panfrost: Remove AFBC format fixups
It's too complicated and probably for no actual benefit. The main reason
we have BGR formats is for display, but that's export and doesn't get
hit by this path. Internal BGRA textures are possible with a Mesa
extension but sufficiently rare that I regret suggesting this as a
possible optimization. My apologies, and thanks for the fish.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 20:04:05 +0000 (16:04 -0400)]
pan/bi: Don't allocate past the end of the reg file
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 18:49:04 +0000 (14:49 -0400)]
pan/bi: Track words instead of bytes in RA
Reduces RA memory footprint by 4x, fixing an OOM in the following dEQP
test that otherwise would allocate 8GB of memory...
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 18:35:52 +0000 (14:35 -0400)]
pan/bi: Simplify spill code
Now allow spilling all nodes. Fixes failed spilling in
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.21
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 22:30:30 +0000 (18:30 -0400)]
pan/bi: Emit a dummy ATEST if needed
Match what the blob does, since Bifrost has so many random errata we'd
be fools not to.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 22:08:41 +0000 (18:08 -0400)]
pan/bi: Lower 64-bit ints again
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 14:46:57 +0000 (10:46 -0400)]
pan/bi: Lower stores with component != 0
If the shader packs multiple varyings into the same location with
different location_frac, we'll need to lower to a single varying store
that collects all of the channels together. This is not trivial during
code gen, but it is trivial to do in NIR right before codegen by relying
on nir_lower_io_to_temporaries. Since we're guaranteed all varyings will
be written exactly once, in the exit block, we can scan the shader
linearly and collect stores together in a single pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 00:24:31 +0000 (20:24 -0400)]
pan/bi: Lower loads with component > 0
We have no native way to swizzle out a nonzero component in a load, but
we can simply load extra components and do the swizzle in shader
instructions. This is inefficient, since it loads data to discard
immediately, but it's required for conformance in some edge cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 22:50:30 +0000 (18:50 -0400)]
pan/bi: Handle images in vertex shaders
We need to offset by the number of attributes, since the primary
attribute table is shared for images and vertex attributes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 19:49:27 +0000 (15:49 -0400)]
pan/bi: Model +BLEND clobbering of r48
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:56:41 +0000 (13:56 -0400)]
pan/bi: Don't restrict the register file in non-blend shaders
Now that preloading is handled correctly, there's nothing 'special'
about R59 and up, so this gets us a few more registers to work with.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:52:56 +0000 (13:52 -0400)]
pan/bi: Allow move/sink in blend shaders
Now that we handle precolouring we don't need to workaround anything.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:50:54 +0000 (13:50 -0400)]
pan/bi: Model interference with preloaded regs
Now that we have affinity masks in RA, we can handle this as an easy
case of register liveness analysis, rather than creating pseudo-nodes
and trying hard to coalesce the resulting moves.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:50:13 +0000 (13:50 -0400)]
pan/bi: Explicit zero reg_live_{in, out} when needed
I want to use these fields for a similar purpose in the register
allocator, so they won't be zero anymore for scheduling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 16:22:55 +0000 (12:22 -0400)]
pan/bi: Inline spilling in RA
Should be faster for both spill and not spill cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:52:48 +0000 (13:52 -0400)]
pan/bi: Use explicit affinities in RA
Inline LCRA to allow us to make the change without disrupting Midgard,
and get some nice cleanup from doing so.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 6 May 2021 17:10:00 +0000 (13:10 -0400)]
pan/bi: Allow IADD.u32 on FMA as *IADDC
There's a common special case, slight boost in scheduler freedom.
total nops in shared programs: 101130 -> 101048 (-0.08%)
nops in affected programs: 1677 -> 1595 (-4.89%)
helped: 13
HURT: 0
helped stats (abs) min: 6 max: 8 x̄: 6.31 x̃: 6
helped stats (rel) min: 3.24% max: 25.00% x̄: 7.42% x̃: 4.48%
95% mean confidence interval for nops value: -6.76 -5.85
95% mean confidence interval for nops %-change: -12.02% -2.81%
Nops are helped.
total clauses in shared programs: 27076 -> 27075 (<.01%)
clauses in affected programs: 8 -> 7 (-12.50%)
helped: 1
HURT: 0
total quadwords in shared programs: 113142 -> 113113 (-0.03%)
quadwords in affected programs: 1935 -> 1906 (-1.50%)
helped: 13
HURT: 0
helped stats (abs) min: 2 max: 4 x̄: 2.23 x̃: 2
helped stats (rel) min: 0.95% max: 7.50% x̄: 2.16% x̃: 1.26%
95% mean confidence interval for quadwords value: -2.59 -1.87
95% mean confidence interval for quadwords %-change: -3.45% -0.88%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 6 May 2021 15:11:09 +0000 (11:11 -0400)]
pan/bi: Track liveness while scheduling
If we know that a value is killed in the next tuple, there is no need to
write it out to the register file. We already handled this as a packing
fixup. However, avoiding this write also frees up an extra slot in the
register block, which offers additional scheduling freedom. To take
advantage of this, we extend liveness analysis to work while scheduling,
and modify the schedulable predicate accordingly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:49:24 +0000 (17:49 -0400)]
pan/bi: Add post-RA optimizer
Delete coalesced moves. Now this is trivial! See e.g shaders/tesseract/118.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:27:07 +0000 (17:27 -0400)]
pan/bi: Bundle after RA
Flag day change to swap the order of the "scheduler" with the register
allocator. This gives RA much more freedom without significantly
hndering bundling.
It also opens up the door to Adult-level Scheduling which would occur
prior to bundling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 5 May 2021 18:06:26 +0000 (14:06 -0400)]
pan/bi: Fix bi_rewrite_passthrough ordering
The ordering is irrelevant for SSA form input, but is very relevant for
register input.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 5 May 2021 19:48:35 +0000 (15:48 -0400)]
pan/bi: Simplify TEXC codegen for sr_count=0
Obscure case.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:42:13 +0000 (17:42 -0400)]
pan/bi: Use TEXS_2D for rect textures
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:20:45 +0000 (17:20 -0400)]
pan/bi: Pull out bi_count_write_registers
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Yiwei Zhang [Thu, 10 Jun 2021 16:26:01 +0000 (16:26 +0000)]
vulkan: fix back compat with Android Oreo and below
buffer_handle_t definition was previously inside the deprecated
system/core/include/system/window.h.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11301>
Neha Bhende [Wed, 9 Jun 2021 18:08:28 +0000 (11:08 -0700)]
svga: Initialize pipe_shader_state for transform shaders
This fixes crashes for opengl apps. Issue is found in vmware
internal testing
Fixes:
f01c0565bb9 ("draw: free the NIR IR.")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11274>
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