Karol Herbst [Mon, 26 Jun 2023 14:34:14 +0000 (16:34 +0200)]
docs/rusticl: add Enabling section
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23859>
Karol Herbst [Mon, 26 Jun 2023 12:48:52 +0000 (14:48 +0200)]
docs/rusticl: mark building section as such
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23859>
Jordan Justen [Tue, 2 May 2023 07:41:12 +0000 (03:41 -0400)]
intel/devinfo/i915: Set has_set_pat_uapi for MTL+
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Mon, 3 Apr 2023 16:51:22 +0000 (12:51 -0400)]
anv: Use set PAT extension on BO creation for MTL
Reworks:
* Drop local pat_index var (suggested by José)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Mon, 3 Apr 2023 08:19:00 +0000 (04:19 -0400)]
iris: Use set PAT extension on BO creation for MTL
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Fri, 23 Jun 2023 04:20:29 +0000 (21:20 -0700)]
drm-uapi/i915_drm.h: Update from drm-next (2023-06-09)
git://anongit.freedesktop.org/drm/drm
2222dcb0775d36de28992f56455ab3967b30d380
The motivation for this change in to get the uapi changes from:
commit
81b1b599dfd71c958418dad586fa72c8d30d1065
Author: Fei Yang <fei.yang@intel.com>
Date: Tue Jun 6 12:00:42 2023 +0200
drm/i915: Allow user to set cache at BO creation
Specifically, the I915_GEM_CREATE_EXT_SET_PAT extension.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Francisco Jerez [Tue, 13 Jun 2023 00:53:35 +0000 (20:53 -0400)]
anv: Swap ordering of memory types on non-LLC platforms to work around application bugs.
The Vulkan specification indicates that if memory types have
properties which are a strict subset of another type's, then they
should appear before that memory type. Otherwise the specification
does not require a specific ordering of memory types.
But, it appears that Aztec Ruins and the Vulkan CTS make an assumption
that the first host-accessible memory type is host-coherent and select
it when they expect data written by the CPU to become visible without
calling vkFlushMappedMemoryRanges(), even though flushing is required
by the spec, which leads to misrendering and hangs on MTL platforms.
We found that other drivers also put a host-coherent, but not cached
memory type as the first host-accessible memory type, so let's do the
same in order to match the expectations of such broken applications.
Host-coherent uncached memory types are currently implemented with a
WC CPU map on non-LLC platforms, so there shouldn't be a huge
performance penalty from this: If an application intends to do heavy
R/W CPU access on a memory range it's expected to loop over the
available memory types and select one marked as host-cached -- If an
application fails to do that and simply selects the first available
type it seems more robust to stay on the safe side and give them a
host-coherent type rather than a cached one.
Rework:
* Jordan: Add initial explanation to body of commmit message.
* Curro: Add additional comments to commit message.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Fri, 7 Apr 2023 21:51:53 +0000 (17:51 -0400)]
iris: Map aux-map with WC on MTL+ (has_set_pat_uapi)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Wed, 10 May 2023 16:56:58 +0000 (09:56 -0700)]
iris/bufmgr: Skip bucket allocation if not using writeback cache PAT index
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Wed, 10 May 2023 16:50:54 +0000 (09:50 -0700)]
iris/bufmgr: Add iris_pat_index_for_bo_flags()
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Thu, 4 May 2023 06:19:06 +0000 (02:19 -0400)]
intel/devinfo: Define PAT indices used on MTL
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Jordan Justen [Tue, 2 May 2023 07:41:12 +0000 (03:41 -0400)]
intel/devinfo: Add has_set_pat_uapi
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Kenneth Graunke [Wed, 5 Apr 2023 22:41:05 +0000 (15:41 -0700)]
iris: Allocate coherent buffers for resources flagged as persistent/coherent
If the application requests a coherent resource, we should honor that.
We technically don't need to ensure coherency for persistent mappings,
but we would have to handle PIPE_BARRIER_MAPPED_BUFFER to ensure that
data became visible at the right times. Instead, we just opt for the
easy plan and mark them coherent too.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878>
Mark Janes [Mon, 26 Jun 2023 22:53:58 +0000 (15:53 -0700)]
intel/dev: update mesa_defs.json from defect database
These modifications represent:
* changes to defects made since May 24, 2023
* changes to handling of defects which were manually cloned
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23865>
Jesse Natalie [Fri, 5 May 2023 20:02:41 +0000 (13:02 -0700)]
dzn: VK_EXT_external_memory_host
When ID3D12Device13 is available, we can support importing host memory.
Imported host memory can be used to back buffers and linear textures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23886>
Jordan Justen [Mon, 15 May 2023 18:53:03 +0000 (14:53 -0400)]
anv: Flush untyped dataport cache DC flush is requested on compute
Although the following is based on this observations for OpenGL, we
probably need this for Vulkan as well.
KHR-GL46.texture_buffer.texture_buffer_operations_ssbo_writes writes
to an SSBO in a compute program, then issues a memory-barrier, which
causes us to add a DC-flush. Then a second compute program samples
from the SSBO written by the first compute program.
Although we expected the DC-flush to make the writes available to the
second compute program, on MTL this wasn't the case. Adding the
"Untyped Data-Port Cache Flush" fixes this.
The PRM indicates that compute programs must set "Untyped Data-Port
Cache Flush" to flush some LSC writes when flushing HDC. Although we
are setting DC-flush, and not HDC-flush, it does appear that the
following reference might also apply to DC-flush.
In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU
Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command
Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0,
Bit 9), there is a programming note:
> When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped
> L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit
> in the PIPE_CONTROL command.
Ref:
a8108f1d444 ("anv: Add missing untyped data port flush on PIPELINE_SELECT")
Ref:
bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>
Jordan Justen [Mon, 15 May 2023 18:53:03 +0000 (14:53 -0400)]
anv: Flush untyped dataport cache when HDC flush is requested on compute
In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU
Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command
Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0,
Bit 9), there is a programming note:
> When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped
> L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit
> in the PIPE_CONTROL command.
Ref:
a8108f1d444 ("anv: Add missing untyped data port flush on PIPELINE_SELECT")
Ref:
bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>
Jordan Justen [Thu, 22 Jun 2023 21:44:20 +0000 (14:44 -0700)]
anv: Clear untyped dataport cache flush bit if not in GPGPU mode
This should be equivalent, but refactoring the code will allow the
next two patches to use an else block for this check.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>
Jordan Justen [Mon, 15 May 2023 18:53:03 +0000 (14:53 -0400)]
iris: Flush untyped dataport cache DC flush is requested on compute
KHR-GL46.texture_buffer.texture_buffer_operations_ssbo_writes writes
to an SSBO in a compute program, then issues a memory-barrier, which
causes us to add a DC-flush. Then a second compute program samples
from the SSBO written by the first compute program.
Although we expected the DC-flush to make the writes available to the
second compute program, on MTL this wasn't the case. Adding the
"Untyped Data-Port Cache Flush" fixes this.
The PRM indicates that compute programs must set "Untyped Data-Port
Cache Flush" to flush some LSC writes when flushing HDC. Although we
are setting DC-flush, and not HDC-flush, it does appear that the
following reference might also apply to DC-flush.
In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU
Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command
Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0,
Bit 9), there is a programming note:
> When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped
> L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit
> in the PIPE_CONTROL command.
Ref:
bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>
Jordan Justen [Mon, 15 May 2023 18:53:03 +0000 (14:53 -0400)]
iris: Flush untyped dataport cache when HDC flush is requested on compute
In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU
Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command
Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0,
Bit 9), there is a programming note:
> When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped
> L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit
> in the PIPE_CONTROL command.
Ref:
bd8e8d204db ("iris: Add missing untyped data port flush on PIPELINE_SELECT")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>
Yonggang Luo [Sat, 3 Jun 2023 04:17:55 +0000 (12:17 +0800)]
ci: Testing -D shared-glapi=disabled with debian-clang-release
Acked-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23409>
Yonggang Luo [Mon, 5 Jun 2023 15:59:53 +0000 (23:59 +0800)]
mapi: Hide OpenGL functions to be exported when shared-glapi is disabled
Fixes the following test error:
135/154 mesa:gallium / osmesa-symbols-check FAIL 0.07s exit status 1
```
src/gallium/targets/osmesa/libOSMesa.so.8.0.0: unknown symbol exported: glAreTexturesResidentEXT
src/gallium/targets/osmesa/libOSMesa.so.8.0.0: unknown symbol exported: glDeleteTexturesEXT
src/gallium/targets/osmesa/libOSMesa.so.8.0.0: unknown symbol exported: glGenTexturesEXT
src/gallium/targets/osmesa/libOSMesa.so.8.0.0: unknown symbol exported: glIsTextureEXT
```
The build options is:
```
-D glx=xlib -D gles1=disabled -D gles2=disabled -D shared-glapi=disabled
```
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23409>
Lionel Landwerlin [Tue, 27 Jun 2023 05:41:35 +0000 (08:41 +0300)]
intel/aubinator_error_decode: add ccs support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23867>
Lionel Landwerlin [Mon, 26 Jun 2023 18:32:48 +0000 (21:32 +0300)]
genxml: enable decoding on compute engine
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23867>
Rhys Perry [Tue, 13 Jun 2023 13:09:26 +0000 (14:09 +0100)]
radv: use nir_opt_intrinsics
No fossil-db changes (navi21).
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
Rhys Perry [Tue, 13 Jun 2023 13:07:53 +0000 (14:07 +0100)]
nir/opt_intrinsic: optimize quad vote
Optimizes a quadAll()/quadAny() pattern created by dxil-spirv:
https://github.com/HansKristian-Work/dxil-spirv/commit/
7adc87d4deaba8078bcdef8dfbebdda0165cd7bc
dxil-spirv can't use clustered reductions because they are not guaranteed
to include helper invocations.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
Rhys Perry [Tue, 13 Jun 2023 14:27:26 +0000 (15:27 +0100)]
nir,aco: add INCLUDE_HELPERS index to reduce intrinsic
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
Rhys Perry [Tue, 13 Jun 2023 14:25:08 +0000 (15:25 +0100)]
aco: include helpers in emit_uniform_{reduce,scan}
Found by inspection.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
Rhys Perry [Tue, 13 Jun 2023 11:35:34 +0000 (12:35 +0100)]
nir/peephole_select: allow some invocation broadcast intrinsics
fossil-db (navi21):
Totals from 3 (0.00% of 133428) affected shaders:
Instrs: 2074 -> 2083 (+0.43%)
CodeSize: 10596 -> 10692 (+0.91%)
Latency: 75754 -> 75946 (+0.25%)
InvThroughput: 16900 -> 16975 (+0.44%)
Copies: 312 -> 309 (-0.96%)
Branches: 150 -> 132 (-12.00%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
Alyssa Rosenzweig [Mon, 26 Jun 2023 15:39:28 +0000 (11:39 -0400)]
treewide: Remove unused builders
-Wunused-variables kicks in now that it can see through the init.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
Alyssa Rosenzweig [Mon, 26 Jun 2023 14:42:47 +0000 (10:42 -0400)]
treewide: Use nir_builder_create more
perl -p0e 's/nir_builder_init\(&([^,]*), /\1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
Alyssa Rosenzweig [Mon, 26 Jun 2023 14:42:29 +0000 (10:42 -0400)]
nir: Use nir_builder_create
perl -p0e 's/nir_builder ([^;]*);\s*nir_builder_init\(&\1, /nir_builder \1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
Alyssa Rosenzweig [Mon, 26 Jun 2023 14:20:04 +0000 (10:20 -0400)]
nir: Add nir_builder_create returning nir_builder
More ergonomic.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
Konstantin Seurer [Mon, 26 Jun 2023 12:23:08 +0000 (14:23 +0200)]
nir/builder_opcodes: Remove nir_build_ prefixed helpers
This patch decreases the size of nir_builder_opcodes.h from 14292 loc to
13763 loc.
nir_build_ versions are still needed if the nir_ is a custom helper.
Intrinsics which need such a helper have to be added to
build_prefixed_intrinsics.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Konstantin Seurer [Mon, 26 Jun 2023 12:18:20 +0000 (14:18 +0200)]
nir: Use nir_ instead of nir_build_ helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Konstantin Seurer [Mon, 26 Jun 2023 12:17:56 +0000 (14:17 +0200)]
vtn: Use nir_ instead of nir_build_ helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Konstantin Seurer [Mon, 26 Jun 2023 12:17:14 +0000 (14:17 +0200)]
freedreno: Use nir_ instead of nir_build_ helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Konstantin Seurer [Mon, 26 Jun 2023 12:16:51 +0000 (14:16 +0200)]
intel: Use nir_ instead of nir_build_ helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Konstantin Seurer [Mon, 26 Jun 2023 12:16:17 +0000 (14:16 +0200)]
microsoft: Use nir_ instead of nir_build_ helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Konstantin Seurer [Mon, 26 Jun 2023 12:15:12 +0000 (14:15 +0200)]
amd: Use nir_ instead of nir_build_ helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
Alyssa Rosenzweig [Mon, 26 Jun 2023 16:54:58 +0000 (12:54 -0400)]
nir/lower_blend: Optimize masked out RTs
While debugging KHR-GLES31.core.draw_buffers_indexed.color_masks, the noise from
piles of store_output(load_output) instructions got in the way. Optimize it out.
This does not fix the test, but if this case ever happened in a real app it
would improve performance. This is only load bearing on Asahi (and PanVK?),
since Panfrost wouldn't call nir_lower_blend at all in this case.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23836>
Alyssa Rosenzweig [Fri, 23 Jun 2023 15:19:18 +0000 (11:19 -0400)]
asahi: Use txf for background program
More straightforward (txf instead of tex, with integer coords). No discrernible
performance difference.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23836>
Alyssa Rosenzweig [Wed, 14 Jun 2023 22:26:44 +0000 (18:26 -0400)]
agx: Use nir_lower_frag_coord_to_pixel_coord
Instead of open-coding the logic.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23836>
Alyssa Rosenzweig [Fri, 23 Jun 2023 14:47:20 +0000 (10:47 -0400)]
pan/bi: Use lower_frag_coord_to_pixel_coord
Instead of vendoring the logic. This has a side benefit of letting NIR
optimize the generated code a bit.
total instructions in shared programs: 2687284 -> 2687281 (<.01%)
instructions in affected programs: 532 -> 529 (-0.56%)
helped: 3
HURT: 1
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 140711.33 -> 140711.31 (<.01%)
cycles in affected programs: 2.53 -> 2.52 (-0.62%)
helped: 1
HURT: 0
total fma in shared programs: 22059.44 -> 22059.39 (<.01%)
fma in affected programs: 2.69 -> 2.64 (-1.74%)
helped: 3
HURT: 0
total cvt in shared programs: 14659.09 -> 14659.09 (0.00%)
cvt in affected programs: 1.56 -> 1.56 (0.00%)
helped: 1
HURT: 1
total quadwords in shared programs: 1455408 -> 1455416 (<.01%)
quadwords in affected programs: 128 -> 136 (6.25%)
helped: 0
HURT: 1
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23836>
Alyssa Rosenzweig [Fri, 23 Jun 2023 14:23:43 +0000 (10:23 -0400)]
nir: Add lower_frag_coord_to_pixel_coord pass
We've open coded this in a few backends.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23836>
Alyssa Rosenzweig [Wed, 14 Jun 2023 22:26:28 +0000 (18:26 -0400)]
nir: Add pixel_coord, frag_coord_zw intrinsics
On some architectures, gl_FragCoord.xy is available as an integer but
gl_FragCoord.zw requires interpolation. Add dedicated intrinsics so we can
lower it all in NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23836>
Mike Blumenkrantz [Tue, 27 Jun 2023 13:03:50 +0000 (09:03 -0400)]
ci: add a test-dozen-deqp flake
this times out regularly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23876>
Samuel Pitoiset [Mon, 12 Jun 2023 16:25:08 +0000 (18:25 +0200)]
radv/amdgpu: workaround a kernel bug when replacing sparse mappings
AMDGPU has a bug when clearing mappings for BOs that are always valid
in VM with OP_REPLACE.
See https://lists.freedesktop.org/archives/amd-gfx/2023-June/094648.html
The current workaround is to re-use OP_MAP/OP_UNMAP until all stable
kernels have the fix.
This partially reverts "radv/winsys: update sparse mappings with
OP_REPLACE instead of OP_MAP/OP_UNMAP".
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23741>
Samuel Pitoiset [Tue, 20 Jun 2023 10:52:26 +0000 (12:52 +0200)]
radv/amdgpu: skip adding per VM BOs for sparse during CS BO list build
This should be similar but it will help for re-introducing
OP_MAP/ON_UNMAP instead of OP_REPLACE.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23741>
Yonggang Luo [Fri, 23 Jun 2023 05:30:31 +0000 (13:30 +0800)]
mapi: Now _glapi_get_dispatch_table_size always equal to sizeof(struct _glapi_table) / sizeof(void *)
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23822>
Yonggang Luo [Fri, 23 Jun 2023 04:29:04 +0000 (12:29 +0800)]
mapi: Fixes compile error with build option "-D shared-glapi=disabled"
Fixes:
398a8d43dc9 ("mapi: Delete dynamic stub generation.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9245
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23822>
Karmjit Mahil [Wed, 14 Jun 2023 14:44:10 +0000 (15:44 +0100)]
pvr: Change winsys flag defines to bitfields
Makes it easier to see which flags are set while debugging, and
prevent errors where the `BITFIELD_BIT()` is missing or using the
wrong flag for something.
Some fields have also been renamed to better fit with the naming
scheme around the code base.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23765>
Karmjit Mahil [Wed, 14 Jun 2023 14:47:23 +0000 (15:47 +0100)]
pvr: Fix missing BITFIELD_BIT for winsys frag job flag
On submission SPMSCRATCHBUFFER was acting like GET_VIS_RESULT +
DEPTH_BUFFER_PRESENT. This was causing hardware resets on barrier
stores as the depth buffer isn't actually present so the
store would be carried out to a NULL address.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23765>
Yonggang Luo [Sun, 11 Jun 2023 17:10:24 +0000 (01:10 +0800)]
util: include "util/compiler.h" instead of "pipe/p_compiler.h"
And pipe/p_compiler.h are removed as it not used any more
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Sun, 11 Jun 2023 17:07:29 +0000 (01:07 +0800)]
util: Merge p_compiler.h into src/util/compiler.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Thu, 22 Jun 2023 16:52:16 +0000 (00:52 +0800)]
treewide: style fixes after replace the usage of ubyte/ushort with uint8_t/uint16_t
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Thu, 22 Jun 2023 16:35:04 +0000 (00:35 +0800)]
treewide: Replace the usage of ubyte/ushort with uint8_t/uint16_t
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Thu, 22 Jun 2023 15:58:38 +0000 (23:58 +0800)]
treewide: Replace the usage of TRUE/FALSE with true/false
this is a separate patch as it's won't affect the code style
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Thu, 22 Jun 2023 15:32:13 +0000 (23:32 +0800)]
treewide: style fixes after replace usage of boolean to bool
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Thu, 22 Jun 2023 16:24:20 +0000 (00:24 +0800)]
treewide: replace usage of boolean to bool
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Sun, 11 Jun 2023 18:59:59 +0000 (02:59 +0800)]
llvmpipe: altivec.h inclusion in -std=c++98..11 causes bool to be redefined
So we carefully include altivec.h in lp_setup_tri.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Sun, 11 Jun 2023 17:21:53 +0000 (01:21 +0800)]
gallium/draw: Replace the usage of ushort to uint16_t in files that can not found by tools
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Yonggang Luo [Sun, 11 Jun 2023 17:04:44 +0000 (01:04 +0800)]
hud: Use bool/true/false to replace boolean/TRUE/FALSE in hud/hud_context.c
auto tools can not find and replace
```
#define HUD_DEFAULT_VISIBILITY TRUE
```
So did the of this line manually,
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
Erik Faye-Lund [Fri, 23 Jun 2023 14:38:10 +0000 (16:38 +0200)]
aux/indices: use stdint.h types
These generated sources uses older, less portable types such as ubyte,
ushort and uint. But we have stdint.h everywhere now, so let's use those
types instead.
To stay consistent, let's talk about UINT8 etc instead of UBYTE for the
entirety of the u_indices infrastructure.
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23853>
Christian Gmeiner [Thu, 22 Jun 2023 18:56:30 +0000 (20:56 +0200)]
etnaviv: linker: add fallback lookup to VARYING_SLOT_BFC[n]
There are valid NIR shaders pairs where the vertex shader has
a VARYING_SLOT_BFC0 shader_out and the corresponding framgent
shader has a VARYING_SLOT_COL0 shader_in.
So at link time if there is no matching VARYING_SLOT_BFC[n],
we must map VARYING_SLOT_BFC0[n] to VARYING_SLOT_COL[n].
Example shader pair from 'spec@!opengl 2.0@vertex-program-two-side back':
shader: MESA_SHADER_VERTEX
source_sha1: {0xf916f77d, 0xffa6ab5e, 0x160976a7, 0xb59fe59c, 0x92e8f3f6}
name: GLSL3
internal: false
stage: 0
next_stage: 4
inputs_read: 0
outputs_written: 0,13
subgroup_size: 1
bit_sizes_float: 0x20
bit_sizes_int: 0x20
first_ubo_is_default_ubo: true
flrp_lowered: true
inputs: 1
outputs: 2
uniforms: 0
decl_var shader_in INTERP_MODE_NONE vec4 gl_Vertex (VERT_ATTRIB_POS.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_BackColor (VARYING_SLOT_BFC0.xyzw, 1, 0)
decl_function main (0 params)
impl main {
block block_0:
/* preds: */
vec1 32 ssa_0 = deref_var &gl_Vertex (shader_in vec4)
vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
vec4 32 ssa_2 = load_const (0x00000000, 0x00000000, 0x3f000000, 0x00000000) = (0.000000, 0.000000, 0.500000, 0.000000)
vec1 32 ssa_5 = deref_var &gl_BackColor (shader_out vec4)
vec4 32 ssa_11 = mov ssa_2
vec4 32 ssa_13 = fsat ssa_11
intrinsic store_deref (ssa_5, ssa_13) (wrmask=xyzw, access=0)
vec1 32 ssa_7 = deref_var &gl_Position (shader_out vec4)
vec4 32 ssa_12 = mov ssa_1
intrinsic store_deref (ssa_7, ssa_12) (wrmask=xyzw, access=0)
/* succs: block_1 */
block block_1:
}
shader: MESA_SHADER_FRAGMENT
source_sha1: {0x5059da66, 0x00c609e5, 0x5329c39a, 0x13e2fc88, 0x8e68cb71}
name: GLSL3
internal: false
stage: 4
next_stage: 4
inputs_read: 1
outputs_written: 2
subgroup_size: 1
first_ubo_is_default_ubo: true
flrp_lowered: true
inputs: 1
outputs: 1
uniforms: 0
decl_var shader_in INTERP_MODE_NONE vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0)
decl_function main (0 params)
impl main {
block block_0:
/* preds: */
vec1 32 ssa_0 = deref_var &gl_Color (shader_in vec4)
vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
vec1 32 ssa_2 = deref_var &gl_FragColor (shader_out vec4)
intrinsic store_deref (ssa_2, ssa_1) (wrmask=xyzw, access=0)
/* succs: block_1 */
block block_1:
}
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23850>
Christian Gmeiner [Wed, 14 Jun 2023 19:19:45 +0000 (21:19 +0200)]
etnaviv: nir: call nir_remove_dead_variables(..) before linking setup
There are cases where there is a chain to an unused nir variable that get removed
by nir_opt_dce. This breaks our current linker as the variable can still be accessed
via nir_foreach_shader_in_variable(..) macro.
So lets call nir_remove_dead_variables(..) just before we setup our linking.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23673>
Christian Gmeiner [Mon, 26 Jun 2023 08:53:58 +0000 (10:53 +0200)]
ir3/analyze_ubo_ranges: Move IR3_DBG_NOUBOOPT check
There is no need to walk the hole nir shader if IR3_DBG_NOUBOOPT
is used.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23854>
Iago Toral Quiroga [Tue, 20 Jun 2023 07:47:57 +0000 (09:47 +0200)]
v3dv: don't use the TLB path if we might be copying partial tiles
With TLB paths we are always storing full tiles, so we can't use it
if the regions we store are not a multiple of the tile size (or the
full image).
Unfortunately, at the point we call this we don't usually have the
tile size yet so for now we skip the path if we are not copying
full mip levels.
Fixes various CTS fails in:
dEQP-VK.ycbcr.copy.*.optimal*buffer_optimal*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23739>
Iago Toral Quiroga [Thu, 22 Jun 2023 06:18:35 +0000 (08:18 +0200)]
v3dv: fix slice size for miplevels >= 2
We want to store the slice size in pixels not the level size
after padding to a power of 2 we use miplevels >= 2.
Fixes:
1cb2d2a5ee ('v3dv: store slice dimensions in pixels')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23739>
Konstantin Seurer [Sat, 20 May 2023 18:21:50 +0000 (20:21 +0200)]
docs: Update envvars used for tracing
Updates the environment variables reference to document the new common
tracing infrastructure.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Sat, 14 Jan 2023 14:18:09 +0000 (15:18 +0100)]
vulkan/rmv,radv: Use common trace trigger
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Sun, 8 Jan 2023 20:29:33 +0000 (21:29 +0100)]
radv/rgp: Use common trace trigger
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Sun, 8 Jan 2023 20:25:59 +0000 (21:25 +0100)]
radv/rra: Use common trace trigger
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Sun, 8 Jan 2023 15:46:13 +0000 (16:46 +0100)]
vulkan/wsi/x11: Capture traces using a hotkey
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Wed, 10 May 2023 17:21:09 +0000 (19:21 +0200)]
radv: Add radv_trace_mode
...and add the RADV specific trace modes to the VK instance.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Sun, 8 Jan 2023 15:44:57 +0000 (16:44 +0100)]
vulkan: Common trace capturing infrastructure
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Sun, 8 Jan 2023 15:44:12 +0000 (16:44 +0100)]
meson: Add a xcb-keysyms dependency
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
Konstantin Seurer [Thu, 22 Jun 2023 20:22:34 +0000 (22:22 +0200)]
radv: Call radv_pipeline_init_scratch per shader
Compute pipelines only have one shader, which was not handled correctly
in the case of ray tracing pipelines. Adding radv_shader as an argument
allows us to handle the ray tracing prolog. The original loop is inlined
into its only user (radv_pipeline_graphics.c).
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23812>
Sagar Ghuge [Thu, 22 Jun 2023 17:46:22 +0000 (10:46 -0700)]
intel/ds: Track CCS cache flush bit
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 17:13:15 +0000 (10:13 -0700)]
iris: implement recommended flush/wait of AUX-TT invalidation
This patch implements the recommended flush/wait of AUX-TT invalidation
according to per command streamer (engine).
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 05:05:08 +0000 (22:05 -0700)]
iris: Fix AUX-TT invalidation
In order to make sure RCS engine is idle, we need to add
DC flush + CS stall + Render target Cache flush + Depth Cache
on Gfx 12 and additional CCS cache flush on Gfx12.5.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 04:35:07 +0000 (21:35 -0700)]
iris: Add CCS cache flush bits
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 19:17:20 +0000 (12:17 -0700)]
anv: implement recommended flush/wait of AUX-TT invalidation on compute
This patch implements the recommended flush/wait of AUX-TT invalidation
for compute/render command streamer.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 04:48:44 +0000 (21:48 -0700)]
anv: Fix AUX-TT invalidation
In order to make sure RCS engine is idle, we need to add
DC flush + CS stall + Render target Cache flush + Depth Cache
on Gfx 12 and additional CCS cache flush on Gfx12.5.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 04:09:26 +0000 (21:09 -0700)]
anv: Add CCS cache flush bits to anv_pipe_bits
This will help us to flush the entries out of the CCS cache.
v2:
- Move enum value close to HW bits section (Lionel)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 16:46:37 +0000 (09:46 -0700)]
intel/genxml: Add Compute/Blitter CCS aux invalidation register
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Sagar Ghuge [Wed, 21 Jun 2023 03:45:26 +0000 (20:45 -0700)]
intel/genxml: Add CCS cache flush field to PIPE_CONTROL
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
Juan A. Suarez Romero [Mon, 26 Jun 2023 16:40:59 +0000 (18:40 +0200)]
vc4/v3d/ci: update expected results
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23862>
Vitaliy Triang3l Kuzmin [Mon, 3 Apr 2023 19:50:12 +0000 (22:50 +0300)]
radv: Enable VK_EXT_fragment_shader_interlock
ACO only currently - not available in LLVM.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Sat, 24 Jun 2023 12:25:40 +0000 (15:25 +0300)]
zink/ci: Add broken fragment shader interlock test to RADV flakes
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Fri, 7 Apr 2023 14:31:04 +0000 (17:31 +0300)]
radv: Disable VRS forcing with Primitive Ordered Pixel Shading
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Thu, 27 Apr 2023 11:40:48 +0000 (14:40 +0300)]
radv: Apply the POPS missed overlap hardware bug workaround
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Mon, 3 Apr 2023 19:40:33 +0000 (22:40 +0300)]
ac/gpu_info: Check whether the device has the POPS missed overlap bug
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Sat, 13 May 2023 21:23:16 +0000 (00:23 +0300)]
radv: Handle Primitive Ordered Pixel Shading in DB_SHADER_CONTROL
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Mon, 3 Apr 2023 19:23:11 +0000 (22:23 +0300)]
radv: Enable the null export workaround with POPS
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Fri, 2 Jun 2023 19:58:47 +0000 (22:58 +0300)]
radv: Enable POPS collision wave ID shader argument
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Fri, 2 Jun 2023 19:55:48 +0000 (22:55 +0300)]
radv: Declare POPS collision wave ID shader argument
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Fri, 2 Jun 2023 21:29:31 +0000 (00:29 +0300)]
radv: Ensure 1x1 shading rate on GFX10.3 with interlock execution mode
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Fri, 2 Jun 2023 21:26:31 +0000 (00:26 +0300)]
radv: Detect the use of Primitive Ordered Pixel Shading
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
Vitaliy Triang3l Kuzmin [Mon, 3 Apr 2023 19:15:37 +0000 (22:15 +0300)]
radv: Remove unconditional POPS_DRAIN_PS_ON_OVERLAP setting
This hardware hang workaround (PAL waMiscPopsMissedOverlap) is needed only
on some Vega chips, and only for 8 or more samples per pixel. It has a
significant performance cost (around 1.5x-2x in
nvpro-samples/vk_order_independent_transparency), so it should be precisely
configured when setting up Primitive Ordered Pixel Shading.
It was added in
47b780be21d917eaa6a6a6c9e30ba9fba52d9acd, when POPS was not
used in Mesa, with the change being described as "this may not be needed
yet, but let's set it now".
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
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