meson: Remove some unnecessary loops.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11609>

meson: Use get_supported_arguments more often.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11609>

lima/ppir: implement gl_FragDepth support

Mali4x0 supports writing depth and stencil from fragment shader
and we've been using it quite a while for depth/stencil buffer reload.

The missing part was specifying output register for depth/stencil.
To figure it out, I changed reload shader to use register $4 as output
and poked RSW bits (or rather consecutive 4 bit groups) until tests
that rely on reload started to pass again.

It turns out that register number for gl_FragDepth/gl_FragStencil is in
rsw->depth_test and register number for gl_FragColor is in
rsw->multi_sample and it's repeated 4 times for some reason (likely for
MSAA?)

With this knowledge we now can modify ppir compiler to support multiple
store_output intrinsics.

To do that just add destination SSA for store_output to the registers
list for regalloc and mark them explicitly as output. Since it's never
read in shader we have to take care about it in liveness analysis -
basically just mark it alive from the time when it's written to the end
of the block. If it's live only in the last instruction, mark it as
live_internal, so regalloc doesn't clobber it.

Then just let regalloc do its job, and then copy register number to the
shader state and program it in RSW.

The tricky part is gl_FragStencil, since it resides in the same register
as gl_FragDepth and with the current design of the compiler it's hard to
merge them. However gl_FragStencil doesn't seem to be part of GL2
or GLES2, so we can just leave it not implemented.

Also we need to take care of stop bit for instructions - now we can't
just set it in every instruction that stores output, since there may be
several outputs. So if there's any store_output instructions in the
block just mark that block has a stop, and set stop bit in the last
instruction in the block. The only exception is discard - we always need
to set stop bit in discard instruction.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13830>

lima/ppir: check if mul node is a source of add node before inserting

We can't insert mul node into add node instruction if it's a virtual dep
(sequence or write_or_read dep), so use ppir_node_has_single_src_succ
in addition to ppir_node_has_single_succ.

We can't use ppir_node_has_single_src_succ alone, since node may have
a virtual dependency in addition to source dependency, and we can't
insert it either in this case.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13830>

svga: fix bitwise/logical and mixup

The function need_temp_reg_initialization looks suspecious.

It will only ever return true if we get past this if:
if (!(emit->info.indirect_files && (1u << TGSI_FILE_TEMPORARY)) ...

Using the logical && means the intended initialization done
based on the result of this check is not performed.

This code was both introduced and altered in MR 5317.
ccb4ea5a introduces the function.
ba37d408 is a collection of performance improvements and misc
fixes. This altered the if from using bitwise to logical and.

This commit changes it back to bitwise.

Spotted from a compile warning.

Fixes: ba37d408da3 ("svga: Performance fixes")

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12157>

nine: remove dead code

This line gets the cap but does not store it. The line has existed
unchanged since the original import in fdd96578.

Fixes a compile warning

Acked-by: Axel Davy davyaxel0@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12155>

android.mk: Add missing variables to the make target

Android build system may use different internal variables to specify
cflags/cppflags.
Small change in product confguration may force Android to use diffrent
set of variables, therefore we should keep all of them attached to the
make rule's target.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5549
Fixes: 8621bd8d5e67 ("android: Add scripts to build using meson")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13914>

lavapipe: fix unused variable

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13892>

vulkan: fix uninitialized variables

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13892>

turnip: implement VK_KHR_buffer_device_address

We don't advertise bufferDeviceAddressCaptureReplay capability and
neither does blob, because at the moment there is no way to allocate
bo with predefined iova.

There is no support of any arithmetic with addresses since shaderInt64
is not enabled. However, we could enable int64 support whenever we want.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8717>

freedreno/ir3: handle global atomics

Only for a6xx since we don't know the instructions for global
atomics on previous gens. Per Qualcomm's docs in OpenCL atomics
are only supported since a5xx together with Generic memory space.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8717>

freedreno/ir3: add a6xx global atomics and separate atomic opcodes

Separating atomic opcodes makes possible to express a6xx global
atomics which take iova in SRC1. They would be needed by
VK_KHR_buffer_device_address.
The change also makes easier to distiguish atomics in conditions.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8717>

llvmpipe: Use lp_build_round_arch on IBM Z (s390x)

LLVM has all the required intrinsics available on IBM Z, so use them for
rounding operations (they will be implemented as a single instruction).
This change makes the test case lp_test_arit pass, because it avoids
using the buggy generic code.

v2: update .gitlab-ci/cross-xfail-s390x to reflect passing lp_test_arit

Signed-off-by: Marius Hillenbrand <mhillen@linux.ibm.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13927>

util/cpu_detect: Add flag for IBM Z (s390x)

As preparation for changing the behavior of LLVMpipe on IBM Z, add a
flag to detect that platform. As it is always known at compile-time, we
do not add it to the struct for cpu flags to avoid inflating that
struct's size.

Signed-off-by: Marius Hillenbrand <mhillen@linux.ibm.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13927>

freedreno/ir3: remove unused actual_in counting

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13918>

virgl: Link shader program

Add a new command associated to glLinkProgram. With this we should be
able to compile and link shaders when requested by the user, thus
avoiding that to happen in the middle of a frame.

Together with the command we pass an array of shader handles attached to
the program, where each position of the array corresponds to a pipe
shader type.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13674>

gallium: add a link shader hook

Allow drivers to register a callback for when a shader program is linked.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13674>

broadcom/compiler: don't move ldvary earlier if current instruction has ldunif

If we did, we would have the instruction coming right after ldvary write
to the same implicit destination as ldvary at the same time. We prevent
this when merging instructions, but we should make sure we prevent this
when we move ldvary around for pipelining too.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13921>

radv: fix emitting VBO when vertex input dynamic state is used

In the following scenario:
    CmdBindPipeline()
    CmdBindVertexBuffers()
    CmdSetVertexInput()
    CmdDraw()
    CmdBindVertexBuffers()
    CmdSetVertexInput()
    CmdDraw()

The VBO won't be updated for the second draw because the state is
cleared when the dynamic state is emitted and the pipeline isn't dirty.

Found by inspection.

Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13855>

radv/winsys: report the real family name instead of OVERRIDDEN

When RADV_FORCE_FAMILY is used, this helps pre-compiling shaders to
make sure cache entries will match real hardware.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13812>

ac: change family names to uppercase in ac_get_family_name()

To print the same device name as real hw.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13812>

radv: convert remaining enums/structs to 1.2 versions

Some were missing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13882>

intel/compiler: Prepare disasm for 16-bit sampler params

v2:
- Update descriptor helper (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/fs: Define and set correct sampler simd mode

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Deprecate ld2dms and use ld2dms_w instead

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Add new variant for TXF_CMS_W

This allows, for example, fs_inst::components_read() without passing
devinfo as extra argument.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Prepare ld2dms_w for 4 mcs components

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Demote sampler params to 16-bit for CMS/UMS/MCS

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler/fs: Add support for 16-bit sampler msg payload

For SIMD8 half float payload, each component takes a full register, so
we can use existing LOAD_PAYLOAD infrastruture for required padding by
alternating plain 8-wide half float vector and null vector.

Also this patch removes an unwanted assertion from
opt_copy_propagation_local for LOAD_PAYLOAD.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Add helper to support half float payload with padding

To support SIMD8 half float payloads, each component takes one full
32bit wide register in both SIMD8H and SIMD16H mode. So we can make use
of existing LOAD_PAYLOAD infrastructure alternating a half float vector
and a null vector, in order to handle required padding.

v2: (Francisco)
- Skip header sources
- Fix comparision units
- Don't allocate VGRF for padded source

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Fix instruction size written calculation

We are always aligning to REG_SIZE but when we have payload sources less
than REG_SIZE, size written is miscalculated.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Don't hardcode padding source type to 32bit

We can use LOAD_PAYLOAD infrastructure in order to handle 16bit float
payload. Let's rely on source type for padding sources, if not set
previously then default one would be 32-bit.

This patch will be used later in the series to handle 16-bit float
payloads.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Handle new sampler descriptor fields for 16bit sampler

Update return format field and add SIMD Mode [2] field in sampler
descriptor. Now we can tell sampler to return data in either 32/16 bit
format precision.

v1:
- Drop unnecessary descriptor fields (Jason)
- Handle return format (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

intel/compiler: Set correct return format for brw_SAMPLE

on GFX8 onwards, we have only single bit to determine correct return
format.

v2:
- Define macro and use it instead of hardcoded value. (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

nir: Un-inline more of nir_builder.h.

Cuts another 470KB of libnir.a in my release build.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13889>

nir: Un-inline nir_builder_alu_instr_finish_and_insert()

This function is big and I don't think it will won't get meaningfully
constant-propagated during inlining without LTO.  Move it to a .c file so
we just have one copy, saving 2.8MB from libnir.a on an amd64 release
build.

      text       data        bss      total filename
before:
  18953406    7768312     687260   27408978 build-release/driver-symlinks/iris_dri.so
   9734366    5542453     481692   15758511 build-release/lib/libvulkan_intel.so
  28687772   13310765    1168952   43167489 (TOTALS)

after:
  15478350    7767864     687260   23933474 build-release/driver-symlinks/iris_dri.so
   6810366    5541685     481692   12833743 build-release/lib/libvulkan_intel.so
  22288716   13309549    1168952   36767217 (TOTALS)

No statistically significant performance difference on iris shader-db, n=8.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13889>

nir: apply interpolated input intrinsics setting when lowering clipdist

For drivers that use this in fragment shaders, load_input is going to
produce incorrect results (flat-shaded values).

Fixes clipping tests on a4xx.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13900>

nir: always keep the clip distance array size updated

Drivers expect to know the number of clip distances irrespective of
whether compact arrays are used or not.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13900>

aco/spill: use spills_entry instead of spills_exit to kill linear VGPRs

If a predecessor has only spilled constants (no temporaries), spills_exit
will be empty.

fossil-db (Sienna Cichlid):
Totals from 2 (0.00% of 128647) affected shaders:
Latency: 139106 -> 139104 (-0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5633
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13821>

freedreno/a[345]xx: fix unorm/snorm blend factors when they're "over"

The float value may be out of range, so must be clamped to the allowed
range. Unclear if a3xx also has a SNORM factor that we're just missing
there, but that will be a separate investigation.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13903>

freedreno/a5xx: add missing L8A8_UNORM format to support TBOs

Fixes arb_texture_buffer_object-formats test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13906>

freedreno/a4xx: add some missing legacy formats to help TBOs

Unlike with regular textures, we really have to support all the formats
directly for TBOs to work properly. Add the missing formats to fix
arb_texture_buffer_object-formats piglit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13906>

freedreno/a4xx: add missing SNORM formats to help tests pass

Otherwise some of these fall back to RGBA_SNORM, which can screw up
blend factors.

Fixes spec@ext_texture_snorm@fbo-blending-formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13904>

panfrost: Handle AFBC_FEATURES in drm-shim

Fixes the warning with drm-shim:

   Unknown DRM_IOCTL_PANFROST_GET_PARAM 40

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13894>

panfrost: Collapse 0 parameters in drm-shim

Makes the code a bit more readable, since this is a sensible default for
many parameters.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13894>

broadcom/compiler: fix scoreboard locking checks

According to the spec the hardware locks the scoreboard on the first
or last thread switch (selected via shader state) and any TLB accesses
executed before this are not synchronized by hardware.

This change updates the logic to ensure we respect this requirement
and that we don't assume that the lock is acquired automatically
on the first TLB access, which is not valid at least since V3D 4.1+.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13910>

broadcom/compiler: don't allow RF writes from signals after thrend

Writes to physical registers are not allowed after thread end. We
were checking this for ALU writes, but we need to check it for
signal writes too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13910>

ir3: print half-dst/src for ldib.b/stib.b

So it would print:
 ldib.b.untyped.1d.u16.1.imm.base0 hr0.z, r0.x, 0
instead of:
 ldib.b.untyped.1d.u16.1.imm.base0 r0.z, r0.x, 0

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13876>

intel: move timestamp scaling helper to intel/perf

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/ds: remove verbose messages

At high frequency sampling, this generates a lot of messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/pps: tweak intel config some more

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/ds: isolate intel/perf from the pps-producer

Otherwise we need to include intel headers in generic code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/ds: drop unused constructors

Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/perf: track end timestamp of queries

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/ds: drop timestamp correlation code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

pps: fixup sporadic missing counters

The issue seems to be that without proper timestamps & clock_id, the
recording might discard some packets if they go backward in time.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

intel/perf: add a helper to read timestamp from reports

On newer HW it will require more work than just reading a dword. It
could also vary depending on the report format.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

pps: allow drivers to report timestamps in their own time domain

For this each driver must :

  - report its clock_id (if no particular clock just default to cpu
    boottime one)

  - be able to sample its clock (gpu_timestamp())

The PPSDataSource will then emit timestamp correlation events in the
trace ensuring perfetto is able to display GPU & CPU events
appropriately on its timeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>

broadcom/compiler: apply constant folding on early GS lowering

This solves a case where a NIR geometry shader was storing the output in
a non-constant:

  vec4 32 ssa_1 = load_const (0xc0800000 /* -4.000000 */, 0xc1100000 /* -9.000000 */, 0x40400000 /* 3.000000 */, 0x40e00000 /* 7.000000 */)
  vec1 32 ssa_7 = load_const (0x00000000 /* 0.000000 */)
  vec1 32 ssa_8 = load_const (0x00000001 /* 0.000000 */)
  vec1 32 ssa_9 = iadd ssa_7, ssa_8
  vec1 32 ssa_19 = mov ssa_1.x
  intrinsic store_output (ssa_19, ssa_9) (1, 1, 0, 160, 288) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=32 slots=2 gs_streams(x=0 y=0 z=0 w=0) */

When lowering the VPM output we check if the destination (ssa_9 in this
case) is a constant to add to the VPM offset. We run a constant folding
optimization in an earlier VS lowering, and we should do the same for
GS.

This fixes multiple dEQP-VK.pipeline.interface_matching.* failures.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13884>

broadcom/compiler: handle array of structs in GS/FS inputs

While fragment and geometry shader were handling structs as inputs, they
weren't doing for it arrays of structures.

This fixes multiple dEQP-VK.pipeline.interface_matching.* failures and
assertions.

v2:
 - Fix style (Iago).

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13884>

intel/fs: fix shader call lowering pass

Now that we removed the intel intrinsic and just use the generic one,
we can skip it in the intel call lowering pass and just deal with it
in the intel rt intrinsic lowering.

v2: rewrite with nir_shader_instructions_pass() (Jason)

v3: handle everything in switch (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 423c47de991643 ("nir: drop the btd_resume_intel intrinsic")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12113>

CI/windows: Upload result.txt as an artifact

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13893>

CI/windows: Uprev piglit

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13893>

Auto-enable TLSDESC support

TLSDESC speeds up access to dynamic TLS. This is especially important
for non-glibc targets, but is also helpful for non-initial-exec TLS
variables.

The entry asm does not support TLSDESC, but it only accesses
initial-exec symbols, so it is not necessary to handle that separately.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>

Use initial-exec TLS for glibc only, enable TLS elsewhere

It is not portable to use initial-exec TLS in dlopened libraries. glibc
and FreeBSD allocate extra memory for extra initial-exec variables
specifically for libGL, but other libcs including musl do not.

Keep initial-exec disabled on FreeBSD since it is apparently broken for
some reason:

https://gitlab.freedesktop.org/mesa/mesa/-/issues/966#note_394512
https://github.com/jbeich/mesa/commit/81dbdb15d55054242eded0eb2f32621d583c1aaf

Enable TLS on OpenBSD and Haiku based on the u_thread.h comment that
emutls is better than pthread_getspecific, which seems plausible given
that emutls has strictly more information to work with.

Fixes #966.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>

mesa: move around current texture object fetching

We have to validate the target before fetching the current texture
object. Move this so that it happens later.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>

mesa: check target/format for Tex(ture)StorageMem*

Noticed while doing an audit around _mesa_get_current_tex usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>

android: define cpp_rtti=false because libLLVM is built w/o RTTI

libLLVM for Android is built without RTTI, but after commit ad86267
mesa inherits meson default RTTI enabled state

cpp_rtti=false is added to meson options in android/mesa3d_cross.mk

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13888>

radeonsi: deduplicate min_esverts code in gfx10_ngg_calculate_subgroup_info

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

radeonsi: implement shader culling in GS

It already does compaction, so we just need to load vertex positions
and cull. This was easier than expected.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

radeonsi: don't use ctx.stage outside of si_llvm_translate_nir

si_llvm_translate_nir() changes ctx.stage, so the outside code shouldn't
use it. This hasn't caused any issues yet. Since ctx.stage starts as 0,
the first use in this commit was a tautology.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

radeonsi: simplify si_get_vs_key_outputs for GS

ngg_culling is always 0 when GS is enabled. This will change in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

radeonsi: add is_gs parameter into si_vs_needs_prolog

and disable the VS prolog code for GS.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

radeonsi: restructure code that declares merged VS-GS and TES-GS SGPRs

no change in the SGPR layout

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

radeonsi: separate culling code from VS/TES (to be reused by GS)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>

mesa/get: allow NV_pixel_buffer_object constants in GLES2

The NV_pixel_buffer_object extension can be available in a GLES2
context, so the PIXEL_PACK_BUFFER_BINDING/PIXEL_UNPACK_BUFFER_BINDING
constants should also be available.

Tested on 8086:2e12, "Mesa DRI Intel(R) Q45/Q43 (ELK)".

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5655
Signed-off-by: Nicholas Bishop <nicholasbishop@google.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13862>

d3d12: Validate opened D3D12 resource matches pipe template

Unlike Linux dma-bufs, D3D12 resources are strongly typed, and
can't necessarily just reinterpret the memory arbitrarily.

Allow importing resources with no description coming from the frontend,
and populate the resource desc from the driver instead. If there was
a template, make sure that it matches the incoming resource.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Generate a pipe format -> typeless mapping table too

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Generate format table using a macro list

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Make format list all use macros

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Handle import/export of fd shared handles

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

winsys/d3d12: Populate winsys handle format

All other winsys handle users do so, and a future commit will
start caring about it.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

gallium, windows: Use HANDLE instead of FD for external objects

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

microsoft/compiler: Handle GLES external textures

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Support RGBX formats mapped to RGBA

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Support PIPE_CAP_MIXED_COLOR_DEPTH_BITS

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

d3d12: Support BGRA 555 and 565 formats

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>

android: Allow forcing softpipe

When dealing with swrast, there's two possibilities: If you have LLVM, you get
llvmpipe, which is pretty fast. If you don't, you get softpipe, which is slow,
but does have a couple nice qualities, like being smaller and not needing
executable memory for JIT.

If you're building a driver that requires LLVM like radeonsi then you need the
LLVM stub for the build to find LLVM. But for swrast, since it can mean either
softpipe/llvmpipe, you don't strictly need LLVM. So this just makes the
Android build files flexible like the Meson build files (where you can specify
-Dllvm=disabled even if LLVM is findable).

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>

android,d3d12: Support using DirectX-Headers dependency from AOSP

Note that the Android build system apparently lowercases stuff,
so add a lowercase "directx-headers" dependency which is searched first,
before falling back to the proper-cased "DirectX-Headers" dependency.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>

mesa/main, android: Log errors to logcat

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>

android: Add a BOARD CFlags option so build can be customized

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>

zink: be consistent about waiting on context queue on context destroy

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>

zink: set batch state queue on creation

make this easier to find

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>

freedreno/a5xx: Emit MSAA state for sysmem rendering, too.

This looked obviously wrong, we want to set the sample counts for sysmem
too just like we do on 6xx.  Turns out it fixes some piglits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>

freedreno/a5xx: Document the sRGB bit on RB_2D_SRC/DST info.

Noticed while looking through my set of traces for where the average bit
might be.  Same spot as on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>

freedreno/a5xx: Define a5xx_2d_surf_info like a6xx has.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>

freedreno/a6xx: Disable sample averaging on non-ubwc z24s8 MSAA blits.

The fallback path we averages unorm textures, but if we don't have ubwc on
either then we can just cast them to uint which then just takes sample 0.

The proper UBWC format I think ends up averaging, though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>

freedreno/a6xx: Disable sample averaging on z/s or integer blits.

We can't generally force fd_blitter_blit() to not average in our fallback
blits, but this should at help some cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>

ir3/lower_pcopy: Fix bug with "illegal" copies and swaps

If the source and destination were within the same full register, like
hr90.x and hr90.y (which both map to r45.x), then we'd perform the
swap/copy with the wrong register. This broke
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35 once BDA is enabled.

Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>

ir3/lower_pcopy: Fix shr.b illegal copy lowering

The immediate shouldn't be half-reg because the other source isn't.
Fixes an assertion failure with
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35.

Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>