Merge branches 'clk-samsung', 'clk-mtk', 'clk-rm', 'clk-ast' and 'clk-qcom' into clk-next

 - Add resets for MediaTek MT8195 PCIe and USB
 - Remove DaVinci DM644x and DM646x clk driver support

* clk-samsung:
  clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
  clk: samsung: exynos850: Implement CMU_MFCMSCL domain
  clk: samsung: exynos850: Implement CMU_IS domain
  clk: samsung: exynos850: Implement CMU_AUD domain
  clk: samsung: exynos850: Style fixes
  clk: samsung: exynosautov9: add fsys1 clock support
  clk: samsung: exynosautov9: add fsys0 clock support
  clk: samsung: exynosautov9: correct register offsets of peric0/c1
  clk: samsung: exynosautov9: add missing gate clks for peric0/c1
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  clk: samsung: exynos7885: Add TREX clocks
  clk: samsung: exynos7885: Implement CMU_FSYS domain
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
  clk: samsung: exynos-clkout: Use of_device_get_match_data()

* clk-mtk: (42 commits)
  clk: mediatek: add driver for MT8365 SoC
  clk: mediatek: Export required common code symbols
  clk: mediatek: Provide mtk_devm_alloc_clk_data
  dt-bindings: clock: mediatek: add bindings for MT8365 SoC
  clk: mediatek: mt8192: deduplicate parent clock lists
  clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()
  clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup
  clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
  clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
  clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
  clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
  clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux
  clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes
  clk: mediatek: mt8183: Add clk mux notifier for MFG mux
  clk: mediatek: mux: add clk notifier functions
  clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
  clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe
  clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
  clk: mediatek: add VDOSYS1 clock
  dt-bindings: clk: mediatek: Add MT8195 DPI clocks
  ...

* clk-rm:
  clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x

* clk-ast:
  clk: ast2600: BCLK comes from EPLL

* clk-qcom: (97 commits)
  clk: qcom: gcc-sm6375: Ensure unsigned long type
  clk: qcom: gcc-sm6375: Remove unused variables
  clk: qcom: kpss-xcc: convert to parent data API
  clk: introduce (devm_)hw_register_mux_parent_data_table API
  clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8939: use parent_hws where possible
  dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
  clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc8280xp: use retention for USB power domains
  clk: qcom: gdsc: add missing error handling
  dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos
  clk: qcom: Add global clock controller driver for SM6375
  dt-bindings: clock: add SM6375 QCOM global clock bindings
  clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit
  clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc
  clk: qcom: gdsc: Fix the handling of PWRSTS_RET support
  clk: qcom: Add SC8280XP GPU clock controller
  dt-bindings: clock: Add Qualcomm SC8280XP GPU binding
  clk: qcom: smd: Add SM6375 clocks
  ...

Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'clk-xilinx' into clk-next

 - Miscellaneous of_node_put() fixes
 - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
 - Convert gpio-clk-gate binding to YAML
 - Various fixes to AMD/Xilinx Zynqmp clk driver
 - Graduate AMD/Xilinx "clocking wizard" driver from staging

* clk-ofnode:
  clk: ti: Balance of_node_get() calls for of_find_node_by_name()
  clk: tegra20: Fix refcount leak in tegra20_clock_init
  clk: tegra: Fix refcount leak in tegra114_clock_init
  clk: tegra: Fix refcount leak in tegra210_clock_init
  clk: sprd: Hold reference returned by of_get_parent()
  clk: berlin: Add of_node_put() for of_get_parent()
  clk: at91: dt-compat: Hold reference returned by of_get_parent()
  clk: qoriq: Hold reference returned by of_get_parent()
  clk: oxnas: Hold reference returned by of_get_parent()
  clk: st: Hold reference returned by of_get_parent()
  clk: tegra: Add missing of_node_put()
  clk: meson: Hold reference returned by of_get_parent()
  clk: nomadik: Add missing of_node_put()

* clk-bindings:
  dt-bindings: clock: drop minItems equal to maxItems
  dt-bindings: clock: gpio-gate-clock: Convert to json-schema
  dt-bindings: clock: Move versaclock.h to dt-bindings/clock
  dt-bindings: clock: Move lochnagar.h to dt-bindings/clock

* clk-cleanup:
  clk: allow building lan966x as a module
  clk: clk-xgene: simplify if-if to if-else
  clk: nxp: fix typo in comment
  clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
  clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
  clkdev: Simplify devm_clk_hw_register_clkdev() function
  clkdev: Remove never used devm_clk_release_clkdev()
  clk: Remove never used devm_of_clk_del_provider()
  clk: pistachio: Fix initconst confusion
  clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data
  clk: do not initialize ret
  clk: remove extra empty line
  clk: Fix comment typo
  clk: move from strlcpy with unused retval to strscpy

* clk-zynq:
  clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
  clk: zynqmp: Check the return type zynqmp_pm_query_data
  clk: zynqmp: Add a check for NULL pointer
  clk: zynqmp: Replaced strncpy() with strscpy()
  clk: zynqmp: Fix stack-out-of-bounds in strncpy`
  clk: zynqmp: make bestdiv unsigned

* clk-xilinx:
  clk: clocking-wizard: Depend on HAS_IOMEM
  clk: clocking-wizard: Use dev_err_probe() helper
  clk: clocking-wizard: Update the compatible
  clk: clocking-wizard: Fix the reconfig for 5.2
  clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs
  clk: clocking-wizard: Move clocking-wizard out
  dt-bindings: add documentation of xilinx clocking wizard

clk: qcom: gcc-sm6375: Ensure unsigned long type

This PLL frequency needs a UL postfix to avoid compiler warnings on
32-bit architectures.

Fixes: 184fdd873d83 ("clk: qcom: Add global clock controller driver for SM6375")
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: gcc-sm6375: Remove unused variables

gcc_parent_data_15 and gcc_parent_map_15 are not used in this driver.
Remove them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20221003211438.25691-1-konrad.dybcio@somainline.org
Fixes: 184fdd873d83 ("clk: qcom: Add global clock controller driver for SM6375")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: kpss-xcc: convert to parent data API

Convert the driver to parent data API. From the Documentation pll8_vote
and pxo should be declared in the DTS so fw_name can be used instead of
parent_names. .name is changed to the legacy pxo_board following how
it's declared in other drivers.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20220914144743.17369-2-ansuelsmth@gmail.com
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: introduce (devm_)hw_register_mux_parent_data_table API

Introduce (devm_)hw_register_mux_parent_data_table new API. We have
basic support for clk_register_mux using parent_data but we lack any API
to provide a custom parent_map. Add these 2 new API to correctly handle
these special configuration instead of using the generic
__(devm_)clk_hw_register_mux API.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20220914144743.17369-1-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'qcom-clk-for-6.1' of https://git./linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

This introduces display clock controllers are introduces for SM6115 and
SM8450, and SC8280XP gains a GPU clock controller.  MSM8909 and SM6375
gains global and SMD RPM clock controller drivers.

The handling of GDSCs with PWRSTS_RET was fixed, to keep the GDSC on
while powering down the parent supply. This solved retention issues
during suspend of USB on sc7180/7280 and SC8280XP.

SM6115 and QCM2260 are moved to reuse PLL configuration. SDM660 SDCC1
was moved to floor ops.

Support for the APCS PLLs for IPQ8064, IPQ8074 and IPQ6018 was
added/fixed. The MSM8996 CPU clocks was updated, with support for ACD
clocks added.

Support for SDM670 was added to the SDM845 Glbal clock controller and
the RPMh clock controller driver.

Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for MSM8660, MSM8916, MSM8939, MSM8960 global clock
controllers, IPQ8064 LPASS clock controller and MSM8960 multimedia clock
controller.

Support for per-reset defined delay of was introduced.

* tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (93 commits)
  clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8939: use parent_hws where possible
  dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
  clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc8280xp: use retention for USB power domains
  clk: qcom: gdsc: add missing error handling
  dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos
  clk: qcom: Add global clock controller driver for SM6375
  dt-bindings: clock: add SM6375 QCOM global clock bindings
  clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit
  clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc
  clk: qcom: gdsc: Fix the handling of PWRSTS_RET support
  clk: qcom: Add SC8280XP GPU clock controller
  dt-bindings: clock: Add Qualcomm SC8280XP GPU binding
  clk: qcom: smd: Add SM6375 clocks
  dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG
  dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375
  clk: qcom: rpmhcc: add sdm670 clocks
  dt-bindings: clock: add rpmhcc bindings for sdm670
  ...

clk: allow building lan966x as a module

Set the COMMON_CLK_LAN966X option as a tristate and switch from
builtin_platform_driver() to module_platform_driver() to allow building
and using this driver as a module.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/r/20220617103306.489466-1-clement.leger@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: clk-xgene: simplify if-if to if-else

Replace `if (!pclk->param.csr_reg)` with `else` for simplification
and add curly brackets according to the kernel coding style:

"Do not unnecessarily use braces where a single statement will do."

...

"This does not apply if only one branch of a conditional statement is
a single statement; in the latter case use braces in both branches"

Please refer to:
https://www.kernel.org/doc/html/v5.17-rc8/process/coding-style.html

Signed-off-by: Yihao Han <hanyihao@vivo.com>
Link: https://lore.kernel.org/r/20220408130617.14963-1-hanyihao@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ast2600: BCLK comes from EPLL

This correction was made in the u-boot SDK recently. There are no
in-tree users of this clock so the impact is minimal.

Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Link: https://github.com/AspeedTech-BMC/u-boot/commit/8ad54a5ae15f27fea5e894cc2539a20d90019717
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: clocking-wizard: Depend on HAS_IOMEM

This driver uses devm_platform_ioremap_resource() and thus depends on
HAS_IOMEM. Add the Kconfig dependency to avoid build issues.

Reported-by: kernel test robot <lkp@intel.com>
Cc: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Fixes: c822490f52da ("clk: clocking-wizard: Move clocking-wizard out")
Link: https://lore.kernel.org/r/20221003202608.2611295-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: clocking-wizard: Use dev_err_probe() helper

dev_err() can be replace with dev_err_probe() which will check if error
code is -EPROBE_DEFER.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220913031442.980720-1-yangyingliang@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: nxp: fix typo in comment

Spelling mistake (triple letters) in comment.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/20220521111145.81697-42-Julia.Lawall@inria.fr
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable

Return the value of_clk_add_hw_provider() directly instead of storing it
in another redundant variable.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Link: https://lore.kernel.org/r/20220906072322.337253-1-ye.xingchen@zte.com.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe

pm_runtime_get_sync() will increment pm usage counter.
Forgetting to putting operation will result in reference leak.
Add missing pm_runtime_put_sync in some error paths.

Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.com
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: Balance of_node_get() calls for of_find_node_by_name()

In ti_find_clock_provider(), of_find_node_by_name() will call
of_node_put() for the 'from' argument, possibly putting the node one too
many times. Let's maintain the of_node_get() from the previous search
and only put when we're exiting the function early. This should avoid a
misbalanced reference count on the node.

Fixes: 51f661ef9a10 ("clk: ti: Add ti_find_clock_provider() to use clock-output-names")
Signed-off-by: Liang He <windhl@126.com>
Link: https://lore.kernel.org/r/20220915031121.4003589-1-windhl@126.com
[sboyd@kernel.org: Rewrite commit text, maintain reference instead of
get again]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: add driver for MT8365 SoC

Add clock drivers for MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Export required common code symbols

To make clk-mt8365 compilable as a module there are a few function
symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the
functions.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-4-msp@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Provide mtk_devm_alloc_clk_data

Provide a helper that replaces the kzalloc with devm_kzalloc so error
handling gets easier.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-3-msp@baylibre.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: mediatek: add bindings for MT8365 SoC

Add the clock bindings for the MediaTek MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-2-msp@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clkdev: Simplify devm_clk_hw_register_clkdev() function

Use devm_add_action_or_reset() instead of devres_alloc() and
devres_add(), which works the same. This will simplify the
code. There is no functional changes.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220623115719.52683-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clkdev: Remove never used devm_clk_release_clkdev()

For the entire history of the devm_clk_release_clkdev() existence
(since 2018) it was never used. Remove it for good.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220623115719.52683-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: Remove never used devm_of_clk_del_provider()

For the entire history of the devm_of_clk_del_provider) existence
(since 2017) it was never used. Remove it for good.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220623115719.52683-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'mtk-clk-for-6.1' of https://git./linux/kernel/git/wens/linux into clk-mtk

Pull MediaTek clk driver updates from Chen-Yu Tsai:

A lot of clean up work, as well as new drivers and new functions

 - New clock drivers for MediaTek Helio X10 MT6795
 - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
   - Fix GPU clock topology on MT8195
   - Propogate rate changes from GPU clock gate up the tree
   - Clock mux notifiers for GPU-related PLLs
 - Conversion of more "simple" drivers to mtk_clk_simple_probe()
 - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
 - Fixes to previous |struct clk| to |struct clk_hw| conversion
 - Shrink MT8192 clock driver by deduplicating clock parent lists

* tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux: (31 commits)
  clk: mediatek: mt8192: deduplicate parent clock lists
  clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()
  clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup
  clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
  clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
  clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
  clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
  clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux
  clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes
  clk: mediatek: mt8183: Add clk mux notifier for MFG mux
  clk: mediatek: mux: add clk notifier functions
  clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
  clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe
  clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
  clk: mediatek: add VDOSYS1 clock
  dt-bindings: clk: mediatek: Add MT8195 DPI clocks
  clk: mediatek: mt8192: add mtk_clk_simple_remove
  clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver
  clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver
  clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driver
  ...

clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220928145609.375860-4-dmitry.baryshkov@linaro.org

clk: qcom: gcc-msm8939: use parent_hws where possible

Use parent_hws instead of hanving parent_data with just a single .hw
entry to speed up and simplify parent lookups.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220928145609.375860-3-dmitry.baryshkov@linaro.org

dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml

The MSM8939 GCC bindings are fully comptible with MSM8916, the clock
controller requires the same parent clocks, move MSM8939 GCC compatible
to qcom,msm8916.yaml

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220928145609.375860-2-dmitry.baryshkov@linaro.org

clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs

The USB controllers on sm6350 do not retain the state when
the system goes into low power state and the GDSCs are
turned off.

This can be observed by the USB connection not coming back alive after
putting the device into suspend, essentially breaking USB.

Fix this by updating the .pwrsts for the USB GDSCs so they only
transition to retention state in low power.

Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220928132853.179425-1-luca.weiss@fairphone.com

clk: qcom: gcc-sc8280xp: use retention for USB power domains

Since commit d399723950c4 ("clk: qcom: gdsc: Fix the handling of
PWRSTS_RET support) retention mode can be used on sc8280xp to maintain
state during suspend instead of leaving the domain always on.

This is needed to eventually allow the parent CX domain to be powered
down during suspend.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220929161124.18138-1-johan+linaro@kernel.org

clk: qcom: gdsc: add missing error handling

Since commit 7eb231c337e0 ("PM / Domains: Convert pm_genpd_init() to
return an error code") pm_genpd_init() can return an error which the
caller must handle.

The current error handling was also incomplete as the runtime PM and
regulator use counts were not balanced in all error paths.

Add the missing error handling to the GDSC initialisation to avoid
continuing as if nothing happened on errors.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220929155816.17425-1-johan+linaro@kernel.org

clk: mediatek: mt8192: deduplicate parent clock lists

Some groups of clocks of the same type share the same list of parents.
These lists were declared separately for each clock in older drivers,
bloating the code.

Merge some obvious duplicate parent clock lists in the MT8192 clock
driver together to reduce the code size. These include:

- apll_i2s*_m_parents into one as apll_i2s_m_parents
- img1_parents & img2_parents into one as img_parents
- msdc30_*_parents into one as msdc30_parents
- camtg*_parents into cam_tg_parents
- seninf*_parents into seninf_parents

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220926102523.2367530-6-wenst@chromium.org
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()

During the previous |struct clk| to |struct clk_hw| clk provider API
migration in commit 6f691a586296 ("clk: mediatek: Switch to clk_hw
provider APIs"), a few clk_unregister_*() calls were missed.

Migrate the remaining ones to the |struct clk_hw| provider API, i.e.
change clk_unregister_*() to clk_hw_unregister_*().

Fixes: 6f691a586296 ("clk: mediatek: Switch to clk_hw provider APIs")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220926102523.2367530-3-wenst@chromium.org
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup

When the cleanup paths for the various clk register APIs in the MediaTek
clk library were added, the one in the dividers type used the wrong type
of unregister function. This would result in incorrect dereferencing of
the clk pointer and freeing of invalid pointers.

Fix this by switching to the correct type of clk unregistration call.

Fixes: 3c3ba2ab0226 ("clk: mediatek: mtk: Implement error handling in register APIs")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220926102523.2367530-2-wenst@chromium.org
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel

Following the changes that were done for mt8183, add a clock notifier
for the GPU PLL selector mux: this allows safe clock rate changes by
temporarily reparenting the GPU to a safe clock (clk26m) while the
MFGPLL is reprogrammed and stabilizes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-11-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent

Following what was done on MT8183 and MT8195, also propagate the rate
changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents

These PLLs are conflicting with GPU rates that can be generated by
the GPU-dedicated MFGPLL and would require a special clock handler
to be used, for very little and ignorable power consumption benefits.
Also, we're in any case unable to set the rate of these PLLs to
something else that is sensible for this task, so simply drop them:
this will make the GPU to be clocked exclusively from MFGPLL for
"fast" rates, while still achieving the right "safe" rate during
PLL frequency locking.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier

Following the changes done to MT8183, register a similar notifier
for MT8195 as well, allowing safe clockrate updates for the MFGPLL.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220927101128.44758-8-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux

This clock was being registered as clk-composite through the helpers
for the same in the MediaTek clock APIs but, in reality, this isn't
a composite clock.

Appropriately register this clock with devm_clk_hw_register_mux().
No functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes

The MFG_BG3D is a gate to enable/disable clock output to the GPU,
but the actual output is decided by multiple muxes; in particular:
mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and
"fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the
26MHz clock and various system PLLs.

The clock gate comes after all the muxes, so its parent is
mfg_ck_fast_reg, not top_mfg_core_tmp.
Reparent MFG_BG3D to the latter to match the hardware and add the
CLK_SET_RATE_PARENT flag to it: this way we ensure propagating
rate changes that are requested on MFG_BG3D along its entire clock
tree.

Fixes: 35016f10c0e5 ("clk: mediatek: Add MT8195 mfgcfg clock support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt8183: Add clk mux notifier for MFG mux

When the MFG PLL clock, which is upstream of the MFG clock, is changed,
the downstream clock and consumers need to be switched away from the PLL
over to a stable clock to avoid glitches.

This is done through the use of the newly added clk mux notifier. The
notifier is set on the mux itself instead of the upstream PLL, but in
practice this works, as the rate change notifitcations are propogated
throughout the sub-tree hanging off the PLL. Just before rate changes,
the MFG mux is temporarily and transparently switched to the 26 MHz
main crystal. After the rate change, the mux is switched back.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
[Angelo: Rebased to assign clk_ops in mtk_mux_nb]
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220927101128.44758-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mux: add clk notifier functions

With device frequency scaling, the mux clock that (indirectly) feeds the
device selects between a dedicated PLL, and some other stable clocks.

When a clk rate change is requested, the (normally) upstream PLL is
reconfigured. It's possible for the clock output of the PLL to become
unstable during this process.

To avoid causing the device to glitch, the mux should temporarily be
switched over to another "stable" clock during the PLL rate change.
This is done with clk notifiers.

This patch adds common functions for notifiers to temporarily and
transparently reparent mux clocks.

This was loosely based on commit 8adfb08605a9 ("clk: sunxi-ng: mux: Add
clk notifier functions").

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
[Angelo: Changed mtk_mux_nb to hold a pointer to clk_ops instead of mtk_mux]
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220927101128.44758-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent

The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
rate change requests to its parent, so that DVFS for the GPU can work
properly.

Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: pistachio: Fix initconst confusion

A variable pointing to const isn't const itself. It has to contain
"const" keyword after "*" too. So to keep it in __initconst (and not
mark properly as __initdata), add the "const" keyword exactly there.

Note we need to update struct pistachio_mux too. On the other hand, the
clk core already counts with "const char *const" already.

[js] more explanatory commit message.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: Martin Liska <mliska@suse.cz>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Link: https://lore.kernel.org/r/20220920055838.22637-1-jslaby@suse.cz
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data

After commit 6a5898411159("clk: clk-npcm7xx: Remove unused static const tables
'npcm7xx_gates' and 'npcm7xx_divs_fx'"), no one use struct
npcm7xx_clk_gate_data and struct npcm7xx_clk_div_fixed_data, so remove them.

Signed-off-by: Yuan Can <yuancan@huawei.com>
Link: https://lore.kernel.org/r/20220927133931.104060-1-yuancan@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos

pipegmux and SuperSpeed are the proper spelling for those terms.

Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921153155.279182-1-ahalaney@redhat.com

clk: qcom: Add global clock controller driver for SM6375

Add support for the global clock controller found on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921001303.56151-3-konrad.dybcio@somainline.org

dt-bindings: clock: add SM6375 QCOM global clock bindings

Add device tree bindings for global clock controller for SM6375 SoCs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921001303.56151-2-konrad.dybcio@somainline.org

clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit

This is used on at least SM6375 and its variations.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921001303.56151-1-konrad.dybcio@somainline.org

clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs

The USB controllers on sc7280 do not retain the state when
the system goes into low power state and the GDSCs are
turned off. This results in the controllers reinitializing and
re-enumerating all the connected devices (resulting in additional
delay while coming out of suspend)
Fix this by updating the .pwrsts for the USB GDSCs so they only
transition to retention state in low power.
Since sc7280 only supports cx (parent of usb gdscs) Retention, there
are no cxcs offsets mentioned in order to support the Retention
state.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220920111517.10407-3-quic_rjendra@quicinc.com

clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc

The USB controller on sc7180 does not retain the state when
the system goes into low power state and the GDSC is
turned off. This results in the controller reinitializing and
re-enumerating all the connected devices (resulting in additional
delay while coming out of suspend)
Fix this by updating the .pwrsts for the USB GDSC so it only
transitions to retention state in low power.
Since sc7180 only supports cx (parent of usb gdsc) Retention, there
are no cxcs offsets mentioned in order to support the Retention
state.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220920111517.10407-2-quic_rjendra@quicinc.com

clk: qcom: gdsc: Fix the handling of PWRSTS_RET support

GDSCs cannot be transitioned into a Retention state in SW.
When either the RETAIN_MEM bit, or both the RETAIN_MEM and
RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW
takes care of retaining the memory/logic for the domain when
the parent domain transitions to power collapse/power off state.

On some platforms where the parent domains lowest power state
itself is Retention, just leaving the GDSC in ON (without any
RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition
it to Retention.

The existing logic handling the PWRSTS_RET seems to set the
RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified
but then explicitly turns the GDSC OFF as part of _gdsc_disable().
Fix that by leaving the GDSC in ON state.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220920111517.10407-1-quic_rjendra@quicinc.com

clk: qcom: Add SC8280XP GPU clock controller

Add driver for the GPU clock controller in the Qualcomm SC8280XP
platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[bjorn: Included kernel.h and lower-cased hex numbers]
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com

dt-bindings: clock: Add Qualcomm SC8280XP GPU binding

Add compatible for the Qualcomm SC8280XP GPU.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926173025.4747-2-quic_bjorande@quicinc.com

clk: qcom: smd: Add SM6375 clocks

Add support for controlling SMD RPM clocks on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921004458.151842-3-konrad.dybcio@somainline.org

dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG

Add the missing definition for the aforementioned clock.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921004458.151842-2-konrad.dybcio@somainline.org

dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375

Add a compatible for RPMCC on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921004458.151842-1-konrad.dybcio@somainline.org

clk: qcom: rpmhcc: add sdm670 clocks

The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in
SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail
to resolve a clock.

Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220920223734.151135-3-mailingradian@gmail.com

dt-bindings: clock: add rpmhcc bindings for sdm670

The Snapdragon 670 uses the RPMh mailbox for some clocks. Document its
support.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220920223734.151135-2-mailingradian@gmail.com

dt-bindings: clock: qcom,a53pll: replace maintainer

Emails to codeaurora.org bounce ("Recipient address rejected:
undeliverable address: No such user here.").

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220924081329.15141-1-krzysztof.kozlowski@linaro.org

clk: qcom: Merge alt alpha plls for qcm2260, sm6115

The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and
BRAMMO alpha pll offsets. Move these common offsets to the shared place
to avoid duplication. The new layouts have a suffix EVO similar to LUCID
and RIVIAN.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com

clk: qcom: gcc-sm6115: Move alpha pll bramo overrides

sm6115 uses a modified default and bramo alpha pll offsets. Put them in
the same place for consistency.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-3-iskren.chernev@gmail.com

clk: qcom: gcc-sm6115: Override default Alpha PLL regs

The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but
currently only BRAMMO ones are overridden. Override DEFAULT ones too.

A very similar thing is happening in gcc-qcm2290 driver.

Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmail.com

clk: qcom: Add support for Display Clock Controller on SM8450

Add support for the dispcc on Qualcomm SM8450 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-4-dmitry.baryshkov@linaro.org

clk: qcom: alpha-pll: add support for power off mode for lucid evo PLL

PLLs can be kept in standby (default configuration) or in off mode
when disabled during power collapse. Hence add support for pll
disable off mode for lucid evo PLL.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-3-dmitry.baryshkov@linaro.org

dt-bindings: clock: qcom: add bindings for dispcc on SM8450

Add device tree bindings for the display clock controller on Qualcomm
SM8450 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-2-dmitry.baryshkov@linaro.org

clk: qcom: Add display clock controller driver for SM6115

Add support for the display clock controller found in SM6115/SM4250
based devices. This clock controller feeds the Multimedia Display
SubSystem (MDSS).
This driver is based upon one submitted for QCM2290.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220911164635.182973-3-a39.skl@gmail.com

dt-bindings: clock: add QCOM SM6115 display clock bindings

Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM6115 SoC.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[bjorn: Minor fix of binding description]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220911164635.182973-2-a39.skl@gmail.com

clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSC

Enabling PCIe GDSC retention to ensure controller and its
dependent clocks won't go down during system suspend.
Update the .pwrsts for PCIe GDSC so it only transitions
to RET in low power.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1663669347-29308-6-git-send-email-quic_krichai@quicinc.com

clk: qcom: lpass: Fix lpass audiocc probe

Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe()
to avoid remapping of memory region for index 0, which is already
being done through qcom_cc_map().

Fixes: 7c6a6641c2 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280")
Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@baylibre.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1663673683-7018-1-git-send-email-quic_c_skakit@quicinc.com

clk: qcom: apss-ipq-pll: add support for IPQ8074

Add support for IPQ8074 since it uses the same PLL setup, however it uses
slightly different Alpha PLL config.

Alpha PLL config was obtained by dumping PLL registers from a running
device.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-7-robimarko@gmail.com

clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL config

Update the IPQ6018 Alpha PLL config to the latest one from the downstream
5.4 kernel[1].

This one should match the production SoC-s.

Tested on IPQ6018 CP01-C1 reference board.

[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-6-robimarko@gmail.com

clk: qcom: apss-ipq-pll: use OF match data for Alpha PLL config

Convert the driver to use OF match data for providing the Alpha PLL config
per compatible.
This is required for IPQ8074 support since it uses a different Alpha PLL
config.

While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make
it clear that it is for IPQ6018 only.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-5-robimarko@gmail.com

dt-bindings: clock: qcom,a53pll: add IPQ8074 compatible

Add IPQ8074 compatible to A53 PLL bindings.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-4-robimarko@gmail.com

clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as critical

While fixing up the driver I noticed that my IPQ8074 board was hanging
after CPUFreq switched the frequency during boot, WDT would eventually
reset it.

So mark apcs_alias0_core_clk as critical since its the clock feeding the
CPU cluster and must never be disabled.

Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-3-robimarko@gmail.com

clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src

While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
currently broken.

More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
clock.
However after debugging why it was always stuck at 800Mhz, it was figured
out that its not regmap_mux compatible at all.
It is a simple mux but it uses RCG2 register layout and control bits, so
utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
having to provide a dummy frequency table.

While we are here, use ARRAY_SIZE for number of parents.

Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.

Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com

clk: qcom: clk-rcg2: add rcg2 mux ops

An RCG may act as a mux that switch between 2 parents.
This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
the CPU cluster clock just switches between XO and the PLL that feeds it.

Add the required ops to add support for this special configuration and use
the generic mux function to determine the rate.

This way we dont have to keep a essentially dummy frequency table to use
RCG2 as a mux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com

clk: qcom: lcc-ipq806x: use ARRAY_SIZE for num_parents

Use ARRAY_SIZE for num_parents instead of raw number to prevent any
confusion/mistake.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220724182329.9891-4-ansuelsmth@gmail.com

clk: qcom: lcc-ipq806x: convert to parent data

Convert lcc-ipq806x driver to parent_data API.
Change parent_name for pll4 to pxo_board to prepare the future to
eventually drop the double pxo board clk.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220724182329.9891-3-ansuelsmth@gmail.com

clk: qcom: lcc-ipq806x: add reset definition

Add reset definition for lcc-ipq806x.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220724182329.9891-2-ansuelsmth@gmail.com

dt-bindings: clock: add pcm reset for ipq806x lcc

Add pcm reset define for ipq806x lcc.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220724182329.9891-1-ansuelsmth@gmail.com

clk: qcom: cpu-8996: use constant mask for pmux

Both pmux instances share the same width and shift. Specify the mask at
compile time to simplify functions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-7-dmitry.baryshkov@linaro.org

clk: qcom: cpu-8996: don't store parents in clk_cpu_8996_pmux

Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use
clk_hw_get_parent_by_index to fetch them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-6-dmitry.baryshkov@linaro.org

clk: qcom: cpu-8996: move ACD logic to clk_cpu_8996_pmux_determine_rate

Rather than telling everybody that we are using PLL as a parent (and
using ACD clock instead) properly select ACD as a pmux parent clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-5-dmitry.baryshkov@linaro.org

clk: qcom: cpu-8996: declare ACD clocks

To simplify the code, define 1:1 fixed factor clocks to represent the
ACD pmux parent.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-4-dmitry.baryshkov@linaro.org

clk: qcom: cpu-8996: switch to devm_clk_notifier_register

Switch to using devres-managed version of clk_notifier_register(). This
allows us to drop driver's remove() callback.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-3-dmitry.baryshkov@linaro.org

clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocks

Replace parent_names in PLLs, secondary muxes and primary muxes with
parent_data. For primary muxes there were never any *cl_pll_acd clocks,
so instead of adding them, put the primary PLLs in both PLL_INDEX and
ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when
setting parent since we always want ACD when using the primary PLLs.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
[DB: switch to parent_hws for pmux clocks]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-2-dmitry.baryshkov@linaro.org

dt-bindings: clock: qcom,msm8996-apcc: Fix clocks

The clocks currently listed in clocks and clock-names are the ones
supplied by this clock controller, not the ones it consumes. Replace
them with the only clock it consumes - the on-board oscillator (XO),
and make the properties required.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-6-y.oudjana@protonmail.com

clk: qcom: msm8996-cpu: Convert secondary muxes to clk_regmap_mux

There is nothing special about the secondary muxes, unlike the
primary muxes which need some extra logic to handle ACD and
switching between primary PLL and secondary mux sources. Turn
them into clk_regmap_mux and rename cpu_clk_msm8996_mux into
cpu_clk_msm8996_pmux to make it specific to primary muxes.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-5-y.oudjana@protonmail.com

clk: qcom: msm8996-cpu: Unify cluster order

The power cluster comes before the performance cluster. Make
everything in the driver follow this order.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-4-y.oudjana@protonmail.com

clk: qcom: msm8996-cpu: Statically define PLL dividers

This will allow for adding them to clk_parent_data arrays
in an upcoming patch.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-3-y.oudjana@protonmail.com

clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX

The parent at this index is the secondary mux, which can connect
not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX
to better reflect the parent.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-2-y.oudjana@protonmail.com

clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe

Register gates with dev in mtk_clk_simple_probe.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220813083319.45455-1-y.oudjana@protonmail.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: gate: Export mtk_clk_register_gates_with_dev

This allows it to be used in drivers built as modules.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220813083249.45427-1-y.oudjana@protonmail.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: add VDOSYS1 clock

Add the clock gate definition for the DPI1 hardware
in VDOSYS1.

The parent clock "hdmi_txpll" is already defined in
`mt8195.dtsi`.

Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220919-v1-2-4844816c9808@baylibre.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

dt-bindings: clk: mediatek: Add MT8195 DPI clocks

Expand dt-bindings slot for VDOSYS1 of MT8195.
This clock is required by the DPI1 hardware
and is a downstream of the HDMI pixel clock.

Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220919-v1-1-4844816c9808@baylibre.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt8192: add mtk_clk_simple_remove

mt8192 is already using mtk_clk_simple_probe,
but not mtk_clk_simple_remove.

Let's add mtk_clk_simple_remove for mt8192.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220922091841.4099-8-miles.chen@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver

mtk_clk_simple_probe was added by Chun-Jie to simply common flow
of MediaTek clock drivers and ChenYu enhanced the error path of
mtk_clk_simple_probe and added mtk_clk_simple_remove.

Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other
MediaTek clock drivers as well.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220922091841.4099-7-miles.chen@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver

mtk_clk_simple_probe was added by Chun-Jie to simply common flow
of MediaTek clock drivers and ChenYu enhanced the error path of
mtk_clk_simple_probe and added mtk_clk_simple_remove.

Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other
MediaTek clock drivers as well.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220922091841.4099-6-miles.chen@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driver

mtk_clk_simple_probe was added by Chun-Jie to simply common flow
of MediaTek clock drivers and ChenYu enhanced the error path of
mtk_clk_simple_probe and added mtk_clk_simple_remove.

Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other
MediaTek clock drivers as well.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220922091841.4099-5-miles.chen@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

clk: mediatek: mt6765: use mtk_clk_simple_probe to simplify driver

mtk_clk_simple_probe was added by Chun-Jie to simply common flow
of MediaTek clock drivers and ChenYu enhanced the error path of
mtk_clk_simple_probe and added mtk_clk_simple_remove.

Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other
MediaTek clock drivers as well.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220922091841.4099-4-miles.chen@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>