Marek Olšák [Mon, 29 Aug 2022 04:21:44 +0000 (00:21 -0400)]
ac/surface: disallow 256KB swizzle modes on gfx11 APUs
It doesn't work.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18340>
Marek Olšák [Mon, 29 Aug 2022 00:50:42 +0000 (20:50 -0400)]
ac/gpu_info: handle LPDDR4 and 5 in ac_memory_ops_per_clock
and update amdgpu_drm.h
Fixes:
50238f495869ce5 - amd/common: Remove redundant code for determining memory ops per clock
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7163
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18340>
Erik Faye-Lund [Mon, 29 Aug 2022 13:50:54 +0000 (15:50 +0200)]
zink: clamp miplodbias when creating sampler
The Vulkan spec states that it's illegal to pass a mipLodBias larger
than maxSamplerLodBias, but the gallium value here hasn't been clamped.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7140
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18295>
Lionel Landwerlin [Fri, 2 Sep 2022 10:32:22 +0000 (13:32 +0300)]
hasvk: expose VK_EXT_depth_clamp_zero_one
Simple enough to expose on hasvk.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18372>
Lionel Landwerlin [Fri, 2 Sep 2022 10:30:40 +0000 (13:30 +0300)]
anv: enable EXT_depth_clamp_zero_one
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18372>
Iago Toral Quiroga [Fri, 2 Sep 2022 09:32:59 +0000 (11:32 +0200)]
v3dv: switch to common code for command buffer lifecycles
This gives us the capacity to recycle command buffers in the pool.
Based on a similar change done by Jason to Anvil.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18388>
Max Kellermann [Mon, 22 Aug 2022 18:11:18 +0000 (20:11 +0200)]
gallium/u_threaded: fix offset calculation for draw_multi slots
This fixes a buffer corruption bug with glMultiDrawElementsEXT(): the
offset for the source index buffer is reset for each draw_multi slot,
copying only the first `dr` values to each slot's index buffer.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18189>
Max Kellermann [Mon, 22 Aug 2022 18:10:46 +0000 (20:10 +0200)]
gallium/u_threaded: add missing reference counts for draw_multi slots
If a glMultiDrawElementsEXT() call doesn't fit into a single slot, the
same pipe_resource pointer is copied into all following slots, the
completion of each will decrement the reference counter; however, it
was never incremented for all but the first slot.
This fixes a use-after-free bug with glMultiDrawElementsEXT().
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18189>
M Henning [Sun, 12 Dec 2021 02:44:27 +0000 (21:44 -0500)]
nv/nir: Set ssbo CacheMode from intrinsic access
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18354>
Alyssa Rosenzweig [Sun, 12 Jun 2022 13:49:24 +0000 (09:49 -0400)]
asahi: Identify stencil test enable
There are a pair of flags controlling the stencil test. One enables
stencil testing in general, the other enables two-sided stencil. Compare
the identical "twosided" flag in src/imagination/csbgen/rogue_ppp.xml's
STATE_ISPCTL structure, at the samebit offset even. Evidently this word of
the "Rasterizer" is, in fact, a derivative of STATE_ISPCTL.
Fixes
dEQP-GLES2.functional.fragment_ops.depth_stencil.*
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.*
dEQP-GLES2.functional.fragment_ops.random.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sun, 15 May 2022 17:22:08 +0000 (13:22 -0400)]
asahi: Fix depth/stencil buffers
There are a bunch of bits we need to set right to get depth/stencil
loads/stores working, including with independent settings for each. The
kernel "helps" us here.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 21:06:09 +0000 (17:06 -0400)]
asahi: Handle out-of-bounds clear_stencil
Just use the bottom 8-bits (we have only 8-bit stencil formats),
otherwise we fail an assertion in GenXML. In this case the wrapping
behaviour is ok.
Fixes:
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil
dEQP-GLES2.functional.depth_stencil_clear.stencil
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 19:02:20 +0000 (15:02 -0400)]
asahi: Add 1D and 1D Array enums
To finish out the enum.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 18:01:03 +0000 (14:01 -0400)]
asahi: Correct SET_SHADER_EXTENDED disambig bit
This is still a guess, but a considerably firmer one as it now corrects
handles the clear pipelines emitted by Metal as well as the regular
vertex/fragment shader, and gets rid of the preshader special cases
seen there. Fixes decode of clear pipeline's preshaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 15:53:46 +0000 (11:53 -0400)]
asahi: Identify and use first level field of texture
As we recently discovered, the layout of level L of a mipmapped 2D image
of size WxH is /not/ the same as the layout of a non-mipmapped 2D image
of size minify(W, L) x minify(H, L). The difference occurs due to
subtleties of the "power of two" miptrees which can force a level to use
a larger tile size than it would have required at root level. To handle
this quirk correctly, the driver must not implement texture views with
address arithmetic -- it must supply instead the base width/height of a
texture and use first/last level fields on the texture descriptor to map
it. Similar issues occur when writing a particular level of a mipmapped
texture, which was handled correctly in the colour case but not the Z/S
case.
Fixes
dEQP-GLES2.functional.texture.mipmap.cube.generate.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 03:19:54 +0000 (23:19 -0400)]
asahi: Fix "stride" for tiled textures
It doesn't exist, but there's a count of mip levels for writeable image
descs. Setting that appropriately matters at high mip levels.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 02:39:07 +0000 (22:39 -0400)]
asahi: Fix nonmipmapped array textures
pot_level can be greater than the number of levels actually included --
don't overallocate. Fix the issue and add a representative unit test.
Fixes:
dEQP-GLES2.functional.texture.size.cube.512x512_rgb888
Fixes:
6ff75da8aa4 ("ail: Introduce image layout module")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 02:23:05 +0000 (22:23 -0400)]
asahi: Fix depth for cube maps
For cube maps, depth=1 in the hardware (but 6 in Gallium). Likewise for
cube map arrays, depth=n in the hardware (but 6n in Gallium). We need to
divide to compensate. This will be relevant for cube map arrays in the
future -- add the dimension XML for cube map arrays too.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 17 Jun 2022 03:30:29 +0000 (23:30 -0400)]
asahi: Label batch flush reasons
This was helpful in identifying the bottleneck in Inochi2D (the clears).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Wed, 10 Aug 2022 01:53:59 +0000 (21:53 -0400)]
asahi: Relax assert in decoder
Seen == 0x8 with >4 render targets.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Mon, 23 May 2022 16:35:39 +0000 (12:35 -0400)]
asahi: Trim garbage at end of set shader
Unfortunately the actual size of this data structure is unclear.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 17 Jun 2022 03:29:18 +0000 (23:29 -0400)]
asahi: Use util_blitter_clear
To avoid flush, use util_blitter_clear to clear with rectangles when
there is already content in the scene. This ~doubles the performance of
Inochi2D, which does frequent stencil clears in the middle of the screen
to implement masking.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Thu, 1 Sep 2022 21:44:02 +0000 (17:44 -0400)]
asahi: Handle empty fragment shaders
When an empty fragment shader is used with Metal, the stop command is
still included but this special bit is set, suppressing tilebuffer
access. Failing to do so but using empty shaders for u_blitter depth
clears causes Glitch Lina:
https://twitter.com/LinaAsahi/status/
1537869064793575424
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 17 Jun 2022 03:10:06 +0000 (23:10 -0400)]
asahi: Export agx_blitter_save
So we can use it for clears.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 17 Jun 2022 03:08:48 +0000 (23:08 -0400)]
asahi: Make ctx->zs a pointer
When we save ZSA state with u_blitter, u_blitter just records the
pointer for the state. It doesn't copy it. That requires an extra
indirection on the context (as other drivers do) to fix restores of ZSA
state with u_blitter.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Thu, 2 Jun 2022 00:43:54 +0000 (20:43 -0400)]
asahi: Note some more unknowns in the XML
Lot of r/e waiting here...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Mon, 23 May 2022 17:13:16 +0000 (13:13 -0400)]
asahi: Split up unk 2b
Seems to be flags.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Thu, 1 Sep 2022 22:20:38 +0000 (18:20 -0400)]
asahi: Fix Indexed Draw command
Add the missing stub in the decoder for it, so we can decode indexed
draws instead of reading back garbage, and fill in some known unknowns
in the structure.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 19:31:15 +0000 (15:31 -0400)]
agx: Plumb through nir_op_txf
nir_op_txf maps to AGX's texture_load, which is encoded like
texture_sample. The one outstanding question with this commit is the
rules for the sample required ... in NIR and APIs (including Metal), txf
is samplerless, but the AGX instruction consumes a sampler. Hopefully
any sampler will do, though?
Passes dEQP-GLES3.functional.shaders.texture_functions.texelfetch.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 2 Sep 2022 03:08:26 +0000 (23:08 -0400)]
agx: Defeature indirect vbufs
vb_mask can include garbage vbufs, we can't rely on it. This will
prevent a regression when switching to u_blitter based clears. This is
also simpler and shrinks the VS shader key so all in all a good thing.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 2 Sep 2022 03:01:51 +0000 (23:01 -0400)]
agx: Don't hardcode uniform enums
Let the compiler number them for us, the numbers are meaningless.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 02:51:47 +0000 (22:51 -0400)]
agx: Add more unit tests for float copyprop
Would have caught the bug fixed by the previous commit.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Sat, 3 Sep 2022 02:53:59 +0000 (22:53 -0400)]
agx: Fix float copyprop of neg(neg) case
They should cancel each other. Fixes:
dEQP-GLES2.functional.shaders.random.basic_expression.combined.0
Fixes:
28801b48493 ("agx: Add forward optimizing pass for fmov")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
Alyssa Rosenzweig [Fri, 2 Sep 2022 00:55:30 +0000 (20:55 -0400)]
agx: Fix tib access in internal shaders
The only case where tilebuffer access can be specially optimized is the
st_tile used in internal clear (or reload) shaders. However, other
shaders (like those used with u_blitter) may have nir->info.internal
set, so we can't key off that. Instead, add a special key for this
optimization to ensure correctness with other internal shaders.
Fixes flaky tests in dEQP-GLES2.functional.color_clear.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
David Heidelberg [Sat, 3 Sep 2022 20:27:51 +0000 (22:27 +0200)]
ci: set venus on lavapipe to manual due to flakes
Flakes too often, see https://gitlab.freedesktop.org/mesa/mesa/-/issues/7093
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18405>
Christian Gmeiner [Sat, 3 Sep 2022 09:35:00 +0000 (11:35 +0200)]
isaspec: Move isa_decode(..) declaration
The implementation of isa_decode(..) is already part of isaspec. So lets
move the function declaration and some related structs to a src/isaspec.
Also make the header C++ safe.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18403>
Matt Coster [Thu, 1 Sep 2022 11:24:50 +0000 (12:24 +0100)]
util: Include stddef.h in util/macros.h
This is required for offsetof, used by the container_of macro.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18368>
Thomas H.P. Andersen [Sat, 3 Sep 2022 11:22:52 +0000 (13:22 +0200)]
ci: remove missing-braces from no-error
The last warnings for missing-braces were fixed in !18307
Remove it from the no-error list on the clang build to catch regressions
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18404>
Jason Ekstrand [Sat, 20 Aug 2022 17:57:06 +0000 (12:57 -0500)]
vulkan: Dirty VP_VIEWPORTS/SCISSORS when copying viewports/scissors
The only reason why we didn't notice before is because ANV always
re-emits all scissors and viewports if the count changes.
Fixes:
fcedb1250bb8 ("vulkan: Add a common data structure for dynamic states")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18160>
Mihai Preda [Wed, 24 Aug 2022 11:22:07 +0000 (14:22 +0300)]
gallivm: fixes for LLVM-15 opaque pointers in lp_bld_format_soa.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Mon, 22 Aug 2022 13:34:30 +0000 (16:34 +0300)]
gallivm: fixes for LLVM-15 opaque pointers in lp_bld_struct.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Sat, 20 Aug 2022 10:50:04 +0000 (13:50 +0300)]
gallivm: fixes for LLVM-15 opaque pointers in lp_bld_format_s3tc.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Tue, 16 Aug 2022 19:55:47 +0000 (22:55 +0300)]
gallivm: fixes for LLVM-15 opaque pointers in lp_bld_jit_types.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Tue, 26 Jul 2022 13:02:52 +0000 (16:02 +0300)]
gallivm: fixes for LLVM-15 opaque pointers in lp_bld_nir_soa.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Tue, 26 Jul 2022 12:43:30 +0000 (15:43 +0300)]
gallivm: fixes for LLVM-15 opaque pointers in lp_bld_nir_aos.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Tue, 16 Aug 2022 08:11:24 +0000 (11:11 +0300)]
gallium: drop unused macros in draw_llvm.h
The reason is that these macros use lp_build_struct_get(), which is
being replaced by lp_build_structure_get2() which takes the explicit
pointer type. Rather than attempt to update these unused macros, simply drop
them.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Tue, 16 Aug 2022 06:44:53 +0000 (09:44 +0300)]
gallivm: drop unused "emit_load" in lp_llvm_buffer_member()
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Mihai Preda [Fri, 19 Aug 2022 08:56:35 +0000 (11:56 +0300)]
gallivm: LLVM-15 opaque pointers: disable LLVMGetElementType(ptr_type)
with opaque pointers, we can't query the element type of a pointer type
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18334>
Roland Scheidegger [Sat, 27 Aug 2022 03:26:34 +0000 (05:26 +0200)]
llvmpipe: fix front/back face system value in the fs
draw needs to inject the face information for tris in line/point fill
mode since llvmpipe only sees lines and points. But for the new style
face information (which is a system value and not an ordinary input
register) we forgot to tell draw.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18285>
Lionel Landwerlin [Fri, 2 Sep 2022 21:24:40 +0000 (00:24 +0300)]
vulkan: fixup 1.3.226 update
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18397>
Lionel Landwerlin [Fri, 2 Sep 2022 21:31:07 +0000 (00:31 +0300)]
anv: remove non present field in upstream spec
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18397>
Dawn Han [Wed, 31 Aug 2022 18:02:20 +0000 (18:02 +0000)]
Enable .VALVE_mutable_descriptor_type in physical_device
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17505>
Dawn Han [Wed, 3 Aug 2022 05:40:20 +0000 (05:40 +0000)]
Track bitset when create descriptor pool
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17505>
Dawn Han [Wed, 3 Aug 2022 05:25:59 +0000 (05:25 +0000)]
Update bitset when init descriptor layout.
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17505>
Dawn Han [Mon, 11 Jul 2022 22:42:35 +0000 (22:42 +0000)]
Increase enum type in vn_descriptor_set.
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17505>
David Heidelberg [Tue, 30 Aug 2022 09:40:17 +0000 (11:40 +0200)]
ci: uprev piglit 2022-08-30
Acked-by: Juan A. Suarez <jasuarez@igalia.com> # for broadcom
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> # for zink
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18318>
Chia-I Wu [Fri, 2 Sep 2022 18:26:05 +0000 (11:26 -0700)]
util/perf: use ALWAYS_INLINE for tracepoints
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
Chia-I Wu [Tue, 30 Aug 2022 00:25:15 +0000 (17:25 -0700)]
util/perf: simplify u_trace_instrument
When ut_perfetto_enabled changes, update _u_trace_instrument as well.
This allows u_trace_instrument to check just a single variable.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
Chia-I Wu [Mon, 29 Aug 2022 23:38:30 +0000 (16:38 -0700)]
util/perf: add u_trace_instrument
It is called from tracepoints. When it returns false, instrumentation
is disabled.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
Chia-I Wu [Mon, 29 Aug 2022 23:46:57 +0000 (16:46 -0700)]
util/perf: remove u_trace::enabled
We can set ut_trace_instrument when either GPU_TRACE or
GPU_TRACE_INSTRUMENT is set. This results in one less variable to check
in tracepoints.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
Chia-I Wu [Tue, 30 Aug 2022 00:01:17 +0000 (17:01 -0700)]
util/perf: ignore ut->enabled for iterators
With perfetto, instrumentation can be enabled in the middle of cmd
buffer recording even when ut->enabled is false. It might be better to
be consistent and ignore ut->enabled for iterators.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
Mike Blumenkrantz [Mon, 22 Aug 2022 14:48:45 +0000 (10:48 -0400)]
mesa: add GLSL_SOURCE
many times I just want to dump glsl and not a trillion lines of IR
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18280>
Marcin Ślusarz [Sat, 30 Apr 2022 11:10:22 +0000 (13:10 +0200)]
anv: enable EXT_mesh_shader
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
Marcin Ślusarz [Sat, 30 Apr 2022 11:09:53 +0000 (13:09 +0200)]
anv: implement draw calls for EXT_mesh_shader
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
Marcin Ślusarz [Sat, 30 Apr 2022 11:07:57 +0000 (13:07 +0200)]
anv: implement EXT_mesh_shader
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
Marcin Ślusarz [Sun, 8 May 2022 00:24:48 +0000 (02:24 +0200)]
anv: replace VK_SHADER_STAGE_[TASK|MESH]_BIT_NV with VK_SHADER_STAGE_[TASK|MESH]_BIT_EXT
They have the same numerical values, so nothing changes.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
Marcin Ślusarz [Sun, 8 May 2022 00:19:35 +0000 (02:19 +0200)]
anv: check EXT_mesh_shader whenever NV_mesh_shader is checked
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
Marcin Ślusarz [Sat, 30 Apr 2022 11:06:42 +0000 (13:06 +0200)]
intel/compiler: implement EXT_mesh_shader
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
Emma Anholt [Wed, 24 Aug 2022 22:34:26 +0000 (15:34 -0700)]
turnip: Treating non-d/s-write pipelines as not having d/s feedback loops.
A subpass in gfxbench has the depth buffer present, but not written to,
for a render pass using the depth buffer as an input attachment. We can
skip single-prim-mode and the associated "oh no don't use sysmem" in that
case.
Improves gfxbench vk-5-normal perf by 1.56193% +/- 0.0743035% (n=14).
Part of #6327.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18241>
Marcin Ślusarz [Tue, 7 Jun 2022 11:03:24 +0000 (13:03 +0200)]
spirv, compiler: add "bool nv" to shader_info.mesh
Not knowing whether we deal with the NV or EXT extension
makes implementation difficult for Intel HW.
NV support will be dropped at some point, so
this ugliness will go away eventually.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Sat, 19 Feb 2022 11:37:06 +0000 (12:37 +0100)]
spirv, nir: Handle EmitMeshTasksEXT opcode.
A task shader must use this instruction to specify the dimensions
of the launched mesh shader workgroups.
It is a terminating instruction.
When the task shader doesn't have the optional payload, use the
pre-existing launch_mesh_workgroups intrinsics.
When the task shader has a payload, use a new
launch_mesh_workgroups_with_payload_deref intrinsics which has
a deref that refers to the payload variable.
We also add this new intrinsic to nir_lower_io which lowers this
to the pre-existing explicit intrinsic.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Sat, 19 Feb 2022 11:31:18 +0000 (12:31 +0100)]
spirv: Support TaskPayloadWorkgroupEXT storage class.
Just use the task_payload NIR storage class for this.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Fri, 21 Jan 2022 18:38:13 +0000 (19:38 +0100)]
spirv: Support the CullPrimitiveEXT mesh shader built-in.
This is a per-primitive builtin output which indicates that a
primitive should be culled (deleted) from the output.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Thu, 20 Jan 2022 15:35:23 +0000 (16:35 +0100)]
spirv: Support EXT_mesh_shader SetMeshOutputsEXT.
Use the set_vertex_and_primitive_count intrinsic to
express the number of vertices and primitives that the
mesh shader workgroup outputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Thu, 20 Jan 2022 15:35:01 +0000 (16:35 +0100)]
spirv: Support EXT_mesh_shader mesh/task stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Thu, 20 Jan 2022 15:34:37 +0000 (16:34 +0100)]
spirv: Add mesh_shading capability for EXT_mesh_shader.
Indicates support for the EXT_mesh_shader SPIR-V capabilities.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Thu, 20 Jan 2022 15:33:27 +0000 (16:33 +0100)]
spirv: Support EXT_mesh_shader indices and mark them per-primitive.
They are not defined as per-primitive in the EXT, but they behave
like per-primitive outputs so it's easier to treat them like that.
They may still require special treatment in the backend in order to
control where and how they are stored.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Timur Kristóf [Fri, 2 Sep 2022 07:38:15 +0000 (09:38 +0200)]
vulkan, spirv: Update to Vulkan 1.3.226 and latest SPIR-V headers.
Done using the "khronos-update.py" script, leaving out parts that
are not relevant to Vulkan.
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Alyssa Rosenzweig [Thu, 28 Jul 2022 15:07:46 +0000 (11:07 -0400)]
pan/bi: Add and use bi_num_successors helper
Makes a few patterns easier to read.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 17:35:34 +0000 (13:35 -0400)]
pan/bi: Add and use bi_replace_src helper
This is a common pattern. Make it more ergonomic. With the help of Coccinelle:
@@
expression E;
expression R;
expression instruction;
@@
-instruction->src[E] = bi_replace_index(instruction->src[E], R);
+bi_replace_src(instruction, E, R);
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 16:27:27 +0000 (12:27 -0400)]
pan/bi: Remove assert(bi_is_ssa(dest))
Prior to register allocation, destinations must be in SSA form, except for the
"fake SSA" briefly used in the current RA (for which bi_is_ssa returns true
anyway). These asserts duplicate the asserts in the validator. If there's any
coverage lost here, that's just a sign the validator needs to run more often.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 16:25:19 +0000 (12:25 -0400)]
pan/bi: Strengenth assert in the validator
We should only see SSA now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 16:22:34 +0000 (12:22 -0400)]
pan/bi: Add and use bi_foreach_ssa_src macro
Frequently, we want to iterate over the SSA variables read by an instruction,
while skipping over constants and uniforms. Add and use a macro for this
pattern. A few redundant asserts are removed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 15:52:29 +0000 (11:52 -0400)]
pan/bi: Simplify bi_get_index prototype
2/3 of its arguments are now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 20:05:22 +0000 (16:05 -0400)]
pan/bi: Remove bi_max_temp
This is no longer needed given the flat indexing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 20:03:08 +0000 (16:03 -0400)]
pan/bi: Inline node_to_index
One user, now trivial.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 20:02:03 +0000 (16:02 -0400)]
pan/bi: Get rid of bi_get_node
Now that variables have flat naming (no more SSA/reg distinction), we can just
use .value directly. This cleans up the RA a bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 20:48:53 +0000 (16:48 -0400)]
pan/bi: Remove NIR registers from the IR
They are now unused, so normal == SSA at this point.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:19:01 +0000 (15:19 -0400)]
pan/bi: Move non-SSA liveness into RA
Now that non-SSA nodes are an internal implementation detail of RA, the
entrypoints should be made private to make sure no other passes use the
RA-specific liveness analysis.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:14:52 +0000 (15:14 -0400)]
pan/bi: Assume SSA for helper invocation analysis
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:13:07 +0000 (15:13 -0400)]
pan/bi: Assume SSA when translating NIR
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:11:25 +0000 (15:11 -0400)]
pan/bi: Assume SSA when scheduling for pressure
This is much simpler now: entire hazards become impossible when the program is
kept in SSA form.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:05:41 +0000 (15:05 -0400)]
pan/bi: Assume SSA in minor passes
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:04:59 +0000 (15:04 -0400)]
pan/bi: Assume non-null sources in constant folding
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:03:36 +0000 (15:03 -0400)]
pan/bi: Assume SSA in CSE
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:01:46 +0000 (15:01 -0400)]
pan/bi: Assume SSA in mod prop
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 25 Jul 2022 19:00:39 +0000 (15:00 -0400)]
pan/bi: Assume SSA in copyprop
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 14:22:14 +0000 (10:22 -0400)]
pan/bi: Don't use bi_temp_reg
We've already broken SSA irreparably at this point. We can just change what
"normal" means and avoid the disjointed indexing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Tue, 26 Jul 2022 14:09:06 +0000 (10:09 -0400)]
pan/bi: Clear reg in squeeze_index
SSA is broken at this point. Let's not pretend otherwise. The numbering produced
by squeeze_index already disambiguates what-used-to-be SSA variables and
registers. A few shader-db changes because this shuffles the register allocation
around because LCRA is stupid.
total instructions in shared programs: 2658849 -> 2650196 (-0.33%)
instructions in affected programs: 463733 -> 455080 (-1.87%)
helped: 1089
HURT: 135
helped stats (abs) min: 1.0 max: 43.0 x̄: 8.20 x̃: 5
helped stats (rel) min: 0.11% max: 17.05% x̄: 2.28% x̃: 1.52%
HURT stats (abs) min: 1.0 max: 7.0 x̄: 2.07 x̃: 2
HURT stats (rel) min: 0.10% max: 2.97% x̄: 1.03% x̃: 0.83%
95% mean confidence interval for instructions value: -7.52 -6.62
95% mean confidence interval for instructions %-change: -2.04% -1.78%
Instructions are helped.
total cycles in shared programs: 140617.52 -> 140613.14 (<.01%)
cycles in affected programs: 227.45 -> 223.08 (-1.92%)
helped: 45
HURT: 1
helped stats (abs) min: 0.015625 max: 0.4375 x̄: 0.10 x̃: 0
helped stats (rel) min: 0.43% max: 17.72% x̄: 2.79% x̃: 1.29%
HURT stats (abs) min: 0.015625 max: 0.015625 x̄: 0.02 x̃: 0
HURT stats (rel) min: 1.47% max: 1.47% x̄: 1.47% x̃: 1.47%
95% mean confidence interval for cycles value: -0.12 -0.07
95% mean confidence interval for cycles %-change: -3.76% -1.64%
Cycles are helped.
total cvt in shared programs: 13877.61 -> 13742.41 (-0.97%)
cvt in affected programs: 3432 -> 3296.80 (-3.94%)
helped: 1089
HURT: 135
helped stats (abs) min: 0.015625 max: 0.671875 x̄: 0.13 x̃: 0
helped stats (rel) min: 0.18% max: 28.36% x̄: 5.05% x̃: 3.38%
HURT stats (abs) min: 0.015625 max: 0.109375 x̄: 0.03 x̃: 0
HURT stats (rel) min: 0.15% max: 8.33% x̄: 2.87% x̃: 2.27%
95% mean confidence interval for cvt value: -0.12 -0.10
95% mean confidence interval for cvt %-change: -4.46% -3.88%
Cvt are helped.
total quadwords in shared programs: 1442328 -> 1437776 (-0.32%)
quadwords in affected programs: 106240 -> 101688 (-4.28%)
helped: 478
HURT: 17
helped stats (abs) min: 8.0 max: 24.0 x̄: 9.81 x̃: 8
helped stats (rel) min: 1.54% max: 20.00% x̄: 5.27% x̃: 3.70%
HURT stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel) min: 1.61% max: 14.29% x̄: 6.42% x̃: 6.25%
95% mean confidence interval for quadwords value: -9.61 -8.78
95% mean confidence interval for quadwords %-change: -5.20% -4.54%
Quadwords are helped.
total threads in shared programs: 53557 -> 53550 (-0.01%)
threads in affected programs: 14 -> 7 (-50.00%)
helped: 0
HURT: 7
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Alyssa Rosenzweig [Mon, 16 May 2022 23:51:03 +0000 (19:51 -0400)]
pan/bi: Clean up after converting to SSA
nir_invalidate_divergence was introduced in
aa765c54bdd ("pan/bi: Add divergent
intrinsic lowering pass"), which needed divergence information for a late NIR
pass but not otherwise in the backend. Unfortunately, nir_convert_from_ssa is
less aggressive about coalescing when divergence information makes it look like
the coalescing would make the code worse -- even though that's not actually an
issue on Mali.
Now that we don't use nir_convert_from_ssa, we don't need the hack.
Likewise for the vec.reg hack, which was introduced because the split/collect
cache relies on SSA form.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>