Erik Faye-Lund [Tue, 6 Jun 2023 11:56:18 +0000 (13:56 +0200)]
nir: add missed nir_cmp_imm-helpers
Seems I missed these in my previous round, let's fix them up now!
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Erik Faye-Lund [Mon, 5 Jun 2023 13:31:47 +0000 (15:31 +0200)]
nir: add and use nir_imod_imm
Just a short-hand, really. Makes the code a bit easier to read.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Erik Faye-Lund [Mon, 5 Jun 2023 13:15:21 +0000 (15:15 +0200)]
nir: add and use nir_fdiv_imm
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Erik Faye-Lund [Mon, 5 Jun 2023 12:54:54 +0000 (14:54 +0200)]
nir: use nir_imm_{true,false}
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Erik Faye-Lund [Mon, 5 Jun 2023 10:41:14 +0000 (12:41 +0200)]
nir: isub -> iadd_imm
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Erik Faye-Lund [Mon, 5 Jun 2023 10:36:39 +0000 (12:36 +0200)]
nir: use more imm-helpers
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Erik Faye-Lund [Mon, 5 Jun 2023 10:20:36 +0000 (12:20 +0200)]
mesa/st: use nir_imm_vec4
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
Alyssa Rosenzweig [Mon, 12 Jun 2023 22:00:39 +0000 (18:00 -0400)]
iris: Don't use STREAMING_LOAD without SSE
isl will assert out otherwise. Hit this with intel_stub_gpu on arm64, but it is
a legitimate bug since someone might plug a DG2 card into a workstation-grade
arm64 or ppc64 supporting PCIe (it exists).
This forward ports the logic from crocus, which checks for both SSE at a
compile-time level as well as in the CPU caps. This might be excessive since DG2
cards apparently wouldn't work properly on old non-SSE x86 boxes anyway? I just
crocus-and-pasted.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23608>
Mike Blumenkrantz [Wed, 14 Jun 2023 15:34:28 +0000 (11:34 -0400)]
dri3: only invalidate drawables on geometry change if geometry has changed
this is otherwise pointless
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23649>
Erik Faye-Lund [Fri, 2 Jun 2023 18:12:29 +0000 (20:12 +0200)]
nir: use new immediate comparison helpers
There's plenty of places we can use these new and shiny helpers, so
let's clean up the code a bit.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23460>
Erik Faye-Lund [Mon, 5 Jun 2023 08:19:58 +0000 (10:19 +0200)]
nir: add nir_[fui]gt_imm and nir_[fui]le_imm helpers
These are similar to the nir_{cmp}_imm variants we already have, except
they negate the condition (apart from equality) and flip the arguments.
The reason we need this, is that we don't have all comparison directions
that would be required to always pass the immediate in the second
argument.
This allows us to create any comparison with an immediate without
having to manually create the immediate value.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23460>
Rhys Perry [Wed, 14 Jun 2023 11:14:19 +0000 (12:14 +0100)]
ac: fix PIPE_FORMAT_R11G11B10_FLOAT DST_SEL_W
Previously, the W component would be incorrect for attributes using this
format when loaded in RADV's vertex shader prologs.
Fixes dEQP-VK.pipeline.fast_linked_library.vertex_input.*b10g11r11*missing_components*
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes:
6a2ada93b49 ("ac: add ac_vtx_format_info")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23645>
Luigi Santivetti [Mon, 5 Jun 2023 22:34:12 +0000 (23:34 +0100)]
pvr: fix division by block size in blit
dEQP-VK.pipeline.monolithic.image.suballocation.\
sampling_type.combined.view_type.2d.\
format.etc2_r8g8b8_unorm_block.count_1.size.13x13
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23591>
Karmjit Mahil [Tue, 13 Jun 2023 10:46:20 +0000 (11:46 +0100)]
pvr: Remove outdated finishme
The color attachment load is being handled just below the finishme.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23619>
Karmjit Mahil [Fri, 10 Feb 2023 16:00:04 +0000 (16:00 +0000)]
pvr: Dedup a check with pvr_is_render_area_tile_aligned()
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22657>
Gert Wollny [Thu, 15 Jun 2023 05:55:45 +0000 (07:55 +0200)]
r600/sfn: Downgrade some error message to warning
This doesn't seem to be an error, so just print a warning when
warnings are enabled.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23665>
Gert Wollny [Thu, 15 Jun 2023 05:54:27 +0000 (07:54 +0200)]
r600/sfn: Silence warnings "overloaded-virtual"
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23665>
Samuel Pitoiset [Mon, 12 Jun 2023 06:43:34 +0000 (08:43 +0200)]
radv: reset some dynamic states when the fragment shader stage is unbound
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23494>
Samuel Pitoiset [Mon, 12 Jun 2023 06:37:10 +0000 (08:37 +0200)]
radv: fix re-emitting early_z/late_z when the bound PS changes
This state depends on the fragment shader.
Fixes:
d740e283e16 ("radv: implement VK_EXT_attachment_feedback_loop_dynamic_state")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23494>
Samuel Pitoiset [Wed, 7 Jun 2023 08:26:38 +0000 (10:26 +0200)]
radv: fix re-emitting some dynamic states when the previous FS is NULL
If the previous FS is NULL, some dynamic states still need to be
re-emitted.
Doesn't fix anything known.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23494>
Christian Gmeiner [Wed, 14 Jun 2023 10:23:39 +0000 (12:23 +0200)]
mesa/arbprog: fix compile errors
When DEBUG_FP is set I see the following compiler errors:
../../src/gitlab_mesa/src/mesa/program/arbprogparse.c: In function '_mesa_parse_arb_fragment_program':
../../src/gitlab_mesa/src/mesa/program/arbprogparse.c:133:4: error: implicit declaration of function '_mesa_print_program'; did you mean '_mesa_parse_arb_program'? [-Werror=implicit-function-declaration]
133 | _mesa_print_program(&program->Base);
| ^~~~~~~~~~~~~~~~~~~
| _mesa_parse_arb_program
../../src/gitlab_mesa/src/mesa/program/arbprogparse.c:133:32: error: 'struct gl_program' has no member named 'Base'
133 | _mesa_print_program(&program->Base);
| ^~
cc1: some warnings being treated as errors
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23644>
Qiang Yu [Mon, 12 Jun 2023 09:50:50 +0000 (17:50 +0800)]
ac/nir/ngg: fix ngg_gs_clear_primflags crash
We get current_clear_primflag_idx_var==NULL when stream 0 output
number is known, so output_compile_time_known==true. But we also
need this variable when stream 1~3 output number is unknown or
vertex number is less than a primitive's needs.
Fixes:
60ac5dda82e1 ("ac: Add NIR lowering for NGG GS.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23614>
Mike Blumenkrantz [Tue, 13 Jun 2023 15:35:04 +0000 (11:35 -0400)]
zink: strip format list when disabling mutable during image creation
drivers shouldn't be getting a format list if it won't be used
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23514>
Mike Blumenkrantz [Wed, 14 Jun 2023 14:46:01 +0000 (10:46 -0400)]
zink: drop dt checks for mutable format init
these are no longer applicable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23514>
Mike Blumenkrantz [Wed, 7 Jun 2023 18:37:16 +0000 (14:37 -0400)]
zink: add srgb mutable for all resources by default
this should enable compression on more intermediate fb attachments
it also means that VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT can now be set
on images where ZINK_BIND_MUTABLE is not set, so non-resource APIs need
to check ZINK_BIND_MUTABLE
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23514>
Mike Blumenkrantz [Wed, 14 Jun 2023 12:49:57 +0000 (08:49 -0400)]
zink: wrap format mismatch checks for blit/surface
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23514>
Mike Blumenkrantz [Wed, 7 Jun 2023 21:02:35 +0000 (17:02 -0400)]
zink: remove redundant conditional in set_sampler_views
it's redundant, but it checks a different flag so it consumes cycles
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23514>
Caio Oliveira [Fri, 26 May 2023 21:05:28 +0000 (14:05 -0700)]
compiler/types: Use hash table pre-hashed functions for type caching
Calculate the hash outside the critical region, then use that both
for search and insertion.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23280>
Caio Oliveira [Sat, 27 May 2023 00:38:13 +0000 (17:38 -0700)]
compiler/types: Tidy up the asserts in get_*_instance functions
Use the local variable in the assertions, move them out the critical region.
No behavior change.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23279>
Caio Oliveira [Fri, 26 May 2023 20:43:05 +0000 (13:43 -0700)]
compiler/types: Be consistent when naming array element/size
The element type passed is different than the array type and it is not
a "base type" in the glsl_type sense, so pick a name that reflects that.
Also stick to a single name for the array_size.
Just renames, no behavior change.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23279>
Jesse Natalie [Tue, 13 Jun 2023 17:04:04 +0000 (10:04 -0700)]
nir_lower_returns: Mark assert-only var as ASSERTED
Fixes:
5d238c0c ("nir_lower_returns: Optimize phis before beginning the pass")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23634>
Dave Airlie [Wed, 14 Jun 2023 02:12:48 +0000 (12:12 +1000)]
radv/video: restrict the number of IBs on video related queues.
The hardware gets given a session context from userspace in each
submission, but if the session context changes the hardware wants
a FENCE to be emitted to know it can give up the current session.
IF a test submits interleaved session ctx access and uses a single
vulkan submit the hardware crashes, unless each IB is submitted
in a separate submission so the fence can be sent.
In theory it could be possible to construct a single command buffer
to trigger this so I do think the hardware should be smarter here.
Should this be fixed in the kernel to always emit a fence between
IBs?
Fixes: dEQP-VK.video.decode.h264_interleaved
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23641>
LingMan [Wed, 14 Jun 2023 07:02:53 +0000 (09:02 +0200)]
rusticl: fix UB in CLProp machinery
Viewing structs as a collection of u8 is not generally sound. Any padding bytes might be
uninitialized and creating an integer from uninitialized memory constitutes producing an invalid
value, which is instant UB.
Since we only copy these bytes around, the fix is to simply work with MaybeUninit<u8>, which can handle uninitialized memory just fine, instead.
See: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23652>
LingMan [Wed, 14 Jun 2023 02:53:19 +0000 (04:53 +0200)]
rusticl: drop cl_prop_for_type macro
There's no reason to differentiate between primitive types and structs here. `cl_prop_for_struct`
can handle primitive types just fine.
Drop `cl_prop_for_type` and rename the existing `cl_prop_for_struct` to `cl_prop_for_type`.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23652>
LingMan [Wed, 14 Jun 2023 06:16:40 +0000 (08:16 +0200)]
rusticl: drop CLProp implementation for String
Route the data to the implementation for &str instead. It works just as fine.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23652>
LingMan [Wed, 14 Jun 2023 05:56:50 +0000 (07:56 +0200)]
rusticl: core: stop using cl_prop from the api module
It's a layering violation and really the wrong tool for the job. Add a new fn to view a given slice
as a &[u8] instead of going though the clprop machinery which creates a new Vec.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23652>
Charmaine Lee [Wed, 14 Jun 2023 05:24:32 +0000 (08:24 +0300)]
svga: fix compute shader type after ntt
Reset compute shader type after ntt.
Fixes:
0ac95418048 ("gallium: Drop PIPE_SHADER_CAP_PREFERRED_IR")
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23659>
Karol Herbst [Wed, 14 Jun 2023 21:06:23 +0000 (23:06 +0200)]
rusticl: enforce using unsafe blocks in unsafe functions
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23660>
Mike Blumenkrantz [Tue, 13 Jun 2023 14:58:12 +0000 (10:58 -0400)]
zink: add mem debugging
modeled off turnip's debug infra, this adds debug printing for oom
scenarios
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23653>
Mike Blumenkrantz [Tue, 13 Jun 2023 14:45:38 +0000 (10:45 -0400)]
zink: break out vk flag unrolling into util function
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23653>
Ian Romanick [Tue, 31 Mar 2020 22:37:00 +0000 (15:37 -0700)]
nir/algebraic: Simplify various trivial bfi
These are mostly just obvious patterns that somebody will eventually
want to add.
DG2, Tiger Lake, Ice Lake, Skylake, Broadwell, and Haswell had similar
results (Ice Lake shown)
total instructions in shared programs:
20570033 ->
20570026 (<.01%)
instructions in affected programs: 7363 -> 7356 (-0.10%)
helped: 6 / HURT: 0
total cycles in shared programs:
902118781 ->
902118854 (<.01%)
cycles in affected programs: 419132 -> 419205 (0.02%)
helped: 4 / HURT: 2
DG2, Tiger Lake, Ice Lake, and Skylake had similar results (Ice Lake shown)
Totals:
Instrs:
152819500 ->
152819380 (-0.00%)
Cycles:
15014627187 ->
15014624437 (-0.00%)
Totals from 115 (0.02% of 662497) affected shaders:
Instrs: 28963 -> 28843 (-0.41%)
Cycles: 404582 -> 401832 (-0.68%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19968>
Ian Romanick [Tue, 26 Jul 2022 19:30:04 +0000 (12:30 -0700)]
nir/algebraic: Optimize some u2f of bfi
v2: Fix a copy-and-paste bug s/('find_lsb', a)/a/ in the patterns. See
piglit!819.
DG2, Tiger Lake, Ice Lake, Skylake, and Broadwell had similar results (Ice Lake shown)
total instructions in shared programs:
20570063 ->
20570033 (<.01%)
instructions in affected programs: 452 -> 422 (-6.64%)
helped: 30 / HURT: 0
total cycles in shared programs:
902118723 ->
902118781 (<.01%)
cycles in affected programs: 1762 -> 1820 (3.29%)
helped: 0 / HURT: 29
DG2, Tiger Lake, Ice Lake, and Skylake had similar results (Ice Lake shown)
Totals:
Instrs:
152819969 ->
152819500 (-0.00%)
Cycles:
15014628652 ->
15014627187 (-0.00%); split: -0.00%, +0.00%
Totals from 469 (0.07% of 662497) affected shaders:
Instrs: 7644 -> 7175 (-6.14%)
Cycles: 31787 -> 30322 (-4.61%); split: -4.90%, +0.29%
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19968>
Ian Romanick [Wed, 16 Nov 2022 21:12:50 +0000 (13:12 -0800)]
intel/fs: Emit better code for bfi(..., 0)
DG2, Tiger Lake, Ice Lake, and Skylake had similar results (Ice Lake shown)
total instructions in shared programs:
20570141 ->
20570063 (<.01%)
instructions in affected programs: 30679 -> 30601 (-0.25%)
helped: 77 / HURT: 0
total cycles in shared programs:
902113977 ->
902118723 (<.01%)
cycles in affected programs: 3255958 -> 3260704 (0.15%)
helped: 60 / HURT: 19
Broadwell
total instructions in shared programs:
18524633 ->
18524547 (<.01%)
instructions in affected programs: 34095 -> 34009 (-0.25%)
helped: 75 / HURT: 2
total cycles in shared programs:
949532394 ->
949543761 (<.01%)
cycles in affected programs: 3419107 -> 3430474 (0.33%)
helped: 57 / HURT: 24
total spills in shared programs: 22484 -> 22484 (0.00%)
spills in affected programs: 516 -> 516 (0.00%)
helped: 2 / HURT: 2
total fills in shared programs: 29346 -> 29338 (-0.03%)
fills in affected programs: 572 -> 564 (-1.40%)
helped: 4 / HURT: 0
Haswell
total instructions in shared programs:
17331356 ->
17331523 (<.01%)
instructions in affected programs: 27920 -> 28087 (0.60%)
helped: 41 / HURT: 4
total cycles in shared programs:
936603192 ->
936574664 (<.01%)
cycles in affected programs: 3417695 -> 3389167 (-0.83%)
helped: 28 / HURT: 21
total spills in shared programs: 19718 -> 19756 (0.19%)
spills in affected programs: 436 -> 474 (8.72%)
helped: 0 / HURT: 4
total fills in shared programs: 22547 -> 22607 (0.27%)
fills in affected programs: 444 -> 504 (13.51%)
helped: 0 / HURT: 4
Ivy Bridge
total cycles in shared programs:
463451277 ->
463451273 (<.01%)
cycles in affected programs: 95870 -> 95866 (<.01%)
helped: 3 / HURT: 2
DG2, Tiger Lake, Ice Lake, and Skylake had similar results (Ice Lake shown)
Totals:
Instrs:
152825278 ->
152819969 (-0.00%); split: -0.00%, +0.00%
Cycles:
15014075626 ->
15014628652 (+0.00%); split: -0.01%, +0.01%
Subgroup size: 8528536 -> 8528560 (+0.00%)
Send messages: 7711431 -> 7711464 (+0.00%)
Spill count: 99907 -> 99509 (-0.40%); split: -0.40%, +0.00%
Fill count: 202459 -> 201598 (-0.43%); split: -0.43%, +0.00%
Scratch Memory Size: 4376576 -> 4371456 (-0.12%)
Totals from 2915 (0.44% of 662497) affected shaders:
Instrs: 2288842 -> 2283533 (-0.23%); split: -0.24%, +0.01%
Cycles:
471633295 ->
472186321 (+0.12%); split: -0.27%, +0.39%
Subgroup size: 27488 -> 27512 (+0.09%)
Send messages: 151344 -> 151377 (+0.02%)
Spill count: 48091 -> 47693 (-0.83%); split: -0.83%, +0.00%
Fill count: 59053 -> 58192 (-1.46%); split: -1.46%, +0.00%
Scratch Memory Size: 1827840 -> 1822720 (-0.28%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19968>
Ian Romanick [Wed, 16 Nov 2022 21:16:25 +0000 (13:16 -0800)]
nir/algebraic: Lower some bfi with two constant sources
All Haswell and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs:
19907054 ->
19906882 (<.01%)
instructions in affected programs: 8103 -> 7931 (-2.12%)
helped: 52 / HURT: 0
total cycles in shared programs:
855779334 ->
855781791 (<.01%)
cycles in affected programs: 724201 -> 726658 (0.34%)
helped: 38 / HURT: 7
total sends in shared programs: 1039308 -> 1039302 (<.01%)
sends in affected programs: 162 -> 156 (-3.70%)
helped: 2 / HURT: 0
No shader-db changes on any older Intel platforms.
All Intel platforms had similar restuls. (Ice Lake shown)
Totals:
Instrs:
153117340 ->
152825222 (-0.19%); split: -0.19%, +0.00%
Cycles:
15011904351 ->
15014072944 (+0.01%); split: -0.04%, +0.05%
Send messages: 7711509 -> 7711421 (-0.00%)
Spill count: 100745 -> 99907 (-0.83%); split: -0.85%, +0.02%
Fill count: 203684 -> 202459 (-0.60%); split: -0.62%, +0.02%
Scratch Memory Size: 4403200 -> 4376576 (-0.60%)
Totals from 18603 (2.81% of 662496) affected shaders:
Instrs: 5258303 -> 4966185 (-5.56%); split: -5.56%, +0.00%
Cycles:
447391388 ->
449559981 (+0.48%); split: -1.29%, +1.77%
Send messages: 559231 -> 559143 (-0.02%)
Spill count: 5009 -> 4171 (-16.73%); split: -17.17%, +0.44%
Fill count: 8769 -> 7544 (-13.97%); split: -14.33%, +0.36%
Scratch Memory Size: 194560 -> 167936 (-13.68%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19968>
Ian Romanick [Tue, 26 Jul 2022 15:55:45 +0000 (08:55 -0700)]
intel/fs: Use nir_opt_reassociate_bfi
All Skylake and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs:
19907072 ->
19907054 (<.01%)
instructions in affected programs: 8859 -> 8841 (-0.20%)
helped: 9 / HURT: 0
total cycles in shared programs:
855791238 ->
855779334 (<.01%)
cycles in affected programs: 3308294 -> 3296390 (-0.36%)
helped: 12 / HURT: 13
Broadwell
total instructions in shared programs:
17818231 ->
17817440 (<.01%)
instructions in affected programs: 9887 -> 9096 (-8.00%)
helped: 9 / HURT: 0
total cycles in shared programs:
902970035 ->
902941221 (<.01%)
cycles in affected programs: 2767243 -> 2738429 (-1.04%)
helped: 14 / HURT: 5
total spills in shared programs: 17784 -> 17718 (-0.37%)
spills in affected programs: 318 -> 252 (-20.75%)
helped: 1 / HURT: 0
total fills in shared programs: 25458 -> 24949 (-2.00%)
fills in affected programs: 1346 -> 837 (-37.82%)
helped: 1 / HURT: 0
Haswell
total instructions in shared programs:
16707799 ->
16707586 (<.01%)
instructions in affected programs: 24049 -> 23836 (-0.89%)
helped: 41 / HURT: 0
total cycles in shared programs:
882730648 ->
882723174 (<.01%)
cycles in affected programs: 5096737 -> 5089263 (-0.15%)
helped: 25 / HURT: 12
total spills in shared programs: 14937 -> 14909 (-0.19%)
spills in affected programs: 436 -> 408 (-6.42%)
helped: 4 / HURT: 0
total fills in shared programs: 17569 -> 17529 (-0.23%)
fills in affected programs: 444 -> 404 (-9.01%)
helped: 4 / HURT: 0
No shader-db changes on any older Intel platforms.
All Intel platforms had similar results. (Ice Lake shown)
Totals:
Instrs:
153118594 ->
153117340 (-0.00%); split: -0.00%, +0.00%
Cycles:
15011967556 ->
15011904351 (-0.00%); split: -0.00%, +0.00%
Fill count: 203692 -> 203684 (-0.00%)
Totals from 703 (0.11% of 662496) affected shaders:
Instrs: 192826 -> 191572 (-0.65%); split: -0.65%, +0.00%
Cycles:
29937640 ->
29874435 (-0.21%); split: -0.25%, +0.04%
Fill count: 4146 -> 4138 (-0.19%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19968>
Ian Romanick [Tue, 26 Jul 2022 15:49:32 +0000 (08:49 -0700)]
nir: Add optimization pass to reassociate some bfi instructions
The needs of this pass are ever so slightly more than what
nir_opt_algebraic can do. :( Specifically, it needs to be able to look
at the relationship of constant values used in an expression tree.
v2: Add nir_mov_alu to handle swizzles on the original sources.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19968>
Mike Blumenkrantz [Wed, 14 Jun 2023 16:53:11 +0000 (12:53 -0400)]
zink: add some ci flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23654>
Daniel Stone [Wed, 14 Jun 2023 15:46:37 +0000 (16:46 +0100)]
CI: Re-enable freedreno CI
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23108>
Daniel Stone [Thu, 18 May 2023 14:43:47 +0000 (15:43 +0100)]
ci: Extend a618_vk_full runtime
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23108>
Daniel Stone [Thu, 18 May 2023 14:37:00 +0000 (15:37 +0100)]
ci: Don't retry manual or scheduled jobs
Only retry when there's some kind of non-job failure, such as
runner-internal issues, or API/network issues, etc. If the job itself
fails or times out, then given the length of these jobs, there's no
point trying again and just tying up the job slots for even more hours.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23108>
Daniel Stone [Thu, 18 May 2023 14:32:35 +0000 (15:32 +0100)]
ci: Elaborate causes for job retries
Rather than always retrying, only retry jobs on a limited set of causes.
This notably excludes retries when a job is stuck due to lack of runners
to schedule it; if we can't get a slot on a runner in time, there's no
reason to try again, since our window of opportunity has gone.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23108>
Emma Anholt [Mon, 5 Jun 2023 20:42:55 +0000 (13:42 -0700)]
ci: Drop some skips of GL CTS ArraysOfArrays tests.
My hope is that with my CTS fix, we can complete these all in time now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23610>
Emma Anholt [Mon, 5 Jun 2023 20:07:01 +0000 (13:07 -0700)]
ci: Drop skips for some previously-invalid CTS tests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23610>
Emma Anholt [Mon, 5 Jun 2023 20:04:00 +0000 (13:04 -0700)]
ci: Update to vulkan-cts-1.3.5.2 (and pull in some more fixes).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23610>
Emma Anholt [Tue, 13 Jun 2023 00:14:11 +0000 (17:14 -0700)]
ci/zink: Update current xfails on tgl.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23610>
Emma Anholt [Tue, 13 Jun 2023 21:18:28 +0000 (14:18 -0700)]
intel: Reduce cost of resetting last_grf_write.
In zink-on-anv fs-mod-dvec3-dvec3.shader_test, we were memsetting 2MB of
last_grf_write 2400 times, multiple times through the scheduler. Just
resetting for the processed instructions reduces runtime from 21s to 16s.
No change on steam shader-db runtime across several runs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23635>
Emma Anholt [Tue, 13 Jun 2023 20:46:56 +0000 (13:46 -0700)]
intel: Allocate the last_grf_write once per scheduler.
No need to re-calloc it per block when we're going to use it again. Also,
this fixes the vec4 backend to avoid allocating giant grf_count-sized
arrays on the stack.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23635>
Emma Anholt [Tue, 13 Jun 2023 19:50:02 +0000 (12:50 -0700)]
intel: Count reads_remaining across all blocks.
We were zeroing it out per block, but it doesn't actually help to count
per block, since the question is "will scheduling this instruction free
the reg?". Saves some memsetting, which was showing up high in the
profile (but not from this source).
No change on iris SKL shader-db.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23635>
Mike Blumenkrantz [Thu, 4 May 2023 17:18:50 +0000 (13:18 -0400)]
egl/dri2: trigger drawable invalidation from surface queries for zink
this mimics dri3 behavior and avoids scenarios where renderbuffers can
get out of sync with their resources
fixes #6744
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22858>
Mike Blumenkrantz [Tue, 13 Jun 2023 22:20:42 +0000 (18:20 -0400)]
lavapipe: add version uuid to shader binary validation
this ensures compatible shader binaries across versions
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23636>
Gert Wollny [Wed, 14 Jun 2023 12:33:25 +0000 (14:33 +0200)]
r600: Disable SB if we use the ariable length DOT
sb doesn't know about this instruction, so don't try to run the
optimizer.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23647>
Gert Wollny [Tue, 13 Jun 2023 15:13:07 +0000 (17:13 +0200)]
600/sfn: Trigger use of ACK for some barriers
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23647>
Gert Wollny [Sun, 14 May 2023 12:48:51 +0000 (14:48 +0200)]
r600/sfn: move kill handling to fully scheduling
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23647>
Gert Wollny [Sun, 14 May 2023 12:50:24 +0000 (14:50 +0200)]
r600: fix handling of use_sb flag
The compiler will use the unsigned bit pattern of the check and combine this
with the 1 bit, which will always result in use_sb to be zero.
Fix this by making use_sb a bool
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23647>
Mike Blumenkrantz [Wed, 31 May 2023 15:20:17 +0000 (11:20 -0400)]
zink: add a dgc debug mode for testing
this is useful for drivers trying to implement DGC since there is no cts
do not use.
it will not make anything faster.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23550>
Lionel Landwerlin [Thu, 8 Jun 2023 18:53:02 +0000 (21:53 +0300)]
intel/fs: handle load_global_constant_uniform_block_intel
Again, load the data just once in GRF, share it across lanes.
Shader-db on dg2:
total instructions in shared programs:
23214555 ->
23215400 (<.01%)
instructions in affected programs: 199977 -> 200822 (0.42%)
helped: 3
HURT: 38
helped stats (abs) min: 5 max: 670 x̄: 283.67 x̃: 176
helped stats (rel) min: 1.34% max: 49.41% x̄: 22.15% x̃: 15.70%
HURT stats (abs) min: 1 max: 185 x̄: 44.63 x̃: 32
HURT stats (rel) min: 0.13% max: 42.86% x̄: 10.25% x̃: 9.30%
95% mean confidence interval for instructions value: -18.65 59.87
95% mean confidence interval for instructions %-change: 3.29% 12.47%
Inconclusive result (value mean confidence interval includes 0).
total loops in shared programs: 5928 -> 5928 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total cycles in shared programs:
851137495 ->
851152449 (<.01%)
cycles in affected programs:
16406137 ->
16421091 (0.09%)
helped: 9
HURT: 32
helped stats (abs) min: 10 max: 13498 x̄: 6443.22 x̃: 5581
helped stats (rel) min: 0.11% max: 4.75% x̄: 1.45% x̃: 0.34%
HURT stats (abs) min: 3 max: 15056 x̄: 2279.47 x̃: 735
HURT stats (rel) min: 0.10% max: 23.71% x̄: 4.58% x̃: 4.65%
95% mean confidence interval for cycles value: -1315.40 2044.87
95% mean confidence interval for cycles %-change: 1.71% 4.80%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 11856 -> 11825 (-0.26%)
spills in affected programs: 2368 -> 2337 (-1.31%)
helped: 4
HURT: 0
total fills in shared programs: 16258 -> 16207 (-0.31%)
fills in affected programs: 2930 -> 2879 (-1.74%)
helped: 4
HURT: 0
total sends in shared programs: 1038194 -> 1038185 (<.01%)
sends in affected programs: 40 -> 31 (-22.50%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 2.25 x̃: 2
helped stats (rel) min: 10.00% max: 33.33% x̄: 21.46% x̃: 21.25%
95% mean confidence interval for sends value: -4.64 0.14
95% mean confidence interval for sends %-change: -40.41% -2.51%
Inconclusive result (value mean confidence interval includes 0).
LOST: 0
GAINED: 0
Some VK/DX titles result (on DG2 only), it's mostly additional
instruction counts except for the unity spaceship demo where a CS
shader gets additional SIMDness. The reason for additional
instructions is that since we're doing block loads, we need to find
the live channels in control flow to select a single lane value that
is valid.
aztec_ruins_high:
Totals from 3 (1.12% of 269) affected shaders:
Instrs: 17732 -> 17896 (+0.92%)
Cycles: 796518 -> 819302 (+2.86%)
cyberpunk_2077:
Totals from 17 (0.17% of 10301) affected shaders:
Instrs: 10848 -> 11658 (+7.47%)
Cycles: 248243 -> 259168 (+4.40%); split: -0.57%, +4.97%
fallout_4_dxvk_g2:
Totals from 2 (0.12% of 1638) affected shaders:
Instrs: 3157 -> 3368 (+6.68%)
Cycles: 487807 -> 490426 (+0.54%); split: -0.26%, +0.79%
Max live registers: 139 -> 141 (+1.44%)
red_dead_redemption2:
Totals from 68 (1.14% of 5970) affected shaders:
Instrs: 34871 -> 36486 (+4.63%)
Cycles: 551430 -> 565211 (+2.50%)
Send messages: 2074 -> 2072 (-0.10%)
Max live registers: 5078 -> 5077 (-0.02%)
total_war_warhammer2:
Totals from 5 (1.05% of 478) affected shaders:
Instrs: 6905 -> 6971 (+0.96%); split: -0.16%, +1.12%
Cycles: 97035 -> 97989 (+0.98%); split: -0.07%, +1.05%
unity spaceship demo (instruction count going up due to a CS shader
bump from SIMD8->16):
Totals from 53 (9.71% of 546) affected shaders:
Instrs: 223748 -> 233223 (+4.23%); split: -0.01%, +4.25%
Cycles:
23134697 ->
25207080 (+8.96%); split: -0.17%, +9.13%
Subgroup size: 480 -> 488 (+1.67%)
Spill count: 2156 -> 2242 (+3.99%); split: -0.19%, +4.17%
Fill count: 4617 -> 4845 (+4.94%); split: -0.09%, +5.02%
Max live registers: 5991 -> 6050 (+0.98%); split: -0.40%, +1.39%
Max dispatch width: 480 -> 488 (+1.67%)
witcher_3_dxvk_g2:
Totals from 27 (2.51% of 1074) affected shaders:
Instrs: 57067 -> 57677 (+1.07%); split: -0.03%, +1.10%
Cycles: 1397871 -> 1436704 (+2.78%); split: -0.35%, +3.13%
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
Lionel Landwerlin [Fri, 9 Jun 2023 10:57:43 +0000 (13:57 +0300)]
nir: add a load_global_constant uniform intel variant
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
Lionel Landwerlin [Tue, 6 Jun 2023 15:03:26 +0000 (18:03 +0300)]
intel/fs: make use of load_ubo_uniform_block_intel
The principle is the same as the load_ssbo_uniform_block_intel.
Whenever we see a uniform offset, load the data only once in GRFs to
reduce register pressure.
Iris shader-db run on DG2 :
total instructions in shared programs:
23001325 ->
23094969 (0.41%)
instructions in affected programs: 1775989 -> 1869633 (5.27%)
helped: 764
HURT: 2097
helped stats (abs) min: 1 max: 102 x̄: 6.96 x̃: 2
helped stats (rel) min: 0.03% max: 16.91% x̄: 1.36% x̃: 0.63%
HURT stats (abs) min: 1 max: 2461 x̄: 47.19 x̃: 7
HURT stats (rel) min: <.01% max: 199.34% x̄: 5.91% x̃: 2.60%
95% mean confidence interval for instructions value: 25.43 40.03
95% mean confidence interval for instructions %-change: 3.60% 4.33%
Instructions are HURT.
total loops in shared programs: 5847 -> 5847 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total cycles in shared programs:
839329852 ->
845491482 (0.73%)
cycles in affected programs:
130229434 ->
136391064 (4.73%)
helped: 1098
HURT: 2228
helped stats (abs) min: 1 max: 130102 x̄: 1340.64 x̃: 22
helped stats (rel) min: <.01% max: 64.25% x̄: 4.03% x̃: 0.71%
HURT stats (abs) min: 1 max: 185309 x̄: 3426.24 x̃: 87
HURT stats (rel) min: <.01% max: 92.85% x̄: 8.12% x̃: 3.82%
95% mean confidence interval for cycles value: 1342.16 2362.97
95% mean confidence interval for cycles %-change: 3.70% 4.52%
Cycles are HURT.
total spills in shared programs: 10768 -> 11856 (10.10%)
spills in affected programs: 9717 -> 10805 (11.20%)
helped: 25
HURT: 28
total fills in shared programs: 13720 -> 16258 (18.50%)
fills in affected programs: 12016 -> 14554 (21.12%)
helped: 25
HURT: 28
total sends in shared programs: 1034790 -> 1031266 (-0.34%)
sends in affected programs: 33416 -> 29892 (-10.55%)
helped: 1005
HURT: 0
helped stats (abs) min: 1 max: 22 x̄: 3.51 x̃: 3
helped stats (rel) min: 1.69% max: 60.00% x̄: 15.20% x̃: 14.08%
95% mean confidence interval for sends value: -3.72 -3.29
95% mean confidence interval for sends %-change: -15.82% -14.57%
Sends are helped.
LOST: 26
GAINED: 183
shader-db on a number of VK/DX titles on DG2 :
PERCENTAGE DELTAS Shaders Instrs Cycles
age_of_wonders_III 1928 +0.02% -0.19%
PERCENTAGE DELTAS Shaders Instrs Cycles Subgroup size Send messages Spill count Fill count Max live registers Max dispatch width
assassins_creed_odyssey 2119 +1.12% -0.42% -0.03% -0.29% -9.10% -4.26% -0.64% +0.65%
PERCENTAGE DELTAS Shaders Instrs Cycles Spill count Fill count Max live registers
aztec_ruins_high 269 -0.05% -0.45% -0.29% -7.27% -0.33%
PERCENTAGE DELTAS Shaders Instrs Cycles Max live registers Max dispatch width
dark_souls_3_dxvk_g2 1420 +0.09% +0.24% +0.21% +0.12%
(stats look bad, but it's just one shader affected)
PERCENTAGE DELTAS Shaders Instrs Cycles Spill count Fill count Scratch Memory Size Max live registers
fallout_4_dxvk_g2 1638 +0.67% +8.32% +16.02% +7.17% +100.00% +0.48%
PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Spill count Fill count Max live registers Max dispatch width
red_dead_redemption2 5969 +0.16% -0.04% -0.04% +0.01% +0.05% -0.20% +0.04%
PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers Max dispatch width
rise_of_the_tomb_raider_g2 12129 +2.19% +1.36% -1.23% -0.36% +2.04%
PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers
shooter-game 693 +0.07% -0.89% -0.09% -0.09%
PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers Max dispatch width
talos_g2 1140 +0.37% +3.80% -0.86% -0.67% +0.19%
PERCENTAGE DELTAS Shaders Instrs Cycles Max live registers Max dispatch width
total_war_warhammer2 477 +0.25% +0.66% -0.17% +0.10%
PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers Max dispatch width
witcher_3_dxvk_g2 1074 +0.75% -10.45% -0.15% -0.16% -0.16%
PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers
wolfenstein_youngblood 1111 +0.52% +0.66% -0.59% -0.03%
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
Lionel Landwerlin [Tue, 6 Jun 2023 15:02:42 +0000 (18:02 +0300)]
nir: add a new ubo uniform loading intrinsic for intel
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
Lionel Landwerlin [Tue, 13 Jun 2023 17:37:22 +0000 (20:37 +0300)]
intel/fs: avoid reusing the VGRF for uniform load_ubo
Only found 3 shaders affected in Red Dead Redemption :
Totals from 3 (0.05% of 5969) affected shaders:
Instrs: 2246 -> 2230 (-0.71%)
Cycles: 156506 -> 148402 (-5.18%); split: -5.23%, +0.05%
This will have a larger effect when we add the
load_ubo_uniform_block_intel intrinsic where we will have larger
blocks (vec8/vec16 vs vec4 only now).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
Lionel Landwerlin [Fri, 9 Jun 2023 08:48:26 +0000 (11:48 +0300)]
intel/fs: print identation for control flow
INTEL_DEBUG=optimizer output changes from :
{ 10} 40: cmp.nz.f0.0(8) null:F, vgrf3470:F, 0f
{ 10} 41: (+f0.0) if(8) (null):UD,
{ 11} 42: txf_logical(8) vgrf3473:UD, vgrf250:D(null):UD, 0d(null):UD(null):UD(null):UD(null):UD, 31u, 0u(null):UD(null):UD(null):UD, 3d, 0d
{ 12} 43: and(8) vgrf262:UD, vgrf3473:UD, 2u
{ 11} 44: cmp.nz.f0.0(8) null:D, vgrf262:D, 0d
{ 10} 45: (+f0.0) if(8) (null):UD,
{ 11} 46: mov(8) vgrf270:D, -
1082130432d
{ 12} 47: mov(8) vgrf271:D,
1082130432d
{ 14} 48: mov(8) vgrf274+0.0:D, 0d
{ 14} 49: mov(8) vgrf274+1.0:D, 0d
to :
{ 10} 40: cmp.nz.f0.0(8) null:F, vgrf3470:F, 0f
{ 10} 41: (+f0.0) if(8) (null):UD,
{ 11} 42: txf_logical(8) vgrf3473:UD, vgrf250:D(null):UD, 0d(null):UD(null):UD(null):UD(null):UD, 31u, 0u(null):UD(null):UD(null):UD, 3d, 0d
{ 12} 43: and(8) vgrf262:UD, vgrf3473:UD, 2u
{ 11} 44: cmp.nz.f0.0(8) null:D, vgrf262:D, 0d
{ 10} 45: (+f0.0) if(8) (null):UD,
{ 11} 46: mov(8) vgrf270:D, -
1082130432d
{ 12} 47: mov(8) vgrf271:D,
1082130432d
{ 14} 48: mov(8) vgrf274+0.0:D, 0d
{ 14} 49: mov(8) vgrf274+1.0:D, 0d
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
Karol Herbst [Tue, 13 Jun 2023 00:07:02 +0000 (02:07 +0200)]
rusticl/queue: overhaul of the queue+event handling
This new approach handles things as follows:
1. Fences won't be attached to events anymore, applications only wait on
the cv attached to the event.
2. Only the queue is allowed to update event status for non user events.
This will eliminate all remaining status updating races between the
queue and applications waiting on events.
3. Queue minimized flushing by bundling events
4. Increase cv wait timeout as there is really no point in waking up too
often.
Reduces amount of emited fences on radeonsi in luxmark 3.1 luxball by 90%
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed by Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23612>
Iago Toral Quiroga [Thu, 13 Apr 2023 08:31:17 +0000 (10:31 +0200)]
broadcom/compiler: only use last thread switch flag to detect final section
Since commit '
c98ddc778a3 broadcom/compiler: force a last thrsw for spilling'
we always ensure we signal the last thread section explicitly with a
last thread switch.
Relying on VPM stores to detect the last thread section is particularly bad,
because we can have VPM stores occurring quite early in a shader program,
which would disable TMU spilling almost entirely.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22461>
Alejandro Piñeiro [Fri, 12 May 2023 12:04:56 +0000 (14:04 +0200)]
broadcom/compiler: clarify use of QFILE_VPM
This was only used for version < 40 (See commit
22a02f3e3).
Adding some extra explanations and asserts of places where it is used.
As we are here also move the definition of a register with QFILE_VPM,
to avoid defining it if not needed.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22984>
Lionel Landwerlin [Thu, 8 Jun 2023 22:05:34 +0000 (01:05 +0300)]
intel/fs: fix bindless/shared surface mistake
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
068bf1378d ("intel/fs: enable SSBO accesses through the bindless heap")
Tested-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23536>
Lionel Landwerlin [Tue, 16 May 2023 19:11:47 +0000 (22:11 +0300)]
anv: enable CmdCopyQueryPoolResults to use shader for copies
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 13 Jun 2023 08:11:27 +0000 (11:11 +0300)]
intel/ds: add query count in query tracepoints
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 18:59:33 +0000 (21:59 +0300)]
anv: add shaders for copying query results
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 13:10:31 +0000 (16:10 +0300)]
anv: generalize internal kernel concept
We'll add more of those kernels for other purposes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 10:13:41 +0000 (13:13 +0300)]
anv: add support for simple internal compute shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 09:54:39 +0000 (12:54 +0300)]
anv: factor out generation kernel dispatch into helper
We would like to reuse this mechanism to dispatch different types of
internal shader. Those would replace some of the command streamer
commands we currently use.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Wed, 17 May 2023 10:40:14 +0000 (13:40 +0300)]
anv: limit ANV_PIPE_RENDER_TARGET_BUFFER_WRITES to blorp operations using 3D
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 06:53:42 +0000 (09:53 +0300)]
anv: fix incorrect batch for 3DSTATE_CONSTANT_ALL emission
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 06:20:09 +0000 (09:20 +0300)]
anv: disable mesh/task for generated draws
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Lionel Landwerlin [Tue, 16 May 2023 06:25:17 +0000 (09:25 +0300)]
anv: only disable mesh when enabled at the VkDevice level
Saving ourselves some instructions since it's not going to get used.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
Samuel Pitoiset [Wed, 24 May 2023 06:20:33 +0000 (08:20 +0200)]
radv: fix smooth lines with graphics pipeline library
Need to be defensive here.
Fixes recent CTS
dEQP-VK.pipeline.fast_linked_library.extended_dynamic_state.*.line_raster_mode_smooth.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23200>
Samuel Pitoiset [Wed, 24 May 2023 12:51:46 +0000 (14:51 +0200)]
radv: do not force VRS 1x1 when smooth lines are enabled
Otherwise this will break VRS with GPL.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23200>
Samuel Pitoiset [Wed, 24 May 2023 12:44:54 +0000 (14:44 +0200)]
radv: add a helper for forcing VRS 1x1 in some situations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23200>
Samuel Pitoiset [Wed, 24 May 2023 12:42:00 +0000 (14:42 +0200)]
radv: gather info about load_poly_line_smooth_enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23200>
Lynne [Tue, 13 Jun 2023 15:50:29 +0000 (17:50 +0200)]
radv/video: reject unsupported hevc profiles and bit depths
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23625>
Lynne [Tue, 13 Jun 2023 15:50:07 +0000 (17:50 +0200)]
radv/video: reject non-8bit H264
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23625>
Lynne [Tue, 13 Jun 2023 15:40:50 +0000 (17:40 +0200)]
radv/video: reject general unsupported video formats
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23625>
Charmaine Lee [Wed, 14 Jun 2023 00:14:41 +0000 (03:14 +0300)]
svga: fix shader type after ntt
Set shader type to TGSI after ntt. Fixes assert in svga_create_shader.
Fixes:
0ac95418048 ("gallium: Drop PIPE_SHADER_CAP_PREFERRED_IR")
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23638>
Mike Blumenkrantz [Mon, 8 May 2023 12:55:03 +0000 (08:55 -0400)]
zink: add some ntv asserts for ms txf
it's illegal to do ms txf without a ms image
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22900>
Mike Blumenkrantz [Mon, 8 May 2023 12:54:26 +0000 (08:54 -0400)]
zink: assert that ntv image creation isn't clobbering existing images
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22900>
Mike Blumenkrantz [Tue, 13 Jun 2023 17:12:37 +0000 (13:12 -0400)]
zink: massively shrink qbo size for timestamp queries
timestamp queries can only ever record a single value, so
the qbo only needs to be large enough for that single value
fixes #9092
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23631>
Dave Airlie [Tue, 13 Jun 2023 00:44:33 +0000 (10:44 +1000)]
radv/video: program hevc max dec pic buffering correctly
This programs it like vaapi does.
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23613>
Dave Airlie [Mon, 12 Jun 2023 01:48:58 +0000 (11:48 +1000)]
radv/video: program frame number correctly.
doesn't appear to fix anything, but is more correct.
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23613>
Lionel Landwerlin [Fri, 9 Jun 2023 13:52:17 +0000 (16:52 +0300)]
anv: always report all pipeline stats regardless of stages
Tools like the scripts in shader-db expect all the fields to be there,
as the stats are put into a CSV file. So just report 0 if a stage
doesn't support workgroup memory size.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23559>
Lionel Landwerlin [Fri, 9 Jun 2023 13:32:17 +0000 (16:32 +0300)]
anv: report max simd width only once for fragment shaders
Reporting the value multiple times is confusing to shader-db scripts
because it believes multiple shaders are affected.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23559>