Oliver Stannard [Fri, 1 Apr 2016 09:14:50 +0000 (09:14 +0000)]
[AArch64] Better errors for out-of-range fixups
When a fixup that can be resolved by the assembler is out of range, we should
report an error in the source, rather than crashing.
Differential Revision: http://reviews.llvm.org/D18402
llvm-svn: 265120
Alexey Bataev [Fri, 1 Apr 2016 08:43:42 +0000 (08:43 +0000)]
Revert "[OPENMP] Allow skip expression after comma in clauses with lists."
This reverts commit http://reviews.llvm.org/rL265003. After some
thoughts decided to emit errors here.
llvm-svn: 265119
Mehdi Amini [Fri, 1 Apr 2016 08:22:59 +0000 (08:22 +0000)]
ThinLTO: move ObjCARCContractPass in the CodeGen pipeline
This is to be coherent with Full LTO.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265118
Haojian Wu [Fri, 1 Apr 2016 07:57:30 +0000 (07:57 +0000)]
[clang-tidy] Don't delete unused parameter in class override method in anonymous namespace.
Summary: Fixes PR26740.
Reviewers: alexfh
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D17926
llvm-svn: 265117
Jeroen Ketema [Fri, 1 Apr 2016 07:56:17 +0000 (07:56 +0000)]
[OCaml] Use LLVMCreateMessage with constant strings when calling llvm_raise
The llvm_string_of_message function, called by llvm_raise, calls
LLVMDisposeMessage, which expects the message to be dynamically
allocated; it fails freeing the message otherwise. So always
dynamically allocate with LLVMCreateMessage.
Differential Revision: http://reviews.llvm.org/D18675
llvm-svn: 265116
Jeroen Ketema [Fri, 1 Apr 2016 07:54:24 +0000 (07:54 +0000)]
[OCaml] Reinstate data_layout
Expose LLVMCreateTargetMachineData as data_layout.
As r263530 did for go. From that commit: "LLVMGetTargetDataLayout was
removed from the C API, and then TargetMachine.TargetData was removed.
Later, LLVMCreateTargetMachineData was added to the C API"
Differential Revision: http://reviews.llvm.org/D18677
llvm-svn: 265115
Tobias Grosser [Fri, 1 Apr 2016 07:15:19 +0000 (07:15 +0000)]
ScoPDetection: Obtain a known free diagnostic ID
... instead of hardcoding something that has been free at some point. This fixes
a crash triggered by r265084, where the diagnostic IDs have been shifted in a
way that resulted our hardcode ID to not be assigned any implementation. Our ID
was likely already wrong earlier on, but this time we really crashed nicely.
llvm-svn: 265114
Mehdi Amini [Fri, 1 Apr 2016 06:47:02 +0000 (06:47 +0000)]
Add a libLTO API to stop/restart ThinLTO between optimizations and CodeGen
This allows the linker to instruct ThinLTO to perform only the
optimization part or only the codegen part of the process.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265113
Chuang-Yu Cheng [Fri, 1 Apr 2016 06:44:32 +0000 (06:44 +0000)]
[PPC64] Bug fix: when enabling sibling-call-opt and shrink-wrapping, the tail call branch instruction might disappear
Bug Pattern:
# BB#0: # %entry
cmpldi 3, 0
beq- 0, .LBB0_2
# BB#1: # %exit
lwz 4, 0(3)
#TC_RETURNd8 LVComputationKind 0
.LBB0_2: # %cond.false
mflr 0
std 0, 16(1)
stdu 1, -96(1)
.Ltmp0:
.cfi_def_cfa_offset 96
.Ltmp1:
.cfi_offset lr, 16
bl __assert_fail
nop
The branch instruction for tail call return is not generated, because the
shrink-wrapping pass choosing a new Restore Point: %cond.false, so %exit
block is not sent to emitEpilogue, that's why the branch is not generated.
Thanks Kit's opinions!
Reviewers: nemanjai hfinkel tjablin kbarton
http://reviews.llvm.org/D17606
llvm-svn: 265112
Mehdi Amini [Fri, 1 Apr 2016 05:33:11 +0000 (05:33 +0000)]
Add a module Hash in the bitcode and the combined index, implementing a kind of "build-id"
This is intended to be used for ThinLTO incremental build.
Differential Revision: http://reviews.llvm.org/D18213
This is a recommit of r265095 after fixing the Windows issues.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265111
Mehdi Amini [Fri, 1 Apr 2016 05:19:14 +0000 (05:19 +0000)]
Fix MSVC warning "comparison of integers of different signs" (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265110
Mehdi Amini [Fri, 1 Apr 2016 05:12:24 +0000 (05:12 +0000)]
Fix S390 big endian detection
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265109
Mehdi Amini [Fri, 1 Apr 2016 05:12:18 +0000 (05:12 +0000)]
Const correctness in raw_sha1_ostream (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265108
Mehdi Amini [Fri, 1 Apr 2016 04:30:16 +0000 (04:30 +0000)]
Add support for computing SHA1 in LLVM
Provide a class to generate a SHA1 from a sequence of bytes, and
a convenience raw_ostream adaptor.
This will be used to provide a "build-id" by hashing the Module
block when writing bitcode. ThinLTO will use this information for
incremental build.
Reapply r265094 which was reverted in r265102 because it broke
MSVC bots (constexpr is not supported).
http://reviews.llvm.org/D16325
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265107
Sean Silva [Fri, 1 Apr 2016 03:54:03 +0000 (03:54 +0000)]
Improve CHECK-NOT robustness of dllexport tests
This changes some dllexport tests, to verify that some symbols that
should not be exported are not, in a way that improves the robustness
of CHECK-SAME interaction with CHECK-NOT.
We plan to enable dllimport/dllexport support for the PS4, and these
changes are for points we noticed in our internal testing.
Patch by Warren Ristow!
llvm-svn: 265106
Michael Kuperstein [Fri, 1 Apr 2016 03:45:08 +0000 (03:45 +0000)]
Use range-based for loops. NFC.
llvm-svn: 265105
Mike Spertus [Fri, 1 Apr 2016 03:31:43 +0000 (03:31 +0000)]
Visual Studio native visualizers for clang::TemplateSpecializationType
Displays a template specialization as, say, A<int, double>. Does not
yet handle UncommonTemplateNameStorage, QualifiedTemplateName, or
DependentTemplateName, but still more than worthwhile
llvm-svn: 265104
Devin Coughlin [Fri, 1 Apr 2016 03:24:13 +0000 (03:24 +0000)]
[analyzer] Prefer accessor method in extension over category in CallEvent.
In ObjCMethodCall:getRuntimeDefinition(), if the method is an accessor in a
category, and it doesn't have a self declaration, first try to find the method
in a class extension. This works around a bug in Sema where multiple accessors
are synthesized for properties in class extensions that are redeclared in a
category. The implicit parameters are not filled in for the method on the
category, which causes a crash when trying to synthesize a getter for the
property in BodyFarm. The Sema bug is tracked as rdar://problem/
25481164.
rdar://problem/
25056531
llvm-svn: 265103
Mehdi Amini [Fri, 1 Apr 2016 03:03:21 +0000 (03:03 +0000)]
Revert "Add support for computing SHA1 in LLVM"
This reverts commit r265096, r265095, and r265094.
Windows build is broken, and the validation does not pass.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265102
Sanjoy Das [Fri, 1 Apr 2016 02:51:30 +0000 (02:51 +0000)]
Don't insert stackrestore on deoptimizing returns
They're not necessary (since the stack pointer is trivially restored on
return), and the way LLVM inserts the stackrestore calls breaks the
IR (we get a stackrestore between the deoptimize call and the return).
llvm-svn: 265101
Sanjoy Das [Fri, 1 Apr 2016 02:51:26 +0000 (02:51 +0000)]
Don't insert lifetime end markers on deoptimizing returns
They're not necessary (since the lifetime of the alloca is trivially
over due to the return), and the way LLVM inserts the lifetime.end
markers breaks the IR (we get a lifetime end marker between the
deoptimize call and the return).
llvm-svn: 265100
Sanjoy Das [Fri, 1 Apr 2016 02:51:21 +0000 (02:51 +0000)]
Don't use an i64 return type with webkit_jscc
Re-enable an assertion enabled by Justin Lebar in rL265092. rL265092
was breaking test/CodeGen/X86/deopt-intrinsic.ll because webkit_jscc
does not like non-i64 return types. Change the test case to not do
that.
llvm-svn: 265099
Matthias Braun [Fri, 1 Apr 2016 02:49:17 +0000 (02:49 +0000)]
AArch64ISelLowering: Remove unused variables/arguments; NFC
llvm-svn: 265098
Chuang-Yu Cheng [Fri, 1 Apr 2016 02:05:29 +0000 (02:05 +0000)]
Fix Sub-register Rewriting in Aggressive Anti-Dependence Breaker
Previously, HandleLastUse would delete RegRef information for sub-registers
if they were dead even if their corresponding super-register were still live.
If the super-register were later renamed, then the definitions of the
sub-register would not be updated appropriately. This patch alters the
behavior so that RegInfo information for sub-registers is only deleted when
the sub-register and super-register are both dead.
This resolves PR26775. This is the mirror image of Hal's r227311 commit.
Author: Tom Jablin (tjablin)
Reviewers: kbarton uweigand nemanjai hfinkel
http://reviews.llvm.org/D18448
llvm-svn: 265097
Mehdi Amini [Fri, 1 Apr 2016 01:37:52 +0000 (01:37 +0000)]
Add missing test for the "Module hash in bitcode" added in r265095
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265096
Mehdi Amini [Fri, 1 Apr 2016 01:30:06 +0000 (01:30 +0000)]
Add a module Hash in the bitcode and the combined index, implementing a kind of "build-id"
This is intended to be used for ThinLTO incremental build.
Differential Revision: http://reviews.llvm.org/D18213
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265095
Mehdi Amini [Fri, 1 Apr 2016 01:29:54 +0000 (01:29 +0000)]
Add support for computing SHA1 in LLVM
Provide a class to generate a SHA1 from a sequence of bytes, and
a convenience raw_ostream adaptor.
This will be used to provide a "build-id" by hashing the Module
block when writing bitcode. ThinLTO will use this information for
incremental build.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265094
Justin Lebar [Fri, 1 Apr 2016 01:23:23 +0000 (01:23 +0000)]
Revert "Protect some assertions with NDEBUG rather than DEBUG()."
This reverts r265092, because it breaks CodeGen/X86/deopt-intrinsic.ll.
llvm-svn: 265093
Justin Lebar [Fri, 1 Apr 2016 01:09:12 +0000 (01:09 +0000)]
Protect some assertions with NDEBUG rather than DEBUG().
DEBUG() only runs if you pass -debug, but these assertions are generally
useful.
llvm-svn: 265092
Justin Lebar [Fri, 1 Apr 2016 01:09:10 +0000 (01:09 +0000)]
[NVPTX] Add a truncate DAG node to some calls.
Summary:
Previously, we were running afoul of the assertion
EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"
in SelectionDAGBuilder.cpp when running the NVPTX/i8-param.ll test.
This is because our backend (for some reason) treats small return values
as i32, but it wasn't ever truncating the i32 back down to the expected
width in the DAG.
Unclear to me whether this fixes any actual bugs -- in this test, at
least, the generated code is unchanged.
Reviewers: jingyue
Subscribers: llvm-commits, tra, jholewinski
Differential Revision: http://reviews.llvm.org/D17872
llvm-svn: 265091
Justin Lebar [Fri, 1 Apr 2016 01:09:07 +0000 (01:09 +0000)]
[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
Summary:
Previously the NVVMReflect pass would read its configuration from
command-line flags or a static configuration given to the pass at
instantiation time.
This doesn't quite work for clang's use-case. It needs to pass a value
for __CUDA_FTZ down on a per-module basis. We use a module flag for
this, so the NVVMReflect pass needs to be updated to read said flag.
Reviewers: tra, rnk
Subscribers: cfe-commits, jholewinski
Differential Revision: http://reviews.llvm.org/D18672
llvm-svn: 265090
Justin Lebar [Fri, 1 Apr 2016 01:09:05 +0000 (01:09 +0000)]
[NVPTX] Annotate some instructions as hasSideEffects = 0.
Summary:
Tablegen tries to infer this from the selection DAG patterns defined for
the instructions, but it can't always.
An instructive example is CLZr64. CLZr32 is correctly inferred to have
no side-effects, but the selection DAG pattern for CLZr64 is slightly
more complicated, and in particular the ctlz DAG node is not at the root
of the pattern. Thus tablegen can't infer that CLZr64 has no
side-effects.
Reviewers: jholewinski
Subscribers: jholewinski, tra, llvm-commits
Differential Revision: http://reviews.llvm.org/D17472
llvm-svn: 265089
Justin Lebar [Fri, 1 Apr 2016 01:09:03 +0000 (01:09 +0000)]
[ifcnv] Add brief comment explaining what ifcnv is.
llvm-svn: 265088
Mehdi Amini [Fri, 1 Apr 2016 00:52:05 +0000 (00:52 +0000)]
Fix Windows build (typo in disk_space() implementation)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265087
Greg Clayton [Fri, 1 Apr 2016 00:41:29 +0000 (00:41 +0000)]
Fixed an issue that could cause debugserver to return two stop reply packets ($T packets) for one \x03 interrupt. The problem was that when a \x03 byte is sent to debugserver while the process is running, and up calling:
rnb_err_t
RNBRemote::HandlePacket_stop_process (const char *p)
{
if (!DNBProcessInterrupt(m_ctx.ProcessID()))
HandlePacket_last_signal (NULL);
return rnb_success;
}
In the call to DNBProcessInterrupt we did:
nub_bool_t
DNBProcessInterrupt(nub_process_t pid)
{
MachProcessSP procSP;
if (GetProcessSP (pid, procSP))
return procSP->Interrupt();
return false;
}
This would always return false. It would cause HandlePacket_stop_process to always call "HandlePacket_last_signal (NULL);" which would send an extra stop reply packet _if_ the process is stopped. On a machine with enough cores, it would call DNBProcessInterrupt(...) and then HandlePacket_last_signal(NULL) so quickly that it will never send out an extra stop reply packet. But if the machine is slow enough or doesn't have enough cores, it could cause the call to HandlePacket_last_signal() to actually succeed and send an extra stop reply packet. This would cause problems up in GDBRemoteCommunicationClient::SendContinuePacketAndWaitForResponse() where it would get the first stop reply packet and then possibly return or execute an async packet. If it returned, then the next packet that was sent will get the second stop reply as its response. If it executes an async packet, the async packet will get the wrong response.
To fix this I did the following:
1 - in debugserver, I fixed "bool MachProcess::Interrupt()" to return true if it sends the signal so we avoid sending the stop reply twice on slower machines
2 - Added a log line to RNBRemote::HandlePacket_stop_process() to say if we ever send an extra stop reply so we will see this in the darwin console output if this does happen
3 - Added response validators to StringExtractorGDBRemote so that we can verify some responses to some packets.
4 - Added validators to packets that often follow stop reply packets like the "m" packet for memory reads, JSON packets since "jThreadsInfo" is often sent immediately following a stop reply.
5 - Modified GDBRemoteCommunicationClient::SendPacketAndWaitForResponseNoLock() to validate responses. Any "StringExtractorGDBRemote &response" that contains a valid response verifier will verify the response and keep looking for correct responses up to 3 times. This will help us get back on track if we do get extra stop replies. If a StringExtractorGDBRemote does not have a response validator, it will accept any packet in response.
6 - In GDBRemoteCommunicationClient::SendPacketAndWaitForResponse we copy the response validator from the "response" argument over into m_async_response so that if we send the packet by interrupting the running process, we can validate the response we actually get in GDBRemoteCommunicationClient::SendContinuePacketAndWaitForResponse()
7 - Modified GDBRemoteCommunicationClient::SendContinuePacketAndWaitForResponse() to always check for an extra stop reply packet for 100ms when the process is interrupted. We were already doing this because we might interrupt a process with a \x03 packet, yet the process was in the process of stopping due to another reason. This race condition could cause an extra stop reply packet because the GDB remote protocol says if a \x03 packet is sent while the process is stopped, we should send a stop reply packet back. Now we always check for an extra stop reply packet when we manually interrupt a process.
The issue was showing up when our IDE would attempt to set a breakpoint while the process is running and this would happen:
--> \x03
<-- $T<stop reply 1>
--> z0,AAAAA,BB (set breakpoint)
<-- $T<stop reply 1> (incorrect extra stop reply packet)
--> c
<-- OK (response from z0 packet)
Now all packet traffic was off by one response. Since we now have a validator on the response for "z" packets, we do this:
--> \x03
<-- $T<stop reply 1>
--> z0,AAAAA,BB (set breakpoint)
<-- $T<stop reply 1> (Ignore this because this can't be the response to z0 packets)
<-- OK -- (we are back on track as this is a valid response to z0)
...
As time goes on we should add more packet validators.
<rdar://problem/
22859505>
llvm-svn: 265086
Davide Italiano [Fri, 1 Apr 2016 00:35:29 +0000 (00:35 +0000)]
[LTO] Inherit options from Codegen before initializing TargetMachine.
This fixes bootstrap of llvm-tblgen (with LTO) and PR27150.
Slightly longer explanation follows.
Emission of .init_array instead of .ctors is supported only on a
subset of the Target LLVM supports. Codegen needs to be conservative
and always emit .ctors unless instructed otherwise (based on target).
If the dynamic linker sees .init_array it completely ignores
what's inside .ctors and therefore some constructors are not called
(and this causes llvm-tblgen to crash on startup).
Teach LLD/LTO about the Codegen options so we end up always emitting
.init_array and avoid this issue.
In future, we might end up supporting mix of .ctors and .init_array
in different input files if this shows up as a real-world use case.
The way gold handles this case is mapping .ctors from input into
.init_array in output. There's also another caveat because
as far as I understand .ctors run in reverse order so when we do
the copy/mapping we need to reverse copy in the output if there's
more than one ctor. That's why I'd rather avoid this complicate logic
unless there's a real need.
An analogous reasoning holds for .dtors/.fini_array.
llvm-svn: 265085
Akira Hatanaka [Fri, 1 Apr 2016 00:34:39 +0000 (00:34 +0000)]
[LoopVectorize] Don't unconditionally print vectorization diagnostics
when compiling with LTO.
r244523 a new class DiagnosticInfoOptimizationRemarkAnalysisAliasing for
optimization analysis remarks related to pointer aliasing without
guarding it in isDiagnosticEnabled in LLVMContext.cpp. This caused the
diagnostic message to be printed unconditionally when compiling with
LTO.
This commit cleans up isDiagnosticEnabled and makes sure all the
vectorization optimization remarks are guarded.
rdar://problem/
25382153
llvm-svn: 265084
Justin Lebar [Fri, 1 Apr 2016 00:25:42 +0000 (00:25 +0000)]
[CUDA] Fix typo in __clang_cuda_runtime_wrapper.h.
We're #including the wrong file!
llvm-svn: 265083
Mehdi Amini [Fri, 1 Apr 2016 00:18:08 +0000 (00:18 +0000)]
Add disk_space() to llvm::fs
Summary: Adapted from Boost::filesystem.
(This is a reapply by reverting commit r265080 and fixing the WinAPI part)
Differential Revision: http://reviews.llvm.org/D18467
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265082
Adrian Prantl [Fri, 1 Apr 2016 00:16:49 +0000 (00:16 +0000)]
testcase gardening: update the emissionKind enum to the new syntax. (NFC)
llvm-svn: 265081
Mehdi Amini [Fri, 1 Apr 2016 00:13:31 +0000 (00:13 +0000)]
Revert "Add disk_space() to llvm::fs"
This reverts commit r265074 and r265068.
Breaks windows build
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265080
Adrian Prantl [Fri, 1 Apr 2016 00:00:27 +0000 (00:00 +0000)]
Fix a captialization error in r265077.
llvm-svn: 265079
Adrian Prantl [Thu, 31 Mar 2016 23:57:45 +0000 (23:57 +0000)]
Adapt to LLVM API change in r265077.
EmissionKind moved from DIBuilder to DICompileUnit.
<rdar://problem/
25427165>
llvm-svn: 265078
Adrian Prantl [Thu, 31 Mar 2016 23:56:58 +0000 (23:56 +0000)]
Move the DebugEmissionKind enum from DIBuilder into DICompileUnit.
This mostly cosmetic patch moves the DebugEmissionKind enum from DIBuilder
into DICompileUnit. DIBuilder is not the right place for this enum to live
in — a metadata consumer should not have to include DIBuilder.h.
I also added a Verifier check that checks that the emission kind of a
DICompileUnit is actually legal.
http://reviews.llvm.org/D18612
<rdar://problem/
25427165>
llvm-svn: 265077
Hans Wennborg [Thu, 31 Mar 2016 23:55:16 +0000 (23:55 +0000)]
Follow-up to r265036: I got these iterators mixed up
llvm-svn: 265076
Mehdi Amini [Thu, 31 Mar 2016 23:27:37 +0000 (23:27 +0000)]
clang-format the large enum definitions in LLVMBitCodes.h
Suggestion from Duncan in a review thread.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265075
Mehdi Amini [Thu, 31 Mar 2016 23:14:45 +0000 (23:14 +0000)]
Use const ref instead of value for Twine in the disk_space() API
Thanks Rui for noticing!
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265074
Peter Collingbourne [Thu, 31 Mar 2016 23:12:18 +0000 (23:12 +0000)]
ELF: Correctly handle --whole-archive for thin archives.
Differential Revision: http://reviews.llvm.org/D18669
llvm-svn: 265073
Eugene Zelenko [Thu, 31 Mar 2016 23:09:42 +0000 (23:09 +0000)]
Update release notes with list of checks added since 3.8.
Fix some checks documentation style.
Differential revision: http://reviews.llvm.org/D18582
llvm-svn: 265072
Matthias Braun [Thu, 31 Mar 2016 23:08:55 +0000 (23:08 +0000)]
lit: python3 compatibility fix
llvm-svn: 265070
Peter Collingbourne [Thu, 31 Mar 2016 23:07:50 +0000 (23:07 +0000)]
Create thin archive in GNU format to fix test on OS X.
llvm-svn: 265069
Mehdi Amini [Thu, 31 Mar 2016 23:05:26 +0000 (23:05 +0000)]
Add disk_space() to llvm::fs
Summary: Adapted from Boost::filesystem.
(This is a reapply by reverting commit r265062 and fixing the WinAPI part)
Differential Revision: http://reviews.llvm.org/D18467
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265068
Tim Shen [Thu, 31 Mar 2016 22:32:10 +0000 (22:32 +0000)]
Move asm-printer-topological-order.ll to PowerPC backend
llvm-svn: 265067
Peter Collingbourne [Thu, 31 Mar 2016 22:08:57 +0000 (22:08 +0000)]
Object: Add function for moving thin archive object buffer vector out of Archive.
Differential Revision: http://reviews.llvm.org/D18664
llvm-svn: 265066
Peter Collingbourne [Thu, 31 Mar 2016 22:08:31 +0000 (22:08 +0000)]
Object: Correctly read thin archives containing absolute paths.
Differential Revision: http://reviews.llvm.org/D18666
llvm-svn: 265065
Tim Shen [Thu, 31 Mar 2016 22:08:19 +0000 (22:08 +0000)]
[AsmPrinter] Print aliases in topological order
Print aliases in topological order, that is, for any alias a = b,
b must be printed before a. This is because on some targets (e.g. PowerPC)
linker expects aliases in such an order to generate correct TOC information.
GCC also prints aliases in topological order.
llvm-svn: 265064
Chandler Carruth [Thu, 31 Mar 2016 21:55:58 +0000 (21:55 +0000)]
Fix PR26940 where compiles times regressed massively.
Patch by Jonas Paulsson. Original description:
Bugfix in buildSchedGraph() to make -dag-maps-huge-region work properly
I found that the reduction of the maps did in fact never happen in this
test case. This was because *all* the stores / loads were made with
addresses from arguments and they thus became "unknown" stores / loads.
Fixed by removing continue statements and making sure that the test for
reduction always takes place.
Differential Revision: http://reviews.llvm.org/D18673
llvm-svn: 265063
Mehdi Amini [Thu, 31 Mar 2016 21:55:35 +0000 (21:55 +0000)]
Revert "Add disk_space() to llvm::fs"
Breaks windows bot.
This reverts commit r265050.
This reverts commit r265055.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265062
Evgeniy Stepanov [Thu, 31 Mar 2016 21:55:11 +0000 (21:55 +0000)]
Preserve blockaddress use edges in the module splitter.
"blockaddress" can not apply to an external function. All
blockaddress constant uses must belong to the same module as the
definition of the target function.
llvm-svn: 265061
David Majnemer [Thu, 31 Mar 2016 21:29:57 +0000 (21:29 +0000)]
[NVPTX] Infer __nvvm_reflect as nounwind, readnone
This patch simply mirrors the attributes we give to @llvm.nvvm.reflect
to the __nvvm_reflect libdevice call. This shaves about 30% of the code
in libdevice away because of CSE opportunities. It's also helps us
figure out that libdevice implementations of transcendental functions
don't have side-effects.
llvm-svn: 265060
Simon Atanasyan [Thu, 31 Mar 2016 21:26:23 +0000 (21:26 +0000)]
[ELF] Implement infrastructure for thunk code creation
Some targets might require creation of thunks. For example, MIPS targets
require stubs to call PIC code from non-PIC one. The patch implements
infrastructure for thunk code creation and provides support for MIPS
LA25 stubs. Any MIPS PIC code function is invoked with its address
in register $t9. So if we have a branch instruction from non-PIC code
to the PIC one we cannot make the jump directly and need to create a small
stub to save the target function address.
See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
- In relocation scanning phase we ask target about thunk creation necessity
by calling `TagetInfo::needsThunk` method. The `InputSection` class
maintains list of Symbols requires thunk creation.
- Reassigning offsets performed for each input sections after relocation
scanning complete because position of each section might change due
thunk creation.
- The patch introduces new dedicated value for DefinedSynthetic symbols
DefinedSynthetic::SectionEnd. Synthetic symbol with that value always
points to the end of the corresponding output section. That allows to
escape updating synthetic symbols if output sections sizes changes after
relocation scanning due thunk creation.
- In the `InputSection::writeTo` method we write thunks after corresponding
input section. Each thunk is written by calling `TargetInfo::writeThunk` method.
- The patch supports the only type of thunk code for each target. For now,
it is enough.
Differential Revision: http://reviews.llvm.org/D17934
llvm-svn: 265059
Peter Collingbourne [Thu, 31 Mar 2016 21:18:34 +0000 (21:18 +0000)]
ELF: Add more variants of ignored flags.
Differential Revision: http://reviews.llvm.org/D18668
llvm-svn: 265058
Chris Bieneman [Thu, 31 Mar 2016 21:17:19 +0000 (21:17 +0000)]
[CMake] Provide the ability to skip stripping when generating dSYMs
For debugging it is useful to be able to generate dSYM files but not strip the executables. This change adds the ability to skip stripping by setting COMPILER_RT_EXTERNALIZE_DEBUGINFO_SKIP_STRIP=On.
llvm-svn: 265057
Rui Ueyama [Thu, 31 Mar 2016 21:15:31 +0000 (21:15 +0000)]
Define a utility function to read -O and lto-O options.
llvm-svn: 265056
Simon Pilgrim [Thu, 31 Mar 2016 21:13:49 +0000 (21:13 +0000)]
Wdocumentation parameter fix
llvm-svn: 265055
Sanjay Patel [Thu, 31 Mar 2016 21:00:48 +0000 (21:00 +0000)]
fix typo; NFC
llvm-svn: 265054
Peter Collingbourne [Thu, 31 Mar 2016 21:00:27 +0000 (21:00 +0000)]
ELF: Add flag for controlling LTO optimization level.
Differential Revision: http://reviews.llvm.org/D18667
llvm-svn: 265053
Simon Pilgrim [Thu, 31 Mar 2016 20:57:36 +0000 (20:57 +0000)]
Fixed signed/unsigned warning
llvm-svn: 265052
Jun Bum Lim [Thu, 31 Mar 2016 20:53:47 +0000 (20:53 +0000)]
[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()
Summary:
This change will allow loads with imp-def to be clustered in machine-scheduler pass.
areMemAccessesTriviallyDisjoint() can also handle loads with imp-def.
Reviewers: mcrosier, jmolloy, t.p.northover
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18665
llvm-svn: 265051
Mehdi Amini [Thu, 31 Mar 2016 20:48:27 +0000 (20:48 +0000)]
Add disk_space() to llvm::fs
Summary: Adapted from Boost::filesystem.
Reviewers: bruno, silvas
Subscribers: tberghammer, danalbert, llvm-commits, srhines
Differential Revision: http://reviews.llvm.org/D18467
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 265050
Hal Finkel [Thu, 31 Mar 2016 20:45:00 +0000 (20:45 +0000)]
[PowerPC] Cleanup test/CodeGen/PowerPC/qpx-load-splat.ll
Removing unnecessary attributes and metadata...
llvm-svn: 265049
Sanjay Patel [Thu, 31 Mar 2016 20:40:32 +0000 (20:40 +0000)]
[x86] add memset tests to show another potential improvement
llvm-svn: 265048
Hal Finkel [Thu, 31 Mar 2016 20:39:41 +0000 (20:39 +0000)]
[PowerPC] Add a late MI-level pass for QPX load/splat simplification
Chapter 3 of the QPX manual states that, "Scalar floating-point load
instructions, defined in the Power ISA, cause a replication of the source data
across all elements of the target register." Thus, if we have a load followed
by a QPX splat (from the first lane), the splat is redundant. This adds a late
MI-level pass to remove the redundant splats in some of these cases
(specifically when both occur in the same basic block).
This optimization is scheduled just prior to post-RA scheduling. It can't happen
before anything that might replace the load with some already-computed quantity
(i.e. store-to-load forwarding).
llvm-svn: 265047
Hans Wennborg [Thu, 31 Mar 2016 20:27:30 +0000 (20:27 +0000)]
Revert r265039 "[X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr (PR27140)"
I think it might have caused these build breakages:
http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/7234/steps/build%20stage%202/logs/stdio
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/19566/steps/run%20tests/logs/stdio
llvm-svn: 265046
Simon Pilgrim [Thu, 31 Mar 2016 20:26:30 +0000 (20:26 +0000)]
[X86][SSE] Some basic tests for variable shuffles
We don't really support non-constant shuffle masks, but these tests are for cases where BUILD_VECTOR is made up from vector extracts (as well as undef/zero scalars).
llvm-svn: 265045
Ed Maste [Thu, 31 Mar 2016 20:26:30 +0000 (20:26 +0000)]
lld: accept and ignore _fbsd suffix in emulation name
Differential Revision: http://reviews.llvm.org/D18661
llvm-svn: 265044
Evgeniy Stepanov [Thu, 31 Mar 2016 20:21:31 +0000 (20:21 +0000)]
Preserve extern_weak linkage in CloneModule.
Only force "extern" linkage if the function used to be a definition
in the source module. Declarations keep their original linkage.
llvm-svn: 265043
Argyrios Kyrtzidis [Thu, 31 Mar 2016 20:18:22 +0000 (20:18 +0000)]
[index] Fix regression where ObjC method declarations may mistakenly get indexed as definition.
rdar://
25372906
llvm-svn: 265042
Chris Bieneman [Thu, 31 Mar 2016 20:03:19 +0000 (20:03 +0000)]
[CMake] Provide the ability to skip stripping when generating dSYMs
For debugging it is useful to be able to generate dSYM files but not strip the executables. This change adds the ability to skip stripping by setting LLVM_EXTERNALIZE_DEBUGINFO_SKIP_STRIP=On.
llvm-svn: 265041
Benjamin Kramer [Thu, 31 Mar 2016 19:42:04 +0000 (19:42 +0000)]
[ARM] Expand v1i64 and v2i64 ctpop.
The default is legal, which results in 'Cannot select' errors. This is
triggered during selfhost due to a recent cost model change.
llvm-svn: 265040
Hans Wennborg [Thu, 31 Mar 2016 19:26:24 +0000 (19:26 +0000)]
[X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr (PR27140)
For code such as:
void f(int, int);
void g() {
f(1, 2);
}
compiled for 32-bit X86 Linux, Clang would previously generate:
subl $12, %esp
subl $8, %esp
pushl $2
pushl $1
calll f
addl $16, %esp
addl $12, %esp
retl
This patch fixes that by merging adjacent stack adjustments in
eliminateCallFramePseudoInstr().
Differential Revision: http://reviews.llvm.org/D18627
llvm-svn: 265039
Tim Northover [Thu, 31 Mar 2016 19:19:24 +0000 (19:19 +0000)]
Diagnostics: remove dodgy handler for bitcode inlineasm diagnostics.
Whatever crash it was there to present appears to have been fixed in the
backend now, and it had the nasty side-effect of causing clang to exit(0) and
leave a .o containing goodness knows what even when an error hit.
llvm-svn: 265038
Betul Buyukkurt [Thu, 31 Mar 2016 18:41:34 +0000 (18:41 +0000)]
[PGO] Avoid instrumenting constants at value sites
Value profiling should not profile constants and/or constant
expressions when they appear as callees in call instructions.
Constant expressions form when a direct callee has bitcasts or
inttoptr(ptrtint (callee)) nests surrounding it. Value profiling
should avoid instrumenting such cases. Mostly NFC.
llvm-svn: 265037
Hans Wennborg [Thu, 31 Mar 2016 18:33:38 +0000 (18:33 +0000)]
Change eliminateCallFramePseudoInstr() to return an iterator
This will become necessary in a subsequent change to make this method
merge adjacent stack adjustments, i.e. it might erase the previous
and/or next instruction.
It also greatly simplifies the calls to this function from Prolog-
EpilogInserter. Previously, that had a bunch of logic to resume iteration
after the call; now it just continues with the returned iterator.
Note that this changes the behaviour of PEI a little. Previously,
it attempted to re-visit the new instruction created by
eliminateCallFramePseudoInstr(). That code was added in r36625,
but I can't see any reason for it: the new instructions will obviously
not be pseudo instructions, they will not have FrameIndex operands,
and we have already accounted for the stack adjustment.
Differential Revision: http://reviews.llvm.org/D18627
llvm-svn: 265036
Akira Hatanaka [Thu, 31 Mar 2016 18:32:38 +0000 (18:32 +0000)]
Fix the comment for the function added in r264998.
llvm-svn: 265035
Daniel Dunbar [Thu, 31 Mar 2016 18:22:55 +0000 (18:22 +0000)]
[lit][googletest] Handle upstream gtest output
Summary:
Upstream googletest prints "Running main() from gtest_main.cc" to stdout prior
to running tests. LLVM removed that print statement in r61540. If a user were
to use lit to run tests that use upstream googletest, however, lit
reports "Running main()" as an invalid test name.
To avoid such a failure, add an extra conditional to `formats/googletest.py`.
Also add tests to demonstrate the modified behavior.
Reviewers: abdulras, ddunbar
Subscribers: ddunbar, llvm-commits, kastiglione
Differential Revision: http://reviews.llvm.org/D18606
llvm-svn: 265034
Etienne Bergeron [Thu, 31 Mar 2016 18:12:23 +0000 (18:12 +0000)]
[clang-tidy] Add a new checker to detect missing comma in initializer list.
Summary:
This checker is able to detect missing comma in
an array of string literals.
```
const char* A[] = {
"abc",
"def" // missing comma (no compiler warnings)
"ghi",
};
```
The ratio of false-positive is reduced by restricting the
size of the array considered and the ratio of missing
comma.
To validate the quantity of false positive, the checker
was tried over LLVM and chromium code and detected these
cases:
[[ http://reviews.llvm.org/D18454 | http://reviews.llvm.org/D18454 ]]
[[https://codereview.chromium.org/
1807753002/ | https://codereview.chromium.org/
1807753002/]]
[[https://codereview.chromium.org/
1826193002/ | https://codereview.chromium.org/
1826193002/]]
[[https://codereview.chromium.org/
1805713002/ | https://codereview.chromium.org/
1805713002/]]
Reviewers: alexfh
Subscribers: LegalizeAdulthood, szdominik, xazax.hun, cfe-commits
Differential Revision: http://reviews.llvm.org/D18457
llvm-svn: 265033
Jacques Pienaar [Thu, 31 Mar 2016 17:58:55 +0000 (17:58 +0000)]
[lanai] isBrImm should accept any non-constant immediate.
isBrImm should accept any non-constant immediate. Previously it was only accepting LanaiMCExpr ones which was wrong.
Differential Revision: http://reviews.llvm.org/D18571
llvm-svn: 265032
Ehsan Amiri [Thu, 31 Mar 2016 17:47:17 +0000 (17:47 +0000)]
[PPC] basic support for Power 9 direct move instructions
http://reviews.llvm.org/D18097
Initial support does not include any patterns to generate this instructions
llvm-svn: 265031
Rong Xu [Thu, 31 Mar 2016 17:39:33 +0000 (17:39 +0000)]
[PGO] use emplace_back. NFC.
Use emplace_back instead of push_back for simplicity.
llvm-svn: 265030
Sanjay Patel [Thu, 31 Mar 2016 17:30:06 +0000 (17:30 +0000)]
[x86] use SSE/AVX ops for non-zero memsets (PR27100)
Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast
targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping
into a codegen sinkhole while trying to splat a byte into an XMM reg.
Follow-on bugs exposed by the current codegen are:
https://llvm.org/bugs/show_bug.cgi?id=27141
https://llvm.org/bugs/show_bug.cgi?id=27143
Differential Revision: http://reviews.llvm.org/D18566
llvm-svn: 265029
Valery Pykhtin [Thu, 31 Mar 2016 17:28:46 +0000 (17:28 +0000)]
[AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.
llvm-svn: 265028
Hans Wennborg [Thu, 31 Mar 2016 16:42:10 +0000 (16:42 +0000)]
More checks in win32-seh-nested-finally.ll after comment on r264966
llvm-svn: 265027
Ulrich Weigand [Thu, 31 Mar 2016 16:38:57 +0000 (16:38 +0000)]
[PowerPC] Attempt to fix fast-isel-i64offset.ll failure
The test case added in r265023 is failing on ninja-x64-msvc-RA-centos6.
Update the test to make less specific assumptions on code generation.
llvm-svn: 265026
Xinliang David Li [Thu, 31 Mar 2016 16:22:17 +0000 (16:22 +0000)]
Minor code cleanup /NFC
llvm-svn: 265025
Stephan Bergmann [Thu, 31 Mar 2016 15:42:01 +0000 (15:42 +0000)]
Don't use potentially invalidated iterator
If the lhs is evaluated before the rhs, FuncletI's operator-> can trigger the
assert(isHandleInSync() && "invalid iterator access!");
at include/llvm/ADT/DenseMap.h:1061. (Happens e.g. when compiled with GCC 6.)
Differential Revision: http://reviews.llvm.org/D18440
llvm-svn: 265024
Ulrich Weigand [Thu, 31 Mar 2016 15:37:06 +0000 (15:37 +0000)]
[PowerPC] Correctly compute 64-bit offsets in fast isel
PPCSimplifyAddress contains this code:
IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
: Type::getInt64Ty(*Context));
to determine the type to be used for an index register, if one needs
to be created. However, the "VT" here is the type of the data being
loaded or stored, *not* the type of an address. This means that if
a data element of type i32 is accessed using an index that does not
not fit into 32 bits, a wrong address is computed here.
Note that PPCFastISel is only ever used on 64-bit currently, so the type
of an address is actually *always* MVT::i64. Other parts of the code,
even in this same PPCSimplifyAddress routine, already rely on that fact.
Thus, this patch changes the code to simply unconditionally use
Type::getInt64Ty(*Context) as OffsetTy.
llvm-svn: 265023
Nemanja Ivanovic [Thu, 31 Mar 2016 15:26:37 +0000 (15:26 +0000)]
[PowerPC] Basic support for P9 atomic loads and stores
This patch corresponds to review:
http://reviews.llvm.org/D18032
This patch provides asm implementation for the following instructions:
lwat, ldat, stwat, stdat, ldmx, mcrxrx
llvm-svn: 265022
Jun Bum Lim [Thu, 31 Mar 2016 14:47:24 +0000 (14:47 +0000)]
[AArch64] Handle missing store pair opportunity
Summary:
This change will handle missing store pair opportunity where the first store
instruction stores zero followed by the non-zero store. For example, this change
will convert :
str wzr, [x8]
str w1, [x8, #4]
into:
stp wzr, w1, [x8]
Reviewers: jmolloy, t.p.northover, mcrosier
Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18570
llvm-svn: 265021
Ulrich Weigand [Thu, 31 Mar 2016 14:44:50 +0000 (14:44 +0000)]
[PowerPC] Remove incorrect use of COPY_TO_REGCLASS in fast isel
The fast isel pass currently emits a COPY_TO_REGCLASS node to convert
from a F4RC to a F8RC register class during conversion of a
floating-point number to integer. There is actually no support in the
common code instruction printers to emit COPY_TO_REGCLASS nodes, so the
PowerPC back-end has special code there to simply ignore
COPY_TO_REGCLASS.
This is correct *if and only if* the source and destination registers of
COPY_TO_REGCLASS are the same (except for the different register class).
But nothing guarantees this to be the case, and if the register
allocator does end up allocating source and destination to different
registers after all, the back-end simply generates incorrect code. I've
included a test case that shows such incorrect code generation.
However, it seems that COPY_TO_REGCLASS is actually not intended to be
used at the MI layer at all. It is used during SelectionDAG, but always
lowered to a plain COPY before emitting MI. Other back-end's fast isel
passes never emit COPY_TO_REGCLASS at all. I suspect it is simply wrong
for the PowerPC back-end to emit it here.
This patch changes the PowerPC back-end to directly emit COPY instead of
COPY_TO_REGCLASS and removes the special handling in the instruction
printers.
Differential Revision: http://reviews.llvm.org/D18605
llvm-svn: 265020