Mark Thompson [Mon, 26 Sep 2016 22:22:31 +0000 (23:22 +0100)]
st/va: Fix vaSyncSurface with no outstanding operation
Fixes crash if the application doesn't do what the state tracker expects.
Reviewed-by: Christian König <christian.koenig@amd.com>
Timothy Arceri [Tue, 27 Sep 2016 02:00:51 +0000 (12:00 +1000)]
glsl: remove remaining tabs in glsl_parser_extras.h
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Ilia Mirkin [Mon, 29 Aug 2016 00:03:24 +0000 (20:03 -0400)]
st/mesa: enable ARB_ES3_2_compatibility when enough available
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sun, 28 Aug 2016 19:55:44 +0000 (15:55 -0400)]
st/mesa: enable GL_ANDROID_extension_pack_es31a when available
For now that's never since advanced blend hasn't been piped through.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Sun, 25 Sep 2016 12:50:25 +0000 (22:50 +1000)]
glsl: move some uniform linking code to new link_assign_uniform_storage()
This makes link_assign_uniform_locations() easier to follow.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 25 Sep 2016 12:50:24 +0000 (22:50 +1000)]
glsl: move some uniform linking code to new link_setup_uniform_remap_tables()
This makes link_assign_uniform_locations() easier to follow.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sat, 18 Jun 2016 06:18:17 +0000 (16:18 +1000)]
i965: create populate key functions for tcs and tes
These will be used by the on disk shader cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 17 Jun 2016 12:02:43 +0000 (22:02 +1000)]
i965: make gs key generation helper available to shader cache
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 14 Apr 2016 06:48:39 +0000 (16:48 +1000)]
glsl: use reproducible name for lowered const arrays
Otherwise we can end up with mismatching names between the cached
binary and the cached metadata.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Carl Worth [Thu, 14 Apr 2016 00:54:38 +0000 (10:54 +1000)]
i965: make vs and fs key generation helpers available to shader cache
Signed-off-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Carl Worth [Thu, 12 Mar 2015 00:31:11 +0000 (17:31 -0700)]
glsl: Prepare standalone compiler to be able to use parameter lists
As part of the shader-cache work an upcoming change will add new
references to _mesa_add_parameter and _mesa_new_parameter_list from
the glsl code. To prepare for that, and to allow the standalone
glsl_compiler to still link, here we add mesa/program/prog_parameter.c
to the libglsl_util sources.
Then, in order to get *that* to work, we also add to stubs to
standalone_scaffolding:
_mesa_program_state_flags
_mesa_program_state_string
These functions aren't actually used by the two functions in
prog_parameter.c that we are actually calling. They are used in other
functions in the same file. So we don't care what the implementation
of these stubs is, (they won't be called by glsl_compiler). We just
need the stubs present so that it can link.
Signed-off-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Samuel Pitoiset [Mon, 26 Sep 2016 19:50:26 +0000 (21:50 +0200)]
nv50/ir: fix comments about instructions info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Wed, 31 Aug 2016 21:44:01 +0000 (17:44 -0400)]
mesa/st: support lowering multi-planar YUV
Support multi-planar YUV for external EGLImage's (currently just in the
dma-buf import path) by lowering to multiple texture fetch's for each
plane and CSC in shader.
There was some discussion of alternative approaches for tracking the
additional UV or U/V planes:
https://lists.freedesktop.org/archives/mesa-dev/2016-September/127832.html
They all seemed worse than pipe_resource::next
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 8 Sep 2016 18:57:25 +0000 (14:57 -0400)]
mesa/st: add nir pass to lower tex_src_plane
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 2 Sep 2016 14:42:22 +0000 (10:42 -0400)]
mesa/st: add lowering pass for YUV samplers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Sirisha Gandikota [Tue, 20 Sep 2016 22:59:28 +0000 (15:59 -0700)]
aubinator: Fix the decoding of values that span two Dwords
Fixed the way the values that span two Dwords are decoded.
Based on the start and end indices of the field, the Dwords
are fetched and decoded accordingly.
v2: rename dw to qw in gen_field_iterator_next
and remove extra white space (Anuj)
v3: change all instances of dw to qw (Anuj)
Earlier, 64-bit fields (such as most pointers on Gen8+)
weren't decoded correctly. gen_field_iterator_next seemed
to walk one DWord at a time, sets v.dw, and then passes it
to field(). So, even though field() takes a uint64_t, we're
passing it a uint32_t (which gets promoted, so the top 32
bits will always be zero). This seems pretty bogus... (Ken)
Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Pitoiset [Wed, 14 Sep 2016 18:37:12 +0000 (20:37 +0200)]
nvc0: allow to force compiling programs in debug build
This adds a new envvar called NV50_PROG_CHIPSET which allows to
compile shaders with a different target, especially useful for
shader-db.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 18:37:13 +0000 (20:37 +0200)]
nv50/ir: drop unused NVISA_XXX_CHIPSET constants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 14 Sep 2016 18:37:11 +0000 (20:37 +0200)]
gallium/util: make use of strtol() in debug_get_num_option()
This allows to use hexadecimal numbers which are automatically
detected by strtol() when the base is 0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Glenn Kennard [Sun, 3 Jan 2016 22:47:18 +0000 (23:47 +0100)]
r600g: Add support for PK2H/UP2H
Based off of Ilia's original patch, but with output values replicated so
that it matches the TGSI semantics.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Sun, 25 Sep 2016 12:50:28 +0000 (22:50 +1000)]
i965: stop passing stage as a function parameter
We already pass the shader so we can just get the stage from this.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Nayan Deshmukh [Sun, 25 Sep 2016 14:12:16 +0000 (19:42 +0530)]
aubinator: fix resource leak
CovID: 1373370
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emilio Cobos Álvarez [Fri, 23 Sep 2016 00:24:00 +0000 (18:24 -0600)]
osmesa: Unbind the current context when given a null context and buffer.
This is needed to be consistent with other drivers.
Signed-off-by: Emilio Cobos Álvarez <me@emiliocobos.me>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 22 Sep 2016 22:10:02 +0000 (16:10 -0600)]
st/mesa: small optimization in swizzle_swizzle()
Usually, there's no user-specified texture swizzle so we can optimize
the swizzle_swizzle() function and skip the loop/switch.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 22 Sep 2016 22:03:40 +0000 (16:03 -0600)]
st/mesa: fix swizzle issue in st_create_sampler_view_from_stobj()
Some demos, like Heaven, were creating and destroying a large number
of sampler views because of a swizzle issue.
Basically, we compute the sampler view's swizzle by examining the
texture format, user swizzle, depth mode, etc. Later, during validation
we recompute that swizzle (in case something like depth mode changes)
and see if it matches the view's swizzle.
In the case of PIPE_FORMAT_RGTC2_UNORM, get_texture_format_swizzle
returned SWIZZLE_XYZW but the u_sampler_view_default_template() function
was setting the sampler view's swizzle to SWIZZLE_XY01. This mismatch
caused the validation step to always "fail" so we'd destroy the old
sampler view and create a new one.
By removing the conditional, the sampler view's swizzle and the computed
texture swizzle match and validation "passes". When creating a new sampler
view, we always want to use the texture swizzle which we just computed.
Fixes VMware issue 1733389.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 20 Sep 2016 23:22:42 +0000 (17:22 -0600)]
svga: set PIPE_BIND_DEPTH_STENCIL flag for new resources when possible
When we create a depth/stencil texture, also check if we can render to
it and set the PIPE_BIND_DEPTH_STENCIL flag. We were previously doing
this for color textures (PIPE_BIND_RENDER_TARGET).
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 22 Sep 2016 15:15:20 +0000 (09:15 -0600)]
svga: don't special case caps for SVGA3D_R32_FLOAT
This may have been needed years ago during development, but not now.
Prevents some regressions after introducing the next patch.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Fri, 23 Sep 2016 14:34:11 +0000 (08:34 -0600)]
svga: use new adjust_z_layer() helper in svga_pipe_blit.c
To handle z/layer fix-ups for blitting and copying. Note that we weren't
doing this properly in svga_blit() before.
Also, remove redundant stex, dtex assignments.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 20 Sep 2016 23:36:32 +0000 (17:36 -0600)]
svga: simplify/improve the format compatibility check for region copies
The util_is_format_compatible() function didn't quite do what we wanted
for vgpu10. This check is more flexible and allows copies between
formats such as R32G32B32A32_FLOAT and R32G32B32A32_INT.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 20 Sep 2016 23:01:20 +0000 (17:01 -0600)]
svga: add const qualifier on svga_translate_format()
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 22 Sep 2016 18:26:55 +0000 (12:26 -0600)]
svga: eliminate unneeded gotos in svga_validate_surface_view()
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Neha Bhende [Fri, 16 Sep 2016 21:53:01 +0000 (14:53 -0700)]
svga: disable srgb format related code from svga_blit()
With latest mesa and latest piglit tests srgb<->linear conversion
is not required as per GL4.4 rules
See commit
b662c70aeab6a92751514f30719c13a6de253b40.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Timothy Arceri [Sat, 24 Sep 2016 00:17:26 +0000 (10:17 +1000)]
Revert "glsl: move xfb BufferStride into gl_transform_feedback_info"
This reverts commit
f5a6aab4031bc4754756c1773411728ad9a73381.
This broke some tests. It seems gl_transform_feedback_info gets memset
to 0 so we were losing the values in BufferStride before we used them.
Kenneth Graunke [Wed, 12 Nov 2014 06:32:27 +0000 (22:32 -0800)]
glsl: Delete linker stuff relating to built-in functions.
Now that we generate built-in functions inline, there's no need to link
against the built-in shader, and no built-in prototypes to consider.
This lets us delete a bunch of code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by; Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Mon, 19 Sep 2016 06:00:33 +0000 (23:00 -0700)]
glsl: Delete ftransform support from builtin_functions.cpp.
This is now handled directly by ast_function.cpp.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by; Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 31 May 2014 06:52:22 +0000 (23:52 -0700)]
glsl: Immediately inline built-ins rather than generating calls.
In the past, we imported the prototypes of built-in functions, generated
calls to those, and waited until link time to resolve the calls and
import the actual code for the built-in functions.
This severely limited our compile-time optimization opportunities: even
trivial functions like dot() were represented as function calls. We
also had no way of reasoning about those calls; they could have been
1,000 line functions with side-effects for all we knew.
Practically all built-in functions are trivial translations to
ir_expression opcodes, so it makes sense to just generate those inline.
Since we eventually inline all functions anyway, we may as well just do
it for all built-in functions.
There's only one snag: built-in functions that refer to built-in global
variables need those remapped to the variables in the shader being
compiled, rather than the ones in the built-in shader. Currently,
ftransform() is the only function matching those criteria, so it seemed
easier to just make it a special case.
On Skylake:
total instructions in shared programs:
12023491 ->
12024010 (0.00%)
instructions in affected programs: 77595 -> 78114 (0.67%)
helped: 97
HURT: 309
total cycles in shared programs:
137239044 ->
137295498 (0.04%)
cycles in affected programs:
16714026 ->
16770480 (0.34%)
helped: 4663
HURT: 4923
while these statistics are in the wrong direction, the number of
hurt programs is small (309 / 41282 = 0.75%), and I don't think
anything can be done about it. A change like this significantly
alters the order in which optimizations are performed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by; Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 21 Sep 2016 09:03:10 +0000 (02:03 -0700)]
glsl: Check TCS barrier restrictions at ast_to_hir time, not link time.
We want to check prior to optimization - otherwise we might fail to
detect cases where barrier() is in control flow which is always taken
(and therefore gets optimized away).
We don't currently loop unroll if there are function calls inside;
otherwise we might have a problem detecting barrier() in loops that
get unrolled as well.
Tapani's switch handling code adds a loop around switch statements, so
even with the mess of if ladders, we'll properly reject it.
Enforcing these rules at compile time makes more sense more sense than
link time. Doing it at ast-to-hir time (rather than as an IR pass)
allows us to emit an error message with proper line numbers.
(Otherwise, I would have preferred the IR pass...)
Fixes spec/arb_tessellation_shader/compiler/barrier-switch-always.tesc.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by; Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Fri, 23 Sep 2016 03:05:20 +0000 (13:05 +1000)]
glsl: move xfb BufferStride into gl_transform_feedback_info
It makes more sense to have this here where we store the other values
from xfb qualifiers. The struct it was previously part of is now only
used to store values that come from the api.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Dylan Baker [Fri, 23 Sep 2016 19:10:08 +0000 (12:10 -0700)]
Revert "mapi: export all GLES 3.2 functions in libGLESv2.so"
This reverts commit
e66a2b879b73bf48800fec7353dafe8fc693ecdb.
Which breaks the scons build in an interesting way, particularly when
BlendBarrier and PrimitiveBoundingBox are added to static_data.py's
functions list. This seems to be related to the fact that the unsuffixed
names are only in GLES3.2, but Desktop GL only has suffixed versions.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Adam Jackson [Wed, 21 Sep 2016 13:13:36 +0000 (09:13 -0400)]
i965: Enable EGL_KHR_gl_texture_3D_image
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Adam Jackson [Wed, 21 Sep 2016 13:11:26 +0000 (09:11 -0400)]
i915: Enable EGL_KHR_gl_texture_3D_image
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Nicolas Koch [Tue, 20 Sep 2016 15:37:36 +0000 (17:37 +0200)]
anv: Check for VK_WHOLE_SIZE in anv_CmdFillBuffer
From the Vulkan spec:
Size is the number of bytes to fill, and must be either a multiple of 4,
or VK_WHOLE_SIZE to fill the range from offset to the end of the buffer.
If VK_WHOLE_SIZE is used and the remaining size of the buffer is not a
multiple of 4, then the nearest smaller multiple is used.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Thu, 22 Sep 2016 22:04:25 +0000 (01:04 +0300)]
anv: get rid of duplicated values from gen_device_info
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 22 Sep 2016 21:41:23 +0000 (00:41 +0300)]
i965: get rid of duplicated values from gen_device_info
Now that we have gen_device_info mutable, we can update its values and drop
all copies we had in brw_context.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 22 Sep 2016 11:58:11 +0000 (14:58 +0300)]
intel/i965: make gen_device_info mutable
Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).
This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Wed, 7 Sep 2016 04:28:19 +0000 (14:28 +1000)]
gallium: remove unused PIPE_CC_GCC_VERSION
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Timothy Arceri [Wed, 7 Sep 2016 04:28:20 +0000 (14:28 +1000)]
util: remove Sun C Compiler support
Support for this compiler was dropped in
51564f04b77e6
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Ilia Mirkin [Fri, 16 Sep 2016 19:43:31 +0000 (15:43 -0400)]
st/mesa: turn on OES_viewport_array when dependencies are met
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 16 Sep 2016 17:52:18 +0000 (13:52 -0400)]
mesa: add implementations for new float depth functions
This just up-converts them to doubles. Not great, but this is what all
the other variants also do.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ilia Mirkin [Fri, 16 Sep 2016 17:43:30 +0000 (13:43 -0400)]
mesa: move ARB_viewport_array params to a GLES 3.1-accessible section
This is needed for GL_OES_viewport_array.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ilia Mirkin [Fri, 16 Sep 2016 17:53:03 +0000 (13:53 -0400)]
mesa: add GL_OES_viewport_array to the extension string
The expectation is that drivers will set this based on
OES_geometry_shader and ARB_viewport_array support. This is a separate
enable on the same reasoning as for OES_texture_cube_map_array.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ilia Mirkin [Fri, 16 Sep 2016 17:59:27 +0000 (13:59 -0400)]
glsl: add OES_viewport_array enables and use them to expose gl_ViewportIndex
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ilia Mirkin [Fri, 16 Sep 2016 17:38:36 +0000 (13:38 -0400)]
mesa: add new entrypoints for GL_OES_viewport_array
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Dylan Baker [Thu, 22 Sep 2016 18:30:42 +0000 (11:30 -0700)]
mapi: export all GLES 3.2 functions in libGLESv2.so
See commit
5921f372c89a68fac6ddefc009442721d9df4db2 for the rational of
this commit.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dylan Baker [Thu, 22 Sep 2016 18:38:28 +0000 (11:38 -0700)]
mapi: sort static_data.py functions
Sorted by vim's builtin "sort i" (keeping the sorting case insensitive)
v2:
- uses case insensitive sorting (Ken)
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dylan Baker [Thu, 22 Sep 2016 17:58:45 +0000 (10:58 -0700)]
mapi: retab static_data.py to be consistent
This file currently uses a mixture of 3 and 4 space indent. I have
changed it all to 4 space indent, matching the settings in
$ROOT/.editorconfig.
This was generated with sed:
sed -i -e 's@^ "@ "@g'
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Mon, 19 Sep 2016 16:14:18 +0000 (17:14 +0100)]
spirv: fix AtomicLoad/Store on images
OpAtomicLoad/Store should have pointer to images just like the rest of the
atomic operators. These couple of lines were poorly copied from the
ssbo/shared_vars cases (the only ones currently tests by the CTS).
Fixes
2afb950161f8 ("spirv/nir: Add support for OpAtomicLoad/Store")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Wed, 7 Sep 2016 02:45:51 +0000 (19:45 -0700)]
nir: Allow opt_peephole_sel to be more aggressive in flattening IFs.
VC4 was running into a major performance regression from enabling control
flow in the glmark2 conditionals test, because of short if statements
containing an ffract.
This pass seems like it was was trying to ensure that we only flattened
IFs that should be entirely a win by guaranteeing that there would be
fewer bcsels than there were MOVs otherwise. However, if the number of
ALU ops is small, we can avoid the overhead of branching (which itself
costs cycles) and still get a win, even if it means moving real
instructions out of the THEN/ELSE blocks.
For now, just turn on aggressive flattening on vc4. i965 will need some
tuning to avoid regressions. It does looks like this may be useful to
replace freedreno code.
Improves glmark2 -b conditionals:fragment-steps=5:vertex-steps=0 from 47
fps to 95 fps on vc4.
vc4 shader-db:
total instructions in shared programs: 101282 -> 99543 (-1.72%)
instructions in affected programs: 17365 -> 15626 (-10.01%)
total uniforms in shared programs: 31295 -> 31172 (-0.39%)
uniforms in affected programs: 3580 -> 3457 (-3.44%)
total estimated cycles in shared programs: 225182 -> 223746 (-0.64%)
estimated cycles in affected programs: 26085 -> 24649 (-5.51%)
v2: Update shader-db output.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Kenneth Graunke [Wed, 21 Sep 2016 18:51:43 +0000 (11:51 -0700)]
docs: Mark ES 3.2 "all done" for i965/gen9+.
Kenneth Graunke [Wed, 21 Sep 2016 18:49:24 +0000 (11:49 -0700)]
docs: Add ES 3.2 to release notes.
Brian Paul [Tue, 20 Sep 2016 22:05:48 +0000 (16:05 -0600)]
gallium/util: add comment on util_is_format_compatible()
From reading the code, it's not obvious what is src/dest compatible.
The list of a->b copy-compatible formats comes from Jose's original
check-in message, with some format name updates.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Fri, 16 Sep 2016 21:22:51 +0000 (15:22 -0600)]
svga: minor simplification in svga_validate_surface_view()
Get rid of unneeded local var.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 19 Sep 2016 22:34:17 +0000 (16:34 -0600)]
svga: remove disable_shader debug variable
Never used, AFAIK.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Kenneth Graunke [Wed, 21 Sep 2016 03:33:54 +0000 (20:33 -0700)]
i965: Enable ES 3.2 on Skylake.
It's already advertised because the version.c extension checks are
fulfilled, but we didn't actually claim support, so trying to create
a ES 3.2 context would fail.
It's all done, and the CTS results look good, so let's turn it on.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Wed, 14 Sep 2016 04:10:13 +0000 (21:10 -0700)]
nir/spirv/glsl450: Add support for the InterpolateAt opcodes
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Wed, 14 Sep 2016 04:09:28 +0000 (21:09 -0700)]
nir/spirv: Claim support for SampleRateShading
We already support all of the decorations that require this capability.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Fri, 16 Sep 2016 02:47:49 +0000 (19:47 -0700)]
nir/spirv: Bring back the spirv2nir helper binary
This was something that I wrote in the early days of the spirv_to_nir code
but deleted once we had a real driver. However, in the absence of a
shader_runner equivalent, it's extremely useful for debugging the
spirv_to_nir code so let's bring it back.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chuanbo Weng [Tue, 13 Sep 2016 17:07:18 +0000 (01:07 +0800)]
i965: implement querying __DRI_IMAGE_ATTRIB_OFFSET.
Implement querying this attribute in intelImageExtension and bump
version of intelImageExtension.
Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chuanbo Weng [Tue, 13 Sep 2016 17:07:10 +0000 (01:07 +0800)]
egl: return corresponding offset of EGLImage instead of 0.
The offset should not always be 0. For example, if EGLImage is
created from a 2D texture with EGL_GL_TEXTURE_LEVEL=1, then the
offset should be the actual start of miplevel 1 in bo.
v2: Add version check of __DRIimageExtension implementation
(Suggested by Axel Davy).
v3: Don't add version check of __DRIimageExtension implementation.
Set the offset only when queryImage() succeeds. (Suggested by Emil
Velikov)
Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
[Emil Velikov: coding style fixes]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Chuanbo Weng [Tue, 13 Sep 2016 17:07:02 +0000 (01:07 +0800)]
dri: add offset attribute and bump version of EGLImage extensions.
Offset is useful for buffer sharing with other components, so add
it to queryImage attributes.
Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 16 Sep 2016 04:43:18 +0000 (21:43 -0700)]
i965/ir: Test thread dispatch packing assumptions.
Not [originally] intended for upstream. Should cause a GPU hang if
some thread is executed with a non-contiguous dispatch mask breaking
assumptions of brw_stage_has_packed_dispatch(). Doesn't cause any
CTS, DEQP or Piglit regressions, while replacing
brw_stage_has_packed_dispatch() with a dummy implementation that
unconditionally returns true on top of this patch causes multiple GPU
hangs.
v2: Refactor into a separate function instead of emitting the test
code directly from emit_nir_code(), drop VEC4 test and clean up
slightly for upstream. (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 16 Sep 2016 00:24:10 +0000 (17:24 -0700)]
i965/ir: Pass identity mask to brw_find_live_channel() in the packed dispatch case.
This avoids emitting a few extra instructions required to take the
dispatch mask into account when it's known to be tightly packed.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 16 Sep 2016 00:20:23 +0000 (17:20 -0700)]
i965/ir: Skip eliminate_find_live_channel() for stages with sparse thread dispatch.
The eliminate_find_live_channel optimization eliminates
FIND_LIVE_CHANNEL instructions in cases where control flow is known to
be uniform, and replaces them with 'MOV 0', which in turn unblocks
subsequent elimination of the BROADCAST instruction frequently used on
the result of FIND_LIVE_CHANNEL. This is however not correct in
per-sample fragment shader dispatch because the PSD can dispatch a
fully unlit sample under certain conditions. Disable the optimization
in that case.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
v2: Add devinfo argument to brw_stage_has_packed_dispatch() to
implement hardware generation check.
Jason Ekstrand [Wed, 14 Sep 2016 22:09:33 +0000 (15:09 -0700)]
i965/fs: Take Dispatch/Vector mask into account in FIND_LIVE_CHANNEL
On at least Sky Lake, ce0 does not contain the full story as far as enabled
channels goes. It is possible to have completely disabled channels where
the corresponding bits in ce0 are 1. In order to get the correct execution
mask, you have to mask off those channels which were disabled from the
beginning by taking the AND of ce0 with either sr0.2 or sr0.3 depending on
the shader stage. Failure to do so can result in FIND_LIVE_CHANNEL
returning a completely dead channel.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: Francisco Jerez <currojerez@riseup.net>
[ Francisco Jerez: Fix a couple of typos, add mask register type
assertion, clarify reason why ce0 can have bits set for disabled
channels, clarify that this may only be a problem when thread
dispatch doesn't pack channels tightly in the SIMD thread. Apply
same treatment to Align16 path. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Wed, 14 Sep 2016 22:09:32 +0000 (15:09 -0700)]
i965/reg: Make brw_sr0_reg take a subnr and return a vec1 reg
The state register sr0 is really a collection of dwords not a SIMD8
anything. It's much more convenient for brw_sr0_reg to return the
particular dword you're looking for rather than a giant blob you have to
massage into what you want.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
[ Francisco Jerez: Trivial simplification of brw_ud1_reg(). ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Lionel Landwerlin [Wed, 7 Sep 2016 16:28:44 +0000 (17:28 +0100)]
anv: pipeline: use correct number of thread for compute
Reproduces this commit :
commit
0fb85ac08d61d365e67c8f79d6955e9f89543560
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon Jun 6 21:37:34 2016 -0700
i965: Use the correct number of threads for compute shaders.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Wed, 7 Sep 2016 16:32:49 +0000 (17:32 +0100)]
anv: allocator: correct scratch space for haswell
This reproduces this commit :
commit
2213ffdb4bb79856f0556bdf2bfd4bdf57720232
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon Jun 6 21:37:34 2016 -0700
i965: Allocate scratch space for the maximum number of compute threads.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Wed, 7 Sep 2016 16:19:35 +0000 (17:19 +0100)]
anv: device: calculate compute thread numbers using subslices numbers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nicolai Hähnle [Thu, 15 Sep 2016 10:17:56 +0000 (12:17 +0200)]
gallivm: support negation on 64-bit integers
This should be analogous to 32-bit integers.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Fri, 10 Jun 2016 02:11:01 +0000 (12:11 +1000)]
radeonsi: prepare 64-bit integer support. (v2)
v2:
- no PIPE_CAP_INT64 yet
- emit DIV/MOD without the divide-by-zero workaround
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 9 Jun 2016 00:19:49 +0000 (10:19 +1000)]
gallivm/llvmpipe: prepare support for ARB_gpu_shader_int64.
This enables 64-bit integer support in gallivm and
llvmpipe.
v2: add conversion opcodes.
v3:
- PIPE_CAP_INT64 is not there yet
- restrict DIV/MOD defaults to the CPU, as for 32 bits
- TGSI_OPCODE_I2U64 becomes TGSI_OPCODE_U2I64
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 9 Jun 2016 00:18:42 +0000 (10:18 +1000)]
tgsi/softpipe: prepare ARB_gpu_shader_int64 support. (v3)
This adds all the opcodes to tgsi_exec for softpipe to use.
v2: add conversion opcodes.
v3:
- no PIPE_CAP_INT64 yet
- change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 9 Jun 2016 00:16:22 +0000 (10:16 +1000)]
gallium/tgsi: add support for 64-bit integer immediates.
This adds support to TGSI for 64-bit integer immediates.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 9 Jun 2016 00:14:51 +0000 (10:14 +1000)]
gallium: add opcode and types for 64-bit integers. (v3)
This just adds the basic support for 64-bit opcodes,
and the new types.
v2: add conversion opcodes.
add documentation.
v3:
- make docs more consistent
- change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kenneth Graunke [Mon, 30 Nov 2015 23:47:13 +0000 (15:47 -0800)]
i965: Rename intelScreen to screen.
"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Tue, 1 Dec 2015 00:04:08 +0000 (16:04 -0800)]
i965: Rename __DRIScreen pointers to "dri_screen".
I want to use "screen" as the variable name for a struct intel_screen
pointer. This means that we can't use it for __DRIscreen pointers.
Sometimes we called it "screen", sometimes "sPriv", sometimes
"driScrnPriv", and sometimes "psp" (Pointer to Screen Private?).
The last one is particularly confusing because we use "psp" to refer to
the Gen4 PIPELINED_STATE_POINTERS packet as well.
Let's be consistent. "dri_screen" is clear, and it's not used often
enough that I'm worried about the verbosity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Dylan Baker [Mon, 19 Sep 2016 22:36:09 +0000 (15:36 -0700)]
mesa: Implement ARB_shader_viewport_layer_array for i965
This extension is a combination of AMD_vertex_shader_viewport_index and
AMD_vertex_shader_layer, making it rather trivial to implement.
For gallium I *think* this needs a new cap because of the addition of
support in tessellation evaluation shaders, and since I don't have any
hardware to test it on, I've left that for someone else to wire up.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Leo Liu [Tue, 20 Sep 2016 14:09:23 +0000 (10:09 -0400)]
radeon/vce: add firmware support for version 52.8.3
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Indrajit Das [Thu, 15 Sep 2016 05:01:15 +0000 (10:31 +0530)]
st/omx/dec/h265: Correct the timestamping
(derived from commit
3b6bda665a5a890f2c98e19d2939d7de92b8cb4c)
v2: fix the tabs(Leo)
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nishanth Peethambaran <nishanth.peethambaran@amd.com>
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Lionel Landwerlin [Fri, 9 Sep 2016 10:22:59 +0000 (11:22 +0100)]
aubinator: add a custom handler for immediate register load
Transforming this :
0x00c77084: 0x11000001: MI_LOAD_REGISTER_IMM
0x00c77088: 0x0000b020 : Dword 1
Register Offset: 0x0000b020
0x00c7708c: 0x00880038 : Dword 2
Data DWord: 8912952
Into this:
0x007880f0: 0x11000001: MI_LOAD_REGISTER_IMM
0x007880f4: 0x0000b020 : Dword 1
Register Offset: 0x0000b020
0x007880f8: 0x00080040 : Dword 2
Data DWord: 524352
register L3CNTLREG2 (0xb020) : 0x80040
SLM Enable: 0
URB Allocation: 32
URB Low Bandwidth: 0
RO Allocation: 32
RO Low Bandwidth: 0
DC Allocation: 0
DC Low Bandwidth: 0
v2: Drop unused arguments (Sirisha)
Print out register name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Nayan Deshmukh [Tue, 20 Sep 2016 04:52:12 +0000 (10:22 +0530)]
st/va: flush the context before calling flush_frontbuffer(v2)
so that the texture is rendered to back buffer before calling
flush_frontbuffer and can be copied to a different buffer in
the function
v2: change comment style
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Nayan Deshmukh [Tue, 20 Sep 2016 04:52:11 +0000 (10:22 +0530)]
st/vdpau: flush the context before calling flush_frontbuffer
so that the texture is rendered to back buffer before calling
flush_frontbuffer and can be copied to a different buffer in
the function
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Nayan Deshmukh [Tue, 20 Sep 2016 04:52:10 +0000 (10:22 +0530)]
vl/dri3: handle the case of different GPU(v4.2)
In case of prime when rendering is done on GPU other then the
server GPU, use a seprate linear buffer for each back buffer
which will be displayed using present extension.
v2: Use a seprate linear buffer for each back buffer (Michel)
v3: Change variable names and fix coding style (Leo and Emil)
v4: Use PIPE_BIND_SAMPLER_VIEW for back buffer in case when
a seprate linear buffer is used (Michel)
v4.1: remove empty line
v4.2: destroy the context and handle the case when
create_context fails (Emil)
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Ilia Mirkin [Wed, 14 Sep 2016 23:16:43 +0000 (19:16 -0400)]
st/vdpau: fix argument type to vlVdpOutputSurfaceDMABuf
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tim Rowley [Mon, 12 Sep 2016 18:08:12 +0000 (13:08 -0500)]
swr: [rasterizer core] Better thread destruction
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Fri, 9 Sep 2016 21:44:21 +0000 (16:44 -0500)]
swr: [rasterizer jitter] Fix missing end-of-file newline
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Tue, 6 Sep 2016 17:36:02 +0000 (12:36 -0500)]
swr: [rasterizer core] Add macros for mapping ArchRast to buckets
Switch all RDTSC_START/STOP macros to use AR_BEGIN/END macros.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Kenneth Graunke [Thu, 15 Sep 2016 09:10:23 +0000 (02:10 -0700)]
glsl: Skip "unsized arrays aren't allowed" check for TCS/TES/GS vars.
Fixes ESEXT-CTS.draw_elements_base_vertex_tests.AEP_shader_stages and
ESEXT-CTS.texture_cube_map_array.texture_size_tesselation_con_sh.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 18 Sep 2016 21:48:05 +0000 (23:48 +0200)]
nvc0: get rid of nvc0_stage_sampler_states_bind_range()
Same thing as nvc0_stage_set_sampler_views_range().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 18 Sep 2016 21:48:04 +0000 (23:48 +0200)]
nvc0: get rid of nvc0_stage_set_sampler_views_range()
This function was quite similar to nvc0_stage_set_sampler_views()
and I don't see any reasons to not remove it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>