Ada: Remove debug line number for DECL_IGNORED_P functions

It was pointed out in PR101598 to be inappropriate, that
ignored Ada decls receive the source line number which was
recorded in the function decl's DECL_SOURCE_LOCATION.
Therefore set all front-end-generated Ada decls with
DECL_IGNORED_P to UNKNOWN_LOCATION.

2021-08-11  Bernd Edlinger  <bernd.edlinger@hotmail.de>

PR debug/101598
* gcc-interface/trans.c (Subprogram_Body_to_gnu): Set the
DECL_SOURCE_LOCATION of DECL_IGNORED_P gnu_subprog_decl to
UNKNOWN_LOCATION.

compiler: don't crash on a, b := int(0)

Fixes PR go/101851

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/341330

Extend ldexp{s,d}f3 to vscalefs{s,d} when TARGET_AVX512F and TARGET_SSE_MATH.

gcc/ChangeLog:

PR target/98309
* config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
when TARGET_AVX512F and TARGET_SSE_MATH.

gcc/testsuite/ChangeLog:

PR target/98309
* gcc.target/i386/pr98309-1.c: New test.
* gcc.target/i386/pr98309-2.c: New test.

gcc.dg/uninit-pred-9_b.c: Xfail for CRIS too

Adding to the growing list, for autotester accounting purposes.

FWIW I see this fails for m68k too:
https://gcc.gnu.org/pipermail/gcc-testresults/2021-August/712395.html
and moxie:
https://gcc.gnu.org/pipermail/gcc-testresults/2021-August/712389.html
and pru:
https://gcc.gnu.org/pipermail/gcc-testresults/2021-August/712366.html

testsuite:
PR middle-end/101674
* gcc.dg/uninit-pred-9_b.c: Xfail for cris-*-* too.

Daily bump.

openmp: Fix up cp/parser.c build with GCC 4.8 to 6

Christophe Lyon reported that cp/parser.c no longer compiles with
GCC 4.8.5 after my recent OpenMP changes.
A goto out; there crosses odsd variable declaration, and odsd has
a vec<...> member where vec has = default; default constructor
and gcc before r7-2822-gd0b0fbd9fce2f30a82558bf2308b3a7b56c2f364
treated that as error.

Fixed by moving the declaration earlier before the goto.

Tested on x86_64-linux with GCC 4.8.5 system gcc, committed to trunk
as obvious.

2021-08-10  Jakub Jelinek  <jakub@redhat.com>

* parser.c (cp_parser_member_declaration): Move odsd declaration
before cp_parser_using_declaration call to avoid errors with
GCC 4.8 to 6.

mklog: support '-b c/101343' format.

contrib/ChangeLog:

* mklog.py: Support additional PRs without PR prefix.

gfortran: Fix in-build-tree testing [PR101305, PR101660]

ISO_Fortran_binding.h is written in the build dir - hence, a previous commit
added it as include directory for in-build-tree testing.  However,
it turned out that -I$specdir/libgfortran interferes with reading .mod files
as they are then no longer regareded as intrinsic modules.  Solution: Create
an extra include/ directory in the libgfortran build dir and copy
ISO_Fortran_binding.h to that directory.  As -B$specdir/libgfortran already
causes gfortran to read that include subdirectory, the -I flag is no longer
needed.

PR libfortran/101305
PR fortran/101660
PR testsuite/101847

libgfortran/ChangeLog:

* Makefile.am (ISO_Fortran_binding.h): Create include/ in the build dir
and copy the include file to it.
(clean-local): Add for removing the 'include' directory.
* Makefile.in: Regenerate.

gcc/testsuite/ChangeLog:

* lib/gfortran.exp (gfortran_init): Remove -I$specpath/libgfortran
from the string used to set GFORTRAN_UNDER_TEST.

Enable gcc.target/i386/pr88531-1a.c for all targets

PR tree-optimization/101809
* gcc.target/i386/pr88531-1a.c: Enable for all targets.

i386: Allow some V32HImode and V64QImode permutations even without AVX512BW [PR80355]

When working on the PR, I've noticed we generate terrible code for
V32HImode or V64QImode permutations for -mavx512f -mno-avx512bw.
Generally we can't do much with such permutations, but since PR68655
we can handle at least some, those expressible using V16SImode or V8DImode
permutations, but that wasn't reachable, because ix86_vectorize_vec_perm_const
didn't even try, it said without TARGET_AVX512BW it can't do anything, and
with it can do everything, no d.testing_p attempts.

This patch makes it try it for TARGET_AVX512F && !TARGET_AVX512BW.

The first hunk is to avoid ICE, expand_vec_perm_even_odd_1 asserts d->vmode
isn't V32HImode because expand_vec_perm_1 for AVX512BW handles already
all permutations, but when we let it through without !TARGET_AVX512BW,
expand_vec_perm_1 doesn't handle it.

If we want, that hunk can be dropped if we implement in
expand_vec_perm_even_odd_1 and its helper the even permutation as
vpmovdw + vpmovdw + vinserti64x4 and odd permutation as
vpsrld $16 + vpsrld $16 + vpmovdw + vpmovdw + vinserti64x4.

2021-08-10  Jakub Jelinek  <jakub@redhat.com>

PR target/80355
* config/i386/i386-expand.c (expand_vec_perm_even_odd): Return false
for V32HImode if !TARGET_AVX512BW.
(ix86_vectorize_vec_perm_const) <case E_V32HImode, case E_V64QImode>:
If !TARGET_AVX512BW and TARGET_AVX512F and d.testing_p, don't fail
early, but actually check the permutation.

* gcc.target/i386/avx512f-pr80355-2.c: New test.

tree-optimization/101809 - support emulated gather for double[int]

This adds emulated gather support for index vectors with more
elements than the data vector.  The internal function gather
vectorization code doesn't currently handle this (but the builtin
decl code does).  This allows vectorization of double data gather
with int indexes on 32bit platforms where there isn't an implicit
widening to 64bit present.

2021-08-10  Richard Biener  <rguenther@suse.de>

PR tree-optimization/101809
* tree-vect-stmts.c (get_load_store_type): Allow emulated
gathers with offset vector nunits being a constant multiple
of the data vector nunits.
(vect_get_gather_scatter_ops): Use the appropriate nunits
for the offset vector defs.
(vectorizable_store): Adjust call to
vect_get_gather_scatter_ops.
(vectorizable_load): Likewise.  Handle the case of less
offset vectors than data vectors.

i386: Improve single operand AVX512F permutations [PR80355]

On the following testcase we emit
vmovdqa32 .LC0(%rip), %zmm1
vpermd %zmm0, %zmm1, %zmm0
and
vmovdqa64 .LC1(%rip), %zmm1
vpermq %zmm0, %zmm1, %zmm0
instead of
vshufi32x4 $78, %zmm0, %zmm0, %zmm0
and
vshufi64x2 $78, %zmm0, %zmm0, %zmm0
we can emit with the patch.  We have patterns that match two argument
permutations for vshuf[if]*, but for one argument it doesn't trigger.
Either we can add two patterns for that, or we would need to add another
routine to i386-expand.c that would transform under certain condition
these cases to the two argument vshuf*, doing it in sse.md looked simpler.
We don't need this for 32-byte vectors, we already emit single insn
permutation that doesn't need memory op there.

2021-08-10  Jakub Jelinek  <jakub@redhat.com>

PR target/80355
* config/i386/sse.md (*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1,
*avx512f_shuf_<shuffletype>32x4_1<mask_name>_1): New define_insn
patterns.

* gcc.target/i386/avx512f-pr80355-1.c: New test.

openmp: Add support for declare simd and declare variant in a attribute syntax

This patch adds support for declare simd and declare variant in attribute
syntax.  Either in attribute-specifier-seq at the start of declaration, in
that case it has similar restriction to pragma-syntax, that there is a single
function declaration/definition in the declaration, rather than variable
declaration or more than one function declarations or mix of function and
variable declarations.  Or after the declarator id, in that case it applies
just to the single function declaration and the same declaration can have
multiple such attributes.  Or both.

Furthermore, cp_parser_statement has been adjusted so that it doesn't
accept [[omp::directive (parallel)]] etc. before statements that don't
take attributes at all, or where those attributes don't appertain to
the statement but something else (e.g. to label, using directive,
declaration, etc.).

2021-08-10  Jakub Jelinek  <jakub@redhat.com>

gcc/cp/
* parser.h (struct cp_omp_declare_simd_data): Remove
in_omp_attribute_pragma and clauses members, add loc and attribs.
(struct cp_oacc_routine_data): Remove loc member, add clauses
member.
* parser.c (cp_finalize_omp_declare_simd): New function.
(cp_parser_handle_statement_omp_attributes): Mention in
function comment the function is used also for
attribute-declaration.
(cp_parser_handle_directive_omp_attributes): New function.
(cp_parser_statement): Don't call
cp_parser_handle_statement_omp_attributes if statement doesn't
have attribute-specifier-seq at the beginning at all or if
if those attributes don't appertain to the statement.
(cp_parser_simple_declaration): Call
cp_parser_handle_directive_omp_attributes and
cp_finalize_omp_declare_simd.
(cp_parser_explicit_instantiation): Likewise.
(cp_parser_init_declarator): Initialize prefix_attributes
only after parsing declarators.
(cp_parser_direct_declarator): Call
cp_parser_handle_directive_omp_attributes and
cp_finalize_omp_declare_simd.
(cp_parser_member_declaration): Likewise.
(cp_parser_single_declaration): Likewise.
(cp_parser_omp_declare_simd): Don't initialize
data.in_omp_attribute_pragma, instead initialize
data.attribs[0] and data.attribs[1].
(cp_finish_omp_declare_variant): Remove
in_omp_attribute_pragma argument, instead use
parser->lexer->in_omp_attribute_pragma.
(cp_parser_late_parsing_omp_declare_simd): Adjust
cp_finish_omp_declare_variant caller.  Handle attribute-syntax
declare simd/variant.
gcc/testsuite/
* g++.dg/gomp/attrs-1.C (bar): Add missing semicolon after
[[omp::directive (threadprivate (t2))]].  Add tests with
if/while/switch after parallel in attribute syntax.
(corge): Add missing omp:: before directive.
* g++.dg/gomp/attrs-2.C (bar): Add missing semicolon after
[[omp::directive (threadprivate (t2))]].
* g++.dg/gomp/attrs-10.C: New test.
* g++.dg/gomp/attrs-11.C: New test.

i386: Fix typos in amxbf16 runtime test.

gcc/testsuite/ChangeLog:

* gcc.target/i386/amxbf16-dpbf16ps-2.c: Fix typos.

tree-optimization/101801 - rework generic vector vectorization more

This builds ontop of the vect_worthwhile_without_simd_p refactoring
done earlier.  It was wrong in dropping the appearant double checks
for operation support since the optab check can happen with an
integer vector emulation mode and thus succeed but vector lowering
might not actually support the operation on word_mode.

The following patch adds a vect_emulated_vector_p helper and
re-instantiates the check where it was previously.  It also adds
appropriate costing of the scalar stmts emitted by vector lowering
to vectorizable_operation which should be the only place such
operations are synthesized.  I've also cared for the case where
the vector mode is supported but the operation is not (though
I think this will be unlikely given we're talking about plus, minus
and negate).

This fixes the observed FAIL of gcc.dg/tree-ssa/gen-vect-11b.c
with -m32 where we end up vectorizing a multiplication that ends up
being teared down to scalars again by vector lowering.

I'm not super happy about all the other places where we're now
and previously feeding scalar modes to optab checks where we
want to know whether we can vectorize sth but well.

2021-09-08  Richard Biener  <rguenther@suse.de>

PR tree-optimization/101801
PR tree-optimization/101819
* tree-vectorizer.h (vect_emulated_vector_p): Declare.
* tree-vect-loop.c (vect_emulated_vector_p): New function.
(vectorizable_reduction): Re-instantiate a check for emulated
operations.
* tree-vect-stmts.c (vectorizable_shift): Likewise.
(vectorizable_operation): Likewise.  Cost emulated vector
operations according to the scalar sequence synthesized by
vector lowering.

middle-end/101824 - properly handle volatiles in nested fn lowering

When we build the COMPONENT_REF of a formerly volatile local off
the FRAME decl we have to make sure to mark the COMPONENT_REF
as TREE_THIS_VOLATILE.  While the GIMPLE operand scanner looks
at the FIELD_DECL this is not how volatile GENERIC refs work.

2021-08-09  Richard Biener  <rguenther@suse.de>

PR middle-end/101824
* tree-nested.c (get_frame_field): Mark the COMPONENT_REF as
volatile in case the variable was.

* gcc.dg/tree-ssa/pr101824.c: New testcase.

Evaluate arguments of sizeof that are structs of variable size.

Evaluate arguments of sizeof for all types of variable size
and not just for VLAs. This fixes some issues related to
[PR29970] where statement expressions need to be evaluated
so that the size is well defined.

2021-08-10  Martin Uecker  <muecker@gwdg.de>

gcc/c/
PR c/29970
* c-typeck.c (c_expr_sizeof_expr): Evaluate
size expressions for structs of variable size.

gcc/testsuite/
PR c/29970
* gcc.dg/vla-stexp-1.c: New test.

x86: Optimize load of const FP all bits set vectors

Check float_vector_all_ones_operand for vector floating-point modes to
optimize load of const floating-point all bits set vectors.

gcc/

PR target/101804
* config/i386/constraints.md (BC): Document for integer SSE
constant all bits set operand.
(BF): New constraint for const floating-point all bits set
vectors.
* config/i386/i386.c (standard_sse_constant_p): Likewise.
(standard_sse_constant_opcode): Likewise.
* config/i386/sse.md (sseconstm1): New mode attribute.
(mov<mode>_internal): Replace BC with <sseconstm1>.

gcc/testsuite/

PR target/101804
* gcc.target/i386/avx2-gather-2.c: Pass -march=skylake instead
of "-mavx2 -mtune=skylake".  Scan vpcmpeqd.

Support cond_ashr/lshr/ashl for vector integer modes under AVX512.

gcc/ChangeLog:

* config/i386/sse.md (cond_<insn><mode>): New expander.
(VI248_AVX512VLBW): New mode iterator.
* config/i386/predicates.md
(nonimmediate_or_const_vec_dup_operand): New predicate.

gcc/testsuite/ChangeLog:

* gcc.target/i386/cond_op_shift_d-1.c: New test.
* gcc.target/i386/cond_op_shift_d-2.c: New test.
* gcc.target/i386/cond_op_shift_q-1.c: New test.
* gcc.target/i386/cond_op_shift_q-2.c: New test.
* gcc.target/i386/cond_op_shift_ud-1.c: New test.
* gcc.target/i386/cond_op_shift_ud-2.c: New test.
* gcc.target/i386/cond_op_shift_uq-1.c: New test.
* gcc.target/i386/cond_op_shift_uq-2.c: New test.
* gcc.target/i386/cond_op_shift_uw-1.c: New test.
* gcc.target/i386/cond_op_shift_uw-2.c: New test.
* gcc.target/i386/cond_op_shift_w-1.c: New test.
* gcc.target/i386/cond_op_shift_w-2.c: New test.

Daily bump.

Ensure toupper and tolower follow the expected pattern.

If the parameter is not compatible with the LHS, assume this is not really a
builtin function to avoid a trap.

gcc/
PR tree-optimization/101741
* gimple-range-fold.cc (fold_using_range::range_of_builtin_call): Check
type of parameter for toupper/tolower.

gcc/testsuite/
* gcc.dg/pr101741.c: New.

libstdc++: Reduce use of debug containers in <regex>

The std::regex code uses std::map and std::vector, which means that when
_GLIBCXX_DEBUG is defined it uses the debug versions of those
containers. That no longer compiles, because I changed <regex> to
include <bits/stl_map.h> and <bits/stl_vector.h> instead of <map> and
<vector>, so the debug versions aren't defined, and std::map doesn't
compile. There is also a use of std::stack, which defaults to std::deque
which is the debug deque when _GLIBCXX_DEBUG is defined.

Using std::map, std::vector, and std::deque is probably a mistake, and
we should qualify them with _GLIBCXX_STD_C instead so that the debug
versions aren't used. We do not need the overhead of checking our own
uses of those containers, which should be correct anyway. The exception
is the vector base class of std::match_results, which exposes iterators
to users, so can benefit from debug mode checks for its iterators. For
other accesses to the vector elements, match_results already does its
own checks, so can access the _GLIBCXX_STD_C::vector base class
directly.

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:

* include/bits/regex.h (basic_regex::transform_primary): Use
_GLIBCXX_STD_C::vector for local variable.
* include/bits/regex.tcc (__regex_algo_impl): Use reference to
_GLIBCXX_STD_C::vector base class of match_results.
* include/bits/regex_automaton.tcc (_StateSeq:_M_clone): Use
_GLIBCXX_STD_C::map and _GLIBCXX_STD_C::deque for local
variables.
* include/bits/regex_compiler.h (_BracketMatcher): Use
_GLIBCXX_STD_C::vector for data members.
* include/bits/regex_executor.h (_Executor): Likewise.
* include/std/regex [_GLIBCXX_DEBUG]: Include <debug/vector>.

libstdc++: [_GLIBCXX_DEBUG] Avoid allocator operator== when always equal

Use std::allocator_traits::is_always_equal to find out if we need to compare
allocator instances on safe container allocator aware move constructor.

libstdc++-v3/ChangeLog:

* include/debug/safe_container.h
(_Safe_container(_Safe_container&&, const _Alloc&, std::true_type)): New.
(_Safe_container(_Safe_container&&, const _Alloc&, std::false_type)): New.
(_Safe_container(_Safe_container&&, const _Alloc&)): Use latters.

ipa: Fix testsuite/gcc.dg/ipa/remref-6.c

I forgot to add -fdump-ipa-inline to options of
testsuite/gcc.dg/ipa/remref-6.c and so the dump scan test were not
PASSing but ended up as UNRESOLVED.  Fixing that revealed that the one
of the dumps it was looking for had a double space, so I removed it
too.

gcc/ChangeLog:

2021-08-09  Martin Jambor  <mjambor@suse.cz>

PR testsuite/101654
* ipa-prop.c (propagate_controlled_uses): Removed a spurious space.

gcc/testsuite/ChangeLog:

2021-08-09  Martin Jambor  <mjambor@suse.cz>

PR testsuite/101654
* gcc.dg/ipa/remref-6.c: Added missing -fdump-ipa-inline option.

Verify destination[source] of a load[store] instruction is a register.

gcc/ChangeLog:

* config/rs6000/rs6000.c (is_load_insn1): Verify destination is a
register.
(is_store_insn1): Verify source is a register.

i386: Name V2SF logic insns [PR101812]

Name V2SF logic insns, so expand_simple_binop works with V2SF modes.

2021-08-09  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
PR target/101812
* config/i386/mmx.md (<any_logic:code>v2sf3):
Rename from *mmx_<any_logic:code>v2sf3

gcc/testsuite/
PR target/101812
* gcc.target/i386/pr101812.c: New test.

Cross-reference parts adapted in 'gcc/omp-oacc-neuter-broadcast.cc'

gcc/
* config/nvptx/nvptx.c: Cross-reference parts adapted in
'gcc/omp-oacc-neuter-broadcast.cc'.
* omp-low.c: Likewise.
* omp-oacc-neuter-broadcast.cc: Cross-reference parts adapted from
the above files.

amdgcn: Enable OpenACC worker partitioning for AMD GCN

gcc/
* config/gcn/gcn.c (gcn_init_builtins): Override decls for
BUILT_IN_GOACC_SINGLE_START, BUILT_IN_GOACC_SINGLE_COPY_START,
BUILT_IN_GOACC_SINGLE_COPY_END and BUILT_IN_GOACC_BARRIER.
(gcn_goacc_validate_dims): Turn on worker partitioning unconditionally.
(gcn_fork_join): Update comment.
* config/gcn/gcn.opt (flag_worker_partitioning): Remove.
(macc_experimental_workers): Remove unused option.
libgomp/
* plugin/plugin-gcn.c (gcn_exec): Change default number of workers to
16.
* testsuite/libgomp.oacc-c-c++-common/acc_prof-kernels-1.c
[acc_device_radeon]: Update.
* testsuite/libgomp.oacc-c-c++-common/loop-dim-default.c
[ACC_DEVICE_TYPE_radeon]: Likewise.
* testsuite/libgomp.oacc-c-c++-common/parallel-dims.c
[acc_device_radeon]: Likewise.
* testsuite/libgomp.oacc-c-c++-common/routine-wv-2.c
[ACC_DEVICE_TYPE_radeon]: Likewise.
* testsuite/libgomp.oacc-fortran/optional-reduction.f90: XFAIL for
'openacc_radeon_accel_selected' and '-O0'.
* testsuite/libgomp.oacc-fortran/reduction-7.f90: Likewise.

Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Thomas Schwinge <thomas@codesourcery.com>

openacc: Middle-end worker-partitioning support

This patch implements worker-partitioning support in the middle end,
by rewriting gimple. The OpenACC execution model requires that code
can run in either "worker single" mode where only a single worker per
gang is active, or "worker partitioned" mode, where multiple workers
per gang are active. This means we need to do something equivalent
to spawning additional workers when transitioning from worker-single
to worker-partitioned mode. However, GPUs typically fix the number of
threads of invoked kernels at launch time, so we need to do something
with the "extra" threads when they are not wanted.

The scheme used is to conditionalise each basic block that executes
in "worker single" mode for worker 0 only. Conditional branches
are handled specially so "idle" (non-0) workers follow along with
worker 0. On transitioning to "worker partitioned" mode, any variables
modified by worker 0 are propagated to the other workers via GPU shared
memory. Special care is taken for routine calls, writes through pointers,
and so forth, as follows:

  - There are two types of function calls to consider in worker-single
    mode: "normal" calls to maths library routines, etc. are called from
    worker 0 only. OpenACC routines may contain worker-partitioned loops
    themselves, so are called from all workers, including "idle" ones.

  - SSA names set in worker-single mode, but used in worker-partitioned
    mode, are copied to shared memory in worker 0. Other workers retrieve
    the value from the appropriate shared-memory location after a barrier,
    and new phi nodes are introduced at the convergence point to resolve
    the worker 0/other worker copies of the value.

  - Local scalar variables (on the stack) also need special handling. We
    broadcast any variables that are written in the current worker-single
    block, and that are read in any worker-partitioned block.  (This is
    believed to be safe, and is flow-insensitive to ease analysis.)

  - Local aggregates (arrays and composites) on the stack are *not*
    broadcast. Instead we force gimple stmts modifying elements/fields of
    local aggregates into fully-partitioned mode. The RHS of the
    assignment is a scalar, and is thus subject to broadcasting as above.

  - Writes through pointers may affect any local variable that has
    its address taken. We use points-to analysis to determine the set
    of potentially-affected variables for a given pointer indirection.
    We broadcast any such variable which is used in worker-partitioned
    mode, on a per-block basis for any block containing a write through
    a pointer.

Some slides about the implementation (from 2018) are available at:

  https://jtb20.github.io/gcnworkers.pdf

gcc/
* Makefile.in (OBJS): Add omp-oacc-neuter-broadcast.o.
* doc/tm.texi.in (TARGET_GOACC_CREATE_WORKER_BROADCAST_RECORD):
Add documentation hook.
* doc/tm.texi: Regenerate.
* omp-oacc-neuter-broadcast.cc: New file.
* omp-builtins.def (BUILT_IN_GOACC_BARRIER)
(BUILT_IN_GOACC_SINGLE_START, BUILT_IN_GOACC_SINGLE_COPY_START)
(BUILT_IN_GOACC_SINGLE_COPY_END): New builtins.
* passes.def (pass_omp_oacc_neuter_broadcast): Add pass.
* target.def (goacc.create_worker_broadcast_record): Add target
hook.
* tree-pass.h (make_pass_omp_oacc_neuter_broadcast): Add
prototype.
* config/gcn/gcn-protos.h (gcn_goacc_adjust_propagation_record):
Rename prototype to...
(gcn_goacc_create_worker_broadcast_record): ... this.
* config/gcn/gcn-tree.c (gcn_goacc_adjust_propagation_record): Rename
function to...
(gcn_goacc_create_worker_broadcast_record): ... this.
* config/gcn/gcn.c (TARGET_GOACC_ADJUST_PROPAGATION_RECORD):
Rename to...
(TARGET_GOACC_CREATE_WORKER_BROADCAST_RECORD): ... this.

Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com> (via 'gcc/config/nvptx/nvptx.c' master)
Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Thomas Schwinge <thomas@codesourcery.com>

PR101609: Use the correct iterator for AArch64 vector right shift pattern

Loops containing long long shifts fail to vectorize due to the vectorizer
not being able to recognize long long right shifts. This is due to a bug
in the iterator used for the vashr and vlshr patterns in aarch64-simd.md.

2021-08-09  Tejas Belagod  <tejas.belagod@arm.com>

gcc/ChangeLog
PR target/101609
* config/aarch64/aarch64-simd.md (vlshr<mode>3, vashr<mode>3): Use
the right iterator.

gcc/testsuite/ChangeLog
* gcc.target/aarch64/vect-shr-reg.c: New testcase.
* gcc.target/aarch64/vect-shr-reg-run.c: Likewise.

Remove 'gcc/omp-offload.c' from 'GTFILES'

Given that it doesn't contain any 'GTY' markers, no 'gcc/gt-omp-offload.h' file
gets generated (and '#include'd anywhere).

Small fix-up for r243673 (Git commit 629b3d75c8c5a244d891a9c292bca6912d4b0dd9)
"Split omp-low into multiple files".

gcc/
* Makefile.in (GTFILES): Remove '$(srcdir)/omp-offload.c'.

Don't consider '-foffload-abi' in 'DEF_GOACC_BUILTIN', 'DEF_GOMP_BUILTIN'

Since Tom's PR64707 commit r220037 (Git commit
1506ae0e1e865fb7a42fc37a47f1799b71f21c53) "Make fopenmp an LTO option" as well
as PR64672 commit r220038 (Git commit a0c88d0629a33161add8d5bc083f1e59f3f756f7)
"Make fopenacc an LTO option", we're now actually passing
'-fopenacc'/'-fopenmp' to the 'mkoffload's, which will pass these on to the
offload compilers.

gcc/
* builtins.def (DEF_GOACC_BUILTIN, DEF_GOMP_BUILTIN): Don't
consider '-foffload-abi'.
* common.opt (-foffload-abi): Remove 'Var', 'Init'.
* opts.c (common_handle_option) <-foffload-abi> [ACCEL_COMPILER]:
Ignore.

Sanity check that 'Init' doesn't appear without 'Var' in '*.opt' files

... as that doesn't make sense.

    @item Init(@var{value})
    The variable specified by the @code{Var} property should be statically
    initialized to @var{value}.  [...]

gcc/
* optc-gen.awk: Sanity check that 'Init' doesn't appear without
'Var'.

[OpenACC] Clean up unused 'BUILT_IN_ACC_GET_DEVICE_TYPE'

Unused as of r229767 (Git commit e50146711b7200e8f822c6d8239430c682b76e4f)
"OpenACC reductions".

gcc/
* omp-builtins.def (BUILT_IN_ACC_GET_DEVICE_TYPE): Remove.

[documentation] No need anymore to "mention ['gt-*.h' file] as a dependency in the 'Makefile'"

... as of r202907 (Git commit b6541edc52ed57b6e47150396356d3080ba81034)
"remove explicit dependencies".

gcc/
* doc/gty.texi (Files): Update.

[documentation] Fix GTY header file example

Fix-up for CVS 'gcc/doc/gty.texi' r1.6 (Subversion r55857, Git
commit cba57c9d40057fa78efc9a404ab4ae7101a59dcb) "Minor doc updates"

gcc/
* doc/gty.texi (Files): Fix GTY header file example.

Improve handling of unknown sign bit in CCP.

This middle-end patch implements several related improvements to
tree-ssa's conditional (bit) constant propagation pass.  The current
code handling ordered comparisons contains the comment "If the
most significant bits are not known we know nothing" which is not
entirely true [this test even prevents this pass understanding these
comparisons always have a zero or one result].  This patch introduces
a new value_mask_to_min_max helper function, that understands the
different semantics of the most significant bit on signed vs.
unsigned values.  This allows us to generalize ordered comparisons,
GE_EXPR, GT_EXPR, LE_EXPR and LT_EXPR, where to code is tweaked to
correctly handle the potential equal cases.  Then finally support
is added for the related tree codes MIN_EXPR, MAX_EXPR, ABS_EXPR
and ABSU_EXPR.

Regression testing revealed three test cases in the testsuite that
were checking for specific optimizations that are now being performed
earlier than expected.  These tests can continue to check their
original transformations by explicitly adding -fno-tree-ccp to their
dg-options (some already specify -fno-ipa-vrp or -fno-tree-forwprop
for the same reason).

2021-08-09  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
* tree-ssa-ccp.c (value_mask_to_min_max): Helper function to
determine the upper and lower bounds from a mask-value pair.
(bit_value_unop) [ABS_EXPR, ABSU_EXPR]: Add support for
absolute value and unsigned absolute value expressions.
(bit_value_binop):  Initialize *VAL's precision.
[LT_EXPR, LE_EXPR]: Use value_mask_to_min_max to determine
upper and lower bounds of operands.  Add LE_EXPR/GE_EXPR
support when the operands are unknown but potentially equal.
[MIN_EXPR, MAX_EXPR]: Support minimum/maximum expressions.

gcc/testsuite/ChangeLog
* gcc.dg/pr68217.c: Add -fno-tree-ccp option.
* gcc.dg/tree-ssa/vrp24.c: Add -fno-tree-ccp option.
* g++.dg/ipa/pure-const-3.C: Add -fno-tree-ccp option.

libstdc++: Make allocator equality comparable in tests

libstdc++-v3/ChangeLog:

* testsuite/23_containers/unordered_map/cons/default.cc: Add
equality comparison operators to allocator.
* testsuite/23_containers/unordered_set/cons/default.cc:
Likewise.

testsuite/lib/gfortran.exp: Add -I for ISO*.h [PR101305, PR101660]

This patch adds -I$specdir/libgfortran to GFORTRAN_UNDER_TEST, when
set by proc gfortran_init. As the $specdir depends on the multilib
setting, it has to be re-set for a different multilib; hence, we track
whether a previous call to gfortran_init set that var or whether it
was set differently.

gcc/testsuite/
PR libfortran/101305
PR fortran/101660

* lib/gfortran.exp (gfortran_init): Add -I $specdir/libgfortran to
GFORTRAN_UNDER_TEST; update it when set by previous gfortran_init call.
* gfortran.dg/ISO_Fortran_binding_1.c: Use <...> not "..." for
ISO_Fortran_binding.h's #include.
* gfortran.dg/ISO_Fortran_binding_10.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_11.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_12.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_15.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_16.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_17.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_18.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_3.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_5.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_6.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_7.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_8.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_9.c: Likewise.
* gfortran.dg/PR94327.c: Likewise.
* gfortran.dg/PR94331.c: Likewise.
* gfortran.dg/bind_c_array_params_3_aux.c: Likewise.
* gfortran.dg/iso_fortran_binding_uint8_array_driver.c: Likewise.
* gfortran.dg/pr93524.c: Likewise.

aarch64: Expand %<w> correctly according to mode iterator

Pattern "*extend<SHORT:mode><GPI:mode>2_aarch64" is duplicated
from the corresponding zero_extend pattern, however %<w> needs
to be expanded according to its mode iterator because the smov
instruction is different to umov.

2021-08-09  Bin Cheng  <bin.cheng@linux.alibaba.com>

gcc/
* config/aarch64/aarch64.md
(*extend<SHORT:mode><GPI:mode>2_aarch64): Use %<GPI:w>0.

testsuite: aarch64: Fix invalid SVE tests

Some scan-assembler tests for SVE code generation were erroneously
split over multiple lines - meaning they became invalid. This patch
gets the tests working again by putting each test on a single line.

The extract_[1234].c tests are corrected to expect that extracted
32-bit values are moved into 'w' registers rather than 'x' registers.

gcc/testsuite/ChangeLog:

2021-08-06  Jonathan Wright  <jonathan.wright@arm.com>

* gcc.target/aarch64/sve/dup_lane_1.c: Don't split
scan-assembler tests over multiple lines. Expect 32-bit
result values in 'w' registers.
* gcc.target/aarch64/sve/extract_1.c: Likewise.
* gcc.target/aarch64/sve/extract_2.c: Likewise.
* gcc.target/aarch64/sve/extract_3.c: Likewise.
* gcc.target/aarch64/sve/extract_4.c: Likewise.

testsuite: aarch64: Fix failing vector structure tests on big-endian

Recent refactoring of the arm_neon.h header enabled better code
generation for intrinsics that manipulate vector structures. New
tests were also added to verify the benefit of these changes. It now
transpires that the code generation improvements are observed only on
little-endian systems. This patch restricts the code generation tests
to little-endian targets.

gcc/testsuite/ChangeLog:

2021-08-04  Jonathan Wright  <jonathan.wright@arm.com>

* gcc.target/aarch64/vector_structure_intrinsics.c: Restrict
tests to little-endian targets.

MAINTAINERS: Add myself for write after approval

ChangeLog:

* MAINTAINERS (Write After Approval): Add myself.

Daily bump.

lra: Fix s/otput/output/ typo in debug output

gcc/
* lra-constraints.c: Fix s/otput/output/ typo.

libstdc++: Fix dg-prune-output assertion message

Since __glibcxx_assert changes in r6b42b5a the generated assertion message
has changed.

libstdc++-v3/ChangeLog:

* testsuite/25_algorithms/copy/debug/constexpr_neg.cc: Replace 'failed_assertion'
dg-prune-output reason with 'builtin_unreachable'.
* testsuite/25_algorithms/copy_backward/debug/constexpr_neg.cc: Likewise.
* testsuite/25_algorithms/equal/debug/constexpr_neg.cc: Likewise.
* testsuite/25_algorithms/lower_bound/debug/constexpr_partitioned_neg.cc: Likewise.
* testsuite/25_algorithms/lower_bound/debug/constexpr_partitioned_pred_neg.cc: Likewise.
* testsuite/25_algorithms/lower_bound/debug/constexpr_valid_range_neg.cc: Likewise.
* testsuite/25_algorithms/upper_bound/debug/constexpr_partitioned_neg.cc: Likewise.
* testsuite/25_algorithms/upper_bound/debug/constexpr_partitioned_pred_neg.cc: Likewise.
* testsuite/25_algorithms/upper_bound/debug/constexpr_valid_range_neg.cc: Likewise.

Fix c6x test compromised by recent improvements to bswap & rotates

gcc/testsuite
* gcc.target/tic6x/rotdi16-scan.c: Pull rotate into its own function.

libstdc++: Tweak timeout for testsuite/std/ranges/iota/max_size_type.cc

A simulator can easily spend more than 10 minutes running
this test-case, and the default timeout is at 5 minutes.
Better allow even slower machines; use 4 as the factor.

Regarding relative runtime numbers (very local; mmixware simulator for
mmix-knuth-mmixware): test01 and test05 finish momentarily; test02 at
about 2 minutes, and test03 about 2m30, but test04 itself runs for
more than 6 minues and so times out.

Not sure if it's better to split up this test, as the excessive
runtime may be unintended, but this seemed simplest.

libstdc++-v3:
* testsuite/std/ranges/iota/max_size_type.cc: Set
dg-timeout-factor to 4.

Daily bump.

compiler: support export/import of unsafe.Add/Slice

For golang/go#19367
For golang/go#40481

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/340549

Fortran: ICE with automatic character object, save, and various options

gcc/fortran/ChangeLog:

PR fortran/68568
* primary.c (gfc_expr_attr): Variable attribute can only be
inquired when symtree is non-NULL.

Add tests for PR tree-optimization/88531

PR tree-optimization/88531
* gcc.target/i386/pr88531-1a.c: New test.
* gcc.target/i386/pr88531-1b.c: Likewise.
* gcc.target/i386/pr88531-1c.c: Likewise.
* gcc.target/i386/pr88531-2a.c: Likewise.
* gcc.target/i386/pr88531-2b.c: Likewise.
* gcc.target/i386/pr88531-2c.c: Likewise.

Daily bump.

Move more code to new gimple-ssa-warn-access pass.

gcc/ChangeLog:

* builtins.c (expand_builtin_memchr): Move to gimple-ssa-warn-access.cc.
(expand_builtin_strcat): Same.
(expand_builtin_stpncpy): Same.
(expand_builtin_strncat): Same.
(check_read_access): Same.
(check_memop_access): Same.
(expand_builtin_strlen): Move checks to gimple-ssa-warn-access.cc.
(expand_builtin_strnlen): Same.
(expand_builtin_memcpy): Same.
(expand_builtin_memmove): Same.
(expand_builtin_mempcpy): Same.
(expand_builtin_strcpy): Same.
(expand_builtin_strcpy_args): Same.
(expand_builtin_stpcpy_1): Same.
(expand_builtin_strncpy): Same.
(expand_builtin_memset): Same.
(expand_builtin_bzero): Same.
(expand_builtin_strcmp): Same.
(expand_builtin_strncmp): Same.
(expand_builtin): Remove handlers.
(fold_builtin_strlen): Add a comment.
* builtins.h (check_access): Move to gimple-ssa-warn-access.cc.
* calls.c (maybe_warn_nonstring_arg): Same.
* diagnostic-spec.c (nowarn_spec_t::nowarn_spec_t): Add warning option.
* gimple-fold.c (gimple_fold_builtin_strcpy): Pass argument to callee.
(gimple_fold_builtin_stpcpy): Same.
* gimple-ssa-warn-access.cc (has_location): New function.
(get_location): Same.
(get_callee_fndecl): Same.
(call_nargs): Same.
(call_arg): Same.
(warn_string_no_nul): Define.
(unterminated_array): Same.
(check_nul_terminated_array): Same.
(maybe_warn_nonstring_arg): Same.
(maybe_warn_for_bound): Same.
(warn_for_access): Same.
(check_access): Same.
(check_memop_access): Same.
(check_read_access): Same.
(warn_dealloc_offset): Use helper functions.
(maybe_emit_free_warning): Same.
(class pass_waccess): Add members.
(check_strcat): New function.
(check_strncat): New function.
(check_stxcpy): New function.
(check_stxncpy): New function.
(check_strncmp): New function.
(pass_waccess::check_builtin): New function.
(pass_waccess::check): Call it.
* gimple-ssa-warn-access.h (warn_string_no_nul): Move here from
builtins.h.
(maybe_warn_for_bound): Same.
(check_access): Same.
(check_memop_access): Same.
(check_read_access): Same.
* pointer-query.h (struct access_data): Define a ctor overload.

gcc/testsuite/ChangeLog:

* c-c++-common/Wsizeof-pointer-memaccess1.c: Also disable
-Wstringop-overread.
* c-c++-common/attr-nonstring-3.c: Adjust pattern of expected message.
* gcc.dg/Warray-bounds-39.c: Add an xfail due to a known bug.
* gcc.dg/Wstring-compare-3.c: Also disable -Wstringop-overread.
* gcc.dg/attr-nonstring-2.c: Adjust pattern of expected message.
* gcc.dg/attr-nonstring-4.c: Same.
* gcc.dg/Wstringop-overread-6.c: New test.
* gcc.dg/sso-14.c: Fix typos to avoid buffer overflow.

compiler: make escape analysis more strict about runtime calls

Following the previous CL, in the escape analysis list all the
expected runtime calls, and fail if an unexpected one is seen.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/340397

arm: Fix pr69245.c testcase for reorder assembler architecture directives [PR101723]

In gcc.target/arm/pr69245.c, to have a .fpu neon-vfpv4 directive, make
sure code for fn1() is emitted, by removing the static keyword.

Fix a typo in gcc.target/arm/pr69245.c, where \s should be \\s.

2021-08-06  Christophe Lyon  <christophe.lyon@foss.st.com>

gcc/testsuite/

PR target/101723
* gcc.target/arm/pr69245.c: Make sure to emit code for fn1, fix
typo.

arm: Fix typos for reorder assembler architecture directives [PR101723]

Two tests had typos preventing them from passing, committed as obvious.

2021-08-06  Christophe Lyon  <christophe.lyon@foss.st.com>

gcc/testsuite/
PR target/101723
* gcc.target/arm/attr-neon3.c: Fix typo.
* gcc.target/arm/pragma_fpu_attribute_2.c: Fix typo.

tree-optimization/101801 - remove vect_worthwhile_without_simd_p

This removes the cost part of vect_worthwhile_without_simd_p, retaining
only the correctness bits.  The reason is that the cost heuristic
do not properly account for SLP plus the check whether "without simd"
applies misfires for AVX512 mask vectors at the moment, leading to
missed vectorizations there.

Any costing decision should take place in the cost modeling, no
single stmt is to disable all vectorization on its own.

2021-08-06  Richard Biener  <rguenther@suse.de>

PR tree-optimization/101801
* tree-vectorizer.h (vect_worthwhile_without_simd_p): Rename...
(vect_can_vectorize_without_simd_p): ... to this.
* tree-vect-loop.c (vect_worthwhile_without_simd_p): Rename...
(vect_can_vectorize_without_simd_p): ... to this and fold
in vect_min_worthwhile_factor.
(vect_min_worthwhile_factor): Remove.
(vectorizable_reduction): Adjust and remove the cost part.
* tree-vect-stmts.c (vectorizable_shift): Likewise.
(vectorizable_operation): Likewise.

libstdc++: Also move the [[nodiscard]] attributes in <compare>

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:

* libsupc++/compare (compare_three_way, strong_order)
(weak_order, partial_order, compare_strong_order_fallback)
(compare_weak_order_fallback, compare_partial_order_fallback):
Move nodiscard attributes to correct location.

i386: Fix conditional move reg-to-reg move elimination peepholes [PR101797]

Add missing operand predicate, otherwise any RTX will match.

2021-08-06  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
PR target/101797
* config/i386/i386.md (cmove reg-to-reg move elimination peephole2s):
Add general_gr_operand predicate to operand 3.

gcc/testsuite/
PR target/101797
* gcc.target/i386/pr101797.c: New test.

Use CFN_BUILT_IN_CLRSB instead of BUILT_IN_CLRSB in switch.

This patch replaces the use of BUILT_IN_CLRSB with CFN_BUILT_IN_CLRSB
in my recent patch to tree-ssa-phiopt.c.  Both of these have identical
values, so there's no change in behavior, but consistent use of the same
enumeration avoids warnings when using clang (or static analysis tools).

2021-08-06  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
* tree-ssa-phiopt.c (cond_removal_in_builtin_zero_pattern): Use
CFN_BUILT_IN_CLRSB* instead of BUILT_IN_CLRSB* for consistency.

middle-end/AArch64: Fix bootstrap after vec changes

The build is broken since a3d3e8c362c2 since it's deleted the ability to pass
vec<> by value and now must be past by reference.

However some language hooks used by AArch64 were not updated and breaks the
build on AArch64.  This patch updates these hooks.

gcc/c/ChangeLog:

* c-decl.c (c_simulate_enum_decl): Pass vec<> by pointer.
* c-tree.h (c_simulate_enum_decl): Likewise.

gcc/ChangeLog:

* config/aarch64/aarch64-sve-builtins.cc (register_svpattern,
register_svprfop): Pass vec<> by pointer.
* langhooks-def.h (lhd_simulate_enum_decl): Likewise.
* langhooks.c (lhd_simulate_enum_decl): Likewise.
* langhooks.h (struct lang_hooks_for_types): Likewise.

gcc/cp/ChangeLog:

* cp-objcp-common.h (cxx_simulate_enum_decl): Pass vec<> by pointer.
* decl.c (cxx_simulate_enum_decl): Likewise.

gcov: Remove <stdint.h> from libgcov-driver.c

In the patch to add __gcov_info_to_gcda(), the include of <stdint.h> was added
to libgcov-driver.c even if inhibit_libc is defined.  It turned out that this
header file is not always available.  Remove the include of <stdint.h> and
replace the intptr_t with the compiler provided __INTPTR_TYPE__.

libgcc/

* libgcov-driver.c (#include <stdint.h>): Remove.
(write_topn_counters): Use __INTPTR_TYPE__ instead of intptr_t.

aarch64: Use memcpy to copy structures in bfloat vst* intrinsics

Use __builtin_memcpy to copy vector structures instead of using a
union - or constructing a new opaque structure one vector at a time -
in each of the vst[234][q] and vst1[q]_x[234] bfloat Neon intrinsics
in arm_neon.h.

Add new code generation tests to verify that superfluous move
instructions are not generated for the vst[234]q or vst1q_x[234]
bfloat intrinsics.

gcc/ChangeLog:

2021-07-30  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/arm_neon.h (vst1_bf16_x2): Use
__builtin_memcpy instead of constructing an additional
__builtin_aarch64_simd_oi one vector at a time.
(vst1q_bf16_x2): Likewise.
(vst1_bf16_x3): Use __builtin_memcpy instead of constructing
an additional __builtin_aarch64_simd_ci one vector at a time.
(vst1q_bf16_x3): Likewise.
(vst1_bf16_x4): Use __builtin_memcpy instead of a union.
(vst1q_bf16_x4): Likewise.
(vst2_bf16): Use __builtin_memcpy instead of constructing an
additional __builtin_aarch64_simd_oi one vector at a time.
(vst2q_bf16): Likewise.
(vst3_bf16): Use __builtin_memcpy instead of constructing an
additional __builtin_aarch64_simd_ci mode one vector at a
time.
(vst3q_bf16): Likewise.
(vst4_bf16): Use __builtin_memcpy instead of constructing an
additional __builtin_aarch64_simd_xi one vector at a time.
(vst4q_bf16): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/vector_structure_intrinsics.c: Add new
tests.

aarch64: Use memcpy to copy structures in vst2[q]_lane intrinsics

Use __builtin_memcpy to copy vector structures instead of using a
union - or constructing a new opaque structure one vector at a time -
in each of the vst2[q]_lane Neon intrinsics in arm_neon.h.

Add new code generation tests to verify that superfluous move
instructions are not generated for the vst2q_lane intrinsics.

gcc/ChangeLog:

2021-07-30  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/arm_neon.h (__ST2_LANE_FUNC): Delete.
(__ST2Q_LANE_FUNC): Delete.
(vst2_lane_f16): Use __builtin_memcpy to copy vector
structure instead of constructing __builtin_aarch64_simd_oi
one vector at a time.
(vst2_lane_f32): Likewise.
(vst2_lane_f64): Likewise.
(vst2_lane_p8): Likewise.
(vst2_lane_p16): Likewise.
(vst2_lane_p64): Likewise.
(vst2_lane_s8): Likewise.
(vst2_lane_s16): Likewise.
(vst2_lane_s32): Likewise.
(vst2_lane_s64): Likewise.
(vst2_lane_u8): Likewise.
(vst2_lane_u16): Likewise.
(vst2_lane_u32): Likewise.
(vst2_lane_u64): Likewise.
(vst2_lane_bf16): Likewise.
(vst2q_lane_f16): Use __builtin_memcpy to copy vector
structure instead of using a union.
(vst2q_lane_f32): Likewise.
(vst2q_lane_f64): Likewise.
(vst2q_lane_p8): Likewise.
(vst2q_lane_p16): Likewise.
(vst2q_lane_p64): Likewise.
(vst2q_lane_s8): Likewise.
(vst2q_lane_s16): Likewise.
(vst2q_lane_s32): Likewise.
(vst2q_lane_s64): Likewise.
(vst2q_lane_u8): Likewise.
(vst2q_lane_u16): Likewise.
(vst2q_lane_u32): Likewise.
(vst2q_lane_u64): Likewise.
(vst2q_lane_bf16): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/vector_structure_intrinsics.c: Add new
tests.

aarch64: Use memcpy to copy structures in vst3[q]_lane intrinsics

Use __builtin_memcpy to copy vector structures instead of using a
union - or constructing a new opaque structure one vector at a time -
in each of the vst3[q]_lane Neon intrinsics in arm_neon.h.

Add new code generation tests to verify that superfluous move
instructions are not generated for the vst3q_lane intrinsics.

gcc/ChangeLog:

2021-07-30  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/arm_neon.h (__ST3_LANE_FUNC): Delete.
(__ST3Q_LANE_FUNC): Delete.
(vst3_lane_f16): Use __builtin_memcpy to copy vector
structure instead of constructing __builtin_aarch64_simd_ci
one vector at a time.
(vst3_lane_f32): Likewise.
(vst3_lane_f64): Likewise.
(vst3_lane_p8): Likewise.
(vst3_lane_p16): Likewise.
(vst3_lane_p64): Likewise.
(vst3_lane_s8): Likewise.
(vst3_lane_s16): Likewise.
(vst3_lane_s32): Likewise.
(vst3_lane_s64): Likewise.
(vst3_lane_u8): Likewise.
(vst3_lane_u16): Likewise.
(vst3_lane_u32): Likewise.
(vst3_lane_u64): Likewise.
(vst3_lane_bf16): Likewise.
(vst3q_lane_f16): Use __builtin_memcpy to copy vector
structure instead of using a union.
(vst3q_lane_f32): Likewise.
(vst3q_lane_f64): Likewise.
(vst3q_lane_p8): Likewise.
(vst3q_lane_p16): Likewise.
(vst3q_lane_p64): Likewise.
(vst3q_lane_s8): Likewise.
(vst3q_lane_s16): Likewise.
(vst3q_lane_s32): Likewise.
(vst3q_lane_s64): Likewise.
(vst3q_lane_u8): Likewise.
(vst3q_lane_u16): Likewise.
(vst3q_lane_u32): Likewise.
(vst3q_lane_u64): Likewise.
(vst3q_lane_bf16): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/vector_structure_intrinsics.c: Add new
tests.

aarch64: Use memcpy to copy structures in vst4[q]_lane intrinsics

Use __builtin_memcpy to copy vector structures instead of using a
union - or constructing a new opaque structure one vector at a time -
in each of the vst4[q]_lane Neon intrinsics in arm_neon.h.

Add new code generation tests to verify that superfluous move
instructions are not generated for the vst4q_lane intrinsics.

gcc/ChangeLog:

2021-07-29  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/arm_neon.h (__ST4_LANE_FUNC): Delete.
(__ST4Q_LANE_FUNC): Delete.
(vst4_lane_f16): Use __builtin_memcpy to copy vector
structure instead of constructing __builtin_aarch64_simd_xi
one vector at a time.
(vst4_lane_f32): Likewise.
(vst4_lane_f64): Likewise.
(vst4_lane_p8): Likewise.
(vst4_lane_p16): Likewise.
(vst4_lane_p64): Likewise.
(vst4_lane_s8): Likewise.
(vst4_lane_s16): Likewise.
(vst4_lane_s32): Likewise.
(vst4_lane_s64): Likewise.
(vst4_lane_u8): Likewise.
(vst4_lane_u16): Likewise.
(vst4_lane_u32): Likewise.
(vst4_lane_u64): Likewise.
(vst4_lane_bf16): Likewise.
(vst4q_lane_f16): Use __builtin_memcpy to copy vector
structure instead of using a union.
(vst4q_lane_f32): Likewise.
(vst4q_lane_f64): Likewise.
(vst4q_lane_p8): Likewise.
(vst4q_lane_p16): Likewise.
(vst4q_lane_p64): Likewise.
(vst4q_lane_s8): Likewise.
(vst4q_lane_s16): Likewise.
(vst4q_lane_s32): Likewise.
(vst4q_lane_s64): Likewise.
(vst4q_lane_u8): Likewise.
(vst4q_lane_u16): Likewise.
(vst4q_lane_u32): Likewise.
(vst4q_lane_u64): Likewise.
(vst4q_lane_bf16): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/vector_structure_intrinsics.c: Add new
tests.

rs6000: Fix restored rs6000_long_double_type_size

As mentioned in the "Fallout: save/restore target options in handle_optimize_attribute"
thread, we need to support target option restore
of rs6000_long_double_type_size == FLOAT_PRECISION_TFmode.

gcc/ChangeLog:

* config/rs6000/rs6000.c (rs6000_option_override_internal): When
a target option is restored, it can have
rs6000_long_double_type_size set to FLOAT_PRECISION_TFmode
and error should not be emitted.

gcc/testsuite/ChangeLog:

* gcc.target/powerpc/pragma-optimize.c: New test.

Fixup gfortran.dg/vect/vect-8.f90 for aarch64

With the emulated gather changes we now consistently vectorize
for aarch64 and we can remove the SVE special-casing.

2021-08-06  Richard Biener  <rguenther@suse.de>

* gfortran.dg/vect/vect-8.f90: Simplify aarch64 scanning.

gcov: Add __gcov_info_to_gdca()

Add __gcov_info_to_gcda() to libgcov to get the gcda data for a gcda info in a
freestanding environment.  It is intended to be used with the
-fprofile-info-section option.  A crude test program which doesn't use a linker
script is (use "gcc -coverage -fprofile-info-section -lgcov test.c" to compile
it):

  #include <gcov.h>
  #include <stdio.h>
  #include <stdlib.h>

  extern const struct gcov_info *my_info;

  static void
  filename (const char *f, void *arg)
  {
    printf("filename: %s\n", f);
  }

  static void
  dump (const void *d, unsigned n, void *arg)
  {
    const unsigned char *c = d;

    for (unsigned i = 0; i < n; ++i)
      printf ("%02x", c[i]);
  }

  static void *
  allocate (unsigned length, void *arg)
  {
    return malloc (length);
  }

  int main()
  {
    __asm__ volatile (".set my_info, .LPBX2");
    __gcov_info_to_gcda (my_info, filename, dump, allocate, NULL);
    return 0;
  }

With this patch, <stdint.h> is included in libgcov-driver.c even if
inhibit_libc is defined.  This header file should be also available for
freestanding environments.  If this is not the case, then we have to define
intptr_t somehow.

The patch removes one use of memset() which makes the <string.h> include
superfluous.

gcc/

* gcov-io.h (gcov_write): Declare.
* gcov-io.c (gcov_write): New.
(gcov_write_counter): Remove.
(gcov_write_tag_length): Likewise.
(gcov_write_summary): Replace gcov_write_tag_length() with calls to
gcov_write_unsigned().
* doc/invoke.texi (fprofile-info-section): Mention
__gcov_info_to_gdca().

gcc/testsuite/

* gcc.dg/gcov-info-to-gcda.c: New test.

libgcc/

* Makefile.in (LIBGCOV_DRIVER): Add _gcov_info_to_gcda.
* gcov.h (gcov_info): Declare.
(__gcov_info_to_gdca): Likewise.
* libgcov.h (gcov_write_counter): Remove.
(gcov_write_tag_length): Likewise.
* libgcov-driver.c (#include <stdint.h>): New.
(#include <string.h>): Remove.
(NEED_L_GCOV): Conditionally define.
(NEED_L_GCOV_INFO_TO_GCDA): Likewise.
(are_all_counters_zero): New.
(gcov_dump_handler): Likewise.
(gcov_allocate_handler): Likewise.
(dump_unsigned): Likewise.
(dump_counter): Likewise.
(write_topn_counters): Add dump_fn, allocate_fn, and arg parameters.
Use dump_unsigned() and dump_counter().
(write_one_data): Add dump_fn, allocate_fn, and arg parameters.  Use
dump_unsigned(), dump_counter(), and are_all_counters_zero().
(__gcov_info_to_gcda): New.

Adjust by-value function vec arguments to by-reference.

gcc/c/ChangeLog:

* c-parser.c (c_parser_declaration_or_fndef): Adjust by-value function
vec arguments to by-reference.
(c_finish_omp_declare_simd): Same.
(c_parser_compound_statement_nostart): Same.
(c_parser_for_statement): Same.
(c_parser_objc_methodprotolist): Same.
(c_parser_oacc_routine): Same.
(c_parser_omp_for_loop): Same.
(c_parser_omp_declare_simd): Same.

gcc/ChangeLog:

* dominance.c (prune_bbs_to_update_dominators): Adjust by-value vec
arguments to by-reference.
(iterate_fix_dominators): Same.
* dominance.h (iterate_fix_dominators): Same.
* ipa-prop.h: Call auto_vec::to_vec_legacy.
* tree-data-ref.c (dump_data_dependence_relation): Adjust by-value vec
arguments to by-reference.
(debug_data_dependence_relation): Same.
(dump_data_dependence_relations): Same.
* tree-data-ref.h (debug_data_dependence_relation): Same.
(dump_data_dependence_relations): Same.
* tree-predcom.c (dump_chains): Same.
(initialize_root_vars_lm): Same.
(determine_unroll_factor): Same.
(replace_phis_by_defined_names): Same.
(insert_init_seqs): Same.
(pcom_worker::tree_predictive_commoning_loop): Call
 auto_vec::to_vec_legacy.
* tree-ssa-pre.c (insert_into_preds_of_block): Adjust by-value vec
arguments to by-reference.
* tree-ssa-threadbackward.c (populate_worklist): Same.
(back_threader::resolve_def): Same.
* tree-vect-data-refs.c (vect_check_nonzero_value): Same.
(vect_enhance_data_refs_alignment): Same.
(vect_check_lower_bound): Same.
(vect_prune_runtime_alias_test_list): Same.
(vect_permute_store_chain): Same.
* tree-vect-slp-patterns.c (vect_normalize_conj_loc): Same.
* tree-vect-stmts.c (vect_create_vectorized_demotion_stmts): Same.
* tree-vectorizer.h (vect_permute_store_chain): Same.
* vec.c (test_init): New function.
(vec_c_tests): Call new function.
* vec.h (vec): Declare ctors, dtor, and assignment.
(auto_vec::vec_to_legacy): New function.
(vec::copy): Adjust initialization.

Daily bump.

runtime: extend internal atomics to comply with sync/atomic

This is the gofrontend version of https://golang.org/cl/289152.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/339690

libstdc++: Move [[nodiscard]] attributes again [PR101782]

Where I moved these nodiscard attributes to made them apply to the
function type, not to the function. This meant they no longer generated
the desired -Wunused-result warnings, and were ill-formed with Clang
(but only a pedwarn with GCC).

Clang also detected ill-formed attributes in <queue> which this fixes.

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:

PR libstdc++/101782
* include/bits/ranges_base.h (ranges::begin, ranges::end)
(ranges::rbegin, ranges::rend, ranges::size, ranges::ssize)
(ranges::empty, ranges::data): Move attribute after the
declarator-id instead of at the end of the declarator.
* include/bits/stl_iterator.h (__gnu_cxx::__normal_iterator):
Move attributes back to the start of the function declarator,
but move the requires-clause to the end.
(common_iterator): Move attribute after the declarator-id.
* include/bits/stl_queue.h (queue): Remove ill-formed attributes
from friend declaration that are not definitions.
* include/std/ranges (views::all, views::filter)
(views::transform, views::take, views::take_while,
views::drop) (views::drop_while, views::join,
views::lazy_split) (views::split, views::counted,
views::common, views::reverse) (views::elements): Move
attributes after the declarator-id.

libcpp: Regenerate ucnid.h using Unicode 13.0.0 files [PR100977]

The following patch (incremental to the makeucnid.c fix) regenerates
ucnid.h with https://www.unicode.org/Public/13.0.0/ucd/ files.

2021-08-05  Jakub Jelinek  <jakub@redhat.com>

PR c++/100977
* ucnid.h: Regenerated using Unicode 13.0.0 files.

libcpp: Fix makeucnid bug with combining values [PR100977]

I've noticed in ucnid.h two adjacent lines that had all flags and combine
values identical and as such were supposed to be merged.

This is due to a bug in makeucnid.c, which records last_flag,
last_combine and really_safe of what has just been printed, but
because of a typo mishandles it for last_combine, always compares against
the combining_value[0] which is 0.

This has two effects on the table, one is that often the table is
unnecessarily large, as for non-zero .combine every character has its own
record instead of adjacent characters with the same flags and combine
being merged.  This means larger tables.
The other is that sometimes the last char that has combine set doesn't
actually have it in the tables, because the code is printing entries only
upon seeing the next character and if that character does have
combining_value of 0 and flags are otherwise the same as previously printed,
it will not print anything.

The following patch fixes that, for clarity what exactly it affects
I've regenerated with the same Unicode files as last time it has
been regenerated.

2021-08-05  Jakub Jelinek  <jakub@redhat.com>

PR c++/100977
* makeucnid.c (write_table): Fix computation of last_combine.
* ucnid.h: Regenerated using Unicode 6.3.0 files.

libgcc: Honor LDFLAGS_FOR_TARGET when linking libgcc_s

When building gcc with some specific LDFLAGS_FOR_TARGET, e.g.
LDFLAGS_FOR_TARGET=-Wl,-z,relro,-z,now
those flags propagate info linking of target shared libraries,
e.g. lib{ubsan,tsan,stdc++,quadmath,objc,lsan,itm,gphobos,gdruntime,gomp,go,gfortran,atomic,asan}.so.*
but there is one important exception, libgcc_s.so.* linking ignores it.

The following patch fixes that.

Bootstrapped/regtested on x86_64-linux with LDFLAGS_FOR_TARGET=-Wl,-z,relro,-z,now
and verified that libgcc_s.so.* is BIND_NOW when it previously wasn't, and
without any LDFLAGS_FOR_TARGET on x86_64-linux and i686-linux.
There on x86_64-linux I've verified that the libgcc_s.so.1 linking command
line for -m64 is identical except for whitespace to one without the patch,
and for -m32 multilib $(LDFLAGS) actually do supply there an extra -m32
that also repeats later in the @multilib_flags@, which should be harmless.

2021-08-04  Jakub Jelinek  <jakub@redhat.com>

* config/t-slibgcc (SHLIB_LINK): Add $(LDFLAGS).
* config/t-slibgcc-darwin (SHLIB_LINK): Likewise.
* config/t-slibgcc-vms (SHLIB_LINK): Likewise.
* config/t-slibgcc-fuchsia (SHLIB_LDFLAGS): Remove $(LDFLAGS).

openmp: Implement omp_get_device_num routine

This patch implements the omp_get_device_num library routine, specified in
OpenMP 5.0.

GOMP_DEVICE_NUM_VAR is a macro symbol which defines name of a "device number"
variable, is defined on the device-side libgomp, has it's address returned to
host-side libgomp during device initialization, and the host libgomp then
sets its value to the designated device number.

libgomp/ChangeLog:

* icv-device.c (omp_get_device_num): New API function, host side.
* fortran.c (omp_get_device_num_): New interface function.
* libgomp-plugin.h (GOMP_DEVICE_NUM_VAR): Define macro symbol.
* libgomp.map (OMP_5.0.2): New version space with omp_get_device_num,
omp_get_device_num_.
* libgomp.texi (omp_get_device_num): Add documentation for new API
function.
* omp.h.in (omp_get_device_num): Add declaration.
* omp_lib.f90.in (omp_get_device_num): Likewise.
* omp_lib.h.in (omp_get_device_num): Likewise.
* target.c (gomp_load_image_to_device): If additional entry for device
number exists at end of returned entries from 'load_image_func' hook,
copy the assigned device number over to the device variable.

* config/gcn/icv-device.c (GOMP_DEVICE_NUM_VAR): Define static global.
(omp_get_device_num): New API function, device side.
* plugin/plugin-gcn.c ("symcat.h"): Add include.
(GOMP_OFFLOAD_load_image): Add addresses of device GOMP_DEVICE_NUM_VAR
at end of returned 'target_table' entries.

* config/nvptx/icv-device.c (GOMP_DEVICE_NUM_VAR): Define static global.
(omp_get_device_num): New API function, device side.
* plugin/plugin-nvptx.c ("symcat.h"): Add include.
(GOMP_OFFLOAD_load_image): Add addresses of device GOMP_DEVICE_NUM_VAR
at end of returned 'target_table' entries.

* testsuite/lib/libgomp.exp
(check_effective_target_offload_target_intelmic): New function for
testing for intelmic offloading.
* testsuite/libgomp.c-c++-common/target-45.c: New test.
* testsuite/libgomp.fortran/target10.f90: New test.

libstdc++: Add [[nodiscard]] to <compare>

This adds the [[nodiscard]] attribute to all conversion operators,
comparison operators, call operators and non-member functions in
<compare>. Nothing in this header except constructors has side effects.

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:

* libsupc++/compare (partial_ordering, weak_ordering)
(strong_ordering, is_eq, is_neq, is_lt, is_lteq, is_gt, is_gteq)
(compare_three_way, strong_order, weak_order, partial_order)
(compare_strong_order_fallback, compare_weak_order_fallback)
(compare_partial_order_fallback, __detail::__synth3way): Add
nodiscard attribute.
* testsuite/18_support/comparisons/categories/zero_neg.cc: Add
-Wno-unused-result to options.

testsuite: Fix warning introduced by nodiscard in libstdc++

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
gcc/testsuite/ChangeLog:

* g++.old-deja/g++.other/inline7.C: Cast nodiscard call to void.

libstdc++: Move attributes that follow requires-clauses [PR101782]

As explained in the PR, the grammar in the Concepts TS means that a [
token following a requires-clause is parsed as part of the
logical-or-expression rather than the start of an attribute. That makes
the following ill-formed when using -fconcepts-ts:

  template<typename T> requires foo<T> [[nodiscard]] int f(T);

This change moves all attributes that follow a requires-clause to the
end of the function declarator.

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:

PR libstdc++/101782
* include/bits/ranges_base.h (ranges::begin, ranges::end)
(ranges::rbegin, ranges::rend, ranges::size, ranges::ssize)
(ranges::empty, ranges::data): Move attribute to the end of
the declarator.
* include/bits/stl_iterator.h (__gnu_cxx::__normal_iterator)
(common_iterator): Likewise for non-member operator functions.
* include/std/ranges (views::all, views::filter)
(views::transform, views::take, views::take_while, views::drop)
(views::drop_while, views::join, views::lazy_split)
(views::split, views::counted, views::common, views::reverse)
(views::elements): Likewise.
* testsuite/std/ranges/access/101782.cc: New test.

<x86gprintrin.h>: Add pragma GCC target("general-regs-only")

1. Intrinsics in <x86gprintrin.h> only require GPR ISAs.  Add

 #if defined __MMX__ || defined __SSE__
 #pragma GCC push_options
 #pragma GCC target("general-regs-only")
 #define __DISABLE_GENERAL_REGS_ONLY__
 #endif

and

 #ifdef __DISABLE_GENERAL_REGS_ONLY__
 #undef __DISABLE_GENERAL_REGS_ONLY__
 #pragma GCC pop_options
 #endif /* __DISABLE_GENERAL_REGS_ONLY__ */

to <x86gprintrin.h> to disable non-GPR ISAs so that they can be used in
functions with __attribute__ ((target("general-regs-only"))).
2. When checking always_inline attribute, if callee only uses GPRs,
ignore MASK_80387 since enable MASK_80387 in caller has no impact on
callee inline.

gcc/

PR target/99744
* config/i386/i386.c (ix86_can_inline_p): Ignore MASK_80387 if
callee only uses GPRs.
* config/i386/ia32intrin.h: Revert commit 5463cee2770.
* config/i386/serializeintrin.h: Revert commit 71958f740f1.
* config/i386/x86gprintrin.h: Add
#pragma GCC target("general-regs-only") and #pragma GCC pop_options
to disable non-GPR ISAs.

gcc/testsuite/

PR target/99744
* gcc.target/i386/pr99744-3.c: New test.
* gcc.target/i386/pr99744-4.c: Likewise.
* gcc.target/i386/pr99744-5.c: Likewise.
* gcc.target/i386/pr99744-6.c: Likewise.
* gcc.target/i386/pr99744-7.c: Likewise.
* gcc.target/i386/pr99744-8.c: Likewise.

doc: Document cond_* shift optabs in md.texi

gcc/
PR middle-end/101787
* doc/md.texi (cond_ashl, cond_ashr, cond_lshr): Document.

vect: Move costing helpers from aarch64 code

aarch64.c has various routines to test for specific kinds of
vector statement cost.  The routines aren't really target-specific,
so following a suggestion from Richi, this patch moves them to a new
section of tree-vectorizer.h.

gcc/
* tree-vectorizer.h (vect_is_store_elt_extraction, vect_is_reduction)
(vect_reduc_type, vect_embedded_comparison_type, vect_comparison_type)
(vect_is_extending_load, vect_is_integer_truncation): New functions,
moved from aarch64.c but given different names.
* config/aarch64/aarch64.c (aarch64_is_store_elt_extraction)
(aarch64_is_reduction, aarch64_reduc_type)
(aarch64_embedded_comparison_type, aarch64_comparison_type)
(aarch64_extending_load_p, aarch64_integer_truncation_p): Delete
in favor of the above.  Update callers accordingly.

arm: reorder assembler architecture directives [PR101723]

A change to the way gas interprets the .fpu directive in binutils-2.34
means that issuing .fpu will clear any features set by .arch_extension
that apply to the floating point or simd units.  This unfortunately
causes problems for more recent versions of the architecture because
we currently emit .arch, .arch_extension and .fpu directives at
different times and try to suppress redundant changes.

This change addresses this by firstly unifying all the places where we
emit these directives to a single block of code and secondly
(re)emitting all the directives if any changes have been made to the
target options.  Whilst this is slightly more than the strict minimum
it should be enough to catch all cases where a change could have
happened.  The new code also emits the directives in the order: .arch,
.fpu, .arch_extension.  This ensures that the additional architectural
extensions are not removed by a later .fpu directive.

Whilst writing this patch I also noticed that in the corner case where
the last function to be compiled had a non-standard set of
architecture flags, the assembler would add an incorrect set of
derived attributes for the file as a whole.  Instead of reflecting the
command-line options it would reflect the flags from the last file in
the function.  To address this I've also added a call to re-emit the
flags from the asm_file_end callback so the assembler will be in the
correct state when it finishes processing the intput.

There's some slight churn to the testsuite as a consequence of this,
because previously we had a hack to suppress emitting a .fpu directive
for one specific case, but with the new order this is no-longer
necessary.

gcc/ChangeLog:

PR target/101723
* config/arm/arm-cpus.in (generic-armv7-a): Add quirk to suppress
writing .cpu directive in asm output.
* config/arm/arm.c (arm_identify_fpu_from_isa): New variable.
(arm_last_printed_arch_string): Delete.
(arm_last-printed_fpu_string): Delete.
(arm_configure_build_target): If use of floating-point/SIMD is
disabled, remove all fp/simd related features from the target ISA.
(last_arm_targ_options): New variable.
(arm_print_asm_arch_directives): Add new parameters.  Change order
of emitted directives and handle all cases here.
(arm_file_start): Always call arm_print_asm_arch_directives, move
all generation of .arch/.arch_extension here.
(arm_file_end): Call arm_print_asm_arch.
(arm_declare_function_name): Call arm_print_asm_arch_directives
instead of printing .arch/.fpu directives directly.

gcc/testsuite/ChangeLog:

PR target/101723
* gcc.target/arm/cortex-m55-nofp-flag-hard.c: Update expected output.
* gcc.target/arm/cortex-m55-nofp-flag-softfp.c: Likewise.
* gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_fpu1.c: Convert to dg-do assemble.
Add a non-no-op function body.
* gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise.
* gcc.target/arm/pr98636.c (dg-options): Add -mfloat-abi=softfp.
* gcc.target/arm/attr-neon.c: Tighten scan-assembler tests.
* gcc.target/arm/attr-neon2.c: Use -Ofast, convert test to use
check-function-bodies.
* gcc.target/arm/attr-neon3.c: Likewise.
* gcc.target/arm/pr69245.c: Tighten scan-assembler match, but allow
multiple instances.
* gcc.target/arm/pragma_fpu_attribute.c: Likewise.
* gcc.target/arm/pragma_fpu_attribute_2.c: Likewise.

arm: Don't reconfigure globals in arm_configure_build_target

arm_configure_build_target is usually used to reconfigure the
arm_active_target structure, which is then used to reconfigure a
number of other global variables describing the current target.
Occasionally, however, we need to use arm_configure_build_target to
construct a temporary target structure and in that case it is wrong to
try to reconfigure the global variables (although probably harmless,
since arm_option_reconfigure_globals() only looks at
arm_active_target).  At the very least, however, this is wasted work,
so it is best not to do it unless needed.  What's more, several
callers of arm_configure_build target call
arm_option_reconfigure_globals themselves within a few lines, making
the call from within arm_configure_build_target completely redundant.

So this patch moves the responsibility of calling of
arm_configure_build_target to its callers (only two places needed
updating).

gcc:
* config/arm/arm.c (arm_configure_build_target): Don't call
arm_option_reconfigure_globals.
(arm_option_restore): Call arm_option_reconfigure_globals after
reconfiguring the target.
* config/arm/arm-c.c (arm_pragma_target_parse): Likewise.

arm: ensure the arch_name is always set for the build target

This should never happen now if GCC is invoked by the driver, but in
the unusual case of calling cc1 (or its ilk) directly from the command
line the build target's arch_name string can remain NULL.  This can
complicate later processing meaning that we need to check for this
case explicitly in some circumstances.  Nothing should rely on this
behaviour, so it's simpler to always set the arch_name when
configuring the build target and be done with it.

gcc:

* config/arm/arm.c (arm_configure_build_target): Ensure the target's
arch_name is always set.

aarch64: Don't include vec_select high-half in SIMD subtract cost

The Neon subtract-long/subract-widen instructions can select the top
or bottom half of the operand registers. This selection does not
change the cost of the underlying instruction and this should be
reflected by the RTL cost function.

This patch adds RTL tree traversal in the Neon subtract cost function
to match vec_select high-half of its operands. This traversal
prevents the cost of the vec_select from being added into the cost of
the subtract - meaning that these instructions can now be emitted in
the combine pass as they are no longer deemed prohibitively
expensive.

gcc/ChangeLog:

2021-07-28  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64.c: Traverse RTL tree to prevent cost
of vec_select high-half from being added into Neon subtract
cost.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/vsubX_high_cost.c: New test.

aarch64: Don't include vec_select high-half in SIMD add cost

The Neon add-long/add-widen instructions can select the top or bottom
half of the operand registers. This selection does not change the
cost of the underlying instruction and this should be reflected by
the RTL cost function.

This patch adds RTL tree traversal in the Neon add cost function to
match vec_select high-half of its operands. This traversal prevents
the cost of the vec_select from being added into the cost of the
subtract - meaning that these instructions can now be emitted in the
combine pass as they are no longer deemed prohibitively expensive.

gcc/ChangeLog:

2021-07-28  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64.c: Traverse RTL tree to prevent cost
of vec_select high-half from being added into Neon add cost.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/vaddX_high_cost.c: New test.

Adjust gcc.dg/vect/bb-slp-pr101756.c

This adjusts the testcase for excess diagnostics emitted by some
targets because of the attribute simd usage like

warning: GCC does not currently support mixed size types for 'simd' functions

on aarch64.

2021-08-05  Richard Biener  <rguenther@suse.de>

* gcc.dg/vect/bb-slp-pr101756.c: Add -w.

cfgloop: Make loops_list support an optional loop_p root

This patch follows Richi's suggestion to add one optional
argument class loop* root to loops_list's CTOR, it can
provide the ability to construct a visiting list starting
from the given class loop* ROOT rather than the default
tree_root of loops_for_fn (FN), for visiting a subset of
the loop tree.

It unifies all orders of walkings into walk_loop_tree, but
it still uses linear search for LI_ONLY_INNERMOST when
looking at the whole loop tree since it has a more stable
bound.

gcc/ChangeLog:

* cfgloop.h (loops_list::loops_list): Add one optional argument
root and adjust accordingly, update loop tree walking and factor
out to ...
* cfgloop.c (loops_list::walk_loop_tree): ... this.  New function.

Fix oversight in handling of reverse SSO in SRA pass

The scalar storage order does not apply to pointer and vector components.

gcc/
PR tree-optimization/101626
* tree-sra.c (propagate_subaccesses_from_rhs): Do not set the
reverse scalar storage order on a pointer or vector component.

gcc/testsuite/
* gcc.dg/sso-15.c: New test.

compiler: make escape analysis more robust about builtin functions

In the places where we handle builtin functions, list all
supported ones, and fail if an unexpected one is seen. So if a
new builtin function is added in the future we can detect it,
instead of silently treating it as nonescaping.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/339992

Support cond_{xor,ior,and} for vector integer mode under AVX512.

gcc/ChangeLog:

* config/i386/sse.md (cond_<code><mode>): New expander.

gcc/testsuite/ChangeLog:

* gcc.target/i386/cond_op_anylogic_d-1.c: New test.
* gcc.target/i386/cond_op_anylogic_d-2.c: New test.
* gcc.target/i386/cond_op_anylogic_q-1.c: New test.
* gcc.target/i386/cond_op_anylogic_q-2.c: New test.

Support cond_{smax,smin} for vector float/double modes under AVX512.

gcc/ChangeLog:

* config/i386/sse.md (cond_<code><mode>): New expander.

gcc/testsuite/ChangeLog:

* gcc.target/i386/cond_op_maxmin_double-1.c: New test.
* gcc.target/i386/cond_op_maxmin_double-2.c: New test.
* gcc.target/i386/cond_op_maxmin_float-1.c: New test.
* gcc.target/i386/cond_op_maxmin_float-2.c: New test.

Support cond_{smax,smin,umax,umin} for vector integer modes under AVX512.

gcc/ChangeLog:

* config/i386/sse.md (cond_<code><mode>): New expander.

gcc/testsuite/ChangeLog:

* gcc.target/i386/cond_op_maxmin_b-1.c: New test.
* gcc.target/i386/cond_op_maxmin_b-2.c: New test.
* gcc.target/i386/cond_op_maxmin_d-1.c: New test.
* gcc.target/i386/cond_op_maxmin_d-2.c: New test.
* gcc.target/i386/cond_op_maxmin_q-1.c: New test.
* gcc.target/i386/cond_op_maxmin_q-2.c: New test.
* gcc.target/i386/cond_op_maxmin_ub-1.c: New test.
* gcc.target/i386/cond_op_maxmin_ub-2.c: New test.
* gcc.target/i386/cond_op_maxmin_ud-1.c: New test.
* gcc.target/i386/cond_op_maxmin_ud-2.c: New test.
* gcc.target/i386/cond_op_maxmin_uq-1.c: New test.
* gcc.target/i386/cond_op_maxmin_uq-2.c: New test.
* gcc.target/i386/cond_op_maxmin_uw-1.c: New test.
* gcc.target/i386/cond_op_maxmin_uw-2.c: New test.
* gcc.target/i386/cond_op_maxmin_w-1.c: New test.
* gcc.target/i386/cond_op_maxmin_w-2.c: New test.

Daily bump.

analyzer: initial implementation of asm support [PR101570]

gcc/ChangeLog:
PR analyzer/101570
* Makefile.in (ANALYZER_OBJS): Add analyzer/region-model-asm.o.

gcc/analyzer/ChangeLog:
PR analyzer/101570
* analyzer.cc (maybe_reconstruct_from_def_stmt): Add GIMPLE_ASM
case.
* analyzer.h (class asm_output_svalue): New forward decl.
(class reachable_regions): New forward decl.
* complexity.cc (complexity::from_vec_svalue): New.
* complexity.h (complexity::from_vec_svalue): New decl.
* engine.cc (feasibility_state::maybe_update_for_edge): Handle
asm stmts by calling on_asm_stmt.
* region-model-asm.cc: New file.
* region-model-manager.cc
(region_model_manager::maybe_fold_asm_output_svalue): New.
(region_model_manager::get_or_create_asm_output_svalue): New.
(region_model_manager::log_stats): Log m_asm_output_values_map.
* region-model.cc (region_model::on_stmt_pre): Handle GIMPLE_ASM.
* region-model.h (visitor::visit_asm_output_svalue): New.
(region_model_manager::get_or_create_asm_output_svalue): New decl.
(region_model_manager::maybe_fold_asm_output_svalue): New decl.
(region_model_manager::asm_output_values_map_t): New typedef.
(region_model_manager::m_asm_output_values_map): New field.
(region_model::on_asm_stmt): New.
* store.cc (binding_cluster::on_asm): New.
* store.h (binding_cluster::on_asm): New decl.
* svalue.cc (svalue::cmp_ptr): Handle SK_ASM_OUTPUT.
(asm_output_svalue::dump_to_pp): New.
(asm_output_svalue::dump_input): New.
(asm_output_svalue::input_idx_to_asm_idx): New.
(asm_output_svalue::accept): New.
* svalue.h (enum svalue_kind): Add SK_ASM_OUTPUT.
(svalue::dyn_cast_asm_output_svalue): New.
(class asm_output_svalue): New.
(is_a_helper <const asm_output_svalue *>::test): New.
(struct default_hash_traits<asm_output_svalue::key_t>): New.

gcc/testsuite/ChangeLog:
PR analyzer/101570
* gcc.dg/analyzer/asm-x86-1.c: New test.
* gcc.dg/analyzer/asm-x86-lp64-1.c: New test.
* gcc.dg/analyzer/asm-x86-lp64-2.c: New test.
* gcc.dg/analyzer/pr101570.c: New test.
* gcc.dg/analyzer/torture/asm-x86-linux-array_index_mask_nospec.c:
New test.
* gcc.dg/analyzer/torture/asm-x86-linux-cpuid-paravirt-1.c: New
test.
* gcc.dg/analyzer/torture/asm-x86-linux-cpuid-paravirt-2.c: New
test.
* gcc.dg/analyzer/torture/asm-x86-linux-cpuid.c: New test.
* gcc.dg/analyzer/torture/asm-x86-linux-rdmsr-paravirt.c: New
test.
* gcc.dg/analyzer/torture/asm-x86-linux-rdmsr.c: New test.
* gcc.dg/analyzer/torture/asm-x86-linux-wfx_get_ps_timeout-full.c:
New test.
* gcc.dg/analyzer/torture/asm-x86-linux-wfx_get_ps_timeout-reduced.c:
New test.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

x86: Update STORE_MAX_PIECES

Update STORE_MAX_PIECES to allow 16/32/64 bytes only if inter-unit move
is enabled since vec_duplicate enabled by inter-unit move is used to
implement store_by_pieces of 16/32/64 bytes.

gcc/

PR target/101742
* config/i386/i386.h (STORE_MAX_PIECES): Allow 16/32/64 bytes
only if TARGET_INTER_UNIT_MOVES_TO_VEC is true.

gcc/testsuite/

PR target/101742
* gcc.target/i386/pr101742a.c: New test.
* gcc.target/i386/pr101742b.c: Likewise.

x86: Avoid stack realignment when copying data with SSE register

To avoid stack realignment, call ix86_gen_scratch_sse_rtx to get a
scratch SSE register to copy data with with SSE register from one
memory location to another.

gcc/

PR target/101772
* config/i386/i386-expand.c (ix86_expand_vector_move): Call
ix86_gen_scratch_sse_rtx to get a scratch SSE register to copy
data with SSE register from one memory location to another.

gcc/testsuite/

PR target/101772
* gcc.target/i386/eh_return-2.c: New test.