Dmitry Sidorov [Thu, 5 Nov 2020 14:16:44 +0000 (17:16 +0300)]
Upstream AP Intel extensions
SPV_INTEL_arbitrary_precision_floating_point and
SPV_INTEL_arbitrary_precision_fixed_point extensions are
being upstreamed.
Specs:
https://github.com/intel/llvm/blob/
2f6e965e686354fbb25f9c177a667a646de302eb/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_fixed_point.asciidoc
https://github.com/intel/llvm/blob/
bd86b218f749ea0e20ddc18c42db491faf54014a/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_floating_point.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Raun Krisch [Wed, 10 Mar 2021 16:49:56 +0000 (10:49 -0600)]
Merge pull request #178 from orbea/datadir
cmake: Install cmake files to CMAKE_INSTALL_DATADIR
Raun Krisch [Fri, 5 Mar 2021 16:31:29 +0000 (10:31 -0600)]
Merge pull request #200 from dneto0/public-spv-khr-linkonce-odr-spv-khr-expect-assume
Support SPV_KHR_linkonce_odr and SPV_KHR_expect_assume
David Neto [Fri, 3 Jul 2020 19:53:15 +0000 (15:53 -0400)]
Support SPV_KHR_expect_assume
David Neto [Fri, 3 Jul 2020 18:35:07 +0000 (14:35 -0400)]
Support SPV_KHR_linkonce_odr
Raun Krisch [Wed, 3 Mar 2021 16:54:46 +0000 (10:54 -0600)]
Merge pull request #198 from alan-baker/read-clock-scope
Change operand name in OpReadClockKHR to match extension
Raun Krisch [Wed, 3 Mar 2021 16:49:56 +0000 (10:49 -0600)]
Merge pull request #195 from kvark/patch-1
Add Naga as SPIR-V generation tool
Alan Baker [Mon, 1 Mar 2021 14:00:33 +0000 (09:00 -0500)]
Change operand name in OpReadClockKHR to match extension
* The grammar was not updated when revision 3 of SPV_KHR_shader_clock
was published
* That revision renamed the *Execution* operand to *Scope*
John Kessenich [Fri, 19 Feb 2021 15:11:04 +0000 (22:11 +0700)]
Merge pull request #193 from bashbaug/DebugInfoFlags-None
add None as a possible value for DebugInfoFlags
Dzmitry Malyshau [Sun, 14 Feb 2021 04:32:27 +0000 (23:32 -0500)]
Add Naga as SPIR-V generation tool
John Kessenich [Wed, 10 Feb 2021 12:35:29 +0000 (05:35 -0700)]
Merge pull request #187 from bashbaug/function_control_bit_16
add function control bitfield reservation section
John Kessenich [Wed, 10 Feb 2021 12:28:03 +0000 (05:28 -0700)]
Merge pull request #190 from dneto0/check-enumerant-ordering
Header generator: Check enumerant ordering
John Kessenich [Wed, 10 Feb 2021 12:24:21 +0000 (05:24 -0700)]
Merge pull request #189 from jekstrand/SPV_EXT_shader_atomic_float_min_max
Add header changes for SPV_EXT_shader_atomic_float_min_max
Jason Ekstrand [Wed, 19 Aug 2020 22:03:06 +0000 (17:03 -0500)]
Add header changes for SPV_EXT_shader_atomic_float_min_max
Jason Ekstrand [Wed, 27 Jan 2021 22:56:58 +0000 (16:56 -0600)]
Re-run buildSpvHeaders to fix indentation
David Neto [Wed, 20 Jan 2021 02:20:44 +0000 (21:20 -0500)]
Header generator: Check enumerant ordering
In the grammar, enforce ordering rules:
- Instructions must appear in order of their opcode
- Non-instructions: each successive enumerant within a single kind must
appear in order
- Reorder enumerants Subgroup*MaskKHR enums to satisfy the rule.
Ben Ashbaugh [Wed, 27 Jan 2021 16:50:30 +0000 (08:50 -0800)]
add generated headers
John Kessenich [Wed, 27 Jan 2021 16:43:46 +0000 (09:43 -0700)]
Merge pull request #192 from cmarcelo/SPV_KHR_workgroup_memory_explicit_layout
Add SPV_KHR_workgroup_memory_explicit_layout
Ben Ashbaugh [Wed, 27 Jan 2021 16:03:49 +0000 (08:03 -0800)]
add None as a possible value for DebugInfoFlags
Caio Marcelo de Oliveira Filho [Mon, 25 Jan 2021 13:57:46 +0000 (05:57 -0800)]
Add SPV_KHR_workgroup_memory_explicit_layout
John Kessenich [Fri, 22 Jan 2021 20:34:02 +0000 (13:34 -0700)]
Merge pull request #191 from dneto0/reorder-enums-in-spec
Push FPDenormMode, FPOperationMode to the end
David Neto [Wed, 20 Jan 2021 21:54:17 +0000 (16:54 -0500)]
Push FPDenormMode, FPOperationMode to the end
This is a cosmetic change for the benefit of generating the SPIR-V spec.
It reorders the "FP Denorm Mode" and "FP Operation Mode" so they are
the last sections in chapter 3 before the instruction listing.
They become 3.37 and 3.38. The idea is to preserve the section numbering
for earlier sections. For example, keep 3.31 as the Capability section.
John Kessenich [Wed, 20 Jan 2021 16:44:51 +0000 (09:44 -0700)]
Merge pull request #176 from MrSidims/private/MrSidims/OtherExtensions
Upstream several Intel extensions
Dmitry Sidorov [Wed, 20 Jan 2021 11:36:25 +0000 (14:36 +0300)]
Apply suggestions to Intel extensions PR
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Wed, 16 Dec 2020 16:35:01 +0000 (19:35 +0300)]
Update generated files
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Wed, 16 Dec 2020 16:34:22 +0000 (19:34 +0300)]
Add SPV_INTEL_long_constant_composite extension
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Wed, 16 Dec 2020 15:47:50 +0000 (18:47 +0300)]
Add SPV_INTEL_loop_fuse extension
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Mon, 23 Nov 2020 08:19:33 +0000 (11:19 +0300)]
Add SPV_INTEL_fpga_cluster_attributes and SPV_INTEL_fp_fast_math_mode
Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/
7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc
https://github.com/KhronosGroup/SPIRV-Registry/blob/
7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fp_fast_math_mode.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Mon, 23 Nov 2020 08:09:22 +0000 (11:09 +0300)]
Update SPV_INTEL_fpga_loop_controls extension
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Mon, 16 Nov 2020 19:41:33 +0000 (22:41 +0300)]
Update SPV_INTEL_kernel_attributes extension
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Mon, 9 Nov 2020 13:05:22 +0000 (16:05 +0300)]
Update SPV_INTEL_function_pointers extension
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Mon, 9 Nov 2020 10:03:22 +0000 (13:03 +0300)]
Upstream SPV_INTEL_float_controls2 extension
Spec:
https://github.com/intel/llvm/blob/
39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Mon, 9 Nov 2020 09:18:01 +0000 (12:18 +0300)]
Upstream SPV_INTEL_vector_compute extension
Spec:
https://github.com/intel/llvm/blob/
e185a6b49e4bc9806a799b774977f1196b24f0d6/sycl/doc/extensions/SPIRV/SPV_INTEL_vector_compute.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Fri, 6 Nov 2020 10:04:08 +0000 (13:04 +0300)]
Upstream SPV_INTEL_fpga_memory_accesses extension
Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Fri, 6 Nov 2020 09:52:16 +0000 (12:52 +0300)]
Upstream SPV_INTEL_io_pipes extension
Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_io_pipes.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Thu, 5 Nov 2020 10:01:03 +0000 (13:01 +0300)]
Upstream SPV_INTEL_variable_length_array extension
Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_variable_length_array.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Thu, 5 Nov 2020 09:29:39 +0000 (12:29 +0300)]
Upstream SPV_INTEL_usm_storage_classes extension
Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_usm_storage_classes.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Thu, 5 Nov 2020 09:05:34 +0000 (12:05 +0300)]
Upstream SPV_INTEL_arbitrary_precision_integers extensions
Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_int.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Thu, 5 Nov 2020 08:45:16 +0000 (11:45 +0300)]
Upstream SPV_INTEL_inline_assembly extension
Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Tue, 3 Nov 2020 13:52:47 +0000 (16:52 +0300)]
Upstream SPV_INTEL_fpga_buffer_location extension
Spec:
https://github.com/intel/llvm/blob/
2237b42035f31cb10b16d4f9abaeed45bed98587/sycl/doc/extensions/SPIRV/SPV_INTEL_fpga_buffer_location.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Ben Ashbaugh [Tue, 5 Jan 2021 22:50:47 +0000 (14:50 -0800)]
add function control bitfield reservation section
reserve bit 16 for an upcoming Intel extension
Raun Krisch [Fri, 27 Nov 2020 23:52:34 +0000 (17:52 -0600)]
Merge pull request #184 from dgkoch/dkoch_remove_hittkhr
remove HitTKHR alias
Daniel Koch [Thu, 26 Nov 2020 22:28:05 +0000 (17:28 -0500)]
remove HitTKHR
It was not added to the SPV_KHR_ray_tracing extension since it is just
an alias of RayTMaxKHR.
David Neto [Mon, 23 Nov 2020 15:16:21 +0000 (10:16 -0500)]
Merge pull request #180 from dneto0/issue-179
MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex
David Neto [Thu, 12 Nov 2020 19:28:10 +0000 (14:28 -0500)]
MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex
Fixes #179
See extension SPV_NV_mesh_shader
Raun Krisch [Mon, 23 Nov 2020 14:58:25 +0000 (08:58 -0600)]
Merge pull request #182 from dgkoch/khr_rt_final
Updates to final ray tracing extensions
Daniel Koch [Fri, 16 Oct 2020 18:18:46 +0000 (14:18 -0400)]
de-alias/reassign OpIgnoreIntersectionKHR/OpTerminateRayKHR
vulkan/vulkan#2374
alelenv [Mon, 29 Jun 2020 18:42:18 +0000 (11:42 -0700)]
Raytracing and Rayquery updates for final
alelenv [Mon, 15 Jun 2020 18:08:39 +0000 (11:08 -0700)]
Updated headers for new trace/executeCallable and acceleration structure cast.
orbea [Fri, 6 Nov 2020 06:08:24 +0000 (22:08 -0800)]
cmake: Install cmake files to CMAKE_INSTALL_DATADIR
Mike Kinsner [Thu, 5 Nov 2020 02:58:17 +0000 (22:58 -0400)]
Reserve additional loop control bit for Intel extension (NoFusionINTEL) (#175)
XAMPPRocky [Mon, 2 Nov 2020 16:14:05 +0000 (17:14 +0100)]
Add EmbarkStudios/rust-gpu to vendor list. (#174)
John Kessenich [Fri, 23 Oct 2020 15:21:38 +0000 (09:21 -0600)]
Bump revision to 4, for SPIR-V 1.5.
Tobski [Mon, 19 Oct 2020 20:56:28 +0000 (21:56 +0100)]
Add SPV_EXT_shader_image_int64 (#170)
Co-authored-by: Arkadiusz Sarwa <arkadiusz.sarwa@amd.com>
Tobski [Mon, 19 Oct 2020 20:55:32 +0000 (21:55 +0100)]
Added SPV_KHR_fragment_shading_rate (#172)
Triang3l [Mon, 12 Oct 2020 16:31:57 +0000 (19:31 +0300)]
Register the Xenia emulator as a generator (#171)
Yuwen Wu [Sun, 27 Sep 2020 03:57:26 +0000 (11:57 +0800)]
Register the Messiah SPIR-V CodeGen (#169)
Shahbaz Youssefi [Thu, 10 Sep 2020 16:03:06 +0000 (12:03 -0400)]
Register the ANGLE compiler (#168)
John Kessenich [Tue, 8 Sep 2020 14:01:38 +0000 (08:01 -0600)]
Rebuild of latest headers, which slightly moves OpTerminateInvocation
Mariusz Merecki [Mon, 3 Aug 2020 09:04:37 +0000 (11:04 +0200)]
Reserve SPIR-V token range for upcoming Intel extensions. (#165)
alan-baker [Wed, 29 Jul 2020 20:56:17 +0000 (16:56 -0400)]
Update BUILD.bazel and BUILD.gn (#166)
* Export NonSemantic.ClspvReflection.h for both
* Add exports for the extended instruction sets in the unified1
directory (for use in SPIRV-Tools)
alan-baker [Wed, 29 Jul 2020 18:23:29 +0000 (14:23 -0400)]
Publish the headers for the clspv embedded reflection non-semantic extended instruction set (#164)
* Clspv non-semantic reflection instruction set
* Version 1
John Kessenich [Wed, 29 Jul 2020 15:38:57 +0000 (09:38 -0600)]
Update the registry in spir-v.xml to modernize and split out opcodes. (#156)
alan-baker [Tue, 21 Jul 2020 06:15:13 +0000 (02:15 -0400)]
Support SPV_KHR_terminate_invocation (#163)
* Support SPV_KHR_terminate_invocation
* Fix order in spirv.core.grammar.json
Co-authored-by: David Neto <dneto@google.com>
John Kessenich [Mon, 20 Jul 2020 17:40:06 +0000 (00:40 +0700)]
Merge pull request #162 from vkushwaha-nv/SPV_EXT_shader_atomic_float
Add changes for SPV_EXT_shader_atomic_float
Vikram Kushwaha [Sun, 19 Jul 2020 22:29:04 +0000 (15:29 -0700)]
Add changes for SPV_EXT_shader_atomic_float
David Neto [Mon, 6 Jul 2020 15:49:37 +0000 (08:49 -0700)]
Merge pull request #160 from dj2/reg_tint
Register the Tint compiler
dan sinclair [Fri, 26 Jun 2020 16:00:08 +0000 (12:00 -0400)]
Register the Tint compiler
John Kessenich [Mon, 1 Jun 2020 16:40:53 +0000 (10:40 -0600)]
Merge pull request #159 from dneto0/fix-quotes
spir-v.xml: Use plain ASCII quotes in comment
David Neto [Mon, 1 Jun 2020 15:58:55 +0000 (11:58 -0400)]
spir-v.xml: Use plain ASCII quotes in comment
Avoids parse error on Windows-based Python3.
John Kessenich [Fri, 29 May 2020 13:50:37 +0000 (07:50 -0600)]
Merge pull request #158 from mkinsner/mkinsner/fpfastmath_allocation_mechanism
Propose bit allocation mechanism for the FP Fast Math Mode bitfield
John Kessenich [Fri, 29 May 2020 13:48:16 +0000 (07:48 -0600)]
Rebuild headers against the previous grammar commit.
John Kessenich [Fri, 29 May 2020 13:47:40 +0000 (07:47 -0600)]
Merge pull request #150 from MrSidims/private/MrSidims/UpstreamIntelExt
Add Intel specific definitions from https://github.com/KhronosGroup/S…
Dmitry Sidorov [Fri, 29 May 2020 11:14:14 +0000 (14:14 +0300)]
Apply suggestions
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
Dmitry Sidorov [Sun, 5 Apr 2020 14:30:50 +0000 (17:30 +0300)]
Add Intel specific definitions from KhronosGroup/SPIRV-LLVM-Translator
List of extensions:
SPV_INTEL_fpga_memory_attributes
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_attributes.asciidoc
SPV_INTEL_kernel_attributes
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_kernel_attributes.asciidoc
SPV_INTEL_fpga_reg
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_reg.asciidoc
SPV_INTEL_blocking_pipes
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_blocking_pipes.asciidoc
SPV_INTEL_fpga_loop_controls
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_loop_controls.asciidoc
SPV_INTEL_unstructured_loop_controls
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_unstructured_loop_controls.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
John Kessenich [Fri, 29 May 2020 09:36:53 +0000 (03:36 -0600)]
Header build from previous grammar update.
John Kessenich [Fri, 29 May 2020 09:28:43 +0000 (03:28 -0600)]
Merge pull request #152 from MrSidims/private/MrSidims/FunctionPointers
Add SPV_INTEL_function_pointers preview extension
Michael Kinsner [Mon, 25 May 2020 20:15:28 +0000 (17:15 -0300)]
Propose bit allocation mechanism for the FP Fast Math Mode bitfield, following from the mechanism previously added for the loop control bitfield.
John Kessenich [Thu, 21 May 2020 11:35:51 +0000 (05:35 -0600)]
Merge pull request #157 from dneto0/update-example
Update example to use unified1 headers
David Neto [Wed, 20 May 2020 15:58:47 +0000 (11:58 -0400)]
Update example to use unified1 headers
Also remove the 1.1-specific example.
John Kessenich [Fri, 24 Apr 2020 14:50:04 +0000 (08:50 -0600)]
Update headers to SPIR-V 1.5 Revision 3
John Kessenich [Fri, 24 Apr 2020 12:50:35 +0000 (06:50 -0600)]
Add a bunch of missing "version" : "None" for ray tracing.
John Kessenich [Fri, 24 Apr 2020 08:56:56 +0000 (02:56 -0600)]
Rebuild the headers with the fixed grammar file.
See previous 2 commits.
John Kessenich [Fri, 24 Apr 2020 07:20:05 +0000 (01:20 -0600)]
Add missing "version" : "None" for ShaderCallKHR
John Kessenich [Fri, 24 Apr 2020 06:26:45 +0000 (00:26 -0600)]
Grammar: The ray-tracing updates were not done in numerical ordering.
This makes management difficult. See the readme:
Care should be taken to follow existing precedent in populating the
details of reserved tokens. This includes:
* keeping enumerants in numeric order
John Kessenich [Mon, 13 Apr 2020 14:10:55 +0000 (08:10 -0600)]
Discuss generator magic number reservations.
Dmitry Sidorov [Sun, 5 Apr 2020 14:25:26 +0000 (17:25 +0300)]
Add SPV_INTEL_function_pointers preview extension
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
John Kessenich [Tue, 17 Mar 2020 13:49:00 +0000 (07:49 -0600)]
Merge pull request #149 from dgkoch/prov_ray_tracing
Add SPV_KHR_ray_{tracing,query} to headers
Daniel Koch [Tue, 17 Mar 2020 11:39:38 +0000 (07:39 -0400)]
Add shadercalls scope
and update copyright notices
Torosdagli [Tue, 3 Mar 2020 23:01:57 +0000 (18:01 -0500)]
Added ray flags, primitive culling flags, queries
John Kessenich [Tue, 17 Mar 2020 06:44:51 +0000 (00:44 -0600)]
Non-functional: Update header build to match Khronos spec. builder.
John Kessenich [Tue, 17 Mar 2020 06:37:33 +0000 (00:37 -0600)]
Merge pull request #135 from vulturm/patch-1
Also propagate SPIRV-Headers version to CMakeLists.txt
alelenv [Fri, 14 Feb 2020 20:51:42 +0000 (12:51 -0800)]
Update headers for SPV_KHR_ray_tracing.
John Kessenich [Sat, 14 Mar 2020 07:23:58 +0000 (01:23 -0600)]
Merge pull request #148 from null77/fix-gn
Add missing header to BUILD.gn.
Jamie Madill [Fri, 13 Mar 2020 20:53:30 +0000 (16:53 -0400)]
Add missing header to BUILD.gn.
File: include/spirv/unified1/NonSemanticDebugPrintf.h was missing.
This was causing a presubmit step to fail in ANGLE.
Steven Perron [Mon, 9 Mar 2020 18:32:37 +0000 (14:32 -0400)]
Merge pull request #146 from s-perron/bazel
Export NonSemanticDebugPrintf.h in bazel build
Steven Perron [Mon, 9 Mar 2020 18:23:42 +0000 (14:23 -0400)]
Export NonSemanticDebugPrintf.h in bazel build
John Kessenich [Thu, 5 Mar 2020 06:55:33 +0000 (23:55 -0700)]
Merge pull request #145 from jeffbolznv/nonsemantic_debugprintf
Add NonSemantic.DebugPrintf JSON/header
Jeff Bolz [Mon, 2 Mar 2020 15:44:14 +0000 (09:44 -0600)]
Add NonSemantic.DebugPrintf JSON/header
Jeff Bolz [Mon, 2 Mar 2020 15:43:49 +0000 (09:43 -0600)]
Fix max enum value